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vc4: Don't bother saturating the dst color for blending.
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "util/u_format.h"
27 #include "util/u_hash.h"
28 #include "util/u_math.h"
29 #include "util/u_memory.h"
30 #include "util/ralloc.h"
31 #include "util/hash_table.h"
32 #include "tgsi/tgsi_dump.h"
33 #include "tgsi/tgsi_info.h"
34 #include "tgsi/tgsi_lowering.h"
35 #include "tgsi/tgsi_parse.h"
36 #include "nir/tgsi_to_nir.h"
37
38 #include "vc4_context.h"
39 #include "vc4_qpu.h"
40 #include "vc4_qir.h"
41 #ifdef USE_VC4_SIMULATOR
42 #include "simpenrose/simpenrose.h"
43 #endif
44
45 static struct qreg
46 ntq_get_src(struct vc4_compile *c, nir_src src, int i);
47
48 static void
49 resize_qreg_array(struct vc4_compile *c,
50 struct qreg **regs,
51 uint32_t *size,
52 uint32_t decl_size)
53 {
54 if (*size >= decl_size)
55 return;
56
57 uint32_t old_size = *size;
58 *size = MAX2(*size * 2, decl_size);
59 *regs = reralloc(c, *regs, struct qreg, *size);
60 if (!*regs) {
61 fprintf(stderr, "Malloc failure\n");
62 abort();
63 }
64
65 for (uint32_t i = old_size; i < *size; i++)
66 (*regs)[i] = c->undef;
67 }
68
69 static struct qreg
70 indirect_uniform_load(struct vc4_compile *c, nir_intrinsic_instr *intr)
71 {
72 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0);
73 uint32_t offset = intr->const_index[0];
74 struct vc4_compiler_ubo_range *range = NULL;
75 unsigned i;
76 for (i = 0; i < c->num_uniform_ranges; i++) {
77 range = &c->ubo_ranges[i];
78 if (offset >= range->src_offset &&
79 offset < range->src_offset + range->size) {
80 break;
81 }
82 }
83 /* The driver-location-based offset always has to be within a declared
84 * uniform range.
85 */
86 assert(range);
87 if (!range->used) {
88 range->used = true;
89 range->dst_offset = c->next_ubo_dst_offset;
90 c->next_ubo_dst_offset += range->size;
91 c->num_ubo_ranges++;
92 };
93
94 offset -= range->src_offset;
95
96 /* Adjust for where we stored the TGSI register base. */
97 indirect_offset = qir_ADD(c, indirect_offset,
98 qir_uniform_ui(c, (range->dst_offset +
99 offset)));
100
101 /* Clamp to [0, array size). Note that MIN/MAX are signed. */
102 indirect_offset = qir_MAX(c, indirect_offset, qir_uniform_ui(c, 0));
103 indirect_offset = qir_MIN(c, indirect_offset,
104 qir_uniform_ui(c, (range->dst_offset +
105 range->size - 4)));
106
107 qir_TEX_DIRECT(c, indirect_offset, qir_uniform(c, QUNIFORM_UBO_ADDR, 0));
108 c->num_texture_samples++;
109 return qir_TEX_RESULT(c);
110 }
111
112 static struct qreg *
113 ntq_get_dest(struct vc4_compile *c, nir_dest dest)
114 {
115 assert(!dest.is_ssa);
116 nir_register *reg = dest.reg.reg;
117 struct hash_entry *entry = _mesa_hash_table_search(c->def_ht, reg);
118 assert(reg->num_array_elems == 0);
119 assert(dest.reg.base_offset == 0);
120
121 struct qreg *qregs = entry->data;
122 return qregs;
123 }
124
125 static struct qreg
126 ntq_get_src(struct vc4_compile *c, nir_src src, int i)
127 {
128 struct hash_entry *entry;
129 if (src.is_ssa) {
130 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
131 assert(i < src.ssa->num_components);
132 } else {
133 nir_register *reg = src.reg.reg;
134 entry = _mesa_hash_table_search(c->def_ht, reg);
135 assert(reg->num_array_elems == 0);
136 assert(src.reg.base_offset == 0);
137 assert(i < reg->num_components);
138 }
139
140 struct qreg *qregs = entry->data;
141 return qregs[i];
142 }
143
144 static struct qreg
145 ntq_get_alu_src(struct vc4_compile *c, nir_alu_instr *instr,
146 unsigned src)
147 {
148 assert(util_is_power_of_two(instr->dest.write_mask));
149 unsigned chan = ffs(instr->dest.write_mask) - 1;
150 struct qreg r = ntq_get_src(c, instr->src[src].src,
151 instr->src[src].swizzle[chan]);
152
153 assert(!instr->src[src].abs);
154 assert(!instr->src[src].negate);
155
156 return r;
157 };
158
159 static struct qreg
160 get_swizzled_channel(struct vc4_compile *c,
161 struct qreg *srcs, int swiz)
162 {
163 switch (swiz) {
164 default:
165 case UTIL_FORMAT_SWIZZLE_NONE:
166 fprintf(stderr, "warning: unknown swizzle\n");
167 /* FALLTHROUGH */
168 case UTIL_FORMAT_SWIZZLE_0:
169 return qir_uniform_f(c, 0.0);
170 case UTIL_FORMAT_SWIZZLE_1:
171 return qir_uniform_f(c, 1.0);
172 case UTIL_FORMAT_SWIZZLE_X:
173 case UTIL_FORMAT_SWIZZLE_Y:
174 case UTIL_FORMAT_SWIZZLE_Z:
175 case UTIL_FORMAT_SWIZZLE_W:
176 return srcs[swiz];
177 }
178 }
179
180 static inline struct qreg
181 qir_SAT(struct vc4_compile *c, struct qreg val)
182 {
183 return qir_FMAX(c,
184 qir_FMIN(c, val, qir_uniform_f(c, 1.0)),
185 qir_uniform_f(c, 0.0));
186 }
187
188 static struct qreg
189 ntq_rcp(struct vc4_compile *c, struct qreg x)
190 {
191 struct qreg r = qir_RCP(c, x);
192
193 /* Apply a Newton-Raphson step to improve the accuracy. */
194 r = qir_FMUL(c, r, qir_FSUB(c,
195 qir_uniform_f(c, 2.0),
196 qir_FMUL(c, x, r)));
197
198 return r;
199 }
200
201 static struct qreg
202 ntq_rsq(struct vc4_compile *c, struct qreg x)
203 {
204 struct qreg r = qir_RSQ(c, x);
205
206 /* Apply a Newton-Raphson step to improve the accuracy. */
207 r = qir_FMUL(c, r, qir_FSUB(c,
208 qir_uniform_f(c, 1.5),
209 qir_FMUL(c,
210 qir_uniform_f(c, 0.5),
211 qir_FMUL(c, x,
212 qir_FMUL(c, r, r)))));
213
214 return r;
215 }
216
217 static struct qreg
218 qir_srgb_decode(struct vc4_compile *c, struct qreg srgb)
219 {
220 struct qreg low = qir_FMUL(c, srgb, qir_uniform_f(c, 1.0 / 12.92));
221 struct qreg high = qir_POW(c,
222 qir_FMUL(c,
223 qir_FADD(c,
224 srgb,
225 qir_uniform_f(c, 0.055)),
226 qir_uniform_f(c, 1.0 / 1.055)),
227 qir_uniform_f(c, 2.4));
228
229 qir_SF(c, qir_FSUB(c, srgb, qir_uniform_f(c, 0.04045)));
230 return qir_SEL_X_Y_NS(c, low, high);
231 }
232
233 static struct qreg
234 qir_srgb_encode(struct vc4_compile *c, struct qreg linear)
235 {
236 struct qreg low = qir_FMUL(c, linear, qir_uniform_f(c, 12.92));
237 struct qreg high = qir_FSUB(c,
238 qir_FMUL(c,
239 qir_uniform_f(c, 1.055),
240 qir_POW(c,
241 linear,
242 qir_uniform_f(c, 0.41666))),
243 qir_uniform_f(c, 0.055));
244
245 qir_SF(c, qir_FSUB(c, linear, qir_uniform_f(c, 0.0031308)));
246 return qir_SEL_X_Y_NS(c, low, high);
247 }
248
249 static struct qreg
250 ntq_umul(struct vc4_compile *c, struct qreg src0, struct qreg src1)
251 {
252 struct qreg src0_hi = qir_SHR(c, src0,
253 qir_uniform_ui(c, 24));
254 struct qreg src1_hi = qir_SHR(c, src1,
255 qir_uniform_ui(c, 24));
256
257 struct qreg hilo = qir_MUL24(c, src0_hi, src1);
258 struct qreg lohi = qir_MUL24(c, src0, src1_hi);
259 struct qreg lolo = qir_MUL24(c, src0, src1);
260
261 return qir_ADD(c, lolo, qir_SHL(c,
262 qir_ADD(c, hilo, lohi),
263 qir_uniform_ui(c, 24)));
264 }
265
266 static void
267 ntq_emit_tex(struct vc4_compile *c, nir_tex_instr *instr)
268 {
269 struct qreg s, t, r, lod, proj, compare;
270 bool is_txb = false, is_txl = false, has_proj = false;
271 unsigned unit = instr->sampler_index;
272
273 for (unsigned i = 0; i < instr->num_srcs; i++) {
274 switch (instr->src[i].src_type) {
275 case nir_tex_src_coord:
276 s = ntq_get_src(c, instr->src[i].src, 0);
277 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D)
278 t = qir_uniform_f(c, 0.5);
279 else
280 t = ntq_get_src(c, instr->src[i].src, 1);
281 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
282 r = ntq_get_src(c, instr->src[i].src, 2);
283 break;
284 case nir_tex_src_bias:
285 lod = ntq_get_src(c, instr->src[i].src, 0);
286 is_txb = true;
287 break;
288 case nir_tex_src_lod:
289 lod = ntq_get_src(c, instr->src[i].src, 0);
290 is_txl = true;
291 break;
292 case nir_tex_src_comparitor:
293 compare = ntq_get_src(c, instr->src[i].src, 0);
294 break;
295 case nir_tex_src_projector:
296 proj = qir_RCP(c, ntq_get_src(c, instr->src[i].src, 0));
297 s = qir_FMUL(c, s, proj);
298 t = qir_FMUL(c, t, proj);
299 has_proj = true;
300 break;
301 default:
302 unreachable("unknown texture source");
303 }
304 }
305
306 struct qreg texture_u[] = {
307 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit),
308 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
309 qir_uniform(c, QUNIFORM_CONSTANT, 0),
310 qir_uniform(c, QUNIFORM_CONSTANT, 0),
311 };
312 uint32_t next_texture_u = 0;
313
314 /* There is no native support for GL texture rectangle coordinates, so
315 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
316 * 1]).
317 */
318 if (instr->sampler_dim == GLSL_SAMPLER_DIM_RECT) {
319 s = qir_FMUL(c, s,
320 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_X, unit));
321 t = qir_FMUL(c, t,
322 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_Y, unit));
323 }
324
325 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE || is_txl) {
326 texture_u[2] = qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P2,
327 unit | (is_txl << 16));
328 }
329
330 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
331 struct qreg ma = qir_FMAXABS(c, qir_FMAXABS(c, s, t), r);
332 struct qreg rcp_ma = qir_RCP(c, ma);
333 s = qir_FMUL(c, s, rcp_ma);
334 t = qir_FMUL(c, t, rcp_ma);
335 r = qir_FMUL(c, r, rcp_ma);
336
337 qir_TEX_R(c, r, texture_u[next_texture_u++]);
338 } else if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
339 c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP ||
340 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
341 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
342 qir_TEX_R(c, qir_uniform(c, QUNIFORM_TEXTURE_BORDER_COLOR, unit),
343 texture_u[next_texture_u++]);
344 }
345
346 if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP) {
347 s = qir_SAT(c, s);
348 }
349
350 if (c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
351 t = qir_SAT(c, t);
352 }
353
354 qir_TEX_T(c, t, texture_u[next_texture_u++]);
355
356 if (is_txl || is_txb)
357 qir_TEX_B(c, lod, texture_u[next_texture_u++]);
358
359 qir_TEX_S(c, s, texture_u[next_texture_u++]);
360
361 c->num_texture_samples++;
362 struct qreg tex = qir_TEX_RESULT(c);
363
364 enum pipe_format format = c->key->tex[unit].format;
365
366 struct qreg unpacked[4];
367 if (util_format_is_depth_or_stencil(format)) {
368 struct qreg depthf = qir_ITOF(c, qir_SHR(c, tex,
369 qir_uniform_ui(c, 8)));
370 struct qreg normalized = qir_FMUL(c, depthf,
371 qir_uniform_f(c, 1.0f/0xffffff));
372
373 struct qreg depth_output;
374
375 struct qreg one = qir_uniform_f(c, 1.0f);
376 if (c->key->tex[unit].compare_mode) {
377 if (has_proj)
378 compare = qir_FMUL(c, compare, proj);
379
380 switch (c->key->tex[unit].compare_func) {
381 case PIPE_FUNC_NEVER:
382 depth_output = qir_uniform_f(c, 0.0f);
383 break;
384 case PIPE_FUNC_ALWAYS:
385 depth_output = one;
386 break;
387 case PIPE_FUNC_EQUAL:
388 qir_SF(c, qir_FSUB(c, compare, normalized));
389 depth_output = qir_SEL_X_0_ZS(c, one);
390 break;
391 case PIPE_FUNC_NOTEQUAL:
392 qir_SF(c, qir_FSUB(c, compare, normalized));
393 depth_output = qir_SEL_X_0_ZC(c, one);
394 break;
395 case PIPE_FUNC_GREATER:
396 qir_SF(c, qir_FSUB(c, compare, normalized));
397 depth_output = qir_SEL_X_0_NC(c, one);
398 break;
399 case PIPE_FUNC_GEQUAL:
400 qir_SF(c, qir_FSUB(c, normalized, compare));
401 depth_output = qir_SEL_X_0_NS(c, one);
402 break;
403 case PIPE_FUNC_LESS:
404 qir_SF(c, qir_FSUB(c, compare, normalized));
405 depth_output = qir_SEL_X_0_NS(c, one);
406 break;
407 case PIPE_FUNC_LEQUAL:
408 qir_SF(c, qir_FSUB(c, normalized, compare));
409 depth_output = qir_SEL_X_0_NC(c, one);
410 break;
411 }
412 } else {
413 depth_output = normalized;
414 }
415
416 for (int i = 0; i < 4; i++)
417 unpacked[i] = depth_output;
418 } else {
419 for (int i = 0; i < 4; i++)
420 unpacked[i] = qir_UNPACK_8_F(c, tex, i);
421 }
422
423 const uint8_t *format_swiz = vc4_get_format_swizzle(format);
424 struct qreg texture_output[4];
425 for (int i = 0; i < 4; i++) {
426 texture_output[i] = get_swizzled_channel(c, unpacked,
427 format_swiz[i]);
428 }
429
430 if (util_format_is_srgb(format)) {
431 for (int i = 0; i < 3; i++)
432 texture_output[i] = qir_srgb_decode(c,
433 texture_output[i]);
434 }
435
436 struct qreg *dest = ntq_get_dest(c, instr->dest);
437 for (int i = 0; i < 4; i++) {
438 dest[i] = get_swizzled_channel(c, texture_output,
439 c->key->tex[unit].swizzle[i]);
440 }
441 }
442
443 /**
444 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
445 * to zero).
446 */
447 static struct qreg
448 ntq_ffract(struct vc4_compile *c, struct qreg src)
449 {
450 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
451 struct qreg diff = qir_FSUB(c, src, trunc);
452 qir_SF(c, diff);
453 return qir_SEL_X_Y_NS(c,
454 qir_FADD(c, diff, qir_uniform_f(c, 1.0)),
455 diff);
456 }
457
458 /**
459 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
460 * zero).
461 */
462 static struct qreg
463 ntq_ffloor(struct vc4_compile *c, struct qreg src)
464 {
465 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
466
467 /* This will be < 0 if we truncated and the truncation was of a value
468 * that was < 0 in the first place.
469 */
470 qir_SF(c, qir_FSUB(c, src, trunc));
471
472 return qir_SEL_X_Y_NS(c,
473 qir_FSUB(c, trunc, qir_uniform_f(c, 1.0)),
474 trunc);
475 }
476
477 /**
478 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
479 * zero).
480 */
481 static struct qreg
482 ntq_fceil(struct vc4_compile *c, struct qreg src)
483 {
484 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
485
486 /* This will be < 0 if we truncated and the truncation was of a value
487 * that was > 0 in the first place.
488 */
489 qir_SF(c, qir_FSUB(c, trunc, src));
490
491 return qir_SEL_X_Y_NS(c,
492 qir_FADD(c, trunc, qir_uniform_f(c, 1.0)),
493 trunc);
494 }
495
496 static struct qreg
497 ntq_fsin(struct vc4_compile *c, struct qreg src)
498 {
499 float coeff[] = {
500 -2.0 * M_PI,
501 pow(2.0 * M_PI, 3) / (3 * 2 * 1),
502 -pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
503 pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
504 -pow(2.0 * M_PI, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
505 };
506
507 struct qreg scaled_x =
508 qir_FMUL(c,
509 src,
510 qir_uniform_f(c, 1.0 / (M_PI * 2.0)));
511
512 struct qreg x = qir_FADD(c,
513 ntq_ffract(c, scaled_x),
514 qir_uniform_f(c, -0.5));
515 struct qreg x2 = qir_FMUL(c, x, x);
516 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
517 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
518 x = qir_FMUL(c, x, x2);
519 sum = qir_FADD(c,
520 sum,
521 qir_FMUL(c,
522 x,
523 qir_uniform_f(c, coeff[i])));
524 }
525 return sum;
526 }
527
528 static struct qreg
529 ntq_fcos(struct vc4_compile *c, struct qreg src)
530 {
531 float coeff[] = {
532 -1.0f,
533 pow(2.0 * M_PI, 2) / (2 * 1),
534 -pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
535 pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
536 -pow(2.0 * M_PI, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
537 pow(2.0 * M_PI, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
538 };
539
540 struct qreg scaled_x =
541 qir_FMUL(c, src,
542 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
543 struct qreg x_frac = qir_FADD(c,
544 ntq_ffract(c, scaled_x),
545 qir_uniform_f(c, -0.5));
546
547 struct qreg sum = qir_uniform_f(c, coeff[0]);
548 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
549 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
550 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
551 if (i != 1)
552 x = qir_FMUL(c, x, x2);
553
554 struct qreg mul = qir_FMUL(c,
555 x,
556 qir_uniform_f(c, coeff[i]));
557 if (i == 0)
558 sum = mul;
559 else
560 sum = qir_FADD(c, sum, mul);
561 }
562 return sum;
563 }
564
565 static struct qreg
566 ntq_fsign(struct vc4_compile *c, struct qreg src)
567 {
568 qir_SF(c, src);
569 return qir_SEL_X_Y_NC(c,
570 qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0)),
571 qir_uniform_f(c, -1.0));
572 }
573
574 static struct qreg
575 get_channel_from_vpm(struct vc4_compile *c,
576 struct qreg *vpm_reads,
577 uint8_t swiz,
578 const struct util_format_description *desc)
579 {
580 const struct util_format_channel_description *chan =
581 &desc->channel[swiz];
582 struct qreg temp;
583
584 if (swiz > UTIL_FORMAT_SWIZZLE_W)
585 return get_swizzled_channel(c, vpm_reads, swiz);
586 else if (chan->size == 32 &&
587 chan->type == UTIL_FORMAT_TYPE_FLOAT) {
588 return get_swizzled_channel(c, vpm_reads, swiz);
589 } else if (chan->size == 32 &&
590 chan->type == UTIL_FORMAT_TYPE_SIGNED) {
591 if (chan->normalized) {
592 return qir_FMUL(c,
593 qir_ITOF(c, vpm_reads[swiz]),
594 qir_uniform_f(c,
595 1.0 / 0x7fffffff));
596 } else {
597 return qir_ITOF(c, vpm_reads[swiz]);
598 }
599 } else if (chan->size == 8 &&
600 (chan->type == UTIL_FORMAT_TYPE_UNSIGNED ||
601 chan->type == UTIL_FORMAT_TYPE_SIGNED)) {
602 struct qreg vpm = vpm_reads[0];
603 if (chan->type == UTIL_FORMAT_TYPE_SIGNED) {
604 temp = qir_XOR(c, vpm, qir_uniform_ui(c, 0x80808080));
605 if (chan->normalized) {
606 return qir_FSUB(c, qir_FMUL(c,
607 qir_UNPACK_8_F(c, temp, swiz),
608 qir_uniform_f(c, 2.0)),
609 qir_uniform_f(c, 1.0));
610 } else {
611 return qir_FADD(c,
612 qir_ITOF(c,
613 qir_UNPACK_8_I(c, temp,
614 swiz)),
615 qir_uniform_f(c, -128.0));
616 }
617 } else {
618 if (chan->normalized) {
619 return qir_UNPACK_8_F(c, vpm, swiz);
620 } else {
621 return qir_ITOF(c, qir_UNPACK_8_I(c, vpm, swiz));
622 }
623 }
624 } else if (chan->size == 16 &&
625 (chan->type == UTIL_FORMAT_TYPE_UNSIGNED ||
626 chan->type == UTIL_FORMAT_TYPE_SIGNED)) {
627 struct qreg vpm = vpm_reads[swiz / 2];
628
629 /* Note that UNPACK_16F eats a half float, not ints, so we use
630 * UNPACK_16_I for all of these.
631 */
632 if (chan->type == UTIL_FORMAT_TYPE_SIGNED) {
633 temp = qir_ITOF(c, qir_UNPACK_16_I(c, vpm, swiz % 2));
634 if (chan->normalized) {
635 return qir_FMUL(c, temp,
636 qir_uniform_f(c, 1/32768.0f));
637 } else {
638 return temp;
639 }
640 } else {
641 /* UNPACK_16I sign-extends, so we have to emit ANDs. */
642 temp = vpm;
643 if (swiz == 1 || swiz == 3)
644 temp = qir_UNPACK_16_I(c, temp, 1);
645 temp = qir_AND(c, temp, qir_uniform_ui(c, 0xffff));
646 temp = qir_ITOF(c, temp);
647
648 if (chan->normalized) {
649 return qir_FMUL(c, temp,
650 qir_uniform_f(c, 1 / 65535.0));
651 } else {
652 return temp;
653 }
654 }
655 } else {
656 return c->undef;
657 }
658 }
659
660 static void
661 emit_vertex_input(struct vc4_compile *c, int attr)
662 {
663 enum pipe_format format = c->vs_key->attr_formats[attr];
664 uint32_t attr_size = util_format_get_blocksize(format);
665 struct qreg vpm_reads[4];
666
667 c->vattr_sizes[attr] = align(attr_size, 4);
668 for (int i = 0; i < align(attr_size, 4) / 4; i++) {
669 struct qreg vpm = { QFILE_VPM, attr * 4 + i };
670 vpm_reads[i] = qir_MOV(c, vpm);
671 c->num_inputs++;
672 }
673
674 bool format_warned = false;
675 const struct util_format_description *desc =
676 util_format_description(format);
677
678 for (int i = 0; i < 4; i++) {
679 uint8_t swiz = desc->swizzle[i];
680 struct qreg result = get_channel_from_vpm(c, vpm_reads,
681 swiz, desc);
682
683 if (result.file == QFILE_NULL) {
684 if (!format_warned) {
685 fprintf(stderr,
686 "vtx element %d unsupported type: %s\n",
687 attr, util_format_name(format));
688 format_warned = true;
689 }
690 result = qir_uniform_f(c, 0.0);
691 }
692 c->inputs[attr * 4 + i] = result;
693 }
694 }
695
696 static void
697 emit_fragcoord_input(struct vc4_compile *c, int attr)
698 {
699 c->inputs[attr * 4 + 0] = qir_FRAG_X(c);
700 c->inputs[attr * 4 + 1] = qir_FRAG_Y(c);
701 c->inputs[attr * 4 + 2] =
702 qir_FMUL(c,
703 qir_ITOF(c, qir_FRAG_Z(c)),
704 qir_uniform_f(c, 1.0 / 0xffffff));
705 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
706 }
707
708 static struct qreg
709 emit_fragment_varying(struct vc4_compile *c, uint8_t semantic,
710 uint8_t index, uint8_t swizzle)
711 {
712 uint32_t i = c->num_input_semantics++;
713 struct qreg vary = {
714 QFILE_VARY,
715 i
716 };
717
718 if (c->num_input_semantics >= c->input_semantics_array_size) {
719 c->input_semantics_array_size =
720 MAX2(4, c->input_semantics_array_size * 2);
721
722 c->input_semantics = reralloc(c, c->input_semantics,
723 struct vc4_varying_semantic,
724 c->input_semantics_array_size);
725 }
726
727 c->input_semantics[i].semantic = semantic;
728 c->input_semantics[i].index = index;
729 c->input_semantics[i].swizzle = swizzle;
730
731 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
732 }
733
734 static void
735 emit_fragment_input(struct vc4_compile *c, int attr,
736 unsigned semantic_name, unsigned semantic_index)
737 {
738 for (int i = 0; i < 4; i++) {
739 c->inputs[attr * 4 + i] =
740 emit_fragment_varying(c,
741 semantic_name,
742 semantic_index,
743 i);
744 c->num_inputs++;
745 }
746 }
747
748 static void
749 add_output(struct vc4_compile *c,
750 uint32_t decl_offset,
751 uint8_t semantic_name,
752 uint8_t semantic_index,
753 uint8_t semantic_swizzle)
754 {
755 uint32_t old_array_size = c->outputs_array_size;
756 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
757 decl_offset + 1);
758
759 if (old_array_size != c->outputs_array_size) {
760 c->output_semantics = reralloc(c,
761 c->output_semantics,
762 struct vc4_varying_semantic,
763 c->outputs_array_size);
764 }
765
766 c->output_semantics[decl_offset].semantic = semantic_name;
767 c->output_semantics[decl_offset].index = semantic_index;
768 c->output_semantics[decl_offset].swizzle = semantic_swizzle;
769 }
770
771 static void
772 declare_uniform_range(struct vc4_compile *c, uint32_t start, uint32_t size)
773 {
774 unsigned array_id = c->num_uniform_ranges++;
775 if (array_id >= c->ubo_ranges_array_size) {
776 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
777 array_id + 1);
778 c->ubo_ranges = reralloc(c, c->ubo_ranges,
779 struct vc4_compiler_ubo_range,
780 c->ubo_ranges_array_size);
781 }
782
783 c->ubo_ranges[array_id].dst_offset = 0;
784 c->ubo_ranges[array_id].src_offset = start;
785 c->ubo_ranges[array_id].size = size;
786 c->ubo_ranges[array_id].used = false;
787 }
788
789 static void
790 ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr)
791 {
792 /* Vectors are special in that they have non-scalarized writemasks,
793 * and just take the first swizzle channel for each argument in order
794 * into each writemask channel.
795 */
796 if (instr->op == nir_op_vec2 ||
797 instr->op == nir_op_vec3 ||
798 instr->op == nir_op_vec4) {
799 struct qreg srcs[4];
800 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
801 srcs[i] = ntq_get_src(c, instr->src[i].src,
802 instr->src[i].swizzle[0]);
803 struct qreg *dest = ntq_get_dest(c, instr->dest.dest);
804 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
805 dest[i] = srcs[i];
806 return;
807 }
808
809 /* General case: We can just grab the one used channel per src. */
810 struct qreg src[nir_op_infos[instr->op].num_inputs];
811 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
812 src[i] = ntq_get_alu_src(c, instr, i);
813 }
814
815 /* Pick the channel to store the output in. */
816 assert(!instr->dest.saturate);
817 struct qreg *dest = ntq_get_dest(c, instr->dest.dest);
818 assert(util_is_power_of_two(instr->dest.write_mask));
819 dest += ffs(instr->dest.write_mask) - 1;
820
821 switch (instr->op) {
822 case nir_op_fmov:
823 case nir_op_imov:
824 *dest = qir_MOV(c, src[0]);
825 break;
826 case nir_op_fmul:
827 *dest = qir_FMUL(c, src[0], src[1]);
828 break;
829 case nir_op_fadd:
830 *dest = qir_FADD(c, src[0], src[1]);
831 break;
832 case nir_op_fsub:
833 *dest = qir_FSUB(c, src[0], src[1]);
834 break;
835 case nir_op_fmin:
836 *dest = qir_FMIN(c, src[0], src[1]);
837 break;
838 case nir_op_fmax:
839 *dest = qir_FMAX(c, src[0], src[1]);
840 break;
841
842 case nir_op_f2i:
843 case nir_op_f2u:
844 *dest = qir_FTOI(c, src[0]);
845 break;
846 case nir_op_i2f:
847 case nir_op_u2f:
848 *dest = qir_ITOF(c, src[0]);
849 break;
850 case nir_op_b2f:
851 *dest = qir_AND(c, src[0], qir_uniform_f(c, 1.0));
852 break;
853 case nir_op_b2i:
854 *dest = qir_AND(c, src[0], qir_uniform_ui(c, 1));
855 break;
856 case nir_op_i2b:
857 case nir_op_f2b:
858 qir_SF(c, src[0]);
859 *dest = qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
860 break;
861
862 case nir_op_iadd:
863 *dest = qir_ADD(c, src[0], src[1]);
864 break;
865 case nir_op_ushr:
866 *dest = qir_SHR(c, src[0], src[1]);
867 break;
868 case nir_op_isub:
869 *dest = qir_SUB(c, src[0], src[1]);
870 break;
871 case nir_op_ishr:
872 *dest = qir_ASR(c, src[0], src[1]);
873 break;
874 case nir_op_ishl:
875 *dest = qir_SHL(c, src[0], src[1]);
876 break;
877 case nir_op_imin:
878 *dest = qir_MIN(c, src[0], src[1]);
879 break;
880 case nir_op_imax:
881 *dest = qir_MAX(c, src[0], src[1]);
882 break;
883 case nir_op_iand:
884 *dest = qir_AND(c, src[0], src[1]);
885 break;
886 case nir_op_ior:
887 *dest = qir_OR(c, src[0], src[1]);
888 break;
889 case nir_op_ixor:
890 *dest = qir_XOR(c, src[0], src[1]);
891 break;
892 case nir_op_inot:
893 *dest = qir_NOT(c, src[0]);
894 break;
895
896 case nir_op_imul:
897 *dest = ntq_umul(c, src[0], src[1]);
898 break;
899
900 case nir_op_seq:
901 qir_SF(c, qir_FSUB(c, src[0], src[1]));
902 *dest = qir_SEL_X_0_ZS(c, qir_uniform_f(c, 1.0));
903 break;
904 case nir_op_sne:
905 qir_SF(c, qir_FSUB(c, src[0], src[1]));
906 *dest = qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0));
907 break;
908 case nir_op_sge:
909 qir_SF(c, qir_FSUB(c, src[0], src[1]));
910 *dest = qir_SEL_X_0_NC(c, qir_uniform_f(c, 1.0));
911 break;
912 case nir_op_slt:
913 qir_SF(c, qir_FSUB(c, src[0], src[1]));
914 *dest = qir_SEL_X_0_NS(c, qir_uniform_f(c, 1.0));
915 break;
916 case nir_op_feq:
917 qir_SF(c, qir_FSUB(c, src[0], src[1]));
918 *dest = qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
919 break;
920 case nir_op_fne:
921 qir_SF(c, qir_FSUB(c, src[0], src[1]));
922 *dest = qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
923 break;
924 case nir_op_fge:
925 qir_SF(c, qir_FSUB(c, src[0], src[1]));
926 *dest = qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
927 break;
928 case nir_op_flt:
929 qir_SF(c, qir_FSUB(c, src[0], src[1]));
930 *dest = qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
931 break;
932 case nir_op_ieq:
933 qir_SF(c, qir_SUB(c, src[0], src[1]));
934 *dest = qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
935 break;
936 case nir_op_ine:
937 qir_SF(c, qir_SUB(c, src[0], src[1]));
938 *dest = qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
939 break;
940 case nir_op_ige:
941 qir_SF(c, qir_SUB(c, src[0], src[1]));
942 *dest = qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
943 break;
944 case nir_op_ilt:
945 qir_SF(c, qir_SUB(c, src[0], src[1]));
946 *dest = qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
947 break;
948
949 case nir_op_bcsel:
950 qir_SF(c, src[0]);
951 *dest = qir_SEL_X_Y_NS(c, src[1], src[2]);
952 break;
953 case nir_op_fcsel:
954 qir_SF(c, src[0]);
955 *dest = qir_SEL_X_Y_ZC(c, src[1], src[2]);
956 break;
957
958 case nir_op_frcp:
959 *dest = ntq_rcp(c, src[0]);
960 break;
961 case nir_op_frsq:
962 *dest = ntq_rsq(c, src[0]);
963 break;
964 case nir_op_fexp2:
965 *dest = qir_EXP2(c, src[0]);
966 break;
967 case nir_op_flog2:
968 *dest = qir_LOG2(c, src[0]);
969 break;
970
971 case nir_op_ftrunc:
972 *dest = qir_ITOF(c, qir_FTOI(c, src[0]));
973 break;
974 case nir_op_fceil:
975 *dest = ntq_fceil(c, src[0]);
976 break;
977 case nir_op_ffract:
978 *dest = ntq_ffract(c, src[0]);
979 break;
980 case nir_op_ffloor:
981 *dest = ntq_ffloor(c, src[0]);
982 break;
983
984 case nir_op_fsin:
985 *dest = ntq_fsin(c, src[0]);
986 break;
987 case nir_op_fcos:
988 *dest = ntq_fcos(c, src[0]);
989 break;
990
991 case nir_op_fsign:
992 *dest = ntq_fsign(c, src[0]);
993 break;
994
995 case nir_op_fabs:
996 *dest = qir_FMAXABS(c, src[0], src[0]);
997 break;
998 case nir_op_iabs:
999 *dest = qir_MAX(c, src[0],
1000 qir_SUB(c, qir_uniform_ui(c, 0), src[0]));
1001 break;
1002
1003 default:
1004 fprintf(stderr, "unknown NIR ALU inst: ");
1005 nir_print_instr(&instr->instr, stderr);
1006 fprintf(stderr, "\n");
1007 abort();
1008 }
1009 }
1010
1011 static struct qreg
1012 vc4_blend_channel(struct vc4_compile *c,
1013 struct qreg *dst,
1014 struct qreg *src,
1015 struct qreg val,
1016 unsigned factor,
1017 int channel)
1018 {
1019 switch(factor) {
1020 case PIPE_BLENDFACTOR_ONE:
1021 return val;
1022 case PIPE_BLENDFACTOR_SRC_COLOR:
1023 return qir_FMUL(c, val, src[channel]);
1024 case PIPE_BLENDFACTOR_SRC_ALPHA:
1025 return qir_FMUL(c, val, src[3]);
1026 case PIPE_BLENDFACTOR_DST_ALPHA:
1027 return qir_FMUL(c, val, dst[3]);
1028 case PIPE_BLENDFACTOR_DST_COLOR:
1029 return qir_FMUL(c, val, dst[channel]);
1030 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
1031 if (channel != 3) {
1032 return qir_FMUL(c,
1033 val,
1034 qir_FMIN(c,
1035 src[3],
1036 qir_FSUB(c,
1037 qir_uniform_f(c, 1.0),
1038 dst[3])));
1039 } else {
1040 return val;
1041 }
1042 case PIPE_BLENDFACTOR_CONST_COLOR:
1043 return qir_FMUL(c, val,
1044 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR,
1045 channel));
1046 case PIPE_BLENDFACTOR_CONST_ALPHA:
1047 return qir_FMUL(c, val,
1048 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR, 3));
1049 case PIPE_BLENDFACTOR_ZERO:
1050 return qir_uniform_f(c, 0.0);
1051 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
1052 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1053 src[channel]));
1054 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
1055 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1056 src[3]));
1057 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
1058 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1059 dst[3]));
1060 case PIPE_BLENDFACTOR_INV_DST_COLOR:
1061 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1062 dst[channel]));
1063 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
1064 return qir_FMUL(c, val,
1065 qir_FSUB(c, qir_uniform_f(c, 1.0),
1066 qir_uniform(c,
1067 QUNIFORM_BLEND_CONST_COLOR,
1068 channel)));
1069 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
1070 return qir_FMUL(c, val,
1071 qir_FSUB(c, qir_uniform_f(c, 1.0),
1072 qir_uniform(c,
1073 QUNIFORM_BLEND_CONST_COLOR,
1074 3)));
1075
1076 default:
1077 case PIPE_BLENDFACTOR_SRC1_COLOR:
1078 case PIPE_BLENDFACTOR_SRC1_ALPHA:
1079 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
1080 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
1081 /* Unsupported. */
1082 fprintf(stderr, "Unknown blend factor %d\n", factor);
1083 return val;
1084 }
1085 }
1086
1087 static struct qreg
1088 vc4_blend_func(struct vc4_compile *c,
1089 struct qreg src, struct qreg dst,
1090 unsigned func)
1091 {
1092 switch (func) {
1093 case PIPE_BLEND_ADD:
1094 return qir_FADD(c, src, dst);
1095 case PIPE_BLEND_SUBTRACT:
1096 return qir_FSUB(c, src, dst);
1097 case PIPE_BLEND_REVERSE_SUBTRACT:
1098 return qir_FSUB(c, dst, src);
1099 case PIPE_BLEND_MIN:
1100 return qir_FMIN(c, src, dst);
1101 case PIPE_BLEND_MAX:
1102 return qir_FMAX(c, src, dst);
1103
1104 default:
1105 /* Unsupported. */
1106 fprintf(stderr, "Unknown blend func %d\n", func);
1107 return src;
1108
1109 }
1110 }
1111
1112 /**
1113 * Implements fixed function blending in shader code.
1114 *
1115 * VC4 doesn't have any hardware support for blending. Instead, you read the
1116 * current contents of the destination from the tile buffer after having
1117 * waited for the scoreboard (which is handled by vc4_qpu_emit.c), then do
1118 * math using your output color and that destination value, and update the
1119 * output color appropriately.
1120 */
1121 static void
1122 vc4_blend(struct vc4_compile *c, struct qreg *result,
1123 struct qreg *dst_color, struct qreg *src_color)
1124 {
1125 struct pipe_rt_blend_state *blend = &c->fs_key->blend;
1126
1127 if (!blend->blend_enable) {
1128 for (int i = 0; i < 4; i++)
1129 result[i] = src_color[i];
1130 return;
1131 }
1132
1133 for (int i = 0; i < 4; i++)
1134 src_color[i] = qir_SAT(c, src_color[i]);
1135
1136 struct qreg src_blend[4], dst_blend[4];
1137 for (int i = 0; i < 3; i++) {
1138 src_blend[i] = vc4_blend_channel(c,
1139 dst_color, src_color,
1140 src_color[i],
1141 blend->rgb_src_factor, i);
1142 dst_blend[i] = vc4_blend_channel(c,
1143 dst_color, src_color,
1144 dst_color[i],
1145 blend->rgb_dst_factor, i);
1146 }
1147 src_blend[3] = vc4_blend_channel(c,
1148 dst_color, src_color,
1149 src_color[3],
1150 blend->alpha_src_factor, 3);
1151 dst_blend[3] = vc4_blend_channel(c,
1152 dst_color, src_color,
1153 dst_color[3],
1154 blend->alpha_dst_factor, 3);
1155
1156 for (int i = 0; i < 3; i++) {
1157 result[i] = vc4_blend_func(c,
1158 src_blend[i], dst_blend[i],
1159 blend->rgb_func);
1160 }
1161 result[3] = vc4_blend_func(c,
1162 src_blend[3], dst_blend[3],
1163 blend->alpha_func);
1164 }
1165
1166 static void
1167 clip_distance_discard(struct vc4_compile *c)
1168 {
1169 for (int i = 0; i < PIPE_MAX_CLIP_PLANES; i++) {
1170 if (!(c->key->ucp_enables & (1 << i)))
1171 continue;
1172
1173 struct qreg dist = emit_fragment_varying(c,
1174 TGSI_SEMANTIC_CLIPDIST,
1175 i,
1176 TGSI_SWIZZLE_X);
1177
1178 qir_SF(c, dist);
1179
1180 if (c->discard.file == QFILE_NULL)
1181 c->discard = qir_uniform_ui(c, 0);
1182
1183 c->discard = qir_SEL_X_Y_NS(c, qir_uniform_ui(c, ~0),
1184 c->discard);
1185 }
1186 }
1187
1188 static void
1189 alpha_test_discard(struct vc4_compile *c)
1190 {
1191 struct qreg src_alpha;
1192 struct qreg alpha_ref = qir_uniform(c, QUNIFORM_ALPHA_REF, 0);
1193
1194 if (!c->fs_key->alpha_test)
1195 return;
1196
1197 if (c->output_color_index != -1)
1198 src_alpha = c->outputs[c->output_color_index + 3];
1199 else
1200 src_alpha = qir_uniform_f(c, 1.0);
1201
1202 if (c->discard.file == QFILE_NULL)
1203 c->discard = qir_uniform_ui(c, 0);
1204
1205 switch (c->fs_key->alpha_test_func) {
1206 case PIPE_FUNC_NEVER:
1207 c->discard = qir_uniform_ui(c, ~0);
1208 break;
1209 case PIPE_FUNC_ALWAYS:
1210 break;
1211 case PIPE_FUNC_EQUAL:
1212 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1213 c->discard = qir_SEL_X_Y_ZS(c, c->discard,
1214 qir_uniform_ui(c, ~0));
1215 break;
1216 case PIPE_FUNC_NOTEQUAL:
1217 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1218 c->discard = qir_SEL_X_Y_ZC(c, c->discard,
1219 qir_uniform_ui(c, ~0));
1220 break;
1221 case PIPE_FUNC_GREATER:
1222 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1223 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1224 qir_uniform_ui(c, ~0));
1225 break;
1226 case PIPE_FUNC_GEQUAL:
1227 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1228 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1229 qir_uniform_ui(c, ~0));
1230 break;
1231 case PIPE_FUNC_LESS:
1232 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1233 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1234 qir_uniform_ui(c, ~0));
1235 break;
1236 case PIPE_FUNC_LEQUAL:
1237 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1238 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1239 qir_uniform_ui(c, ~0));
1240 break;
1241 }
1242 }
1243
1244 static struct qreg
1245 vc4_logicop(struct vc4_compile *c, struct qreg src, struct qreg dst)
1246 {
1247 switch (c->fs_key->logicop_func) {
1248 case PIPE_LOGICOP_CLEAR:
1249 return qir_uniform_f(c, 0.0);
1250 case PIPE_LOGICOP_NOR:
1251 return qir_NOT(c, qir_OR(c, src, dst));
1252 case PIPE_LOGICOP_AND_INVERTED:
1253 return qir_AND(c, qir_NOT(c, src), dst);
1254 case PIPE_LOGICOP_COPY_INVERTED:
1255 return qir_NOT(c, src);
1256 case PIPE_LOGICOP_AND_REVERSE:
1257 return qir_AND(c, src, qir_NOT(c, dst));
1258 case PIPE_LOGICOP_INVERT:
1259 return qir_NOT(c, dst);
1260 case PIPE_LOGICOP_XOR:
1261 return qir_XOR(c, src, dst);
1262 case PIPE_LOGICOP_NAND:
1263 return qir_NOT(c, qir_AND(c, src, dst));
1264 case PIPE_LOGICOP_AND:
1265 return qir_AND(c, src, dst);
1266 case PIPE_LOGICOP_EQUIV:
1267 return qir_NOT(c, qir_XOR(c, src, dst));
1268 case PIPE_LOGICOP_NOOP:
1269 return dst;
1270 case PIPE_LOGICOP_OR_INVERTED:
1271 return qir_OR(c, qir_NOT(c, src), dst);
1272 case PIPE_LOGICOP_OR_REVERSE:
1273 return qir_OR(c, src, qir_NOT(c, dst));
1274 case PIPE_LOGICOP_OR:
1275 return qir_OR(c, src, dst);
1276 case PIPE_LOGICOP_SET:
1277 return qir_uniform_ui(c, ~0);
1278 case PIPE_LOGICOP_COPY:
1279 default:
1280 return src;
1281 }
1282 }
1283
1284 /**
1285 * Applies the GL blending pipeline and returns the packed (8888) output
1286 * color.
1287 */
1288 static struct qreg
1289 blend_pipeline(struct vc4_compile *c)
1290 {
1291 enum pipe_format color_format = c->fs_key->color_format;
1292 const uint8_t *format_swiz = vc4_get_format_swizzle(color_format);
1293 struct qreg tlb_read_color[4] = { c->undef, c->undef, c->undef, c->undef };
1294 struct qreg dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1295 struct qreg linear_dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1296 struct qreg packed_dst_color = c->undef;
1297
1298 if (c->fs_key->blend.blend_enable ||
1299 c->fs_key->blend.colormask != 0xf ||
1300 c->fs_key->logicop_func != PIPE_LOGICOP_COPY) {
1301 packed_dst_color = qir_TLB_COLOR_READ(c);
1302 for (int i = 0; i < 4; i++)
1303 tlb_read_color[i] = qir_UNPACK_8_F(c,
1304 packed_dst_color, i);
1305 for (int i = 0; i < 4; i++) {
1306 dst_color[i] = get_swizzled_channel(c,
1307 tlb_read_color,
1308 format_swiz[i]);
1309 if (util_format_is_srgb(color_format) && i != 3) {
1310 linear_dst_color[i] =
1311 qir_srgb_decode(c, dst_color[i]);
1312 } else {
1313 linear_dst_color[i] = dst_color[i];
1314 }
1315 }
1316 }
1317
1318 struct qreg undef_array[4] = { c->undef, c->undef, c->undef, c->undef };
1319 const struct qreg *output_colors = (c->output_color_index != -1 ?
1320 c->outputs + c->output_color_index :
1321 undef_array);
1322 struct qreg blend_src_color[4];
1323 for (int i = 0; i < 4; i++)
1324 blend_src_color[i] = output_colors[i];
1325
1326 struct qreg blend_color[4];
1327 vc4_blend(c, blend_color, linear_dst_color, blend_src_color);
1328
1329 if (util_format_is_srgb(color_format)) {
1330 for (int i = 0; i < 3; i++)
1331 blend_color[i] = qir_srgb_encode(c, blend_color[i]);
1332 }
1333
1334 /* Debug: Sometimes you're getting a black output and just want to see
1335 * if the FS is getting executed at all. Spam magenta into the color
1336 * output.
1337 */
1338 if (0) {
1339 blend_color[0] = qir_uniform_f(c, 1.0);
1340 blend_color[1] = qir_uniform_f(c, 0.0);
1341 blend_color[2] = qir_uniform_f(c, 1.0);
1342 blend_color[3] = qir_uniform_f(c, 0.5);
1343 }
1344
1345 struct qreg swizzled_outputs[4];
1346 for (int i = 0; i < 4; i++) {
1347 swizzled_outputs[i] = get_swizzled_channel(c, blend_color,
1348 format_swiz[i]);
1349 }
1350
1351 struct qreg packed_color = c->undef;
1352 for (int i = 0; i < 4; i++) {
1353 if (swizzled_outputs[i].file == QFILE_NULL)
1354 continue;
1355 if (packed_color.file == QFILE_NULL) {
1356 packed_color = qir_PACK_8888_F(c, swizzled_outputs[i]);
1357 } else {
1358 packed_color = qir_PACK_8_F(c,
1359 packed_color,
1360 swizzled_outputs[i],
1361 i);
1362 }
1363 }
1364
1365 if (packed_color.file == QFILE_NULL)
1366 packed_color = qir_uniform_ui(c, 0);
1367
1368 if (c->fs_key->logicop_func != PIPE_LOGICOP_COPY) {
1369 packed_color = vc4_logicop(c, packed_color, packed_dst_color);
1370 }
1371
1372 /* If the bit isn't set in the color mask, then just return the
1373 * original dst color, instead.
1374 */
1375 uint32_t colormask = 0xffffffff;
1376 for (int i = 0; i < 4; i++) {
1377 if (format_swiz[i] < 4 &&
1378 !(c->fs_key->blend.colormask & (1 << format_swiz[i]))) {
1379 colormask &= ~(0xff << (i * 8));
1380 }
1381 }
1382 if (colormask != 0xffffffff) {
1383 packed_color = qir_OR(c,
1384 qir_AND(c, packed_color,
1385 qir_uniform_ui(c, colormask)),
1386 qir_AND(c, packed_dst_color,
1387 qir_uniform_ui(c, ~colormask)));
1388 }
1389
1390 return packed_color;
1391 }
1392
1393 static void
1394 emit_frag_end(struct vc4_compile *c)
1395 {
1396 clip_distance_discard(c);
1397 alpha_test_discard(c);
1398 struct qreg color = blend_pipeline(c);
1399
1400 if (c->discard.file != QFILE_NULL)
1401 qir_TLB_DISCARD_SETUP(c, c->discard);
1402
1403 if (c->fs_key->stencil_enabled) {
1404 qir_TLB_STENCIL_SETUP(c, qir_uniform(c, QUNIFORM_STENCIL, 0));
1405 if (c->fs_key->stencil_twoside) {
1406 qir_TLB_STENCIL_SETUP(c, qir_uniform(c, QUNIFORM_STENCIL, 1));
1407 }
1408 if (c->fs_key->stencil_full_writemasks) {
1409 qir_TLB_STENCIL_SETUP(c, qir_uniform(c, QUNIFORM_STENCIL, 2));
1410 }
1411 }
1412
1413 if (c->fs_key->depth_enabled) {
1414 struct qreg z;
1415 if (c->output_position_index != -1) {
1416 z = qir_FTOI(c, qir_FMUL(c, c->outputs[c->output_position_index + 2],
1417 qir_uniform_f(c, 0xffffff)));
1418 } else {
1419 z = qir_FRAG_Z(c);
1420 }
1421 qir_TLB_Z_WRITE(c, z);
1422 }
1423
1424 qir_TLB_COLOR_WRITE(c, color);
1425 }
1426
1427 static void
1428 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1429 {
1430 struct qreg xyi[2];
1431
1432 for (int i = 0; i < 2; i++) {
1433 struct qreg scale =
1434 qir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1435
1436 xyi[i] = qir_FTOI(c, qir_FMUL(c,
1437 qir_FMUL(c,
1438 c->outputs[c->output_position_index + i],
1439 scale),
1440 rcp_w));
1441 }
1442
1443 qir_VPM_WRITE(c, qir_PACK_SCALED(c, xyi[0], xyi[1]));
1444 }
1445
1446 static void
1447 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1448 {
1449 struct qreg zscale = qir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1450 struct qreg zoffset = qir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1451
1452 qir_VPM_WRITE(c, qir_FADD(c, qir_FMUL(c, qir_FMUL(c,
1453 c->outputs[c->output_position_index + 2],
1454 zscale),
1455 rcp_w),
1456 zoffset));
1457 }
1458
1459 static void
1460 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1461 {
1462 qir_VPM_WRITE(c, rcp_w);
1463 }
1464
1465 static void
1466 emit_point_size_write(struct vc4_compile *c)
1467 {
1468 struct qreg point_size;
1469
1470 if (c->output_point_size_index != -1)
1471 point_size = c->outputs[c->output_point_size_index + 3];
1472 else
1473 point_size = qir_uniform_f(c, 1.0);
1474
1475 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1476 * BCM21553).
1477 */
1478 point_size = qir_FMAX(c, point_size, qir_uniform_f(c, .125));
1479
1480 qir_VPM_WRITE(c, point_size);
1481 }
1482
1483 /**
1484 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1485 *
1486 * The simulator insists that there be at least one vertex attribute, so
1487 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also
1488 * insists that all vertex attributes loaded get read by the VS/CS, so we have
1489 * to consume it here.
1490 */
1491 static void
1492 emit_stub_vpm_read(struct vc4_compile *c)
1493 {
1494 if (c->num_inputs)
1495 return;
1496
1497 c->vattr_sizes[0] = 4;
1498 struct qreg vpm = { QFILE_VPM, 0 };
1499 (void)qir_MOV(c, vpm);
1500 c->num_inputs++;
1501 }
1502
1503 static void
1504 emit_ucp_clipdistance(struct vc4_compile *c)
1505 {
1506 unsigned cv;
1507 if (c->output_clipvertex_index != -1)
1508 cv = c->output_clipvertex_index;
1509 else if (c->output_position_index != -1)
1510 cv = c->output_position_index;
1511 else
1512 return;
1513
1514 for (int plane = 0; plane < PIPE_MAX_CLIP_PLANES; plane++) {
1515 if (!(c->key->ucp_enables & (1 << plane)))
1516 continue;
1517
1518 /* Pick the next outputs[] that hasn't been written to, since
1519 * there are no other program writes left to be processed at
1520 * this point. If something had been declared but not written
1521 * (like a w component), we'll just smash over the top of it.
1522 */
1523 uint32_t output_index = c->num_outputs++;
1524 add_output(c, output_index,
1525 TGSI_SEMANTIC_CLIPDIST,
1526 plane,
1527 TGSI_SWIZZLE_X);
1528
1529
1530 struct qreg dist = qir_uniform_f(c, 0.0);
1531 for (int i = 0; i < 4; i++) {
1532 struct qreg pos_chan = c->outputs[cv + i];
1533 struct qreg ucp =
1534 qir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1535 plane * 4 + i);
1536 dist = qir_FADD(c, dist, qir_FMUL(c, pos_chan, ucp));
1537 }
1538
1539 c->outputs[output_index] = dist;
1540 }
1541 }
1542
1543 static void
1544 emit_vert_end(struct vc4_compile *c,
1545 struct vc4_varying_semantic *fs_inputs,
1546 uint32_t num_fs_inputs)
1547 {
1548 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1549
1550 emit_stub_vpm_read(c);
1551 emit_ucp_clipdistance(c);
1552
1553 emit_scaled_viewport_write(c, rcp_w);
1554 emit_zs_write(c, rcp_w);
1555 emit_rcp_wc_write(c, rcp_w);
1556 if (c->vs_key->per_vertex_point_size)
1557 emit_point_size_write(c);
1558
1559 for (int i = 0; i < num_fs_inputs; i++) {
1560 struct vc4_varying_semantic *input = &fs_inputs[i];
1561 int j;
1562
1563 for (j = 0; j < c->num_outputs; j++) {
1564 struct vc4_varying_semantic *output =
1565 &c->output_semantics[j];
1566
1567 if (input->semantic == output->semantic &&
1568 input->index == output->index &&
1569 input->swizzle == output->swizzle) {
1570 qir_VPM_WRITE(c, c->outputs[j]);
1571 break;
1572 }
1573 }
1574 /* Emit padding if we didn't find a declared VS output for
1575 * this FS input.
1576 */
1577 if (j == c->num_outputs)
1578 qir_VPM_WRITE(c, qir_uniform_f(c, 0.0));
1579 }
1580 }
1581
1582 static void
1583 emit_coord_end(struct vc4_compile *c)
1584 {
1585 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1586
1587 emit_stub_vpm_read(c);
1588
1589 for (int i = 0; i < 4; i++)
1590 qir_VPM_WRITE(c, c->outputs[c->output_position_index + i]);
1591
1592 emit_scaled_viewport_write(c, rcp_w);
1593 emit_zs_write(c, rcp_w);
1594 emit_rcp_wc_write(c, rcp_w);
1595 if (c->vs_key->per_vertex_point_size)
1596 emit_point_size_write(c);
1597 }
1598
1599 static void
1600 vc4_optimize_nir(struct nir_shader *s)
1601 {
1602 bool progress;
1603
1604 do {
1605 progress = false;
1606
1607 nir_lower_vars_to_ssa(s);
1608 nir_lower_alu_to_scalar(s);
1609
1610 progress = nir_copy_prop(s) || progress;
1611 progress = nir_opt_dce(s) || progress;
1612 progress = nir_opt_cse(s) || progress;
1613 progress = nir_opt_peephole_select(s) || progress;
1614 progress = nir_opt_algebraic(s) || progress;
1615 progress = nir_opt_constant_folding(s) || progress;
1616 } while (progress);
1617 }
1618
1619 static int
1620 driver_location_compare(const void *in_a, const void *in_b)
1621 {
1622 const nir_variable *const *a = in_a;
1623 const nir_variable *const *b = in_b;
1624
1625 return (*a)->data.driver_location - (*b)->data.driver_location;
1626 }
1627
1628 static void
1629 ntq_setup_inputs(struct vc4_compile *c)
1630 {
1631 unsigned num_entries = 0;
1632 foreach_list_typed(nir_variable, var, node, &c->s->inputs)
1633 num_entries++;
1634
1635 nir_variable *vars[num_entries];
1636
1637 unsigned i = 0;
1638 foreach_list_typed(nir_variable, var, node, &c->s->inputs)
1639 vars[i++] = var;
1640
1641 /* Sort the variables so that we emit the input setup in
1642 * driver_location order. This is required for VPM reads, whose data
1643 * is fetched into the VPM in driver_location (TGSI register index)
1644 * order.
1645 */
1646 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1647
1648 for (unsigned i = 0; i < num_entries; i++) {
1649 nir_variable *var = vars[i];
1650 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1651 /* XXX: map loc slots to semantics */
1652 unsigned semantic_name = var->data.location;
1653 unsigned semantic_index = var->data.index;
1654 unsigned loc = var->data.driver_location;
1655
1656 assert(array_len == 1);
1657 (void)array_len;
1658 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1659 (loc + 1) * 4);
1660
1661 if (c->stage == QSTAGE_FRAG) {
1662 if (semantic_name == TGSI_SEMANTIC_POSITION) {
1663 emit_fragcoord_input(c, loc);
1664 } else if (semantic_name == TGSI_SEMANTIC_FACE) {
1665 c->inputs[loc * 4 + 0] = qir_FRAG_REV_FLAG(c);
1666 } else if (semantic_name == TGSI_SEMANTIC_GENERIC &&
1667 (c->fs_key->point_sprite_mask &
1668 (1 << semantic_index))) {
1669 c->inputs[loc * 4 + 0] = c->point_x;
1670 c->inputs[loc * 4 + 1] = c->point_y;
1671 } else {
1672 emit_fragment_input(c, loc,
1673 semantic_name,
1674 semantic_index);
1675 }
1676 } else {
1677 emit_vertex_input(c, loc);
1678 }
1679 }
1680 }
1681
1682 static void
1683 ntq_setup_outputs(struct vc4_compile *c)
1684 {
1685 foreach_list_typed(nir_variable, var, node, &c->s->outputs) {
1686 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1687 /* XXX: map loc slots to semantics */
1688 unsigned semantic_name = var->data.location;
1689 unsigned semantic_index = var->data.index;
1690 unsigned loc = var->data.driver_location * 4;
1691
1692 assert(array_len == 1);
1693 (void)array_len;
1694
1695 /* NIR hack to pass through
1696 * TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS */
1697 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1698 semantic_index == -1)
1699 semantic_index = 0;
1700
1701 for (int i = 0; i < 4; i++) {
1702 add_output(c,
1703 loc + i,
1704 semantic_name,
1705 semantic_index,
1706 i);
1707 }
1708
1709 switch (semantic_name) {
1710 case TGSI_SEMANTIC_POSITION:
1711 c->output_position_index = loc;
1712 break;
1713 case TGSI_SEMANTIC_CLIPVERTEX:
1714 c->output_clipvertex_index = loc;
1715 break;
1716 case TGSI_SEMANTIC_COLOR:
1717 c->output_color_index = loc;
1718 break;
1719 case TGSI_SEMANTIC_PSIZE:
1720 c->output_point_size_index = loc;
1721 break;
1722 }
1723
1724 }
1725 }
1726
1727 static void
1728 ntq_setup_uniforms(struct vc4_compile *c)
1729 {
1730 foreach_list_typed(nir_variable, var, node, &c->s->uniforms) {
1731 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1732 unsigned array_elem_size = 4 * sizeof(float);
1733
1734 declare_uniform_range(c, var->data.driver_location * array_elem_size,
1735 array_len * array_elem_size);
1736
1737 }
1738 }
1739
1740 /**
1741 * Sets up the mapping from nir_register to struct qreg *.
1742 *
1743 * Each nir_register gets a struct qreg per 32-bit component being stored.
1744 */
1745 static void
1746 ntq_setup_registers(struct vc4_compile *c, struct exec_list *list)
1747 {
1748 foreach_list_typed(nir_register, nir_reg, node, list) {
1749 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1750 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1751 array_len *
1752 nir_reg->num_components);
1753
1754 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1755
1756 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1757 qregs[i] = qir_uniform_ui(c, 0);
1758 }
1759 }
1760
1761 static void
1762 ntq_emit_load_const(struct vc4_compile *c, nir_load_const_instr *instr)
1763 {
1764 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1765 instr->def.num_components);
1766 for (int i = 0; i < instr->def.num_components; i++)
1767 qregs[i] = qir_uniform_ui(c, instr->value.u[i]);
1768
1769 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1770 }
1771
1772 static void
1773 ntq_emit_intrinsic(struct vc4_compile *c, nir_intrinsic_instr *instr)
1774 {
1775 const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
1776 struct qreg *dest = NULL;
1777
1778 if (info->has_dest) {
1779 dest = ntq_get_dest(c, instr->dest);
1780 }
1781
1782 switch (instr->intrinsic) {
1783 case nir_intrinsic_load_uniform:
1784 assert(instr->num_components == 1);
1785 *dest = qir_uniform(c, QUNIFORM_UNIFORM, instr->const_index[0]);
1786 break;
1787
1788 case nir_intrinsic_load_uniform_indirect:
1789 *dest = indirect_uniform_load(c, instr);
1790
1791 break;
1792
1793 case nir_intrinsic_load_input:
1794 assert(instr->num_components == 1);
1795 *dest = c->inputs[instr->const_index[0]];
1796
1797 break;
1798
1799 case nir_intrinsic_store_output:
1800 assert(instr->num_components == 1);
1801 c->outputs[instr->const_index[0]] =
1802 qir_MOV(c, ntq_get_src(c, instr->src[0], 0));
1803 c->num_outputs = MAX2(c->num_outputs, instr->const_index[0] + 1);
1804 break;
1805
1806 case nir_intrinsic_discard:
1807 c->discard = qir_uniform_ui(c, ~0);
1808 break;
1809
1810 case nir_intrinsic_discard_if:
1811 if (c->discard.file == QFILE_NULL)
1812 c->discard = qir_uniform_ui(c, 0);
1813 c->discard = qir_OR(c, c->discard,
1814 ntq_get_src(c, instr->src[0], 0));
1815 break;
1816
1817 default:
1818 fprintf(stderr, "Unknown intrinsic: ");
1819 nir_print_instr(&instr->instr, stderr);
1820 fprintf(stderr, "\n");
1821 break;
1822 }
1823 }
1824
1825 static void
1826 ntq_emit_if(struct vc4_compile *c, nir_if *if_stmt)
1827 {
1828 fprintf(stderr, "general IF statements not handled.\n");
1829 }
1830
1831 static void
1832 ntq_emit_instr(struct vc4_compile *c, nir_instr *instr)
1833 {
1834 switch (instr->type) {
1835 case nir_instr_type_alu:
1836 ntq_emit_alu(c, nir_instr_as_alu(instr));
1837 break;
1838
1839 case nir_instr_type_intrinsic:
1840 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
1841 break;
1842
1843 case nir_instr_type_load_const:
1844 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
1845 break;
1846
1847 case nir_instr_type_tex:
1848 ntq_emit_tex(c, nir_instr_as_tex(instr));
1849 break;
1850
1851 default:
1852 fprintf(stderr, "Unknown NIR instr type: ");
1853 nir_print_instr(instr, stderr);
1854 fprintf(stderr, "\n");
1855 abort();
1856 }
1857 }
1858
1859 static void
1860 ntq_emit_block(struct vc4_compile *c, nir_block *block)
1861 {
1862 nir_foreach_instr(block, instr) {
1863 ntq_emit_instr(c, instr);
1864 }
1865 }
1866
1867 static void
1868 ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list)
1869 {
1870 foreach_list_typed(nir_cf_node, node, node, list) {
1871 switch (node->type) {
1872 /* case nir_cf_node_loop: */
1873 case nir_cf_node_block:
1874 ntq_emit_block(c, nir_cf_node_as_block(node));
1875 break;
1876
1877 case nir_cf_node_if:
1878 ntq_emit_if(c, nir_cf_node_as_if(node));
1879 break;
1880
1881 default:
1882 assert(0);
1883 }
1884 }
1885 }
1886
1887 static void
1888 ntq_emit_impl(struct vc4_compile *c, nir_function_impl *impl)
1889 {
1890 ntq_setup_registers(c, &impl->registers);
1891 ntq_emit_cf_list(c, &impl->body);
1892 }
1893
1894 static void
1895 nir_to_qir(struct vc4_compile *c)
1896 {
1897 ntq_setup_inputs(c);
1898 ntq_setup_outputs(c);
1899 ntq_setup_uniforms(c);
1900 ntq_setup_registers(c, &c->s->registers);
1901
1902 /* Find the main function and emit the body. */
1903 nir_foreach_overload(c->s, overload) {
1904 assert(strcmp(overload->function->name, "main") == 0);
1905 assert(overload->impl);
1906 ntq_emit_impl(c, overload->impl);
1907 }
1908 }
1909
1910 static const nir_shader_compiler_options nir_options = {
1911 .lower_ffma = true,
1912 .lower_flrp = true,
1913 .lower_fpow = true,
1914 .lower_fsat = true,
1915 .lower_fsqrt = true,
1916 .lower_negate = true,
1917 };
1918
1919 static bool
1920 count_nir_instrs_in_block(nir_block *block, void *state)
1921 {
1922 int *count = (int *) state;
1923 nir_foreach_instr(block, instr) {
1924 *count = *count + 1;
1925 }
1926 return true;
1927 }
1928
1929 static int
1930 count_nir_instrs(nir_shader *nir)
1931 {
1932 int count = 0;
1933 nir_foreach_overload(nir, overload) {
1934 if (!overload->impl)
1935 continue;
1936 nir_foreach_block(overload->impl, count_nir_instrs_in_block, &count);
1937 }
1938 return count;
1939 }
1940
1941 static struct vc4_compile *
1942 vc4_shader_ntq(struct vc4_context *vc4, enum qstage stage,
1943 struct vc4_key *key)
1944 {
1945 struct vc4_compile *c = qir_compile_init();
1946
1947 c->stage = stage;
1948 c->shader_state = &key->shader_state->base;
1949 c->program_id = key->shader_state->program_id;
1950 c->variant_id = key->shader_state->compiled_variant_count++;
1951
1952 c->key = key;
1953 switch (stage) {
1954 case QSTAGE_FRAG:
1955 c->fs_key = (struct vc4_fs_key *)key;
1956 if (c->fs_key->is_points) {
1957 c->point_x = emit_fragment_varying(c, ~0, ~0, 0);
1958 c->point_y = emit_fragment_varying(c, ~0, ~0, 0);
1959 } else if (c->fs_key->is_lines) {
1960 c->line_x = emit_fragment_varying(c, ~0, ~0, 0);
1961 }
1962 break;
1963 case QSTAGE_VERT:
1964 c->vs_key = (struct vc4_vs_key *)key;
1965 break;
1966 case QSTAGE_COORD:
1967 c->vs_key = (struct vc4_vs_key *)key;
1968 break;
1969 }
1970
1971 const struct tgsi_token *tokens = key->shader_state->base.tokens;
1972 if (c->fs_key && c->fs_key->light_twoside) {
1973 if (!key->shader_state->twoside_tokens) {
1974 const struct tgsi_lowering_config lowering_config = {
1975 .color_two_side = true,
1976 };
1977 struct tgsi_shader_info info;
1978 key->shader_state->twoside_tokens =
1979 tgsi_transform_lowering(&lowering_config,
1980 key->shader_state->base.tokens,
1981 &info);
1982
1983 /* If no transformation occurred, then NULL is
1984 * returned and we just use our original tokens.
1985 */
1986 if (!key->shader_state->twoside_tokens) {
1987 key->shader_state->twoside_tokens =
1988 key->shader_state->base.tokens;
1989 }
1990 }
1991 tokens = key->shader_state->twoside_tokens;
1992 }
1993
1994 if (vc4_debug & VC4_DEBUG_TGSI) {
1995 fprintf(stderr, "%s prog %d/%d TGSI:\n",
1996 qir_get_stage_name(c->stage),
1997 c->program_id, c->variant_id);
1998 tgsi_dump(tokens, 0);
1999 }
2000
2001 c->s = tgsi_to_nir(tokens, &nir_options);
2002 nir_opt_global_to_local(c->s);
2003 nir_convert_to_ssa(c->s);
2004 vc4_nir_lower_io(c);
2005 nir_lower_idiv(c->s);
2006
2007 vc4_optimize_nir(c->s);
2008
2009 nir_remove_dead_variables(c->s);
2010
2011 nir_convert_from_ssa(c->s, false);
2012
2013 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2014 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d NIR instructions\n",
2015 qir_get_stage_name(c->stage),
2016 c->program_id, c->variant_id,
2017 count_nir_instrs(c->s));
2018 }
2019
2020 if (vc4_debug & VC4_DEBUG_NIR) {
2021 fprintf(stderr, "%s prog %d/%d NIR:\n",
2022 qir_get_stage_name(c->stage),
2023 c->program_id, c->variant_id);
2024 nir_print_shader(c->s, stderr);
2025 }
2026
2027 nir_to_qir(c);
2028
2029 switch (stage) {
2030 case QSTAGE_FRAG:
2031 emit_frag_end(c);
2032 break;
2033 case QSTAGE_VERT:
2034 emit_vert_end(c,
2035 vc4->prog.fs->input_semantics,
2036 vc4->prog.fs->num_inputs);
2037 break;
2038 case QSTAGE_COORD:
2039 emit_coord_end(c);
2040 break;
2041 }
2042
2043 if (vc4_debug & VC4_DEBUG_QIR) {
2044 fprintf(stderr, "%s prog %d/%d pre-opt QIR:\n",
2045 qir_get_stage_name(c->stage),
2046 c->program_id, c->variant_id);
2047 qir_dump(c);
2048 }
2049
2050 qir_optimize(c);
2051 qir_lower_uniforms(c);
2052
2053 if (vc4_debug & VC4_DEBUG_QIR) {
2054 fprintf(stderr, "%s prog %d/%d QIR:\n",
2055 qir_get_stage_name(c->stage),
2056 c->program_id, c->variant_id);
2057 qir_dump(c);
2058 }
2059 qir_reorder_uniforms(c);
2060 vc4_generate_code(vc4, c);
2061
2062 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2063 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d instructions\n",
2064 qir_get_stage_name(c->stage),
2065 c->program_id, c->variant_id,
2066 c->qpu_inst_count);
2067 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d uniforms\n",
2068 qir_get_stage_name(c->stage),
2069 c->program_id, c->variant_id,
2070 c->num_uniforms);
2071 }
2072
2073 ralloc_free(c->s);
2074
2075 return c;
2076 }
2077
2078 static void *
2079 vc4_shader_state_create(struct pipe_context *pctx,
2080 const struct pipe_shader_state *cso)
2081 {
2082 struct vc4_context *vc4 = vc4_context(pctx);
2083 struct vc4_uncompiled_shader *so = CALLOC_STRUCT(vc4_uncompiled_shader);
2084 if (!so)
2085 return NULL;
2086
2087 so->base.tokens = tgsi_dup_tokens(cso->tokens);
2088 so->program_id = vc4->next_uncompiled_program_id++;
2089
2090 return so;
2091 }
2092
2093 static void
2094 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
2095 struct vc4_compile *c)
2096 {
2097 int count = c->num_uniforms;
2098 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
2099
2100 uinfo->count = count;
2101 uinfo->data = ralloc_array(shader, uint32_t, count);
2102 memcpy(uinfo->data, c->uniform_data,
2103 count * sizeof(*uinfo->data));
2104 uinfo->contents = ralloc_array(shader, enum quniform_contents, count);
2105 memcpy(uinfo->contents, c->uniform_contents,
2106 count * sizeof(*uinfo->contents));
2107 uinfo->num_texture_samples = c->num_texture_samples;
2108
2109 vc4_set_shader_uniform_dirty_flags(shader);
2110 }
2111
2112 static struct vc4_compiled_shader *
2113 vc4_get_compiled_shader(struct vc4_context *vc4, enum qstage stage,
2114 struct vc4_key *key)
2115 {
2116 struct hash_table *ht;
2117 uint32_t key_size;
2118 if (stage == QSTAGE_FRAG) {
2119 ht = vc4->fs_cache;
2120 key_size = sizeof(struct vc4_fs_key);
2121 } else {
2122 ht = vc4->vs_cache;
2123 key_size = sizeof(struct vc4_vs_key);
2124 }
2125
2126 struct vc4_compiled_shader *shader;
2127 struct hash_entry *entry = _mesa_hash_table_search(ht, key);
2128 if (entry)
2129 return entry->data;
2130
2131 struct vc4_compile *c = vc4_shader_ntq(vc4, stage, key);
2132 shader = rzalloc(NULL, struct vc4_compiled_shader);
2133
2134 shader->program_id = vc4->next_compiled_program_id++;
2135 if (stage == QSTAGE_FRAG) {
2136 bool input_live[c->num_input_semantics];
2137
2138 memset(input_live, 0, sizeof(input_live));
2139 list_for_each_entry(struct qinst, inst, &c->instructions, link) {
2140 for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) {
2141 if (inst->src[i].file == QFILE_VARY)
2142 input_live[inst->src[i].index] = true;
2143 }
2144 }
2145
2146 shader->input_semantics = ralloc_array(shader,
2147 struct vc4_varying_semantic,
2148 c->num_input_semantics);
2149
2150 for (int i = 0; i < c->num_input_semantics; i++) {
2151 struct vc4_varying_semantic *sem = &c->input_semantics[i];
2152
2153 if (!input_live[i])
2154 continue;
2155
2156 /* Skip non-VS-output inputs. */
2157 if (sem->semantic == (uint8_t)~0)
2158 continue;
2159
2160 if (sem->semantic == TGSI_SEMANTIC_COLOR ||
2161 sem->semantic == TGSI_SEMANTIC_BCOLOR) {
2162 shader->color_inputs |= (1 << shader->num_inputs);
2163 }
2164
2165 shader->input_semantics[shader->num_inputs] = *sem;
2166 shader->num_inputs++;
2167 }
2168 } else {
2169 shader->num_inputs = c->num_inputs;
2170
2171 shader->vattr_offsets[0] = 0;
2172 for (int i = 0; i < 8; i++) {
2173 shader->vattr_offsets[i + 1] =
2174 shader->vattr_offsets[i] + c->vattr_sizes[i];
2175
2176 if (c->vattr_sizes[i])
2177 shader->vattrs_live |= (1 << i);
2178 }
2179 }
2180
2181 copy_uniform_state_to_shader(shader, c);
2182 shader->bo = vc4_bo_alloc_shader(vc4->screen, c->qpu_insts,
2183 c->qpu_inst_count * sizeof(uint64_t));
2184
2185 /* Copy the compiler UBO range state to the compiled shader, dropping
2186 * out arrays that were never referenced by an indirect load.
2187 *
2188 * (Note that QIR dead code elimination of an array access still
2189 * leaves that array alive, though)
2190 */
2191 if (c->num_ubo_ranges) {
2192 shader->num_ubo_ranges = c->num_ubo_ranges;
2193 shader->ubo_ranges = ralloc_array(shader, struct vc4_ubo_range,
2194 c->num_ubo_ranges);
2195 uint32_t j = 0;
2196 for (int i = 0; i < c->num_uniform_ranges; i++) {
2197 struct vc4_compiler_ubo_range *range =
2198 &c->ubo_ranges[i];
2199 if (!range->used)
2200 continue;
2201
2202 shader->ubo_ranges[j].dst_offset = range->dst_offset;
2203 shader->ubo_ranges[j].src_offset = range->src_offset;
2204 shader->ubo_ranges[j].size = range->size;
2205 shader->ubo_size += c->ubo_ranges[i].size;
2206 j++;
2207 }
2208 }
2209 if (shader->ubo_size) {
2210 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2211 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d UBO uniforms\n",
2212 qir_get_stage_name(c->stage),
2213 c->program_id, c->variant_id,
2214 shader->ubo_size / 4);
2215 }
2216 }
2217
2218 qir_compile_destroy(c);
2219
2220 struct vc4_key *dup_key;
2221 dup_key = ralloc_size(shader, key_size);
2222 memcpy(dup_key, key, key_size);
2223 _mesa_hash_table_insert(ht, dup_key, shader);
2224
2225 return shader;
2226 }
2227
2228 static void
2229 vc4_setup_shared_key(struct vc4_context *vc4, struct vc4_key *key,
2230 struct vc4_texture_stateobj *texstate)
2231 {
2232 for (int i = 0; i < texstate->num_textures; i++) {
2233 struct pipe_sampler_view *sampler = texstate->textures[i];
2234 struct pipe_sampler_state *sampler_state =
2235 texstate->samplers[i];
2236
2237 if (sampler) {
2238 key->tex[i].format = sampler->format;
2239 key->tex[i].swizzle[0] = sampler->swizzle_r;
2240 key->tex[i].swizzle[1] = sampler->swizzle_g;
2241 key->tex[i].swizzle[2] = sampler->swizzle_b;
2242 key->tex[i].swizzle[3] = sampler->swizzle_a;
2243 key->tex[i].compare_mode = sampler_state->compare_mode;
2244 key->tex[i].compare_func = sampler_state->compare_func;
2245 key->tex[i].wrap_s = sampler_state->wrap_s;
2246 key->tex[i].wrap_t = sampler_state->wrap_t;
2247 }
2248 }
2249
2250 key->ucp_enables = vc4->rasterizer->base.clip_plane_enable;
2251 }
2252
2253 static void
2254 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
2255 {
2256 struct vc4_fs_key local_key;
2257 struct vc4_fs_key *key = &local_key;
2258
2259 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2260 VC4_DIRTY_BLEND |
2261 VC4_DIRTY_FRAMEBUFFER |
2262 VC4_DIRTY_ZSA |
2263 VC4_DIRTY_RASTERIZER |
2264 VC4_DIRTY_FRAGTEX |
2265 VC4_DIRTY_TEXSTATE |
2266 VC4_DIRTY_UNCOMPILED_FS))) {
2267 return;
2268 }
2269
2270 memset(key, 0, sizeof(*key));
2271 vc4_setup_shared_key(vc4, &key->base, &vc4->fragtex);
2272 key->base.shader_state = vc4->prog.bind_fs;
2273 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
2274 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
2275 prim_mode <= PIPE_PRIM_LINE_STRIP);
2276 key->blend = vc4->blend->rt[0];
2277 if (vc4->blend->logicop_enable) {
2278 key->logicop_func = vc4->blend->logicop_func;
2279 } else {
2280 key->logicop_func = PIPE_LOGICOP_COPY;
2281 }
2282 if (vc4->framebuffer.cbufs[0])
2283 key->color_format = vc4->framebuffer.cbufs[0]->format;
2284
2285 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
2286 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
2287 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
2288 key->depth_enabled = (vc4->zsa->base.depth.enabled ||
2289 key->stencil_enabled);
2290 if (vc4->zsa->base.alpha.enabled) {
2291 key->alpha_test = true;
2292 key->alpha_test_func = vc4->zsa->base.alpha.func;
2293 }
2294
2295 if (key->is_points) {
2296 key->point_sprite_mask =
2297 vc4->rasterizer->base.sprite_coord_enable;
2298 key->point_coord_upper_left =
2299 (vc4->rasterizer->base.sprite_coord_mode ==
2300 PIPE_SPRITE_COORD_UPPER_LEFT);
2301 }
2302
2303 key->light_twoside = vc4->rasterizer->base.light_twoside;
2304
2305 struct vc4_compiled_shader *old_fs = vc4->prog.fs;
2306 vc4->prog.fs = vc4_get_compiled_shader(vc4, QSTAGE_FRAG, &key->base);
2307 if (vc4->prog.fs == old_fs)
2308 return;
2309
2310 vc4->dirty |= VC4_DIRTY_COMPILED_FS;
2311 if (vc4->rasterizer->base.flatshade &&
2312 old_fs && vc4->prog.fs->color_inputs != old_fs->color_inputs) {
2313 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
2314 }
2315 }
2316
2317 static void
2318 vc4_update_compiled_vs(struct vc4_context *vc4, uint8_t prim_mode)
2319 {
2320 struct vc4_vs_key local_key;
2321 struct vc4_vs_key *key = &local_key;
2322
2323 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2324 VC4_DIRTY_RASTERIZER |
2325 VC4_DIRTY_VERTTEX |
2326 VC4_DIRTY_TEXSTATE |
2327 VC4_DIRTY_VTXSTATE |
2328 VC4_DIRTY_UNCOMPILED_VS |
2329 VC4_DIRTY_COMPILED_FS))) {
2330 return;
2331 }
2332
2333 memset(key, 0, sizeof(*key));
2334 vc4_setup_shared_key(vc4, &key->base, &vc4->verttex);
2335 key->base.shader_state = vc4->prog.bind_vs;
2336 key->compiled_fs_id = vc4->prog.fs->program_id;
2337
2338 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
2339 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
2340
2341 key->per_vertex_point_size =
2342 (prim_mode == PIPE_PRIM_POINTS &&
2343 vc4->rasterizer->base.point_size_per_vertex);
2344
2345 struct vc4_compiled_shader *vs =
2346 vc4_get_compiled_shader(vc4, QSTAGE_VERT, &key->base);
2347 if (vs != vc4->prog.vs) {
2348 vc4->prog.vs = vs;
2349 vc4->dirty |= VC4_DIRTY_COMPILED_VS;
2350 }
2351
2352 key->is_coord = true;
2353 struct vc4_compiled_shader *cs =
2354 vc4_get_compiled_shader(vc4, QSTAGE_COORD, &key->base);
2355 if (cs != vc4->prog.cs) {
2356 vc4->prog.cs = cs;
2357 vc4->dirty |= VC4_DIRTY_COMPILED_CS;
2358 }
2359 }
2360
2361 void
2362 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
2363 {
2364 vc4_update_compiled_fs(vc4, prim_mode);
2365 vc4_update_compiled_vs(vc4, prim_mode);
2366 }
2367
2368 static uint32_t
2369 fs_cache_hash(const void *key)
2370 {
2371 return _mesa_hash_data(key, sizeof(struct vc4_fs_key));
2372 }
2373
2374 static uint32_t
2375 vs_cache_hash(const void *key)
2376 {
2377 return _mesa_hash_data(key, sizeof(struct vc4_vs_key));
2378 }
2379
2380 static bool
2381 fs_cache_compare(const void *key1, const void *key2)
2382 {
2383 return memcmp(key1, key2, sizeof(struct vc4_fs_key)) == 0;
2384 }
2385
2386 static bool
2387 vs_cache_compare(const void *key1, const void *key2)
2388 {
2389 return memcmp(key1, key2, sizeof(struct vc4_vs_key)) == 0;
2390 }
2391
2392 static void
2393 delete_from_cache_if_matches(struct hash_table *ht,
2394 struct hash_entry *entry,
2395 struct vc4_uncompiled_shader *so)
2396 {
2397 const struct vc4_key *key = entry->key;
2398
2399 if (key->shader_state == so) {
2400 struct vc4_compiled_shader *shader = entry->data;
2401 _mesa_hash_table_remove(ht, entry);
2402 vc4_bo_unreference(&shader->bo);
2403 ralloc_free(shader);
2404 }
2405 }
2406
2407 static void
2408 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
2409 {
2410 struct vc4_context *vc4 = vc4_context(pctx);
2411 struct vc4_uncompiled_shader *so = hwcso;
2412
2413 struct hash_entry *entry;
2414 hash_table_foreach(vc4->fs_cache, entry)
2415 delete_from_cache_if_matches(vc4->fs_cache, entry, so);
2416 hash_table_foreach(vc4->vs_cache, entry)
2417 delete_from_cache_if_matches(vc4->vs_cache, entry, so);
2418
2419 if (so->twoside_tokens != so->base.tokens)
2420 free((void *)so->twoside_tokens);
2421 free((void *)so->base.tokens);
2422 free(so);
2423 }
2424
2425 static void
2426 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
2427 {
2428 struct vc4_context *vc4 = vc4_context(pctx);
2429 vc4->prog.bind_fs = hwcso;
2430 vc4->dirty |= VC4_DIRTY_UNCOMPILED_FS;
2431 }
2432
2433 static void
2434 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
2435 {
2436 struct vc4_context *vc4 = vc4_context(pctx);
2437 vc4->prog.bind_vs = hwcso;
2438 vc4->dirty |= VC4_DIRTY_UNCOMPILED_VS;
2439 }
2440
2441 void
2442 vc4_program_init(struct pipe_context *pctx)
2443 {
2444 struct vc4_context *vc4 = vc4_context(pctx);
2445
2446 pctx->create_vs_state = vc4_shader_state_create;
2447 pctx->delete_vs_state = vc4_shader_state_delete;
2448
2449 pctx->create_fs_state = vc4_shader_state_create;
2450 pctx->delete_fs_state = vc4_shader_state_delete;
2451
2452 pctx->bind_fs_state = vc4_fp_state_bind;
2453 pctx->bind_vs_state = vc4_vp_state_bind;
2454
2455 vc4->fs_cache = _mesa_hash_table_create(pctx, fs_cache_hash,
2456 fs_cache_compare);
2457 vc4->vs_cache = _mesa_hash_table_create(pctx, vs_cache_hash,
2458 vs_cache_compare);
2459 }
2460
2461 void
2462 vc4_program_fini(struct pipe_context *pctx)
2463 {
2464 struct vc4_context *vc4 = vc4_context(pctx);
2465
2466 struct hash_entry *entry;
2467 hash_table_foreach(vc4->fs_cache, entry) {
2468 struct vc4_compiled_shader *shader = entry->data;
2469 vc4_bo_unreference(&shader->bo);
2470 ralloc_free(shader);
2471 _mesa_hash_table_remove(vc4->fs_cache, entry);
2472 }
2473
2474 hash_table_foreach(vc4->vs_cache, entry) {
2475 struct vc4_compiled_shader *shader = entry->data;
2476 vc4_bo_unreference(&shader->bo);
2477 ralloc_free(shader);
2478 _mesa_hash_table_remove(vc4->vs_cache, entry);
2479 }
2480 }