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vc4: Move some FS input lowering into NIR.
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "util/u_format.h"
27 #include "util/u_hash.h"
28 #include "util/u_math.h"
29 #include "util/u_memory.h"
30 #include "util/ralloc.h"
31 #include "util/hash_table.h"
32 #include "tgsi/tgsi_dump.h"
33 #include "tgsi/tgsi_info.h"
34 #include "tgsi/tgsi_lowering.h"
35 #include "tgsi/tgsi_parse.h"
36 #include "nir/tgsi_to_nir.h"
37
38 #include "vc4_context.h"
39 #include "vc4_qpu.h"
40 #include "vc4_qir.h"
41 #ifdef USE_VC4_SIMULATOR
42 #include "simpenrose/simpenrose.h"
43 #endif
44
45 static void
46 resize_qreg_array(struct vc4_compile *c,
47 struct qreg **regs,
48 uint32_t *size,
49 uint32_t decl_size)
50 {
51 if (*size >= decl_size)
52 return;
53
54 uint32_t old_size = *size;
55 *size = MAX2(*size * 2, decl_size);
56 *regs = reralloc(c, *regs, struct qreg, *size);
57 if (!*regs) {
58 fprintf(stderr, "Malloc failure\n");
59 abort();
60 }
61
62 for (uint32_t i = old_size; i < *size; i++)
63 (*regs)[i] = c->undef;
64 }
65
66 static struct qreg
67 indirect_uniform_load(struct vc4_compile *c,
68 struct qreg indirect_offset,
69 unsigned offset)
70 {
71 struct vc4_compiler_ubo_range *range = NULL;
72 unsigned i;
73 for (i = 0; i < c->num_uniform_ranges; i++) {
74 range = &c->ubo_ranges[i];
75 if (offset >= range->src_offset &&
76 offset < range->src_offset + range->size) {
77 break;
78 }
79 }
80 /* The driver-location-based offset always has to be within a declared
81 * uniform range.
82 */
83 assert(range);
84 if (!range->used) {
85 range->used = true;
86 range->dst_offset = c->next_ubo_dst_offset;
87 c->next_ubo_dst_offset += range->size;
88 c->num_ubo_ranges++;
89 };
90
91 offset -= range->src_offset;
92 /* Translate the user's TGSI register index from the TGSI register
93 * base to a byte offset.
94 */
95 indirect_offset = qir_SHL(c, indirect_offset, qir_uniform_ui(c, 4));
96
97 /* Adjust for where we stored the TGSI register base. */
98 indirect_offset = qir_ADD(c, indirect_offset,
99 qir_uniform_ui(c, (range->dst_offset +
100 offset)));
101
102 /* Clamp to [0, array size). Note that MIN/MAX are signed. */
103 indirect_offset = qir_MAX(c, indirect_offset, qir_uniform_ui(c, 0));
104 indirect_offset = qir_MIN(c, indirect_offset,
105 qir_uniform_ui(c, (range->dst_offset +
106 range->size - 4)));
107
108 qir_TEX_DIRECT(c, indirect_offset, qir_uniform(c, QUNIFORM_UBO_ADDR, 0));
109 struct qreg r4 = qir_TEX_RESULT(c);
110 c->num_texture_samples++;
111 return qir_MOV(c, r4);
112 }
113
114 static struct qreg *
115 ntq_get_dest(struct vc4_compile *c, nir_dest dest)
116 {
117 assert(!dest.is_ssa);
118 nir_register *reg = dest.reg.reg;
119 struct hash_entry *entry = _mesa_hash_table_search(c->def_ht, reg);
120 assert(reg->num_array_elems == 0);
121 assert(dest.reg.base_offset == 0);
122
123 struct qreg *qregs = entry->data;
124 return qregs;
125 }
126
127 static struct qreg
128 ntq_get_src(struct vc4_compile *c, nir_src src, int i)
129 {
130 struct hash_entry *entry;
131 if (src.is_ssa) {
132 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
133 assert(i < src.ssa->num_components);
134 } else {
135 nir_register *reg = src.reg.reg;
136 entry = _mesa_hash_table_search(c->def_ht, reg);
137 assert(reg->num_array_elems == 0);
138 assert(src.reg.base_offset == 0);
139 assert(i < reg->num_components);
140 }
141
142 struct qreg *qregs = entry->data;
143 return qregs[i];
144 }
145
146 static struct qreg
147 ntq_get_alu_src(struct vc4_compile *c, nir_alu_instr *instr,
148 unsigned src)
149 {
150 assert(util_is_power_of_two(instr->dest.write_mask));
151 unsigned chan = ffs(instr->dest.write_mask) - 1;
152 struct qreg r = ntq_get_src(c, instr->src[src].src,
153 instr->src[src].swizzle[chan]);
154
155 assert(!instr->src[src].abs);
156 assert(!instr->src[src].negate);
157
158 return r;
159 };
160
161 static struct qreg
162 get_swizzled_channel(struct vc4_compile *c,
163 struct qreg *srcs, int swiz)
164 {
165 switch (swiz) {
166 default:
167 case UTIL_FORMAT_SWIZZLE_NONE:
168 fprintf(stderr, "warning: unknown swizzle\n");
169 /* FALLTHROUGH */
170 case UTIL_FORMAT_SWIZZLE_0:
171 return qir_uniform_f(c, 0.0);
172 case UTIL_FORMAT_SWIZZLE_1:
173 return qir_uniform_f(c, 1.0);
174 case UTIL_FORMAT_SWIZZLE_X:
175 case UTIL_FORMAT_SWIZZLE_Y:
176 case UTIL_FORMAT_SWIZZLE_Z:
177 case UTIL_FORMAT_SWIZZLE_W:
178 return srcs[swiz];
179 }
180 }
181
182 static inline struct qreg
183 qir_SAT(struct vc4_compile *c, struct qreg val)
184 {
185 return qir_FMAX(c,
186 qir_FMIN(c, val, qir_uniform_f(c, 1.0)),
187 qir_uniform_f(c, 0.0));
188 }
189
190 static struct qreg
191 ntq_rcp(struct vc4_compile *c, struct qreg x)
192 {
193 struct qreg r = qir_RCP(c, x);
194
195 /* Apply a Newton-Raphson step to improve the accuracy. */
196 r = qir_FMUL(c, r, qir_FSUB(c,
197 qir_uniform_f(c, 2.0),
198 qir_FMUL(c, x, r)));
199
200 return r;
201 }
202
203 static struct qreg
204 ntq_rsq(struct vc4_compile *c, struct qreg x)
205 {
206 struct qreg r = qir_RSQ(c, x);
207
208 /* Apply a Newton-Raphson step to improve the accuracy. */
209 r = qir_FMUL(c, r, qir_FSUB(c,
210 qir_uniform_f(c, 1.5),
211 qir_FMUL(c,
212 qir_uniform_f(c, 0.5),
213 qir_FMUL(c, x,
214 qir_FMUL(c, r, r)))));
215
216 return r;
217 }
218
219 static struct qreg
220 qir_srgb_decode(struct vc4_compile *c, struct qreg srgb)
221 {
222 struct qreg low = qir_FMUL(c, srgb, qir_uniform_f(c, 1.0 / 12.92));
223 struct qreg high = qir_POW(c,
224 qir_FMUL(c,
225 qir_FADD(c,
226 srgb,
227 qir_uniform_f(c, 0.055)),
228 qir_uniform_f(c, 1.0 / 1.055)),
229 qir_uniform_f(c, 2.4));
230
231 qir_SF(c, qir_FSUB(c, srgb, qir_uniform_f(c, 0.04045)));
232 return qir_SEL_X_Y_NS(c, low, high);
233 }
234
235 static struct qreg
236 qir_srgb_encode(struct vc4_compile *c, struct qreg linear)
237 {
238 struct qreg low = qir_FMUL(c, linear, qir_uniform_f(c, 12.92));
239 struct qreg high = qir_FSUB(c,
240 qir_FMUL(c,
241 qir_uniform_f(c, 1.055),
242 qir_POW(c,
243 linear,
244 qir_uniform_f(c, 0.41666))),
245 qir_uniform_f(c, 0.055));
246
247 qir_SF(c, qir_FSUB(c, linear, qir_uniform_f(c, 0.0031308)));
248 return qir_SEL_X_Y_NS(c, low, high);
249 }
250
251 static struct qreg
252 ntq_umul(struct vc4_compile *c, struct qreg src0, struct qreg src1)
253 {
254 struct qreg src0_hi = qir_SHR(c, src0,
255 qir_uniform_ui(c, 24));
256 struct qreg src1_hi = qir_SHR(c, src1,
257 qir_uniform_ui(c, 24));
258
259 struct qreg hilo = qir_MUL24(c, src0_hi, src1);
260 struct qreg lohi = qir_MUL24(c, src0, src1_hi);
261 struct qreg lolo = qir_MUL24(c, src0, src1);
262
263 return qir_ADD(c, lolo, qir_SHL(c,
264 qir_ADD(c, hilo, lohi),
265 qir_uniform_ui(c, 24)));
266 }
267
268 static void
269 ntq_emit_tex(struct vc4_compile *c, nir_tex_instr *instr)
270 {
271 struct qreg s, t, r, lod, proj, compare;
272 bool is_txb = false, is_txl = false, has_proj = false;
273 unsigned unit = instr->sampler_index;
274
275 for (unsigned i = 0; i < instr->num_srcs; i++) {
276 switch (instr->src[i].src_type) {
277 case nir_tex_src_coord:
278 s = ntq_get_src(c, instr->src[i].src, 0);
279 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D)
280 t = qir_uniform_f(c, 0.5);
281 else
282 t = ntq_get_src(c, instr->src[i].src, 1);
283 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
284 r = ntq_get_src(c, instr->src[i].src, 2);
285 break;
286 case nir_tex_src_bias:
287 lod = ntq_get_src(c, instr->src[i].src, 0);
288 is_txb = true;
289 break;
290 case nir_tex_src_lod:
291 lod = ntq_get_src(c, instr->src[i].src, 0);
292 is_txl = true;
293 break;
294 case nir_tex_src_comparitor:
295 compare = ntq_get_src(c, instr->src[i].src, 0);
296 break;
297 case nir_tex_src_projector:
298 proj = qir_RCP(c, ntq_get_src(c, instr->src[i].src, 0));
299 s = qir_FMUL(c, s, proj);
300 t = qir_FMUL(c, t, proj);
301 has_proj = true;
302 break;
303 default:
304 unreachable("unknown texture source");
305 }
306 }
307
308 struct qreg texture_u[] = {
309 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit),
310 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
311 qir_uniform(c, QUNIFORM_CONSTANT, 0),
312 qir_uniform(c, QUNIFORM_CONSTANT, 0),
313 };
314 uint32_t next_texture_u = 0;
315
316 /* There is no native support for GL texture rectangle coordinates, so
317 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
318 * 1]).
319 */
320 if (instr->sampler_dim == GLSL_SAMPLER_DIM_RECT) {
321 s = qir_FMUL(c, s,
322 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_X, unit));
323 t = qir_FMUL(c, t,
324 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_Y, unit));
325 }
326
327 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE || is_txl) {
328 texture_u[2] = qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P2,
329 unit | (is_txl << 16));
330 }
331
332 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
333 struct qreg ma = qir_FMAXABS(c, qir_FMAXABS(c, s, t), r);
334 struct qreg rcp_ma = qir_RCP(c, ma);
335 s = qir_FMUL(c, s, rcp_ma);
336 t = qir_FMUL(c, t, rcp_ma);
337 r = qir_FMUL(c, r, rcp_ma);
338
339 qir_TEX_R(c, r, texture_u[next_texture_u++]);
340 } else if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
341 c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP ||
342 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
343 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
344 qir_TEX_R(c, qir_uniform(c, QUNIFORM_TEXTURE_BORDER_COLOR, unit),
345 texture_u[next_texture_u++]);
346 }
347
348 if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP) {
349 s = qir_SAT(c, s);
350 }
351
352 if (c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
353 t = qir_SAT(c, t);
354 }
355
356 qir_TEX_T(c, t, texture_u[next_texture_u++]);
357
358 if (is_txl || is_txb)
359 qir_TEX_B(c, lod, texture_u[next_texture_u++]);
360
361 qir_TEX_S(c, s, texture_u[next_texture_u++]);
362
363 c->num_texture_samples++;
364 struct qreg r4 = qir_TEX_RESULT(c);
365
366 enum pipe_format format = c->key->tex[unit].format;
367
368 struct qreg unpacked[4];
369 if (util_format_is_depth_or_stencil(format)) {
370 struct qreg depthf = qir_ITOF(c, qir_SHR(c, r4,
371 qir_uniform_ui(c, 8)));
372 struct qreg normalized = qir_FMUL(c, depthf,
373 qir_uniform_f(c, 1.0f/0xffffff));
374
375 struct qreg depth_output;
376
377 struct qreg one = qir_uniform_f(c, 1.0f);
378 if (c->key->tex[unit].compare_mode) {
379 if (has_proj)
380 compare = qir_FMUL(c, compare, proj);
381
382 switch (c->key->tex[unit].compare_func) {
383 case PIPE_FUNC_NEVER:
384 depth_output = qir_uniform_f(c, 0.0f);
385 break;
386 case PIPE_FUNC_ALWAYS:
387 depth_output = one;
388 break;
389 case PIPE_FUNC_EQUAL:
390 qir_SF(c, qir_FSUB(c, compare, normalized));
391 depth_output = qir_SEL_X_0_ZS(c, one);
392 break;
393 case PIPE_FUNC_NOTEQUAL:
394 qir_SF(c, qir_FSUB(c, compare, normalized));
395 depth_output = qir_SEL_X_0_ZC(c, one);
396 break;
397 case PIPE_FUNC_GREATER:
398 qir_SF(c, qir_FSUB(c, compare, normalized));
399 depth_output = qir_SEL_X_0_NC(c, one);
400 break;
401 case PIPE_FUNC_GEQUAL:
402 qir_SF(c, qir_FSUB(c, normalized, compare));
403 depth_output = qir_SEL_X_0_NS(c, one);
404 break;
405 case PIPE_FUNC_LESS:
406 qir_SF(c, qir_FSUB(c, compare, normalized));
407 depth_output = qir_SEL_X_0_NS(c, one);
408 break;
409 case PIPE_FUNC_LEQUAL:
410 qir_SF(c, qir_FSUB(c, normalized, compare));
411 depth_output = qir_SEL_X_0_NC(c, one);
412 break;
413 }
414 } else {
415 depth_output = normalized;
416 }
417
418 for (int i = 0; i < 4; i++)
419 unpacked[i] = depth_output;
420 } else {
421 for (int i = 0; i < 4; i++)
422 unpacked[i] = qir_R4_UNPACK(c, r4, i);
423 }
424
425 const uint8_t *format_swiz = vc4_get_format_swizzle(format);
426 struct qreg texture_output[4];
427 for (int i = 0; i < 4; i++) {
428 texture_output[i] = get_swizzled_channel(c, unpacked,
429 format_swiz[i]);
430 }
431
432 if (util_format_is_srgb(format)) {
433 for (int i = 0; i < 3; i++)
434 texture_output[i] = qir_srgb_decode(c,
435 texture_output[i]);
436 }
437
438 struct qreg *dest = ntq_get_dest(c, instr->dest);
439 for (int i = 0; i < 4; i++) {
440 dest[i] = get_swizzled_channel(c, texture_output,
441 c->key->tex[unit].swizzle[i]);
442 }
443 }
444
445 /**
446 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
447 * to zero).
448 */
449 static struct qreg
450 ntq_ffract(struct vc4_compile *c, struct qreg src)
451 {
452 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
453 struct qreg diff = qir_FSUB(c, src, trunc);
454 qir_SF(c, diff);
455 return qir_SEL_X_Y_NS(c,
456 qir_FADD(c, diff, qir_uniform_f(c, 1.0)),
457 diff);
458 }
459
460 /**
461 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
462 * zero).
463 */
464 static struct qreg
465 ntq_ffloor(struct vc4_compile *c, struct qreg src)
466 {
467 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
468
469 /* This will be < 0 if we truncated and the truncation was of a value
470 * that was < 0 in the first place.
471 */
472 qir_SF(c, qir_FSUB(c, src, trunc));
473
474 return qir_SEL_X_Y_NS(c,
475 qir_FSUB(c, trunc, qir_uniform_f(c, 1.0)),
476 trunc);
477 }
478
479 /**
480 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
481 * zero).
482 */
483 static struct qreg
484 ntq_fceil(struct vc4_compile *c, struct qreg src)
485 {
486 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
487
488 /* This will be < 0 if we truncated and the truncation was of a value
489 * that was > 0 in the first place.
490 */
491 qir_SF(c, qir_FSUB(c, trunc, src));
492
493 return qir_SEL_X_Y_NS(c,
494 qir_FADD(c, trunc, qir_uniform_f(c, 1.0)),
495 trunc);
496 }
497
498 static struct qreg
499 ntq_fsin(struct vc4_compile *c, struct qreg src)
500 {
501 float coeff[] = {
502 -2.0 * M_PI,
503 pow(2.0 * M_PI, 3) / (3 * 2 * 1),
504 -pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
505 pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
506 -pow(2.0 * M_PI, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
507 };
508
509 struct qreg scaled_x =
510 qir_FMUL(c,
511 src,
512 qir_uniform_f(c, 1.0 / (M_PI * 2.0)));
513
514 struct qreg x = qir_FADD(c,
515 ntq_ffract(c, scaled_x),
516 qir_uniform_f(c, -0.5));
517 struct qreg x2 = qir_FMUL(c, x, x);
518 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
519 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
520 x = qir_FMUL(c, x, x2);
521 sum = qir_FADD(c,
522 sum,
523 qir_FMUL(c,
524 x,
525 qir_uniform_f(c, coeff[i])));
526 }
527 return sum;
528 }
529
530 static struct qreg
531 ntq_fcos(struct vc4_compile *c, struct qreg src)
532 {
533 float coeff[] = {
534 -1.0f,
535 pow(2.0 * M_PI, 2) / (2 * 1),
536 -pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
537 pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
538 -pow(2.0 * M_PI, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
539 pow(2.0 * M_PI, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
540 };
541
542 struct qreg scaled_x =
543 qir_FMUL(c, src,
544 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
545 struct qreg x_frac = qir_FADD(c,
546 ntq_ffract(c, scaled_x),
547 qir_uniform_f(c, -0.5));
548
549 struct qreg sum = qir_uniform_f(c, coeff[0]);
550 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
551 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
552 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
553 if (i != 1)
554 x = qir_FMUL(c, x, x2);
555
556 struct qreg mul = qir_FMUL(c,
557 x,
558 qir_uniform_f(c, coeff[i]));
559 if (i == 0)
560 sum = mul;
561 else
562 sum = qir_FADD(c, sum, mul);
563 }
564 return sum;
565 }
566
567 static struct qreg
568 ntq_fsign(struct vc4_compile *c, struct qreg src)
569 {
570 qir_SF(c, src);
571 return qir_SEL_X_Y_NC(c,
572 qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0)),
573 qir_uniform_f(c, -1.0));
574 }
575
576 static struct qreg
577 get_channel_from_vpm(struct vc4_compile *c,
578 struct qreg *vpm_reads,
579 uint8_t swiz,
580 const struct util_format_description *desc)
581 {
582 const struct util_format_channel_description *chan =
583 &desc->channel[swiz];
584 struct qreg temp;
585
586 if (swiz > UTIL_FORMAT_SWIZZLE_W)
587 return get_swizzled_channel(c, vpm_reads, swiz);
588 else if (chan->size == 32 &&
589 chan->type == UTIL_FORMAT_TYPE_FLOAT) {
590 return get_swizzled_channel(c, vpm_reads, swiz);
591 } else if (chan->size == 32 &&
592 chan->type == UTIL_FORMAT_TYPE_SIGNED) {
593 if (chan->normalized) {
594 return qir_FMUL(c,
595 qir_ITOF(c, vpm_reads[swiz]),
596 qir_uniform_f(c,
597 1.0 / 0x7fffffff));
598 } else {
599 return qir_ITOF(c, vpm_reads[swiz]);
600 }
601 } else if (chan->size == 8 &&
602 (chan->type == UTIL_FORMAT_TYPE_UNSIGNED ||
603 chan->type == UTIL_FORMAT_TYPE_SIGNED)) {
604 struct qreg vpm = vpm_reads[0];
605 if (chan->type == UTIL_FORMAT_TYPE_SIGNED) {
606 temp = qir_XOR(c, vpm, qir_uniform_ui(c, 0x80808080));
607 if (chan->normalized) {
608 return qir_FSUB(c, qir_FMUL(c,
609 qir_UNPACK_8_F(c, temp, swiz),
610 qir_uniform_f(c, 2.0)),
611 qir_uniform_f(c, 1.0));
612 } else {
613 return qir_FADD(c,
614 qir_ITOF(c,
615 qir_UNPACK_8_I(c, temp,
616 swiz)),
617 qir_uniform_f(c, -128.0));
618 }
619 } else {
620 if (chan->normalized) {
621 return qir_UNPACK_8_F(c, vpm, swiz);
622 } else {
623 return qir_ITOF(c, qir_UNPACK_8_I(c, vpm, swiz));
624 }
625 }
626 } else if (chan->size == 16 &&
627 (chan->type == UTIL_FORMAT_TYPE_UNSIGNED ||
628 chan->type == UTIL_FORMAT_TYPE_SIGNED)) {
629 struct qreg vpm = vpm_reads[swiz / 2];
630
631 /* Note that UNPACK_16F eats a half float, not ints, so we use
632 * UNPACK_16_I for all of these.
633 */
634 if (chan->type == UTIL_FORMAT_TYPE_SIGNED) {
635 temp = qir_ITOF(c, qir_UNPACK_16_I(c, vpm, swiz % 2));
636 if (chan->normalized) {
637 return qir_FMUL(c, temp,
638 qir_uniform_f(c, 1/32768.0f));
639 } else {
640 return temp;
641 }
642 } else {
643 /* UNPACK_16I sign-extends, so we have to emit ANDs. */
644 temp = vpm;
645 if (swiz == 1 || swiz == 3)
646 temp = qir_UNPACK_16_I(c, temp, 1);
647 temp = qir_AND(c, temp, qir_uniform_ui(c, 0xffff));
648 temp = qir_ITOF(c, temp);
649
650 if (chan->normalized) {
651 return qir_FMUL(c, temp,
652 qir_uniform_f(c, 1 / 65535.0));
653 } else {
654 return temp;
655 }
656 }
657 } else {
658 return c->undef;
659 }
660 }
661
662 static void
663 emit_vertex_input(struct vc4_compile *c, int attr)
664 {
665 enum pipe_format format = c->vs_key->attr_formats[attr];
666 uint32_t attr_size = util_format_get_blocksize(format);
667 struct qreg vpm_reads[4];
668
669 c->vattr_sizes[attr] = align(attr_size, 4);
670 for (int i = 0; i < align(attr_size, 4) / 4; i++) {
671 struct qreg vpm = { QFILE_VPM, attr * 4 + i };
672 vpm_reads[i] = qir_MOV(c, vpm);
673 c->num_inputs++;
674 }
675
676 bool format_warned = false;
677 const struct util_format_description *desc =
678 util_format_description(format);
679
680 for (int i = 0; i < 4; i++) {
681 uint8_t swiz = desc->swizzle[i];
682 struct qreg result = get_channel_from_vpm(c, vpm_reads,
683 swiz, desc);
684
685 if (result.file == QFILE_NULL) {
686 if (!format_warned) {
687 fprintf(stderr,
688 "vtx element %d unsupported type: %s\n",
689 attr, util_format_name(format));
690 format_warned = true;
691 }
692 result = qir_uniform_f(c, 0.0);
693 }
694 c->inputs[attr * 4 + i] = result;
695 }
696 }
697
698 static void
699 emit_fragcoord_input(struct vc4_compile *c, int attr)
700 {
701 c->inputs[attr * 4 + 0] = qir_FRAG_X(c);
702 c->inputs[attr * 4 + 1] = qir_FRAG_Y(c);
703 c->inputs[attr * 4 + 2] =
704 qir_FMUL(c,
705 qir_ITOF(c, qir_FRAG_Z(c)),
706 qir_uniform_f(c, 1.0 / 0xffffff));
707 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
708 }
709
710 static struct qreg
711 emit_fragment_varying(struct vc4_compile *c, uint8_t semantic,
712 uint8_t index, uint8_t swizzle)
713 {
714 uint32_t i = c->num_input_semantics++;
715 struct qreg vary = {
716 QFILE_VARY,
717 i
718 };
719
720 if (c->num_input_semantics >= c->input_semantics_array_size) {
721 c->input_semantics_array_size =
722 MAX2(4, c->input_semantics_array_size * 2);
723
724 c->input_semantics = reralloc(c, c->input_semantics,
725 struct vc4_varying_semantic,
726 c->input_semantics_array_size);
727 }
728
729 c->input_semantics[i].semantic = semantic;
730 c->input_semantics[i].index = index;
731 c->input_semantics[i].swizzle = swizzle;
732
733 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
734 }
735
736 static void
737 emit_fragment_input(struct vc4_compile *c, int attr,
738 unsigned semantic_name, unsigned semantic_index)
739 {
740 for (int i = 0; i < 4; i++) {
741 c->inputs[attr * 4 + i] =
742 emit_fragment_varying(c,
743 semantic_name,
744 semantic_index,
745 i);
746 c->num_inputs++;
747 }
748 }
749
750 static void
751 add_output(struct vc4_compile *c,
752 uint32_t decl_offset,
753 uint8_t semantic_name,
754 uint8_t semantic_index,
755 uint8_t semantic_swizzle)
756 {
757 uint32_t old_array_size = c->outputs_array_size;
758 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
759 decl_offset + 1);
760
761 if (old_array_size != c->outputs_array_size) {
762 c->output_semantics = reralloc(c,
763 c->output_semantics,
764 struct vc4_varying_semantic,
765 c->outputs_array_size);
766 }
767
768 c->output_semantics[decl_offset].semantic = semantic_name;
769 c->output_semantics[decl_offset].index = semantic_index;
770 c->output_semantics[decl_offset].swizzle = semantic_swizzle;
771 }
772
773 static void
774 declare_uniform_range(struct vc4_compile *c, uint32_t start, uint32_t size)
775 {
776 unsigned array_id = c->num_uniform_ranges++;
777 if (array_id >= c->ubo_ranges_array_size) {
778 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
779 array_id + 1);
780 c->ubo_ranges = reralloc(c, c->ubo_ranges,
781 struct vc4_compiler_ubo_range,
782 c->ubo_ranges_array_size);
783 }
784
785 c->ubo_ranges[array_id].dst_offset = 0;
786 c->ubo_ranges[array_id].src_offset = start;
787 c->ubo_ranges[array_id].size = size;
788 c->ubo_ranges[array_id].used = false;
789 }
790
791 static void
792 ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr)
793 {
794 /* Vectors are special in that they have non-scalarized writemasks,
795 * and just take the first swizzle channel for each argument in order
796 * into each writemask channel.
797 */
798 if (instr->op == nir_op_vec2 ||
799 instr->op == nir_op_vec3 ||
800 instr->op == nir_op_vec4) {
801 struct qreg srcs[4];
802 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
803 srcs[i] = ntq_get_src(c, instr->src[i].src,
804 instr->src[i].swizzle[0]);
805 struct qreg *dest = ntq_get_dest(c, instr->dest.dest);
806 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
807 dest[i] = srcs[i];
808 return;
809 }
810
811 /* General case: We can just grab the one used channel per src. */
812 struct qreg src[nir_op_infos[instr->op].num_inputs];
813 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
814 src[i] = ntq_get_alu_src(c, instr, i);
815 }
816
817 /* Pick the channel to store the output in. */
818 assert(!instr->dest.saturate);
819 struct qreg *dest = ntq_get_dest(c, instr->dest.dest);
820 assert(util_is_power_of_two(instr->dest.write_mask));
821 dest += ffs(instr->dest.write_mask) - 1;
822
823 switch (instr->op) {
824 case nir_op_fmov:
825 case nir_op_imov:
826 *dest = qir_MOV(c, src[0]);
827 break;
828 case nir_op_fmul:
829 *dest = qir_FMUL(c, src[0], src[1]);
830 break;
831 case nir_op_fadd:
832 *dest = qir_FADD(c, src[0], src[1]);
833 break;
834 case nir_op_fsub:
835 *dest = qir_FSUB(c, src[0], src[1]);
836 break;
837 case nir_op_fmin:
838 *dest = qir_FMIN(c, src[0], src[1]);
839 break;
840 case nir_op_fmax:
841 *dest = qir_FMAX(c, src[0], src[1]);
842 break;
843
844 case nir_op_f2i:
845 case nir_op_f2u:
846 *dest = qir_FTOI(c, src[0]);
847 break;
848 case nir_op_i2f:
849 case nir_op_u2f:
850 *dest = qir_ITOF(c, src[0]);
851 break;
852 case nir_op_b2f:
853 *dest = qir_AND(c, src[0], qir_uniform_f(c, 1.0));
854 break;
855 case nir_op_b2i:
856 *dest = qir_AND(c, src[0], qir_uniform_ui(c, 1));
857 break;
858 case nir_op_i2b:
859 case nir_op_f2b:
860 qir_SF(c, src[0]);
861 *dest = qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
862 break;
863
864 case nir_op_iadd:
865 *dest = qir_ADD(c, src[0], src[1]);
866 break;
867 case nir_op_ushr:
868 *dest = qir_SHR(c, src[0], src[1]);
869 break;
870 case nir_op_isub:
871 *dest = qir_SUB(c, src[0], src[1]);
872 break;
873 case nir_op_ishr:
874 *dest = qir_ASR(c, src[0], src[1]);
875 break;
876 case nir_op_ishl:
877 *dest = qir_SHL(c, src[0], src[1]);
878 break;
879 case nir_op_imin:
880 *dest = qir_MIN(c, src[0], src[1]);
881 break;
882 case nir_op_imax:
883 *dest = qir_MAX(c, src[0], src[1]);
884 break;
885 case nir_op_iand:
886 *dest = qir_AND(c, src[0], src[1]);
887 break;
888 case nir_op_ior:
889 *dest = qir_OR(c, src[0], src[1]);
890 break;
891 case nir_op_ixor:
892 *dest = qir_XOR(c, src[0], src[1]);
893 break;
894 case nir_op_inot:
895 *dest = qir_NOT(c, src[0]);
896 break;
897
898 case nir_op_imul:
899 *dest = ntq_umul(c, src[0], src[1]);
900 break;
901
902 case nir_op_seq:
903 qir_SF(c, qir_FSUB(c, src[0], src[1]));
904 *dest = qir_SEL_X_0_ZS(c, qir_uniform_f(c, 1.0));
905 break;
906 case nir_op_sne:
907 qir_SF(c, qir_FSUB(c, src[0], src[1]));
908 *dest = qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0));
909 break;
910 case nir_op_sge:
911 qir_SF(c, qir_FSUB(c, src[0], src[1]));
912 *dest = qir_SEL_X_0_NC(c, qir_uniform_f(c, 1.0));
913 break;
914 case nir_op_slt:
915 qir_SF(c, qir_FSUB(c, src[0], src[1]));
916 *dest = qir_SEL_X_0_NS(c, qir_uniform_f(c, 1.0));
917 break;
918 case nir_op_feq:
919 qir_SF(c, qir_FSUB(c, src[0], src[1]));
920 *dest = qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
921 break;
922 case nir_op_fne:
923 qir_SF(c, qir_FSUB(c, src[0], src[1]));
924 *dest = qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
925 break;
926 case nir_op_fge:
927 qir_SF(c, qir_FSUB(c, src[0], src[1]));
928 *dest = qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
929 break;
930 case nir_op_flt:
931 qir_SF(c, qir_FSUB(c, src[0], src[1]));
932 *dest = qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
933 break;
934 case nir_op_ieq:
935 qir_SF(c, qir_SUB(c, src[0], src[1]));
936 *dest = qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
937 break;
938 case nir_op_ine:
939 qir_SF(c, qir_SUB(c, src[0], src[1]));
940 *dest = qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
941 break;
942 case nir_op_ige:
943 qir_SF(c, qir_SUB(c, src[0], src[1]));
944 *dest = qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
945 break;
946 case nir_op_ilt:
947 qir_SF(c, qir_SUB(c, src[0], src[1]));
948 *dest = qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
949 break;
950
951 case nir_op_bcsel:
952 qir_SF(c, src[0]);
953 *dest = qir_SEL_X_Y_NS(c, src[1], src[2]);
954 break;
955 case nir_op_fcsel:
956 qir_SF(c, src[0]);
957 *dest = qir_SEL_X_Y_ZC(c, src[1], src[2]);
958 break;
959
960 case nir_op_frcp:
961 *dest = ntq_rcp(c, src[0]);
962 break;
963 case nir_op_frsq:
964 *dest = ntq_rsq(c, src[0]);
965 break;
966 case nir_op_fexp2:
967 *dest = qir_EXP2(c, src[0]);
968 break;
969 case nir_op_flog2:
970 *dest = qir_LOG2(c, src[0]);
971 break;
972
973 case nir_op_ftrunc:
974 *dest = qir_ITOF(c, qir_FTOI(c, src[0]));
975 break;
976 case nir_op_fceil:
977 *dest = ntq_fceil(c, src[0]);
978 break;
979 case nir_op_ffract:
980 *dest = ntq_ffract(c, src[0]);
981 break;
982 case nir_op_ffloor:
983 *dest = ntq_ffloor(c, src[0]);
984 break;
985
986 case nir_op_fsin:
987 *dest = ntq_fsin(c, src[0]);
988 break;
989 case nir_op_fcos:
990 *dest = ntq_fcos(c, src[0]);
991 break;
992
993 case nir_op_fsign:
994 *dest = ntq_fsign(c, src[0]);
995 break;
996
997 case nir_op_fabs:
998 *dest = qir_FMAXABS(c, src[0], src[0]);
999 break;
1000 case nir_op_iabs:
1001 *dest = qir_MAX(c, src[0],
1002 qir_SUB(c, qir_uniform_ui(c, 0), src[0]));
1003 break;
1004
1005 default:
1006 fprintf(stderr, "unknown NIR ALU inst: ");
1007 nir_print_instr(&instr->instr, stderr);
1008 fprintf(stderr, "\n");
1009 abort();
1010 }
1011 }
1012
1013 static struct qreg
1014 vc4_blend_channel(struct vc4_compile *c,
1015 struct qreg *dst,
1016 struct qreg *src,
1017 struct qreg val,
1018 unsigned factor,
1019 int channel)
1020 {
1021 switch(factor) {
1022 case PIPE_BLENDFACTOR_ONE:
1023 return val;
1024 case PIPE_BLENDFACTOR_SRC_COLOR:
1025 return qir_FMUL(c, val, src[channel]);
1026 case PIPE_BLENDFACTOR_SRC_ALPHA:
1027 return qir_FMUL(c, val, src[3]);
1028 case PIPE_BLENDFACTOR_DST_ALPHA:
1029 return qir_FMUL(c, val, dst[3]);
1030 case PIPE_BLENDFACTOR_DST_COLOR:
1031 return qir_FMUL(c, val, dst[channel]);
1032 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
1033 if (channel != 3) {
1034 return qir_FMUL(c,
1035 val,
1036 qir_FMIN(c,
1037 src[3],
1038 qir_FSUB(c,
1039 qir_uniform_f(c, 1.0),
1040 dst[3])));
1041 } else {
1042 return val;
1043 }
1044 case PIPE_BLENDFACTOR_CONST_COLOR:
1045 return qir_FMUL(c, val,
1046 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR,
1047 channel));
1048 case PIPE_BLENDFACTOR_CONST_ALPHA:
1049 return qir_FMUL(c, val,
1050 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR, 3));
1051 case PIPE_BLENDFACTOR_ZERO:
1052 return qir_uniform_f(c, 0.0);
1053 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
1054 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1055 src[channel]));
1056 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
1057 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1058 src[3]));
1059 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
1060 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1061 dst[3]));
1062 case PIPE_BLENDFACTOR_INV_DST_COLOR:
1063 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1064 dst[channel]));
1065 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
1066 return qir_FMUL(c, val,
1067 qir_FSUB(c, qir_uniform_f(c, 1.0),
1068 qir_uniform(c,
1069 QUNIFORM_BLEND_CONST_COLOR,
1070 channel)));
1071 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
1072 return qir_FMUL(c, val,
1073 qir_FSUB(c, qir_uniform_f(c, 1.0),
1074 qir_uniform(c,
1075 QUNIFORM_BLEND_CONST_COLOR,
1076 3)));
1077
1078 default:
1079 case PIPE_BLENDFACTOR_SRC1_COLOR:
1080 case PIPE_BLENDFACTOR_SRC1_ALPHA:
1081 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
1082 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
1083 /* Unsupported. */
1084 fprintf(stderr, "Unknown blend factor %d\n", factor);
1085 return val;
1086 }
1087 }
1088
1089 static struct qreg
1090 vc4_blend_func(struct vc4_compile *c,
1091 struct qreg src, struct qreg dst,
1092 unsigned func)
1093 {
1094 switch (func) {
1095 case PIPE_BLEND_ADD:
1096 return qir_FADD(c, src, dst);
1097 case PIPE_BLEND_SUBTRACT:
1098 return qir_FSUB(c, src, dst);
1099 case PIPE_BLEND_REVERSE_SUBTRACT:
1100 return qir_FSUB(c, dst, src);
1101 case PIPE_BLEND_MIN:
1102 return qir_FMIN(c, src, dst);
1103 case PIPE_BLEND_MAX:
1104 return qir_FMAX(c, src, dst);
1105
1106 default:
1107 /* Unsupported. */
1108 fprintf(stderr, "Unknown blend func %d\n", func);
1109 return src;
1110
1111 }
1112 }
1113
1114 /**
1115 * Implements fixed function blending in shader code.
1116 *
1117 * VC4 doesn't have any hardware support for blending. Instead, you read the
1118 * current contents of the destination from the tile buffer after having
1119 * waited for the scoreboard (which is handled by vc4_qpu_emit.c), then do
1120 * math using your output color and that destination value, and update the
1121 * output color appropriately.
1122 */
1123 static void
1124 vc4_blend(struct vc4_compile *c, struct qreg *result,
1125 struct qreg *dst_color, struct qreg *src_color)
1126 {
1127 struct pipe_rt_blend_state *blend = &c->fs_key->blend;
1128
1129 if (!blend->blend_enable) {
1130 for (int i = 0; i < 4; i++)
1131 result[i] = src_color[i];
1132 return;
1133 }
1134
1135 struct qreg clamped_src[4];
1136 struct qreg clamped_dst[4];
1137 for (int i = 0; i < 4; i++) {
1138 clamped_src[i] = qir_SAT(c, src_color[i]);
1139 clamped_dst[i] = qir_SAT(c, dst_color[i]);
1140 }
1141 src_color = clamped_src;
1142 dst_color = clamped_dst;
1143
1144 struct qreg src_blend[4], dst_blend[4];
1145 for (int i = 0; i < 3; i++) {
1146 src_blend[i] = vc4_blend_channel(c,
1147 dst_color, src_color,
1148 src_color[i],
1149 blend->rgb_src_factor, i);
1150 dst_blend[i] = vc4_blend_channel(c,
1151 dst_color, src_color,
1152 dst_color[i],
1153 blend->rgb_dst_factor, i);
1154 }
1155 src_blend[3] = vc4_blend_channel(c,
1156 dst_color, src_color,
1157 src_color[3],
1158 blend->alpha_src_factor, 3);
1159 dst_blend[3] = vc4_blend_channel(c,
1160 dst_color, src_color,
1161 dst_color[3],
1162 blend->alpha_dst_factor, 3);
1163
1164 for (int i = 0; i < 3; i++) {
1165 result[i] = vc4_blend_func(c,
1166 src_blend[i], dst_blend[i],
1167 blend->rgb_func);
1168 }
1169 result[3] = vc4_blend_func(c,
1170 src_blend[3], dst_blend[3],
1171 blend->alpha_func);
1172 }
1173
1174 static void
1175 clip_distance_discard(struct vc4_compile *c)
1176 {
1177 for (int i = 0; i < PIPE_MAX_CLIP_PLANES; i++) {
1178 if (!(c->key->ucp_enables & (1 << i)))
1179 continue;
1180
1181 struct qreg dist = emit_fragment_varying(c,
1182 TGSI_SEMANTIC_CLIPDIST,
1183 i,
1184 TGSI_SWIZZLE_X);
1185
1186 qir_SF(c, dist);
1187
1188 if (c->discard.file == QFILE_NULL)
1189 c->discard = qir_uniform_ui(c, 0);
1190
1191 c->discard = qir_SEL_X_Y_NS(c, qir_uniform_ui(c, ~0),
1192 c->discard);
1193 }
1194 }
1195
1196 static void
1197 alpha_test_discard(struct vc4_compile *c)
1198 {
1199 struct qreg src_alpha;
1200 struct qreg alpha_ref = qir_uniform(c, QUNIFORM_ALPHA_REF, 0);
1201
1202 if (!c->fs_key->alpha_test)
1203 return;
1204
1205 if (c->output_color_index != -1)
1206 src_alpha = c->outputs[c->output_color_index + 3];
1207 else
1208 src_alpha = qir_uniform_f(c, 1.0);
1209
1210 if (c->discard.file == QFILE_NULL)
1211 c->discard = qir_uniform_ui(c, 0);
1212
1213 switch (c->fs_key->alpha_test_func) {
1214 case PIPE_FUNC_NEVER:
1215 c->discard = qir_uniform_ui(c, ~0);
1216 break;
1217 case PIPE_FUNC_ALWAYS:
1218 break;
1219 case PIPE_FUNC_EQUAL:
1220 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1221 c->discard = qir_SEL_X_Y_ZS(c, c->discard,
1222 qir_uniform_ui(c, ~0));
1223 break;
1224 case PIPE_FUNC_NOTEQUAL:
1225 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1226 c->discard = qir_SEL_X_Y_ZC(c, c->discard,
1227 qir_uniform_ui(c, ~0));
1228 break;
1229 case PIPE_FUNC_GREATER:
1230 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1231 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1232 qir_uniform_ui(c, ~0));
1233 break;
1234 case PIPE_FUNC_GEQUAL:
1235 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1236 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1237 qir_uniform_ui(c, ~0));
1238 break;
1239 case PIPE_FUNC_LESS:
1240 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1241 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1242 qir_uniform_ui(c, ~0));
1243 break;
1244 case PIPE_FUNC_LEQUAL:
1245 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1246 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1247 qir_uniform_ui(c, ~0));
1248 break;
1249 }
1250 }
1251
1252 static struct qreg
1253 vc4_logicop(struct vc4_compile *c, struct qreg src, struct qreg dst)
1254 {
1255 switch (c->fs_key->logicop_func) {
1256 case PIPE_LOGICOP_CLEAR:
1257 return qir_uniform_f(c, 0.0);
1258 case PIPE_LOGICOP_NOR:
1259 return qir_NOT(c, qir_OR(c, src, dst));
1260 case PIPE_LOGICOP_AND_INVERTED:
1261 return qir_AND(c, qir_NOT(c, src), dst);
1262 case PIPE_LOGICOP_COPY_INVERTED:
1263 return qir_NOT(c, src);
1264 case PIPE_LOGICOP_AND_REVERSE:
1265 return qir_AND(c, src, qir_NOT(c, dst));
1266 case PIPE_LOGICOP_INVERT:
1267 return qir_NOT(c, dst);
1268 case PIPE_LOGICOP_XOR:
1269 return qir_XOR(c, src, dst);
1270 case PIPE_LOGICOP_NAND:
1271 return qir_NOT(c, qir_AND(c, src, dst));
1272 case PIPE_LOGICOP_AND:
1273 return qir_AND(c, src, dst);
1274 case PIPE_LOGICOP_EQUIV:
1275 return qir_NOT(c, qir_XOR(c, src, dst));
1276 case PIPE_LOGICOP_NOOP:
1277 return dst;
1278 case PIPE_LOGICOP_OR_INVERTED:
1279 return qir_OR(c, qir_NOT(c, src), dst);
1280 case PIPE_LOGICOP_OR_REVERSE:
1281 return qir_OR(c, src, qir_NOT(c, dst));
1282 case PIPE_LOGICOP_OR:
1283 return qir_OR(c, src, dst);
1284 case PIPE_LOGICOP_SET:
1285 return qir_uniform_ui(c, ~0);
1286 case PIPE_LOGICOP_COPY:
1287 default:
1288 return src;
1289 }
1290 }
1291
1292 /**
1293 * Applies the GL blending pipeline and returns the packed (8888) output
1294 * color.
1295 */
1296 static struct qreg
1297 blend_pipeline(struct vc4_compile *c)
1298 {
1299 enum pipe_format color_format = c->fs_key->color_format;
1300 const uint8_t *format_swiz = vc4_get_format_swizzle(color_format);
1301 struct qreg tlb_read_color[4] = { c->undef, c->undef, c->undef, c->undef };
1302 struct qreg dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1303 struct qreg linear_dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1304 struct qreg packed_dst_color = c->undef;
1305
1306 if (c->fs_key->blend.blend_enable ||
1307 c->fs_key->blend.colormask != 0xf ||
1308 c->fs_key->logicop_func != PIPE_LOGICOP_COPY) {
1309 struct qreg r4 = qir_TLB_COLOR_READ(c);
1310 for (int i = 0; i < 4; i++)
1311 tlb_read_color[i] = qir_R4_UNPACK(c, r4, i);
1312 for (int i = 0; i < 4; i++) {
1313 dst_color[i] = get_swizzled_channel(c,
1314 tlb_read_color,
1315 format_swiz[i]);
1316 if (util_format_is_srgb(color_format) && i != 3) {
1317 linear_dst_color[i] =
1318 qir_srgb_decode(c, dst_color[i]);
1319 } else {
1320 linear_dst_color[i] = dst_color[i];
1321 }
1322 }
1323
1324 /* Save the packed value for logic ops. Can't reuse r4
1325 * because other things might smash it (like sRGB)
1326 */
1327 packed_dst_color = qir_MOV(c, r4);
1328 }
1329
1330 struct qreg undef_array[4] = { c->undef, c->undef, c->undef, c->undef };
1331 const struct qreg *output_colors = (c->output_color_index != -1 ?
1332 c->outputs + c->output_color_index :
1333 undef_array);
1334 struct qreg blend_src_color[4];
1335 for (int i = 0; i < 4; i++)
1336 blend_src_color[i] = output_colors[i];
1337
1338 struct qreg blend_color[4];
1339 vc4_blend(c, blend_color, linear_dst_color, blend_src_color);
1340
1341 if (util_format_is_srgb(color_format)) {
1342 for (int i = 0; i < 3; i++)
1343 blend_color[i] = qir_srgb_encode(c, blend_color[i]);
1344 }
1345
1346 /* Debug: Sometimes you're getting a black output and just want to see
1347 * if the FS is getting executed at all. Spam magenta into the color
1348 * output.
1349 */
1350 if (0) {
1351 blend_color[0] = qir_uniform_f(c, 1.0);
1352 blend_color[1] = qir_uniform_f(c, 0.0);
1353 blend_color[2] = qir_uniform_f(c, 1.0);
1354 blend_color[3] = qir_uniform_f(c, 0.5);
1355 }
1356
1357 struct qreg swizzled_outputs[4];
1358 for (int i = 0; i < 4; i++) {
1359 swizzled_outputs[i] = get_swizzled_channel(c, blend_color,
1360 format_swiz[i]);
1361 }
1362
1363 struct qreg packed_color = c->undef;
1364 for (int i = 0; i < 4; i++) {
1365 if (swizzled_outputs[i].file == QFILE_NULL)
1366 continue;
1367 if (packed_color.file == QFILE_NULL) {
1368 packed_color = qir_PACK_8888_F(c, swizzled_outputs[i]);
1369 } else {
1370 packed_color = qir_PACK_8_F(c,
1371 packed_color,
1372 swizzled_outputs[i],
1373 i);
1374 }
1375 }
1376
1377 if (packed_color.file == QFILE_NULL)
1378 packed_color = qir_uniform_ui(c, 0);
1379
1380 if (c->fs_key->logicop_func != PIPE_LOGICOP_COPY) {
1381 packed_color = vc4_logicop(c, packed_color, packed_dst_color);
1382 }
1383
1384 /* If the bit isn't set in the color mask, then just return the
1385 * original dst color, instead.
1386 */
1387 uint32_t colormask = 0xffffffff;
1388 for (int i = 0; i < 4; i++) {
1389 if (format_swiz[i] < 4 &&
1390 !(c->fs_key->blend.colormask & (1 << format_swiz[i]))) {
1391 colormask &= ~(0xff << (i * 8));
1392 }
1393 }
1394 if (colormask != 0xffffffff) {
1395 packed_color = qir_OR(c,
1396 qir_AND(c, packed_color,
1397 qir_uniform_ui(c, colormask)),
1398 qir_AND(c, packed_dst_color,
1399 qir_uniform_ui(c, ~colormask)));
1400 }
1401
1402 return packed_color;
1403 }
1404
1405 static void
1406 emit_frag_end(struct vc4_compile *c)
1407 {
1408 clip_distance_discard(c);
1409 alpha_test_discard(c);
1410 struct qreg color = blend_pipeline(c);
1411
1412 if (c->discard.file != QFILE_NULL)
1413 qir_TLB_DISCARD_SETUP(c, c->discard);
1414
1415 if (c->fs_key->stencil_enabled) {
1416 qir_TLB_STENCIL_SETUP(c, qir_uniform(c, QUNIFORM_STENCIL, 0));
1417 if (c->fs_key->stencil_twoside) {
1418 qir_TLB_STENCIL_SETUP(c, qir_uniform(c, QUNIFORM_STENCIL, 1));
1419 }
1420 if (c->fs_key->stencil_full_writemasks) {
1421 qir_TLB_STENCIL_SETUP(c, qir_uniform(c, QUNIFORM_STENCIL, 2));
1422 }
1423 }
1424
1425 if (c->fs_key->depth_enabled) {
1426 struct qreg z;
1427 if (c->output_position_index != -1) {
1428 z = qir_FTOI(c, qir_FMUL(c, c->outputs[c->output_position_index + 2],
1429 qir_uniform_f(c, 0xffffff)));
1430 } else {
1431 z = qir_FRAG_Z(c);
1432 }
1433 qir_TLB_Z_WRITE(c, z);
1434 }
1435
1436 qir_TLB_COLOR_WRITE(c, color);
1437 }
1438
1439 static void
1440 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1441 {
1442 struct qreg xyi[2];
1443
1444 for (int i = 0; i < 2; i++) {
1445 struct qreg scale =
1446 qir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1447
1448 xyi[i] = qir_FTOI(c, qir_FMUL(c,
1449 qir_FMUL(c,
1450 c->outputs[c->output_position_index + i],
1451 scale),
1452 rcp_w));
1453 }
1454
1455 qir_VPM_WRITE(c, qir_PACK_SCALED(c, xyi[0], xyi[1]));
1456 }
1457
1458 static void
1459 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1460 {
1461 struct qreg zscale = qir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1462 struct qreg zoffset = qir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1463
1464 qir_VPM_WRITE(c, qir_FADD(c, qir_FMUL(c, qir_FMUL(c,
1465 c->outputs[c->output_position_index + 2],
1466 zscale),
1467 rcp_w),
1468 zoffset));
1469 }
1470
1471 static void
1472 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1473 {
1474 qir_VPM_WRITE(c, rcp_w);
1475 }
1476
1477 static void
1478 emit_point_size_write(struct vc4_compile *c)
1479 {
1480 struct qreg point_size;
1481
1482 if (c->output_point_size_index != -1)
1483 point_size = c->outputs[c->output_point_size_index + 3];
1484 else
1485 point_size = qir_uniform_f(c, 1.0);
1486
1487 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1488 * BCM21553).
1489 */
1490 point_size = qir_FMAX(c, point_size, qir_uniform_f(c, .125));
1491
1492 qir_VPM_WRITE(c, point_size);
1493 }
1494
1495 /**
1496 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1497 *
1498 * The simulator insists that there be at least one vertex attribute, so
1499 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also
1500 * insists that all vertex attributes loaded get read by the VS/CS, so we have
1501 * to consume it here.
1502 */
1503 static void
1504 emit_stub_vpm_read(struct vc4_compile *c)
1505 {
1506 if (c->num_inputs)
1507 return;
1508
1509 c->vattr_sizes[0] = 4;
1510 struct qreg vpm = { QFILE_VPM, 0 };
1511 (void)qir_MOV(c, vpm);
1512 c->num_inputs++;
1513 }
1514
1515 static void
1516 emit_ucp_clipdistance(struct vc4_compile *c)
1517 {
1518 unsigned cv;
1519 if (c->output_clipvertex_index != -1)
1520 cv = c->output_clipvertex_index;
1521 else if (c->output_position_index != -1)
1522 cv = c->output_position_index;
1523 else
1524 return;
1525
1526 for (int plane = 0; plane < PIPE_MAX_CLIP_PLANES; plane++) {
1527 if (!(c->key->ucp_enables & (1 << plane)))
1528 continue;
1529
1530 /* Pick the next outputs[] that hasn't been written to, since
1531 * there are no other program writes left to be processed at
1532 * this point. If something had been declared but not written
1533 * (like a w component), we'll just smash over the top of it.
1534 */
1535 uint32_t output_index = c->num_outputs++;
1536 add_output(c, output_index,
1537 TGSI_SEMANTIC_CLIPDIST,
1538 plane,
1539 TGSI_SWIZZLE_X);
1540
1541
1542 struct qreg dist = qir_uniform_f(c, 0.0);
1543 for (int i = 0; i < 4; i++) {
1544 struct qreg pos_chan = c->outputs[cv + i];
1545 struct qreg ucp =
1546 qir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1547 plane * 4 + i);
1548 dist = qir_FADD(c, dist, qir_FMUL(c, pos_chan, ucp));
1549 }
1550
1551 c->outputs[output_index] = dist;
1552 }
1553 }
1554
1555 static void
1556 emit_vert_end(struct vc4_compile *c,
1557 struct vc4_varying_semantic *fs_inputs,
1558 uint32_t num_fs_inputs)
1559 {
1560 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1561
1562 emit_stub_vpm_read(c);
1563 emit_ucp_clipdistance(c);
1564
1565 emit_scaled_viewport_write(c, rcp_w);
1566 emit_zs_write(c, rcp_w);
1567 emit_rcp_wc_write(c, rcp_w);
1568 if (c->vs_key->per_vertex_point_size)
1569 emit_point_size_write(c);
1570
1571 for (int i = 0; i < num_fs_inputs; i++) {
1572 struct vc4_varying_semantic *input = &fs_inputs[i];
1573 int j;
1574
1575 for (j = 0; j < c->num_outputs; j++) {
1576 struct vc4_varying_semantic *output =
1577 &c->output_semantics[j];
1578
1579 if (input->semantic == output->semantic &&
1580 input->index == output->index &&
1581 input->swizzle == output->swizzle) {
1582 qir_VPM_WRITE(c, c->outputs[j]);
1583 break;
1584 }
1585 }
1586 /* Emit padding if we didn't find a declared VS output for
1587 * this FS input.
1588 */
1589 if (j == c->num_outputs)
1590 qir_VPM_WRITE(c, qir_uniform_f(c, 0.0));
1591 }
1592 }
1593
1594 static void
1595 emit_coord_end(struct vc4_compile *c)
1596 {
1597 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1598
1599 emit_stub_vpm_read(c);
1600
1601 for (int i = 0; i < 4; i++)
1602 qir_VPM_WRITE(c, c->outputs[c->output_position_index + i]);
1603
1604 emit_scaled_viewport_write(c, rcp_w);
1605 emit_zs_write(c, rcp_w);
1606 emit_rcp_wc_write(c, rcp_w);
1607 if (c->vs_key->per_vertex_point_size)
1608 emit_point_size_write(c);
1609 }
1610
1611 static void
1612 vc4_optimize_nir(struct nir_shader *s)
1613 {
1614 bool progress;
1615
1616 do {
1617 progress = false;
1618
1619 nir_lower_vars_to_ssa(s);
1620 nir_lower_alu_to_scalar(s);
1621
1622 progress = nir_copy_prop(s) || progress;
1623 progress = nir_opt_dce(s) || progress;
1624 progress = nir_opt_cse(s) || progress;
1625 progress = nir_opt_peephole_select(s) || progress;
1626 progress = nir_opt_algebraic(s) || progress;
1627 progress = nir_opt_constant_folding(s) || progress;
1628 } while (progress);
1629 }
1630
1631 static int
1632 driver_location_compare(const void *in_a, const void *in_b)
1633 {
1634 const nir_variable *const *a = in_a;
1635 const nir_variable *const *b = in_b;
1636
1637 return (*a)->data.driver_location - (*b)->data.driver_location;
1638 }
1639
1640 static void
1641 ntq_setup_inputs(struct vc4_compile *c)
1642 {
1643 unsigned num_entries = 0;
1644 foreach_list_typed(nir_variable, var, node, &c->s->inputs)
1645 num_entries++;
1646
1647 nir_variable *vars[num_entries];
1648
1649 unsigned i = 0;
1650 foreach_list_typed(nir_variable, var, node, &c->s->inputs)
1651 vars[i++] = var;
1652
1653 /* Sort the variables so that we emit the input setup in
1654 * driver_location order. This is required for VPM reads, whose data
1655 * is fetched into the VPM in driver_location (TGSI register index)
1656 * order.
1657 */
1658 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1659
1660 for (unsigned i = 0; i < num_entries; i++) {
1661 nir_variable *var = vars[i];
1662 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1663 /* XXX: map loc slots to semantics */
1664 unsigned semantic_name = var->data.location;
1665 unsigned semantic_index = var->data.index;
1666 unsigned loc = var->data.driver_location;
1667
1668 assert(array_len == 1);
1669 (void)array_len;
1670 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1671 (loc + 1) * 4);
1672
1673 if (c->stage == QSTAGE_FRAG) {
1674 if (semantic_name == TGSI_SEMANTIC_POSITION) {
1675 emit_fragcoord_input(c, loc);
1676 } else if (semantic_name == TGSI_SEMANTIC_FACE) {
1677 c->inputs[loc * 4 + 0] = qir_FRAG_REV_FLAG(c);
1678 } else if (semantic_name == TGSI_SEMANTIC_GENERIC &&
1679 (c->fs_key->point_sprite_mask &
1680 (1 << semantic_index))) {
1681 c->inputs[loc * 4 + 0] = c->point_x;
1682 c->inputs[loc * 4 + 1] = c->point_y;
1683 } else {
1684 emit_fragment_input(c, loc,
1685 semantic_name,
1686 semantic_index);
1687 }
1688 } else {
1689 emit_vertex_input(c, loc);
1690 }
1691 }
1692 }
1693
1694 static void
1695 ntq_setup_outputs(struct vc4_compile *c)
1696 {
1697 foreach_list_typed(nir_variable, var, node, &c->s->outputs) {
1698 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1699 /* XXX: map loc slots to semantics */
1700 unsigned semantic_name = var->data.location;
1701 unsigned semantic_index = var->data.index;
1702 unsigned loc = var->data.driver_location * 4;
1703
1704 assert(array_len == 1);
1705 (void)array_len;
1706
1707 /* NIR hack to pass through
1708 * TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS */
1709 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1710 semantic_index == -1)
1711 semantic_index = 0;
1712
1713 for (int i = 0; i < 4; i++) {
1714 add_output(c,
1715 loc + i,
1716 semantic_name,
1717 semantic_index,
1718 i);
1719 }
1720
1721 switch (semantic_name) {
1722 case TGSI_SEMANTIC_POSITION:
1723 c->output_position_index = loc;
1724 break;
1725 case TGSI_SEMANTIC_CLIPVERTEX:
1726 c->output_clipvertex_index = loc;
1727 break;
1728 case TGSI_SEMANTIC_COLOR:
1729 c->output_color_index = loc;
1730 break;
1731 case TGSI_SEMANTIC_PSIZE:
1732 c->output_point_size_index = loc;
1733 break;
1734 }
1735
1736 }
1737 }
1738
1739 static void
1740 ntq_setup_uniforms(struct vc4_compile *c)
1741 {
1742 foreach_list_typed(nir_variable, var, node, &c->s->uniforms) {
1743 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1744 unsigned array_elem_size = 4 * sizeof(float);
1745
1746 declare_uniform_range(c, var->data.driver_location * array_elem_size,
1747 array_len * array_elem_size);
1748
1749 }
1750 }
1751
1752 /**
1753 * Sets up the mapping from nir_register to struct qreg *.
1754 *
1755 * Each nir_register gets a struct qreg per 32-bit component being stored.
1756 */
1757 static void
1758 ntq_setup_registers(struct vc4_compile *c, struct exec_list *list)
1759 {
1760 foreach_list_typed(nir_register, nir_reg, node, list) {
1761 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1762 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1763 array_len *
1764 nir_reg->num_components);
1765
1766 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1767
1768 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1769 qregs[i] = qir_uniform_ui(c, 0);
1770 }
1771 }
1772
1773 static void
1774 ntq_emit_load_const(struct vc4_compile *c, nir_load_const_instr *instr)
1775 {
1776 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1777 instr->def.num_components);
1778 for (int i = 0; i < instr->def.num_components; i++)
1779 qregs[i] = qir_uniform_ui(c, instr->value.u[i]);
1780
1781 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1782 }
1783
1784 static void
1785 ntq_emit_intrinsic(struct vc4_compile *c, nir_intrinsic_instr *instr)
1786 {
1787 const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
1788 struct qreg *dest = NULL;
1789
1790 if (info->has_dest) {
1791 dest = ntq_get_dest(c, instr->dest);
1792 }
1793
1794 switch (instr->intrinsic) {
1795 case nir_intrinsic_load_uniform:
1796 for (int i = 0; i < instr->num_components; i++) {
1797 dest[i] = qir_uniform(c, QUNIFORM_UNIFORM,
1798 instr->const_index[0] * 4 + i);
1799 }
1800 break;
1801
1802 case nir_intrinsic_load_uniform_indirect:
1803 for (int i = 0; i < instr->num_components; i++) {
1804 dest[i] = indirect_uniform_load(c,
1805 ntq_get_src(c, instr->src[0], 0),
1806 (instr->const_index[0] *
1807 4 + i) * sizeof(float));
1808 }
1809
1810 break;
1811
1812 case nir_intrinsic_load_input:
1813 assert(instr->num_components == 1);
1814 *dest = c->inputs[instr->const_index[0]];
1815
1816 break;
1817
1818 case nir_intrinsic_store_output:
1819 assert(instr->num_components == 1);
1820 c->outputs[instr->const_index[0]] =
1821 qir_MOV(c, ntq_get_src(c, instr->src[0], 0));
1822 c->num_outputs = MAX2(c->num_outputs, instr->const_index[0] + 1);
1823 break;
1824
1825 case nir_intrinsic_discard:
1826 c->discard = qir_uniform_ui(c, ~0);
1827 break;
1828
1829 case nir_intrinsic_discard_if:
1830 if (c->discard.file == QFILE_NULL)
1831 c->discard = qir_uniform_ui(c, 0);
1832 c->discard = qir_OR(c, c->discard,
1833 ntq_get_src(c, instr->src[0], 0));
1834 break;
1835
1836 default:
1837 fprintf(stderr, "Unknown intrinsic: ");
1838 nir_print_instr(&instr->instr, stderr);
1839 fprintf(stderr, "\n");
1840 break;
1841 }
1842 }
1843
1844 static void
1845 ntq_emit_if(struct vc4_compile *c, nir_if *if_stmt)
1846 {
1847 fprintf(stderr, "general IF statements not handled.\n");
1848 }
1849
1850 static void
1851 ntq_emit_instr(struct vc4_compile *c, nir_instr *instr)
1852 {
1853 switch (instr->type) {
1854 case nir_instr_type_alu:
1855 ntq_emit_alu(c, nir_instr_as_alu(instr));
1856 break;
1857
1858 case nir_instr_type_intrinsic:
1859 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
1860 break;
1861
1862 case nir_instr_type_load_const:
1863 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
1864 break;
1865
1866 case nir_instr_type_tex:
1867 ntq_emit_tex(c, nir_instr_as_tex(instr));
1868 break;
1869
1870 default:
1871 fprintf(stderr, "Unknown NIR instr type: ");
1872 nir_print_instr(instr, stderr);
1873 fprintf(stderr, "\n");
1874 abort();
1875 }
1876 }
1877
1878 static void
1879 ntq_emit_block(struct vc4_compile *c, nir_block *block)
1880 {
1881 nir_foreach_instr(block, instr) {
1882 ntq_emit_instr(c, instr);
1883 }
1884 }
1885
1886 static void
1887 ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list)
1888 {
1889 foreach_list_typed(nir_cf_node, node, node, list) {
1890 switch (node->type) {
1891 /* case nir_cf_node_loop: */
1892 case nir_cf_node_block:
1893 ntq_emit_block(c, nir_cf_node_as_block(node));
1894 break;
1895
1896 case nir_cf_node_if:
1897 ntq_emit_if(c, nir_cf_node_as_if(node));
1898 break;
1899
1900 default:
1901 assert(0);
1902 }
1903 }
1904 }
1905
1906 static void
1907 ntq_emit_impl(struct vc4_compile *c, nir_function_impl *impl)
1908 {
1909 ntq_setup_registers(c, &impl->registers);
1910 ntq_emit_cf_list(c, &impl->body);
1911 }
1912
1913 static void
1914 nir_to_qir(struct vc4_compile *c)
1915 {
1916 ntq_setup_inputs(c);
1917 ntq_setup_outputs(c);
1918 ntq_setup_uniforms(c);
1919 ntq_setup_registers(c, &c->s->registers);
1920
1921 /* Find the main function and emit the body. */
1922 nir_foreach_overload(c->s, overload) {
1923 assert(strcmp(overload->function->name, "main") == 0);
1924 assert(overload->impl);
1925 ntq_emit_impl(c, overload->impl);
1926 }
1927 }
1928
1929 static const nir_shader_compiler_options nir_options = {
1930 .lower_ffma = true,
1931 .lower_flrp = true,
1932 .lower_fpow = true,
1933 .lower_fsat = true,
1934 .lower_fsqrt = true,
1935 .lower_negate = true,
1936 };
1937
1938 static bool
1939 count_nir_instrs_in_block(nir_block *block, void *state)
1940 {
1941 int *count = (int *) state;
1942 nir_foreach_instr(block, instr) {
1943 *count = *count + 1;
1944 }
1945 return true;
1946 }
1947
1948 static int
1949 count_nir_instrs(nir_shader *nir)
1950 {
1951 int count = 0;
1952 nir_foreach_overload(nir, overload) {
1953 if (!overload->impl)
1954 continue;
1955 nir_foreach_block(overload->impl, count_nir_instrs_in_block, &count);
1956 }
1957 return count;
1958 }
1959
1960 static struct vc4_compile *
1961 vc4_shader_ntq(struct vc4_context *vc4, enum qstage stage,
1962 struct vc4_key *key)
1963 {
1964 struct vc4_compile *c = qir_compile_init();
1965
1966 c->stage = stage;
1967 c->shader_state = &key->shader_state->base;
1968 c->program_id = key->shader_state->program_id;
1969 c->variant_id = key->shader_state->compiled_variant_count++;
1970
1971 c->key = key;
1972 switch (stage) {
1973 case QSTAGE_FRAG:
1974 c->fs_key = (struct vc4_fs_key *)key;
1975 if (c->fs_key->is_points) {
1976 c->point_x = emit_fragment_varying(c, ~0, ~0, 0);
1977 c->point_y = emit_fragment_varying(c, ~0, ~0, 0);
1978 } else if (c->fs_key->is_lines) {
1979 c->line_x = emit_fragment_varying(c, ~0, ~0, 0);
1980 }
1981 break;
1982 case QSTAGE_VERT:
1983 c->vs_key = (struct vc4_vs_key *)key;
1984 break;
1985 case QSTAGE_COORD:
1986 c->vs_key = (struct vc4_vs_key *)key;
1987 break;
1988 }
1989
1990 const struct tgsi_token *tokens = key->shader_state->base.tokens;
1991 if (c->fs_key && c->fs_key->light_twoside) {
1992 if (!key->shader_state->twoside_tokens) {
1993 const struct tgsi_lowering_config lowering_config = {
1994 .color_two_side = true,
1995 };
1996 struct tgsi_shader_info info;
1997 key->shader_state->twoside_tokens =
1998 tgsi_transform_lowering(&lowering_config,
1999 key->shader_state->base.tokens,
2000 &info);
2001
2002 /* If no transformation occurred, then NULL is
2003 * returned and we just use our original tokens.
2004 */
2005 if (!key->shader_state->twoside_tokens) {
2006 key->shader_state->twoside_tokens =
2007 key->shader_state->base.tokens;
2008 }
2009 }
2010 tokens = key->shader_state->twoside_tokens;
2011 }
2012
2013 if (vc4_debug & VC4_DEBUG_TGSI) {
2014 fprintf(stderr, "%s prog %d/%d TGSI:\n",
2015 qir_get_stage_name(c->stage),
2016 c->program_id, c->variant_id);
2017 tgsi_dump(tokens, 0);
2018 }
2019
2020 c->s = tgsi_to_nir(tokens, &nir_options);
2021 nir_opt_global_to_local(c->s);
2022 nir_convert_to_ssa(c->s);
2023 vc4_nir_lower_io(c);
2024 nir_lower_idiv(c->s);
2025
2026 vc4_optimize_nir(c->s);
2027
2028 nir_remove_dead_variables(c->s);
2029
2030 nir_convert_from_ssa(c->s, false);
2031
2032 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2033 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d NIR instructions\n",
2034 qir_get_stage_name(c->stage),
2035 c->program_id, c->variant_id,
2036 count_nir_instrs(c->s));
2037 }
2038
2039 if (vc4_debug & VC4_DEBUG_NIR) {
2040 fprintf(stderr, "%s prog %d/%d NIR:\n",
2041 qir_get_stage_name(c->stage),
2042 c->program_id, c->variant_id);
2043 nir_print_shader(c->s, stderr);
2044 }
2045
2046 nir_to_qir(c);
2047
2048 switch (stage) {
2049 case QSTAGE_FRAG:
2050 emit_frag_end(c);
2051 break;
2052 case QSTAGE_VERT:
2053 emit_vert_end(c,
2054 vc4->prog.fs->input_semantics,
2055 vc4->prog.fs->num_inputs);
2056 break;
2057 case QSTAGE_COORD:
2058 emit_coord_end(c);
2059 break;
2060 }
2061
2062 if (vc4_debug & VC4_DEBUG_QIR) {
2063 fprintf(stderr, "%s prog %d/%d pre-opt QIR:\n",
2064 qir_get_stage_name(c->stage),
2065 c->program_id, c->variant_id);
2066 qir_dump(c);
2067 }
2068
2069 qir_optimize(c);
2070 qir_lower_uniforms(c);
2071
2072 if (vc4_debug & VC4_DEBUG_QIR) {
2073 fprintf(stderr, "%s prog %d/%d QIR:\n",
2074 qir_get_stage_name(c->stage),
2075 c->program_id, c->variant_id);
2076 qir_dump(c);
2077 }
2078 qir_reorder_uniforms(c);
2079 vc4_generate_code(vc4, c);
2080
2081 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2082 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d instructions\n",
2083 qir_get_stage_name(c->stage),
2084 c->program_id, c->variant_id,
2085 c->qpu_inst_count);
2086 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d uniforms\n",
2087 qir_get_stage_name(c->stage),
2088 c->program_id, c->variant_id,
2089 c->num_uniforms);
2090 }
2091
2092 ralloc_free(c->s);
2093
2094 return c;
2095 }
2096
2097 static void *
2098 vc4_shader_state_create(struct pipe_context *pctx,
2099 const struct pipe_shader_state *cso)
2100 {
2101 struct vc4_context *vc4 = vc4_context(pctx);
2102 struct vc4_uncompiled_shader *so = CALLOC_STRUCT(vc4_uncompiled_shader);
2103 if (!so)
2104 return NULL;
2105
2106 so->base.tokens = tgsi_dup_tokens(cso->tokens);
2107 so->program_id = vc4->next_uncompiled_program_id++;
2108
2109 return so;
2110 }
2111
2112 static void
2113 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
2114 struct vc4_compile *c)
2115 {
2116 int count = c->num_uniforms;
2117 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
2118
2119 uinfo->count = count;
2120 uinfo->data = ralloc_array(shader, uint32_t, count);
2121 memcpy(uinfo->data, c->uniform_data,
2122 count * sizeof(*uinfo->data));
2123 uinfo->contents = ralloc_array(shader, enum quniform_contents, count);
2124 memcpy(uinfo->contents, c->uniform_contents,
2125 count * sizeof(*uinfo->contents));
2126 uinfo->num_texture_samples = c->num_texture_samples;
2127
2128 vc4_set_shader_uniform_dirty_flags(shader);
2129 }
2130
2131 static struct vc4_compiled_shader *
2132 vc4_get_compiled_shader(struct vc4_context *vc4, enum qstage stage,
2133 struct vc4_key *key)
2134 {
2135 struct hash_table *ht;
2136 uint32_t key_size;
2137 if (stage == QSTAGE_FRAG) {
2138 ht = vc4->fs_cache;
2139 key_size = sizeof(struct vc4_fs_key);
2140 } else {
2141 ht = vc4->vs_cache;
2142 key_size = sizeof(struct vc4_vs_key);
2143 }
2144
2145 struct vc4_compiled_shader *shader;
2146 struct hash_entry *entry = _mesa_hash_table_search(ht, key);
2147 if (entry)
2148 return entry->data;
2149
2150 struct vc4_compile *c = vc4_shader_ntq(vc4, stage, key);
2151 shader = rzalloc(NULL, struct vc4_compiled_shader);
2152
2153 shader->program_id = vc4->next_compiled_program_id++;
2154 if (stage == QSTAGE_FRAG) {
2155 bool input_live[c->num_input_semantics];
2156
2157 memset(input_live, 0, sizeof(input_live));
2158 list_for_each_entry(struct qinst, inst, &c->instructions, link) {
2159 for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) {
2160 if (inst->src[i].file == QFILE_VARY)
2161 input_live[inst->src[i].index] = true;
2162 }
2163 }
2164
2165 shader->input_semantics = ralloc_array(shader,
2166 struct vc4_varying_semantic,
2167 c->num_input_semantics);
2168
2169 for (int i = 0; i < c->num_input_semantics; i++) {
2170 struct vc4_varying_semantic *sem = &c->input_semantics[i];
2171
2172 if (!input_live[i])
2173 continue;
2174
2175 /* Skip non-VS-output inputs. */
2176 if (sem->semantic == (uint8_t)~0)
2177 continue;
2178
2179 if (sem->semantic == TGSI_SEMANTIC_COLOR ||
2180 sem->semantic == TGSI_SEMANTIC_BCOLOR) {
2181 shader->color_inputs |= (1 << shader->num_inputs);
2182 }
2183
2184 shader->input_semantics[shader->num_inputs] = *sem;
2185 shader->num_inputs++;
2186 }
2187 } else {
2188 shader->num_inputs = c->num_inputs;
2189
2190 shader->vattr_offsets[0] = 0;
2191 for (int i = 0; i < 8; i++) {
2192 shader->vattr_offsets[i + 1] =
2193 shader->vattr_offsets[i] + c->vattr_sizes[i];
2194
2195 if (c->vattr_sizes[i])
2196 shader->vattrs_live |= (1 << i);
2197 }
2198 }
2199
2200 copy_uniform_state_to_shader(shader, c);
2201 shader->bo = vc4_bo_alloc_shader(vc4->screen, c->qpu_insts,
2202 c->qpu_inst_count * sizeof(uint64_t));
2203
2204 /* Copy the compiler UBO range state to the compiled shader, dropping
2205 * out arrays that were never referenced by an indirect load.
2206 *
2207 * (Note that QIR dead code elimination of an array access still
2208 * leaves that array alive, though)
2209 */
2210 if (c->num_ubo_ranges) {
2211 shader->num_ubo_ranges = c->num_ubo_ranges;
2212 shader->ubo_ranges = ralloc_array(shader, struct vc4_ubo_range,
2213 c->num_ubo_ranges);
2214 uint32_t j = 0;
2215 for (int i = 0; i < c->num_uniform_ranges; i++) {
2216 struct vc4_compiler_ubo_range *range =
2217 &c->ubo_ranges[i];
2218 if (!range->used)
2219 continue;
2220
2221 shader->ubo_ranges[j].dst_offset = range->dst_offset;
2222 shader->ubo_ranges[j].src_offset = range->src_offset;
2223 shader->ubo_ranges[j].size = range->size;
2224 shader->ubo_size += c->ubo_ranges[i].size;
2225 j++;
2226 }
2227 }
2228 if (shader->ubo_size) {
2229 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2230 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d UBO uniforms\n",
2231 qir_get_stage_name(c->stage),
2232 c->program_id, c->variant_id,
2233 shader->ubo_size / 4);
2234 }
2235 }
2236
2237 qir_compile_destroy(c);
2238
2239 struct vc4_key *dup_key;
2240 dup_key = ralloc_size(shader, key_size);
2241 memcpy(dup_key, key, key_size);
2242 _mesa_hash_table_insert(ht, dup_key, shader);
2243
2244 return shader;
2245 }
2246
2247 static void
2248 vc4_setup_shared_key(struct vc4_context *vc4, struct vc4_key *key,
2249 struct vc4_texture_stateobj *texstate)
2250 {
2251 for (int i = 0; i < texstate->num_textures; i++) {
2252 struct pipe_sampler_view *sampler = texstate->textures[i];
2253 struct pipe_sampler_state *sampler_state =
2254 texstate->samplers[i];
2255
2256 if (sampler) {
2257 key->tex[i].format = sampler->format;
2258 key->tex[i].swizzle[0] = sampler->swizzle_r;
2259 key->tex[i].swizzle[1] = sampler->swizzle_g;
2260 key->tex[i].swizzle[2] = sampler->swizzle_b;
2261 key->tex[i].swizzle[3] = sampler->swizzle_a;
2262 key->tex[i].compare_mode = sampler_state->compare_mode;
2263 key->tex[i].compare_func = sampler_state->compare_func;
2264 key->tex[i].wrap_s = sampler_state->wrap_s;
2265 key->tex[i].wrap_t = sampler_state->wrap_t;
2266 }
2267 }
2268
2269 key->ucp_enables = vc4->rasterizer->base.clip_plane_enable;
2270 }
2271
2272 static void
2273 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
2274 {
2275 struct vc4_fs_key local_key;
2276 struct vc4_fs_key *key = &local_key;
2277
2278 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2279 VC4_DIRTY_BLEND |
2280 VC4_DIRTY_FRAMEBUFFER |
2281 VC4_DIRTY_ZSA |
2282 VC4_DIRTY_RASTERIZER |
2283 VC4_DIRTY_FRAGTEX |
2284 VC4_DIRTY_TEXSTATE |
2285 VC4_DIRTY_UNCOMPILED_FS))) {
2286 return;
2287 }
2288
2289 memset(key, 0, sizeof(*key));
2290 vc4_setup_shared_key(vc4, &key->base, &vc4->fragtex);
2291 key->base.shader_state = vc4->prog.bind_fs;
2292 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
2293 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
2294 prim_mode <= PIPE_PRIM_LINE_STRIP);
2295 key->blend = vc4->blend->rt[0];
2296 if (vc4->blend->logicop_enable) {
2297 key->logicop_func = vc4->blend->logicop_func;
2298 } else {
2299 key->logicop_func = PIPE_LOGICOP_COPY;
2300 }
2301 if (vc4->framebuffer.cbufs[0])
2302 key->color_format = vc4->framebuffer.cbufs[0]->format;
2303
2304 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
2305 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
2306 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
2307 key->depth_enabled = (vc4->zsa->base.depth.enabled ||
2308 key->stencil_enabled);
2309 if (vc4->zsa->base.alpha.enabled) {
2310 key->alpha_test = true;
2311 key->alpha_test_func = vc4->zsa->base.alpha.func;
2312 }
2313
2314 if (key->is_points) {
2315 key->point_sprite_mask =
2316 vc4->rasterizer->base.sprite_coord_enable;
2317 key->point_coord_upper_left =
2318 (vc4->rasterizer->base.sprite_coord_mode ==
2319 PIPE_SPRITE_COORD_UPPER_LEFT);
2320 }
2321
2322 key->light_twoside = vc4->rasterizer->base.light_twoside;
2323
2324 struct vc4_compiled_shader *old_fs = vc4->prog.fs;
2325 vc4->prog.fs = vc4_get_compiled_shader(vc4, QSTAGE_FRAG, &key->base);
2326 if (vc4->prog.fs == old_fs)
2327 return;
2328
2329 vc4->dirty |= VC4_DIRTY_COMPILED_FS;
2330 if (vc4->rasterizer->base.flatshade &&
2331 old_fs && vc4->prog.fs->color_inputs != old_fs->color_inputs) {
2332 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
2333 }
2334 }
2335
2336 static void
2337 vc4_update_compiled_vs(struct vc4_context *vc4, uint8_t prim_mode)
2338 {
2339 struct vc4_vs_key local_key;
2340 struct vc4_vs_key *key = &local_key;
2341
2342 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2343 VC4_DIRTY_RASTERIZER |
2344 VC4_DIRTY_VERTTEX |
2345 VC4_DIRTY_TEXSTATE |
2346 VC4_DIRTY_VTXSTATE |
2347 VC4_DIRTY_UNCOMPILED_VS |
2348 VC4_DIRTY_COMPILED_FS))) {
2349 return;
2350 }
2351
2352 memset(key, 0, sizeof(*key));
2353 vc4_setup_shared_key(vc4, &key->base, &vc4->verttex);
2354 key->base.shader_state = vc4->prog.bind_vs;
2355 key->compiled_fs_id = vc4->prog.fs->program_id;
2356
2357 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
2358 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
2359
2360 key->per_vertex_point_size =
2361 (prim_mode == PIPE_PRIM_POINTS &&
2362 vc4->rasterizer->base.point_size_per_vertex);
2363
2364 struct vc4_compiled_shader *vs =
2365 vc4_get_compiled_shader(vc4, QSTAGE_VERT, &key->base);
2366 if (vs != vc4->prog.vs) {
2367 vc4->prog.vs = vs;
2368 vc4->dirty |= VC4_DIRTY_COMPILED_VS;
2369 }
2370
2371 key->is_coord = true;
2372 struct vc4_compiled_shader *cs =
2373 vc4_get_compiled_shader(vc4, QSTAGE_COORD, &key->base);
2374 if (cs != vc4->prog.cs) {
2375 vc4->prog.cs = cs;
2376 vc4->dirty |= VC4_DIRTY_COMPILED_CS;
2377 }
2378 }
2379
2380 void
2381 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
2382 {
2383 vc4_update_compiled_fs(vc4, prim_mode);
2384 vc4_update_compiled_vs(vc4, prim_mode);
2385 }
2386
2387 static uint32_t
2388 fs_cache_hash(const void *key)
2389 {
2390 return _mesa_hash_data(key, sizeof(struct vc4_fs_key));
2391 }
2392
2393 static uint32_t
2394 vs_cache_hash(const void *key)
2395 {
2396 return _mesa_hash_data(key, sizeof(struct vc4_vs_key));
2397 }
2398
2399 static bool
2400 fs_cache_compare(const void *key1, const void *key2)
2401 {
2402 return memcmp(key1, key2, sizeof(struct vc4_fs_key)) == 0;
2403 }
2404
2405 static bool
2406 vs_cache_compare(const void *key1, const void *key2)
2407 {
2408 return memcmp(key1, key2, sizeof(struct vc4_vs_key)) == 0;
2409 }
2410
2411 static void
2412 delete_from_cache_if_matches(struct hash_table *ht,
2413 struct hash_entry *entry,
2414 struct vc4_uncompiled_shader *so)
2415 {
2416 const struct vc4_key *key = entry->key;
2417
2418 if (key->shader_state == so) {
2419 struct vc4_compiled_shader *shader = entry->data;
2420 _mesa_hash_table_remove(ht, entry);
2421 vc4_bo_unreference(&shader->bo);
2422 ralloc_free(shader);
2423 }
2424 }
2425
2426 static void
2427 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
2428 {
2429 struct vc4_context *vc4 = vc4_context(pctx);
2430 struct vc4_uncompiled_shader *so = hwcso;
2431
2432 struct hash_entry *entry;
2433 hash_table_foreach(vc4->fs_cache, entry)
2434 delete_from_cache_if_matches(vc4->fs_cache, entry, so);
2435 hash_table_foreach(vc4->vs_cache, entry)
2436 delete_from_cache_if_matches(vc4->vs_cache, entry, so);
2437
2438 if (so->twoside_tokens != so->base.tokens)
2439 free((void *)so->twoside_tokens);
2440 free((void *)so->base.tokens);
2441 free(so);
2442 }
2443
2444 static void
2445 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
2446 {
2447 struct vc4_context *vc4 = vc4_context(pctx);
2448 vc4->prog.bind_fs = hwcso;
2449 vc4->dirty |= VC4_DIRTY_UNCOMPILED_FS;
2450 }
2451
2452 static void
2453 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
2454 {
2455 struct vc4_context *vc4 = vc4_context(pctx);
2456 vc4->prog.bind_vs = hwcso;
2457 vc4->dirty |= VC4_DIRTY_UNCOMPILED_VS;
2458 }
2459
2460 void
2461 vc4_program_init(struct pipe_context *pctx)
2462 {
2463 struct vc4_context *vc4 = vc4_context(pctx);
2464
2465 pctx->create_vs_state = vc4_shader_state_create;
2466 pctx->delete_vs_state = vc4_shader_state_delete;
2467
2468 pctx->create_fs_state = vc4_shader_state_create;
2469 pctx->delete_fs_state = vc4_shader_state_delete;
2470
2471 pctx->bind_fs_state = vc4_fp_state_bind;
2472 pctx->bind_vs_state = vc4_vp_state_bind;
2473
2474 vc4->fs_cache = _mesa_hash_table_create(pctx, fs_cache_hash,
2475 fs_cache_compare);
2476 vc4->vs_cache = _mesa_hash_table_create(pctx, vs_cache_hash,
2477 vs_cache_compare);
2478 }
2479
2480 void
2481 vc4_program_fini(struct pipe_context *pctx)
2482 {
2483 struct vc4_context *vc4 = vc4_context(pctx);
2484
2485 struct hash_entry *entry;
2486 hash_table_foreach(vc4->fs_cache, entry) {
2487 struct vc4_compiled_shader *shader = entry->data;
2488 vc4_bo_unreference(&shader->bo);
2489 ralloc_free(shader);
2490 _mesa_hash_table_remove(vc4->fs_cache, entry);
2491 }
2492
2493 hash_table_foreach(vc4->vs_cache, entry) {
2494 struct vc4_compiled_shader *shader = entry->data;
2495 vc4_bo_unreference(&shader->bo);
2496 ralloc_free(shader);
2497 _mesa_hash_table_remove(vc4->vs_cache, entry);
2498 }
2499 }