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vc4: Lower uniform loads to scalar in NIR.
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "util/u_format.h"
27 #include "util/u_hash.h"
28 #include "util/u_math.h"
29 #include "util/u_memory.h"
30 #include "util/ralloc.h"
31 #include "util/hash_table.h"
32 #include "tgsi/tgsi_dump.h"
33 #include "tgsi/tgsi_info.h"
34 #include "tgsi/tgsi_lowering.h"
35 #include "tgsi/tgsi_parse.h"
36 #include "nir/tgsi_to_nir.h"
37
38 #include "vc4_context.h"
39 #include "vc4_qpu.h"
40 #include "vc4_qir.h"
41 #ifdef USE_VC4_SIMULATOR
42 #include "simpenrose/simpenrose.h"
43 #endif
44
45 static struct qreg
46 ntq_get_src(struct vc4_compile *c, nir_src src, int i);
47
48 static void
49 resize_qreg_array(struct vc4_compile *c,
50 struct qreg **regs,
51 uint32_t *size,
52 uint32_t decl_size)
53 {
54 if (*size >= decl_size)
55 return;
56
57 uint32_t old_size = *size;
58 *size = MAX2(*size * 2, decl_size);
59 *regs = reralloc(c, *regs, struct qreg, *size);
60 if (!*regs) {
61 fprintf(stderr, "Malloc failure\n");
62 abort();
63 }
64
65 for (uint32_t i = old_size; i < *size; i++)
66 (*regs)[i] = c->undef;
67 }
68
69 static struct qreg
70 indirect_uniform_load(struct vc4_compile *c, nir_intrinsic_instr *intr)
71 {
72 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0);
73 uint32_t offset = intr->const_index[0];
74 struct vc4_compiler_ubo_range *range = NULL;
75 unsigned i;
76 for (i = 0; i < c->num_uniform_ranges; i++) {
77 range = &c->ubo_ranges[i];
78 if (offset >= range->src_offset &&
79 offset < range->src_offset + range->size) {
80 break;
81 }
82 }
83 /* The driver-location-based offset always has to be within a declared
84 * uniform range.
85 */
86 assert(range);
87 if (!range->used) {
88 range->used = true;
89 range->dst_offset = c->next_ubo_dst_offset;
90 c->next_ubo_dst_offset += range->size;
91 c->num_ubo_ranges++;
92 };
93
94 offset -= range->src_offset;
95
96 /* Adjust for where we stored the TGSI register base. */
97 indirect_offset = qir_ADD(c, indirect_offset,
98 qir_uniform_ui(c, (range->dst_offset +
99 offset)));
100
101 /* Clamp to [0, array size). Note that MIN/MAX are signed. */
102 indirect_offset = qir_MAX(c, indirect_offset, qir_uniform_ui(c, 0));
103 indirect_offset = qir_MIN(c, indirect_offset,
104 qir_uniform_ui(c, (range->dst_offset +
105 range->size - 4)));
106
107 qir_TEX_DIRECT(c, indirect_offset, qir_uniform(c, QUNIFORM_UBO_ADDR, 0));
108 struct qreg r4 = qir_TEX_RESULT(c);
109 c->num_texture_samples++;
110 return qir_MOV(c, r4);
111 }
112
113 static struct qreg *
114 ntq_get_dest(struct vc4_compile *c, nir_dest dest)
115 {
116 assert(!dest.is_ssa);
117 nir_register *reg = dest.reg.reg;
118 struct hash_entry *entry = _mesa_hash_table_search(c->def_ht, reg);
119 assert(reg->num_array_elems == 0);
120 assert(dest.reg.base_offset == 0);
121
122 struct qreg *qregs = entry->data;
123 return qregs;
124 }
125
126 static struct qreg
127 ntq_get_src(struct vc4_compile *c, nir_src src, int i)
128 {
129 struct hash_entry *entry;
130 if (src.is_ssa) {
131 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
132 assert(i < src.ssa->num_components);
133 } else {
134 nir_register *reg = src.reg.reg;
135 entry = _mesa_hash_table_search(c->def_ht, reg);
136 assert(reg->num_array_elems == 0);
137 assert(src.reg.base_offset == 0);
138 assert(i < reg->num_components);
139 }
140
141 struct qreg *qregs = entry->data;
142 return qregs[i];
143 }
144
145 static struct qreg
146 ntq_get_alu_src(struct vc4_compile *c, nir_alu_instr *instr,
147 unsigned src)
148 {
149 assert(util_is_power_of_two(instr->dest.write_mask));
150 unsigned chan = ffs(instr->dest.write_mask) - 1;
151 struct qreg r = ntq_get_src(c, instr->src[src].src,
152 instr->src[src].swizzle[chan]);
153
154 assert(!instr->src[src].abs);
155 assert(!instr->src[src].negate);
156
157 return r;
158 };
159
160 static struct qreg
161 get_swizzled_channel(struct vc4_compile *c,
162 struct qreg *srcs, int swiz)
163 {
164 switch (swiz) {
165 default:
166 case UTIL_FORMAT_SWIZZLE_NONE:
167 fprintf(stderr, "warning: unknown swizzle\n");
168 /* FALLTHROUGH */
169 case UTIL_FORMAT_SWIZZLE_0:
170 return qir_uniform_f(c, 0.0);
171 case UTIL_FORMAT_SWIZZLE_1:
172 return qir_uniform_f(c, 1.0);
173 case UTIL_FORMAT_SWIZZLE_X:
174 case UTIL_FORMAT_SWIZZLE_Y:
175 case UTIL_FORMAT_SWIZZLE_Z:
176 case UTIL_FORMAT_SWIZZLE_W:
177 return srcs[swiz];
178 }
179 }
180
181 static inline struct qreg
182 qir_SAT(struct vc4_compile *c, struct qreg val)
183 {
184 return qir_FMAX(c,
185 qir_FMIN(c, val, qir_uniform_f(c, 1.0)),
186 qir_uniform_f(c, 0.0));
187 }
188
189 static struct qreg
190 ntq_rcp(struct vc4_compile *c, struct qreg x)
191 {
192 struct qreg r = qir_RCP(c, x);
193
194 /* Apply a Newton-Raphson step to improve the accuracy. */
195 r = qir_FMUL(c, r, qir_FSUB(c,
196 qir_uniform_f(c, 2.0),
197 qir_FMUL(c, x, r)));
198
199 return r;
200 }
201
202 static struct qreg
203 ntq_rsq(struct vc4_compile *c, struct qreg x)
204 {
205 struct qreg r = qir_RSQ(c, x);
206
207 /* Apply a Newton-Raphson step to improve the accuracy. */
208 r = qir_FMUL(c, r, qir_FSUB(c,
209 qir_uniform_f(c, 1.5),
210 qir_FMUL(c,
211 qir_uniform_f(c, 0.5),
212 qir_FMUL(c, x,
213 qir_FMUL(c, r, r)))));
214
215 return r;
216 }
217
218 static struct qreg
219 qir_srgb_decode(struct vc4_compile *c, struct qreg srgb)
220 {
221 struct qreg low = qir_FMUL(c, srgb, qir_uniform_f(c, 1.0 / 12.92));
222 struct qreg high = qir_POW(c,
223 qir_FMUL(c,
224 qir_FADD(c,
225 srgb,
226 qir_uniform_f(c, 0.055)),
227 qir_uniform_f(c, 1.0 / 1.055)),
228 qir_uniform_f(c, 2.4));
229
230 qir_SF(c, qir_FSUB(c, srgb, qir_uniform_f(c, 0.04045)));
231 return qir_SEL_X_Y_NS(c, low, high);
232 }
233
234 static struct qreg
235 qir_srgb_encode(struct vc4_compile *c, struct qreg linear)
236 {
237 struct qreg low = qir_FMUL(c, linear, qir_uniform_f(c, 12.92));
238 struct qreg high = qir_FSUB(c,
239 qir_FMUL(c,
240 qir_uniform_f(c, 1.055),
241 qir_POW(c,
242 linear,
243 qir_uniform_f(c, 0.41666))),
244 qir_uniform_f(c, 0.055));
245
246 qir_SF(c, qir_FSUB(c, linear, qir_uniform_f(c, 0.0031308)));
247 return qir_SEL_X_Y_NS(c, low, high);
248 }
249
250 static struct qreg
251 ntq_umul(struct vc4_compile *c, struct qreg src0, struct qreg src1)
252 {
253 struct qreg src0_hi = qir_SHR(c, src0,
254 qir_uniform_ui(c, 24));
255 struct qreg src1_hi = qir_SHR(c, src1,
256 qir_uniform_ui(c, 24));
257
258 struct qreg hilo = qir_MUL24(c, src0_hi, src1);
259 struct qreg lohi = qir_MUL24(c, src0, src1_hi);
260 struct qreg lolo = qir_MUL24(c, src0, src1);
261
262 return qir_ADD(c, lolo, qir_SHL(c,
263 qir_ADD(c, hilo, lohi),
264 qir_uniform_ui(c, 24)));
265 }
266
267 static void
268 ntq_emit_tex(struct vc4_compile *c, nir_tex_instr *instr)
269 {
270 struct qreg s, t, r, lod, proj, compare;
271 bool is_txb = false, is_txl = false, has_proj = false;
272 unsigned unit = instr->sampler_index;
273
274 for (unsigned i = 0; i < instr->num_srcs; i++) {
275 switch (instr->src[i].src_type) {
276 case nir_tex_src_coord:
277 s = ntq_get_src(c, instr->src[i].src, 0);
278 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D)
279 t = qir_uniform_f(c, 0.5);
280 else
281 t = ntq_get_src(c, instr->src[i].src, 1);
282 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
283 r = ntq_get_src(c, instr->src[i].src, 2);
284 break;
285 case nir_tex_src_bias:
286 lod = ntq_get_src(c, instr->src[i].src, 0);
287 is_txb = true;
288 break;
289 case nir_tex_src_lod:
290 lod = ntq_get_src(c, instr->src[i].src, 0);
291 is_txl = true;
292 break;
293 case nir_tex_src_comparitor:
294 compare = ntq_get_src(c, instr->src[i].src, 0);
295 break;
296 case nir_tex_src_projector:
297 proj = qir_RCP(c, ntq_get_src(c, instr->src[i].src, 0));
298 s = qir_FMUL(c, s, proj);
299 t = qir_FMUL(c, t, proj);
300 has_proj = true;
301 break;
302 default:
303 unreachable("unknown texture source");
304 }
305 }
306
307 struct qreg texture_u[] = {
308 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit),
309 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
310 qir_uniform(c, QUNIFORM_CONSTANT, 0),
311 qir_uniform(c, QUNIFORM_CONSTANT, 0),
312 };
313 uint32_t next_texture_u = 0;
314
315 /* There is no native support for GL texture rectangle coordinates, so
316 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
317 * 1]).
318 */
319 if (instr->sampler_dim == GLSL_SAMPLER_DIM_RECT) {
320 s = qir_FMUL(c, s,
321 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_X, unit));
322 t = qir_FMUL(c, t,
323 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_Y, unit));
324 }
325
326 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE || is_txl) {
327 texture_u[2] = qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P2,
328 unit | (is_txl << 16));
329 }
330
331 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
332 struct qreg ma = qir_FMAXABS(c, qir_FMAXABS(c, s, t), r);
333 struct qreg rcp_ma = qir_RCP(c, ma);
334 s = qir_FMUL(c, s, rcp_ma);
335 t = qir_FMUL(c, t, rcp_ma);
336 r = qir_FMUL(c, r, rcp_ma);
337
338 qir_TEX_R(c, r, texture_u[next_texture_u++]);
339 } else if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
340 c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP ||
341 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
342 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
343 qir_TEX_R(c, qir_uniform(c, QUNIFORM_TEXTURE_BORDER_COLOR, unit),
344 texture_u[next_texture_u++]);
345 }
346
347 if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP) {
348 s = qir_SAT(c, s);
349 }
350
351 if (c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
352 t = qir_SAT(c, t);
353 }
354
355 qir_TEX_T(c, t, texture_u[next_texture_u++]);
356
357 if (is_txl || is_txb)
358 qir_TEX_B(c, lod, texture_u[next_texture_u++]);
359
360 qir_TEX_S(c, s, texture_u[next_texture_u++]);
361
362 c->num_texture_samples++;
363 struct qreg r4 = qir_TEX_RESULT(c);
364
365 enum pipe_format format = c->key->tex[unit].format;
366
367 struct qreg unpacked[4];
368 if (util_format_is_depth_or_stencil(format)) {
369 struct qreg depthf = qir_ITOF(c, qir_SHR(c, r4,
370 qir_uniform_ui(c, 8)));
371 struct qreg normalized = qir_FMUL(c, depthf,
372 qir_uniform_f(c, 1.0f/0xffffff));
373
374 struct qreg depth_output;
375
376 struct qreg one = qir_uniform_f(c, 1.0f);
377 if (c->key->tex[unit].compare_mode) {
378 if (has_proj)
379 compare = qir_FMUL(c, compare, proj);
380
381 switch (c->key->tex[unit].compare_func) {
382 case PIPE_FUNC_NEVER:
383 depth_output = qir_uniform_f(c, 0.0f);
384 break;
385 case PIPE_FUNC_ALWAYS:
386 depth_output = one;
387 break;
388 case PIPE_FUNC_EQUAL:
389 qir_SF(c, qir_FSUB(c, compare, normalized));
390 depth_output = qir_SEL_X_0_ZS(c, one);
391 break;
392 case PIPE_FUNC_NOTEQUAL:
393 qir_SF(c, qir_FSUB(c, compare, normalized));
394 depth_output = qir_SEL_X_0_ZC(c, one);
395 break;
396 case PIPE_FUNC_GREATER:
397 qir_SF(c, qir_FSUB(c, compare, normalized));
398 depth_output = qir_SEL_X_0_NC(c, one);
399 break;
400 case PIPE_FUNC_GEQUAL:
401 qir_SF(c, qir_FSUB(c, normalized, compare));
402 depth_output = qir_SEL_X_0_NS(c, one);
403 break;
404 case PIPE_FUNC_LESS:
405 qir_SF(c, qir_FSUB(c, compare, normalized));
406 depth_output = qir_SEL_X_0_NS(c, one);
407 break;
408 case PIPE_FUNC_LEQUAL:
409 qir_SF(c, qir_FSUB(c, normalized, compare));
410 depth_output = qir_SEL_X_0_NC(c, one);
411 break;
412 }
413 } else {
414 depth_output = normalized;
415 }
416
417 for (int i = 0; i < 4; i++)
418 unpacked[i] = depth_output;
419 } else {
420 for (int i = 0; i < 4; i++)
421 unpacked[i] = qir_R4_UNPACK(c, r4, i);
422 }
423
424 const uint8_t *format_swiz = vc4_get_format_swizzle(format);
425 struct qreg texture_output[4];
426 for (int i = 0; i < 4; i++) {
427 texture_output[i] = get_swizzled_channel(c, unpacked,
428 format_swiz[i]);
429 }
430
431 if (util_format_is_srgb(format)) {
432 for (int i = 0; i < 3; i++)
433 texture_output[i] = qir_srgb_decode(c,
434 texture_output[i]);
435 }
436
437 struct qreg *dest = ntq_get_dest(c, instr->dest);
438 for (int i = 0; i < 4; i++) {
439 dest[i] = get_swizzled_channel(c, texture_output,
440 c->key->tex[unit].swizzle[i]);
441 }
442 }
443
444 /**
445 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
446 * to zero).
447 */
448 static struct qreg
449 ntq_ffract(struct vc4_compile *c, struct qreg src)
450 {
451 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
452 struct qreg diff = qir_FSUB(c, src, trunc);
453 qir_SF(c, diff);
454 return qir_SEL_X_Y_NS(c,
455 qir_FADD(c, diff, qir_uniform_f(c, 1.0)),
456 diff);
457 }
458
459 /**
460 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
461 * zero).
462 */
463 static struct qreg
464 ntq_ffloor(struct vc4_compile *c, struct qreg src)
465 {
466 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
467
468 /* This will be < 0 if we truncated and the truncation was of a value
469 * that was < 0 in the first place.
470 */
471 qir_SF(c, qir_FSUB(c, src, trunc));
472
473 return qir_SEL_X_Y_NS(c,
474 qir_FSUB(c, trunc, qir_uniform_f(c, 1.0)),
475 trunc);
476 }
477
478 /**
479 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
480 * zero).
481 */
482 static struct qreg
483 ntq_fceil(struct vc4_compile *c, struct qreg src)
484 {
485 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
486
487 /* This will be < 0 if we truncated and the truncation was of a value
488 * that was > 0 in the first place.
489 */
490 qir_SF(c, qir_FSUB(c, trunc, src));
491
492 return qir_SEL_X_Y_NS(c,
493 qir_FADD(c, trunc, qir_uniform_f(c, 1.0)),
494 trunc);
495 }
496
497 static struct qreg
498 ntq_fsin(struct vc4_compile *c, struct qreg src)
499 {
500 float coeff[] = {
501 -2.0 * M_PI,
502 pow(2.0 * M_PI, 3) / (3 * 2 * 1),
503 -pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
504 pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
505 -pow(2.0 * M_PI, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
506 };
507
508 struct qreg scaled_x =
509 qir_FMUL(c,
510 src,
511 qir_uniform_f(c, 1.0 / (M_PI * 2.0)));
512
513 struct qreg x = qir_FADD(c,
514 ntq_ffract(c, scaled_x),
515 qir_uniform_f(c, -0.5));
516 struct qreg x2 = qir_FMUL(c, x, x);
517 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
518 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
519 x = qir_FMUL(c, x, x2);
520 sum = qir_FADD(c,
521 sum,
522 qir_FMUL(c,
523 x,
524 qir_uniform_f(c, coeff[i])));
525 }
526 return sum;
527 }
528
529 static struct qreg
530 ntq_fcos(struct vc4_compile *c, struct qreg src)
531 {
532 float coeff[] = {
533 -1.0f,
534 pow(2.0 * M_PI, 2) / (2 * 1),
535 -pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
536 pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
537 -pow(2.0 * M_PI, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
538 pow(2.0 * M_PI, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
539 };
540
541 struct qreg scaled_x =
542 qir_FMUL(c, src,
543 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
544 struct qreg x_frac = qir_FADD(c,
545 ntq_ffract(c, scaled_x),
546 qir_uniform_f(c, -0.5));
547
548 struct qreg sum = qir_uniform_f(c, coeff[0]);
549 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
550 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
551 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
552 if (i != 1)
553 x = qir_FMUL(c, x, x2);
554
555 struct qreg mul = qir_FMUL(c,
556 x,
557 qir_uniform_f(c, coeff[i]));
558 if (i == 0)
559 sum = mul;
560 else
561 sum = qir_FADD(c, sum, mul);
562 }
563 return sum;
564 }
565
566 static struct qreg
567 ntq_fsign(struct vc4_compile *c, struct qreg src)
568 {
569 qir_SF(c, src);
570 return qir_SEL_X_Y_NC(c,
571 qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0)),
572 qir_uniform_f(c, -1.0));
573 }
574
575 static struct qreg
576 get_channel_from_vpm(struct vc4_compile *c,
577 struct qreg *vpm_reads,
578 uint8_t swiz,
579 const struct util_format_description *desc)
580 {
581 const struct util_format_channel_description *chan =
582 &desc->channel[swiz];
583 struct qreg temp;
584
585 if (swiz > UTIL_FORMAT_SWIZZLE_W)
586 return get_swizzled_channel(c, vpm_reads, swiz);
587 else if (chan->size == 32 &&
588 chan->type == UTIL_FORMAT_TYPE_FLOAT) {
589 return get_swizzled_channel(c, vpm_reads, swiz);
590 } else if (chan->size == 32 &&
591 chan->type == UTIL_FORMAT_TYPE_SIGNED) {
592 if (chan->normalized) {
593 return qir_FMUL(c,
594 qir_ITOF(c, vpm_reads[swiz]),
595 qir_uniform_f(c,
596 1.0 / 0x7fffffff));
597 } else {
598 return qir_ITOF(c, vpm_reads[swiz]);
599 }
600 } else if (chan->size == 8 &&
601 (chan->type == UTIL_FORMAT_TYPE_UNSIGNED ||
602 chan->type == UTIL_FORMAT_TYPE_SIGNED)) {
603 struct qreg vpm = vpm_reads[0];
604 if (chan->type == UTIL_FORMAT_TYPE_SIGNED) {
605 temp = qir_XOR(c, vpm, qir_uniform_ui(c, 0x80808080));
606 if (chan->normalized) {
607 return qir_FSUB(c, qir_FMUL(c,
608 qir_UNPACK_8_F(c, temp, swiz),
609 qir_uniform_f(c, 2.0)),
610 qir_uniform_f(c, 1.0));
611 } else {
612 return qir_FADD(c,
613 qir_ITOF(c,
614 qir_UNPACK_8_I(c, temp,
615 swiz)),
616 qir_uniform_f(c, -128.0));
617 }
618 } else {
619 if (chan->normalized) {
620 return qir_UNPACK_8_F(c, vpm, swiz);
621 } else {
622 return qir_ITOF(c, qir_UNPACK_8_I(c, vpm, swiz));
623 }
624 }
625 } else if (chan->size == 16 &&
626 (chan->type == UTIL_FORMAT_TYPE_UNSIGNED ||
627 chan->type == UTIL_FORMAT_TYPE_SIGNED)) {
628 struct qreg vpm = vpm_reads[swiz / 2];
629
630 /* Note that UNPACK_16F eats a half float, not ints, so we use
631 * UNPACK_16_I for all of these.
632 */
633 if (chan->type == UTIL_FORMAT_TYPE_SIGNED) {
634 temp = qir_ITOF(c, qir_UNPACK_16_I(c, vpm, swiz % 2));
635 if (chan->normalized) {
636 return qir_FMUL(c, temp,
637 qir_uniform_f(c, 1/32768.0f));
638 } else {
639 return temp;
640 }
641 } else {
642 /* UNPACK_16I sign-extends, so we have to emit ANDs. */
643 temp = vpm;
644 if (swiz == 1 || swiz == 3)
645 temp = qir_UNPACK_16_I(c, temp, 1);
646 temp = qir_AND(c, temp, qir_uniform_ui(c, 0xffff));
647 temp = qir_ITOF(c, temp);
648
649 if (chan->normalized) {
650 return qir_FMUL(c, temp,
651 qir_uniform_f(c, 1 / 65535.0));
652 } else {
653 return temp;
654 }
655 }
656 } else {
657 return c->undef;
658 }
659 }
660
661 static void
662 emit_vertex_input(struct vc4_compile *c, int attr)
663 {
664 enum pipe_format format = c->vs_key->attr_formats[attr];
665 uint32_t attr_size = util_format_get_blocksize(format);
666 struct qreg vpm_reads[4];
667
668 c->vattr_sizes[attr] = align(attr_size, 4);
669 for (int i = 0; i < align(attr_size, 4) / 4; i++) {
670 struct qreg vpm = { QFILE_VPM, attr * 4 + i };
671 vpm_reads[i] = qir_MOV(c, vpm);
672 c->num_inputs++;
673 }
674
675 bool format_warned = false;
676 const struct util_format_description *desc =
677 util_format_description(format);
678
679 for (int i = 0; i < 4; i++) {
680 uint8_t swiz = desc->swizzle[i];
681 struct qreg result = get_channel_from_vpm(c, vpm_reads,
682 swiz, desc);
683
684 if (result.file == QFILE_NULL) {
685 if (!format_warned) {
686 fprintf(stderr,
687 "vtx element %d unsupported type: %s\n",
688 attr, util_format_name(format));
689 format_warned = true;
690 }
691 result = qir_uniform_f(c, 0.0);
692 }
693 c->inputs[attr * 4 + i] = result;
694 }
695 }
696
697 static void
698 emit_fragcoord_input(struct vc4_compile *c, int attr)
699 {
700 c->inputs[attr * 4 + 0] = qir_FRAG_X(c);
701 c->inputs[attr * 4 + 1] = qir_FRAG_Y(c);
702 c->inputs[attr * 4 + 2] =
703 qir_FMUL(c,
704 qir_ITOF(c, qir_FRAG_Z(c)),
705 qir_uniform_f(c, 1.0 / 0xffffff));
706 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
707 }
708
709 static struct qreg
710 emit_fragment_varying(struct vc4_compile *c, uint8_t semantic,
711 uint8_t index, uint8_t swizzle)
712 {
713 uint32_t i = c->num_input_semantics++;
714 struct qreg vary = {
715 QFILE_VARY,
716 i
717 };
718
719 if (c->num_input_semantics >= c->input_semantics_array_size) {
720 c->input_semantics_array_size =
721 MAX2(4, c->input_semantics_array_size * 2);
722
723 c->input_semantics = reralloc(c, c->input_semantics,
724 struct vc4_varying_semantic,
725 c->input_semantics_array_size);
726 }
727
728 c->input_semantics[i].semantic = semantic;
729 c->input_semantics[i].index = index;
730 c->input_semantics[i].swizzle = swizzle;
731
732 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
733 }
734
735 static void
736 emit_fragment_input(struct vc4_compile *c, int attr,
737 unsigned semantic_name, unsigned semantic_index)
738 {
739 for (int i = 0; i < 4; i++) {
740 c->inputs[attr * 4 + i] =
741 emit_fragment_varying(c,
742 semantic_name,
743 semantic_index,
744 i);
745 c->num_inputs++;
746 }
747 }
748
749 static void
750 add_output(struct vc4_compile *c,
751 uint32_t decl_offset,
752 uint8_t semantic_name,
753 uint8_t semantic_index,
754 uint8_t semantic_swizzle)
755 {
756 uint32_t old_array_size = c->outputs_array_size;
757 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
758 decl_offset + 1);
759
760 if (old_array_size != c->outputs_array_size) {
761 c->output_semantics = reralloc(c,
762 c->output_semantics,
763 struct vc4_varying_semantic,
764 c->outputs_array_size);
765 }
766
767 c->output_semantics[decl_offset].semantic = semantic_name;
768 c->output_semantics[decl_offset].index = semantic_index;
769 c->output_semantics[decl_offset].swizzle = semantic_swizzle;
770 }
771
772 static void
773 declare_uniform_range(struct vc4_compile *c, uint32_t start, uint32_t size)
774 {
775 unsigned array_id = c->num_uniform_ranges++;
776 if (array_id >= c->ubo_ranges_array_size) {
777 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
778 array_id + 1);
779 c->ubo_ranges = reralloc(c, c->ubo_ranges,
780 struct vc4_compiler_ubo_range,
781 c->ubo_ranges_array_size);
782 }
783
784 c->ubo_ranges[array_id].dst_offset = 0;
785 c->ubo_ranges[array_id].src_offset = start;
786 c->ubo_ranges[array_id].size = size;
787 c->ubo_ranges[array_id].used = false;
788 }
789
790 static void
791 ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr)
792 {
793 /* Vectors are special in that they have non-scalarized writemasks,
794 * and just take the first swizzle channel for each argument in order
795 * into each writemask channel.
796 */
797 if (instr->op == nir_op_vec2 ||
798 instr->op == nir_op_vec3 ||
799 instr->op == nir_op_vec4) {
800 struct qreg srcs[4];
801 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
802 srcs[i] = ntq_get_src(c, instr->src[i].src,
803 instr->src[i].swizzle[0]);
804 struct qreg *dest = ntq_get_dest(c, instr->dest.dest);
805 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
806 dest[i] = srcs[i];
807 return;
808 }
809
810 /* General case: We can just grab the one used channel per src. */
811 struct qreg src[nir_op_infos[instr->op].num_inputs];
812 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
813 src[i] = ntq_get_alu_src(c, instr, i);
814 }
815
816 /* Pick the channel to store the output in. */
817 assert(!instr->dest.saturate);
818 struct qreg *dest = ntq_get_dest(c, instr->dest.dest);
819 assert(util_is_power_of_two(instr->dest.write_mask));
820 dest += ffs(instr->dest.write_mask) - 1;
821
822 switch (instr->op) {
823 case nir_op_fmov:
824 case nir_op_imov:
825 *dest = qir_MOV(c, src[0]);
826 break;
827 case nir_op_fmul:
828 *dest = qir_FMUL(c, src[0], src[1]);
829 break;
830 case nir_op_fadd:
831 *dest = qir_FADD(c, src[0], src[1]);
832 break;
833 case nir_op_fsub:
834 *dest = qir_FSUB(c, src[0], src[1]);
835 break;
836 case nir_op_fmin:
837 *dest = qir_FMIN(c, src[0], src[1]);
838 break;
839 case nir_op_fmax:
840 *dest = qir_FMAX(c, src[0], src[1]);
841 break;
842
843 case nir_op_f2i:
844 case nir_op_f2u:
845 *dest = qir_FTOI(c, src[0]);
846 break;
847 case nir_op_i2f:
848 case nir_op_u2f:
849 *dest = qir_ITOF(c, src[0]);
850 break;
851 case nir_op_b2f:
852 *dest = qir_AND(c, src[0], qir_uniform_f(c, 1.0));
853 break;
854 case nir_op_b2i:
855 *dest = qir_AND(c, src[0], qir_uniform_ui(c, 1));
856 break;
857 case nir_op_i2b:
858 case nir_op_f2b:
859 qir_SF(c, src[0]);
860 *dest = qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
861 break;
862
863 case nir_op_iadd:
864 *dest = qir_ADD(c, src[0], src[1]);
865 break;
866 case nir_op_ushr:
867 *dest = qir_SHR(c, src[0], src[1]);
868 break;
869 case nir_op_isub:
870 *dest = qir_SUB(c, src[0], src[1]);
871 break;
872 case nir_op_ishr:
873 *dest = qir_ASR(c, src[0], src[1]);
874 break;
875 case nir_op_ishl:
876 *dest = qir_SHL(c, src[0], src[1]);
877 break;
878 case nir_op_imin:
879 *dest = qir_MIN(c, src[0], src[1]);
880 break;
881 case nir_op_imax:
882 *dest = qir_MAX(c, src[0], src[1]);
883 break;
884 case nir_op_iand:
885 *dest = qir_AND(c, src[0], src[1]);
886 break;
887 case nir_op_ior:
888 *dest = qir_OR(c, src[0], src[1]);
889 break;
890 case nir_op_ixor:
891 *dest = qir_XOR(c, src[0], src[1]);
892 break;
893 case nir_op_inot:
894 *dest = qir_NOT(c, src[0]);
895 break;
896
897 case nir_op_imul:
898 *dest = ntq_umul(c, src[0], src[1]);
899 break;
900
901 case nir_op_seq:
902 qir_SF(c, qir_FSUB(c, src[0], src[1]));
903 *dest = qir_SEL_X_0_ZS(c, qir_uniform_f(c, 1.0));
904 break;
905 case nir_op_sne:
906 qir_SF(c, qir_FSUB(c, src[0], src[1]));
907 *dest = qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0));
908 break;
909 case nir_op_sge:
910 qir_SF(c, qir_FSUB(c, src[0], src[1]));
911 *dest = qir_SEL_X_0_NC(c, qir_uniform_f(c, 1.0));
912 break;
913 case nir_op_slt:
914 qir_SF(c, qir_FSUB(c, src[0], src[1]));
915 *dest = qir_SEL_X_0_NS(c, qir_uniform_f(c, 1.0));
916 break;
917 case nir_op_feq:
918 qir_SF(c, qir_FSUB(c, src[0], src[1]));
919 *dest = qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
920 break;
921 case nir_op_fne:
922 qir_SF(c, qir_FSUB(c, src[0], src[1]));
923 *dest = qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
924 break;
925 case nir_op_fge:
926 qir_SF(c, qir_FSUB(c, src[0], src[1]));
927 *dest = qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
928 break;
929 case nir_op_flt:
930 qir_SF(c, qir_FSUB(c, src[0], src[1]));
931 *dest = qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
932 break;
933 case nir_op_ieq:
934 qir_SF(c, qir_SUB(c, src[0], src[1]));
935 *dest = qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
936 break;
937 case nir_op_ine:
938 qir_SF(c, qir_SUB(c, src[0], src[1]));
939 *dest = qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
940 break;
941 case nir_op_ige:
942 qir_SF(c, qir_SUB(c, src[0], src[1]));
943 *dest = qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
944 break;
945 case nir_op_ilt:
946 qir_SF(c, qir_SUB(c, src[0], src[1]));
947 *dest = qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
948 break;
949
950 case nir_op_bcsel:
951 qir_SF(c, src[0]);
952 *dest = qir_SEL_X_Y_NS(c, src[1], src[2]);
953 break;
954 case nir_op_fcsel:
955 qir_SF(c, src[0]);
956 *dest = qir_SEL_X_Y_ZC(c, src[1], src[2]);
957 break;
958
959 case nir_op_frcp:
960 *dest = ntq_rcp(c, src[0]);
961 break;
962 case nir_op_frsq:
963 *dest = ntq_rsq(c, src[0]);
964 break;
965 case nir_op_fexp2:
966 *dest = qir_EXP2(c, src[0]);
967 break;
968 case nir_op_flog2:
969 *dest = qir_LOG2(c, src[0]);
970 break;
971
972 case nir_op_ftrunc:
973 *dest = qir_ITOF(c, qir_FTOI(c, src[0]));
974 break;
975 case nir_op_fceil:
976 *dest = ntq_fceil(c, src[0]);
977 break;
978 case nir_op_ffract:
979 *dest = ntq_ffract(c, src[0]);
980 break;
981 case nir_op_ffloor:
982 *dest = ntq_ffloor(c, src[0]);
983 break;
984
985 case nir_op_fsin:
986 *dest = ntq_fsin(c, src[0]);
987 break;
988 case nir_op_fcos:
989 *dest = ntq_fcos(c, src[0]);
990 break;
991
992 case nir_op_fsign:
993 *dest = ntq_fsign(c, src[0]);
994 break;
995
996 case nir_op_fabs:
997 *dest = qir_FMAXABS(c, src[0], src[0]);
998 break;
999 case nir_op_iabs:
1000 *dest = qir_MAX(c, src[0],
1001 qir_SUB(c, qir_uniform_ui(c, 0), src[0]));
1002 break;
1003
1004 default:
1005 fprintf(stderr, "unknown NIR ALU inst: ");
1006 nir_print_instr(&instr->instr, stderr);
1007 fprintf(stderr, "\n");
1008 abort();
1009 }
1010 }
1011
1012 static struct qreg
1013 vc4_blend_channel(struct vc4_compile *c,
1014 struct qreg *dst,
1015 struct qreg *src,
1016 struct qreg val,
1017 unsigned factor,
1018 int channel)
1019 {
1020 switch(factor) {
1021 case PIPE_BLENDFACTOR_ONE:
1022 return val;
1023 case PIPE_BLENDFACTOR_SRC_COLOR:
1024 return qir_FMUL(c, val, src[channel]);
1025 case PIPE_BLENDFACTOR_SRC_ALPHA:
1026 return qir_FMUL(c, val, src[3]);
1027 case PIPE_BLENDFACTOR_DST_ALPHA:
1028 return qir_FMUL(c, val, dst[3]);
1029 case PIPE_BLENDFACTOR_DST_COLOR:
1030 return qir_FMUL(c, val, dst[channel]);
1031 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
1032 if (channel != 3) {
1033 return qir_FMUL(c,
1034 val,
1035 qir_FMIN(c,
1036 src[3],
1037 qir_FSUB(c,
1038 qir_uniform_f(c, 1.0),
1039 dst[3])));
1040 } else {
1041 return val;
1042 }
1043 case PIPE_BLENDFACTOR_CONST_COLOR:
1044 return qir_FMUL(c, val,
1045 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR,
1046 channel));
1047 case PIPE_BLENDFACTOR_CONST_ALPHA:
1048 return qir_FMUL(c, val,
1049 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR, 3));
1050 case PIPE_BLENDFACTOR_ZERO:
1051 return qir_uniform_f(c, 0.0);
1052 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
1053 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1054 src[channel]));
1055 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
1056 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1057 src[3]));
1058 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
1059 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1060 dst[3]));
1061 case PIPE_BLENDFACTOR_INV_DST_COLOR:
1062 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1063 dst[channel]));
1064 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
1065 return qir_FMUL(c, val,
1066 qir_FSUB(c, qir_uniform_f(c, 1.0),
1067 qir_uniform(c,
1068 QUNIFORM_BLEND_CONST_COLOR,
1069 channel)));
1070 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
1071 return qir_FMUL(c, val,
1072 qir_FSUB(c, qir_uniform_f(c, 1.0),
1073 qir_uniform(c,
1074 QUNIFORM_BLEND_CONST_COLOR,
1075 3)));
1076
1077 default:
1078 case PIPE_BLENDFACTOR_SRC1_COLOR:
1079 case PIPE_BLENDFACTOR_SRC1_ALPHA:
1080 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
1081 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
1082 /* Unsupported. */
1083 fprintf(stderr, "Unknown blend factor %d\n", factor);
1084 return val;
1085 }
1086 }
1087
1088 static struct qreg
1089 vc4_blend_func(struct vc4_compile *c,
1090 struct qreg src, struct qreg dst,
1091 unsigned func)
1092 {
1093 switch (func) {
1094 case PIPE_BLEND_ADD:
1095 return qir_FADD(c, src, dst);
1096 case PIPE_BLEND_SUBTRACT:
1097 return qir_FSUB(c, src, dst);
1098 case PIPE_BLEND_REVERSE_SUBTRACT:
1099 return qir_FSUB(c, dst, src);
1100 case PIPE_BLEND_MIN:
1101 return qir_FMIN(c, src, dst);
1102 case PIPE_BLEND_MAX:
1103 return qir_FMAX(c, src, dst);
1104
1105 default:
1106 /* Unsupported. */
1107 fprintf(stderr, "Unknown blend func %d\n", func);
1108 return src;
1109
1110 }
1111 }
1112
1113 /**
1114 * Implements fixed function blending in shader code.
1115 *
1116 * VC4 doesn't have any hardware support for blending. Instead, you read the
1117 * current contents of the destination from the tile buffer after having
1118 * waited for the scoreboard (which is handled by vc4_qpu_emit.c), then do
1119 * math using your output color and that destination value, and update the
1120 * output color appropriately.
1121 */
1122 static void
1123 vc4_blend(struct vc4_compile *c, struct qreg *result,
1124 struct qreg *dst_color, struct qreg *src_color)
1125 {
1126 struct pipe_rt_blend_state *blend = &c->fs_key->blend;
1127
1128 if (!blend->blend_enable) {
1129 for (int i = 0; i < 4; i++)
1130 result[i] = src_color[i];
1131 return;
1132 }
1133
1134 struct qreg clamped_src[4];
1135 struct qreg clamped_dst[4];
1136 for (int i = 0; i < 4; i++) {
1137 clamped_src[i] = qir_SAT(c, src_color[i]);
1138 clamped_dst[i] = qir_SAT(c, dst_color[i]);
1139 }
1140 src_color = clamped_src;
1141 dst_color = clamped_dst;
1142
1143 struct qreg src_blend[4], dst_blend[4];
1144 for (int i = 0; i < 3; i++) {
1145 src_blend[i] = vc4_blend_channel(c,
1146 dst_color, src_color,
1147 src_color[i],
1148 blend->rgb_src_factor, i);
1149 dst_blend[i] = vc4_blend_channel(c,
1150 dst_color, src_color,
1151 dst_color[i],
1152 blend->rgb_dst_factor, i);
1153 }
1154 src_blend[3] = vc4_blend_channel(c,
1155 dst_color, src_color,
1156 src_color[3],
1157 blend->alpha_src_factor, 3);
1158 dst_blend[3] = vc4_blend_channel(c,
1159 dst_color, src_color,
1160 dst_color[3],
1161 blend->alpha_dst_factor, 3);
1162
1163 for (int i = 0; i < 3; i++) {
1164 result[i] = vc4_blend_func(c,
1165 src_blend[i], dst_blend[i],
1166 blend->rgb_func);
1167 }
1168 result[3] = vc4_blend_func(c,
1169 src_blend[3], dst_blend[3],
1170 blend->alpha_func);
1171 }
1172
1173 static void
1174 clip_distance_discard(struct vc4_compile *c)
1175 {
1176 for (int i = 0; i < PIPE_MAX_CLIP_PLANES; i++) {
1177 if (!(c->key->ucp_enables & (1 << i)))
1178 continue;
1179
1180 struct qreg dist = emit_fragment_varying(c,
1181 TGSI_SEMANTIC_CLIPDIST,
1182 i,
1183 TGSI_SWIZZLE_X);
1184
1185 qir_SF(c, dist);
1186
1187 if (c->discard.file == QFILE_NULL)
1188 c->discard = qir_uniform_ui(c, 0);
1189
1190 c->discard = qir_SEL_X_Y_NS(c, qir_uniform_ui(c, ~0),
1191 c->discard);
1192 }
1193 }
1194
1195 static void
1196 alpha_test_discard(struct vc4_compile *c)
1197 {
1198 struct qreg src_alpha;
1199 struct qreg alpha_ref = qir_uniform(c, QUNIFORM_ALPHA_REF, 0);
1200
1201 if (!c->fs_key->alpha_test)
1202 return;
1203
1204 if (c->output_color_index != -1)
1205 src_alpha = c->outputs[c->output_color_index + 3];
1206 else
1207 src_alpha = qir_uniform_f(c, 1.0);
1208
1209 if (c->discard.file == QFILE_NULL)
1210 c->discard = qir_uniform_ui(c, 0);
1211
1212 switch (c->fs_key->alpha_test_func) {
1213 case PIPE_FUNC_NEVER:
1214 c->discard = qir_uniform_ui(c, ~0);
1215 break;
1216 case PIPE_FUNC_ALWAYS:
1217 break;
1218 case PIPE_FUNC_EQUAL:
1219 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1220 c->discard = qir_SEL_X_Y_ZS(c, c->discard,
1221 qir_uniform_ui(c, ~0));
1222 break;
1223 case PIPE_FUNC_NOTEQUAL:
1224 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1225 c->discard = qir_SEL_X_Y_ZC(c, c->discard,
1226 qir_uniform_ui(c, ~0));
1227 break;
1228 case PIPE_FUNC_GREATER:
1229 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1230 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1231 qir_uniform_ui(c, ~0));
1232 break;
1233 case PIPE_FUNC_GEQUAL:
1234 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1235 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1236 qir_uniform_ui(c, ~0));
1237 break;
1238 case PIPE_FUNC_LESS:
1239 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1240 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1241 qir_uniform_ui(c, ~0));
1242 break;
1243 case PIPE_FUNC_LEQUAL:
1244 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1245 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1246 qir_uniform_ui(c, ~0));
1247 break;
1248 }
1249 }
1250
1251 static struct qreg
1252 vc4_logicop(struct vc4_compile *c, struct qreg src, struct qreg dst)
1253 {
1254 switch (c->fs_key->logicop_func) {
1255 case PIPE_LOGICOP_CLEAR:
1256 return qir_uniform_f(c, 0.0);
1257 case PIPE_LOGICOP_NOR:
1258 return qir_NOT(c, qir_OR(c, src, dst));
1259 case PIPE_LOGICOP_AND_INVERTED:
1260 return qir_AND(c, qir_NOT(c, src), dst);
1261 case PIPE_LOGICOP_COPY_INVERTED:
1262 return qir_NOT(c, src);
1263 case PIPE_LOGICOP_AND_REVERSE:
1264 return qir_AND(c, src, qir_NOT(c, dst));
1265 case PIPE_LOGICOP_INVERT:
1266 return qir_NOT(c, dst);
1267 case PIPE_LOGICOP_XOR:
1268 return qir_XOR(c, src, dst);
1269 case PIPE_LOGICOP_NAND:
1270 return qir_NOT(c, qir_AND(c, src, dst));
1271 case PIPE_LOGICOP_AND:
1272 return qir_AND(c, src, dst);
1273 case PIPE_LOGICOP_EQUIV:
1274 return qir_NOT(c, qir_XOR(c, src, dst));
1275 case PIPE_LOGICOP_NOOP:
1276 return dst;
1277 case PIPE_LOGICOP_OR_INVERTED:
1278 return qir_OR(c, qir_NOT(c, src), dst);
1279 case PIPE_LOGICOP_OR_REVERSE:
1280 return qir_OR(c, src, qir_NOT(c, dst));
1281 case PIPE_LOGICOP_OR:
1282 return qir_OR(c, src, dst);
1283 case PIPE_LOGICOP_SET:
1284 return qir_uniform_ui(c, ~0);
1285 case PIPE_LOGICOP_COPY:
1286 default:
1287 return src;
1288 }
1289 }
1290
1291 /**
1292 * Applies the GL blending pipeline and returns the packed (8888) output
1293 * color.
1294 */
1295 static struct qreg
1296 blend_pipeline(struct vc4_compile *c)
1297 {
1298 enum pipe_format color_format = c->fs_key->color_format;
1299 const uint8_t *format_swiz = vc4_get_format_swizzle(color_format);
1300 struct qreg tlb_read_color[4] = { c->undef, c->undef, c->undef, c->undef };
1301 struct qreg dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1302 struct qreg linear_dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1303 struct qreg packed_dst_color = c->undef;
1304
1305 if (c->fs_key->blend.blend_enable ||
1306 c->fs_key->blend.colormask != 0xf ||
1307 c->fs_key->logicop_func != PIPE_LOGICOP_COPY) {
1308 struct qreg r4 = qir_TLB_COLOR_READ(c);
1309 for (int i = 0; i < 4; i++)
1310 tlb_read_color[i] = qir_R4_UNPACK(c, r4, i);
1311 for (int i = 0; i < 4; i++) {
1312 dst_color[i] = get_swizzled_channel(c,
1313 tlb_read_color,
1314 format_swiz[i]);
1315 if (util_format_is_srgb(color_format) && i != 3) {
1316 linear_dst_color[i] =
1317 qir_srgb_decode(c, dst_color[i]);
1318 } else {
1319 linear_dst_color[i] = dst_color[i];
1320 }
1321 }
1322
1323 /* Save the packed value for logic ops. Can't reuse r4
1324 * because other things might smash it (like sRGB)
1325 */
1326 packed_dst_color = qir_MOV(c, r4);
1327 }
1328
1329 struct qreg undef_array[4] = { c->undef, c->undef, c->undef, c->undef };
1330 const struct qreg *output_colors = (c->output_color_index != -1 ?
1331 c->outputs + c->output_color_index :
1332 undef_array);
1333 struct qreg blend_src_color[4];
1334 for (int i = 0; i < 4; i++)
1335 blend_src_color[i] = output_colors[i];
1336
1337 struct qreg blend_color[4];
1338 vc4_blend(c, blend_color, linear_dst_color, blend_src_color);
1339
1340 if (util_format_is_srgb(color_format)) {
1341 for (int i = 0; i < 3; i++)
1342 blend_color[i] = qir_srgb_encode(c, blend_color[i]);
1343 }
1344
1345 /* Debug: Sometimes you're getting a black output and just want to see
1346 * if the FS is getting executed at all. Spam magenta into the color
1347 * output.
1348 */
1349 if (0) {
1350 blend_color[0] = qir_uniform_f(c, 1.0);
1351 blend_color[1] = qir_uniform_f(c, 0.0);
1352 blend_color[2] = qir_uniform_f(c, 1.0);
1353 blend_color[3] = qir_uniform_f(c, 0.5);
1354 }
1355
1356 struct qreg swizzled_outputs[4];
1357 for (int i = 0; i < 4; i++) {
1358 swizzled_outputs[i] = get_swizzled_channel(c, blend_color,
1359 format_swiz[i]);
1360 }
1361
1362 struct qreg packed_color = c->undef;
1363 for (int i = 0; i < 4; i++) {
1364 if (swizzled_outputs[i].file == QFILE_NULL)
1365 continue;
1366 if (packed_color.file == QFILE_NULL) {
1367 packed_color = qir_PACK_8888_F(c, swizzled_outputs[i]);
1368 } else {
1369 packed_color = qir_PACK_8_F(c,
1370 packed_color,
1371 swizzled_outputs[i],
1372 i);
1373 }
1374 }
1375
1376 if (packed_color.file == QFILE_NULL)
1377 packed_color = qir_uniform_ui(c, 0);
1378
1379 if (c->fs_key->logicop_func != PIPE_LOGICOP_COPY) {
1380 packed_color = vc4_logicop(c, packed_color, packed_dst_color);
1381 }
1382
1383 /* If the bit isn't set in the color mask, then just return the
1384 * original dst color, instead.
1385 */
1386 uint32_t colormask = 0xffffffff;
1387 for (int i = 0; i < 4; i++) {
1388 if (format_swiz[i] < 4 &&
1389 !(c->fs_key->blend.colormask & (1 << format_swiz[i]))) {
1390 colormask &= ~(0xff << (i * 8));
1391 }
1392 }
1393 if (colormask != 0xffffffff) {
1394 packed_color = qir_OR(c,
1395 qir_AND(c, packed_color,
1396 qir_uniform_ui(c, colormask)),
1397 qir_AND(c, packed_dst_color,
1398 qir_uniform_ui(c, ~colormask)));
1399 }
1400
1401 return packed_color;
1402 }
1403
1404 static void
1405 emit_frag_end(struct vc4_compile *c)
1406 {
1407 clip_distance_discard(c);
1408 alpha_test_discard(c);
1409 struct qreg color = blend_pipeline(c);
1410
1411 if (c->discard.file != QFILE_NULL)
1412 qir_TLB_DISCARD_SETUP(c, c->discard);
1413
1414 if (c->fs_key->stencil_enabled) {
1415 qir_TLB_STENCIL_SETUP(c, qir_uniform(c, QUNIFORM_STENCIL, 0));
1416 if (c->fs_key->stencil_twoside) {
1417 qir_TLB_STENCIL_SETUP(c, qir_uniform(c, QUNIFORM_STENCIL, 1));
1418 }
1419 if (c->fs_key->stencil_full_writemasks) {
1420 qir_TLB_STENCIL_SETUP(c, qir_uniform(c, QUNIFORM_STENCIL, 2));
1421 }
1422 }
1423
1424 if (c->fs_key->depth_enabled) {
1425 struct qreg z;
1426 if (c->output_position_index != -1) {
1427 z = qir_FTOI(c, qir_FMUL(c, c->outputs[c->output_position_index + 2],
1428 qir_uniform_f(c, 0xffffff)));
1429 } else {
1430 z = qir_FRAG_Z(c);
1431 }
1432 qir_TLB_Z_WRITE(c, z);
1433 }
1434
1435 qir_TLB_COLOR_WRITE(c, color);
1436 }
1437
1438 static void
1439 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1440 {
1441 struct qreg xyi[2];
1442
1443 for (int i = 0; i < 2; i++) {
1444 struct qreg scale =
1445 qir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1446
1447 xyi[i] = qir_FTOI(c, qir_FMUL(c,
1448 qir_FMUL(c,
1449 c->outputs[c->output_position_index + i],
1450 scale),
1451 rcp_w));
1452 }
1453
1454 qir_VPM_WRITE(c, qir_PACK_SCALED(c, xyi[0], xyi[1]));
1455 }
1456
1457 static void
1458 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1459 {
1460 struct qreg zscale = qir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1461 struct qreg zoffset = qir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1462
1463 qir_VPM_WRITE(c, qir_FADD(c, qir_FMUL(c, qir_FMUL(c,
1464 c->outputs[c->output_position_index + 2],
1465 zscale),
1466 rcp_w),
1467 zoffset));
1468 }
1469
1470 static void
1471 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1472 {
1473 qir_VPM_WRITE(c, rcp_w);
1474 }
1475
1476 static void
1477 emit_point_size_write(struct vc4_compile *c)
1478 {
1479 struct qreg point_size;
1480
1481 if (c->output_point_size_index != -1)
1482 point_size = c->outputs[c->output_point_size_index + 3];
1483 else
1484 point_size = qir_uniform_f(c, 1.0);
1485
1486 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1487 * BCM21553).
1488 */
1489 point_size = qir_FMAX(c, point_size, qir_uniform_f(c, .125));
1490
1491 qir_VPM_WRITE(c, point_size);
1492 }
1493
1494 /**
1495 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1496 *
1497 * The simulator insists that there be at least one vertex attribute, so
1498 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also
1499 * insists that all vertex attributes loaded get read by the VS/CS, so we have
1500 * to consume it here.
1501 */
1502 static void
1503 emit_stub_vpm_read(struct vc4_compile *c)
1504 {
1505 if (c->num_inputs)
1506 return;
1507
1508 c->vattr_sizes[0] = 4;
1509 struct qreg vpm = { QFILE_VPM, 0 };
1510 (void)qir_MOV(c, vpm);
1511 c->num_inputs++;
1512 }
1513
1514 static void
1515 emit_ucp_clipdistance(struct vc4_compile *c)
1516 {
1517 unsigned cv;
1518 if (c->output_clipvertex_index != -1)
1519 cv = c->output_clipvertex_index;
1520 else if (c->output_position_index != -1)
1521 cv = c->output_position_index;
1522 else
1523 return;
1524
1525 for (int plane = 0; plane < PIPE_MAX_CLIP_PLANES; plane++) {
1526 if (!(c->key->ucp_enables & (1 << plane)))
1527 continue;
1528
1529 /* Pick the next outputs[] that hasn't been written to, since
1530 * there are no other program writes left to be processed at
1531 * this point. If something had been declared but not written
1532 * (like a w component), we'll just smash over the top of it.
1533 */
1534 uint32_t output_index = c->num_outputs++;
1535 add_output(c, output_index,
1536 TGSI_SEMANTIC_CLIPDIST,
1537 plane,
1538 TGSI_SWIZZLE_X);
1539
1540
1541 struct qreg dist = qir_uniform_f(c, 0.0);
1542 for (int i = 0; i < 4; i++) {
1543 struct qreg pos_chan = c->outputs[cv + i];
1544 struct qreg ucp =
1545 qir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1546 plane * 4 + i);
1547 dist = qir_FADD(c, dist, qir_FMUL(c, pos_chan, ucp));
1548 }
1549
1550 c->outputs[output_index] = dist;
1551 }
1552 }
1553
1554 static void
1555 emit_vert_end(struct vc4_compile *c,
1556 struct vc4_varying_semantic *fs_inputs,
1557 uint32_t num_fs_inputs)
1558 {
1559 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1560
1561 emit_stub_vpm_read(c);
1562 emit_ucp_clipdistance(c);
1563
1564 emit_scaled_viewport_write(c, rcp_w);
1565 emit_zs_write(c, rcp_w);
1566 emit_rcp_wc_write(c, rcp_w);
1567 if (c->vs_key->per_vertex_point_size)
1568 emit_point_size_write(c);
1569
1570 for (int i = 0; i < num_fs_inputs; i++) {
1571 struct vc4_varying_semantic *input = &fs_inputs[i];
1572 int j;
1573
1574 for (j = 0; j < c->num_outputs; j++) {
1575 struct vc4_varying_semantic *output =
1576 &c->output_semantics[j];
1577
1578 if (input->semantic == output->semantic &&
1579 input->index == output->index &&
1580 input->swizzle == output->swizzle) {
1581 qir_VPM_WRITE(c, c->outputs[j]);
1582 break;
1583 }
1584 }
1585 /* Emit padding if we didn't find a declared VS output for
1586 * this FS input.
1587 */
1588 if (j == c->num_outputs)
1589 qir_VPM_WRITE(c, qir_uniform_f(c, 0.0));
1590 }
1591 }
1592
1593 static void
1594 emit_coord_end(struct vc4_compile *c)
1595 {
1596 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1597
1598 emit_stub_vpm_read(c);
1599
1600 for (int i = 0; i < 4; i++)
1601 qir_VPM_WRITE(c, c->outputs[c->output_position_index + i]);
1602
1603 emit_scaled_viewport_write(c, rcp_w);
1604 emit_zs_write(c, rcp_w);
1605 emit_rcp_wc_write(c, rcp_w);
1606 if (c->vs_key->per_vertex_point_size)
1607 emit_point_size_write(c);
1608 }
1609
1610 static void
1611 vc4_optimize_nir(struct nir_shader *s)
1612 {
1613 bool progress;
1614
1615 do {
1616 progress = false;
1617
1618 nir_lower_vars_to_ssa(s);
1619 nir_lower_alu_to_scalar(s);
1620
1621 progress = nir_copy_prop(s) || progress;
1622 progress = nir_opt_dce(s) || progress;
1623 progress = nir_opt_cse(s) || progress;
1624 progress = nir_opt_peephole_select(s) || progress;
1625 progress = nir_opt_algebraic(s) || progress;
1626 progress = nir_opt_constant_folding(s) || progress;
1627 } while (progress);
1628 }
1629
1630 static int
1631 driver_location_compare(const void *in_a, const void *in_b)
1632 {
1633 const nir_variable *const *a = in_a;
1634 const nir_variable *const *b = in_b;
1635
1636 return (*a)->data.driver_location - (*b)->data.driver_location;
1637 }
1638
1639 static void
1640 ntq_setup_inputs(struct vc4_compile *c)
1641 {
1642 unsigned num_entries = 0;
1643 foreach_list_typed(nir_variable, var, node, &c->s->inputs)
1644 num_entries++;
1645
1646 nir_variable *vars[num_entries];
1647
1648 unsigned i = 0;
1649 foreach_list_typed(nir_variable, var, node, &c->s->inputs)
1650 vars[i++] = var;
1651
1652 /* Sort the variables so that we emit the input setup in
1653 * driver_location order. This is required for VPM reads, whose data
1654 * is fetched into the VPM in driver_location (TGSI register index)
1655 * order.
1656 */
1657 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1658
1659 for (unsigned i = 0; i < num_entries; i++) {
1660 nir_variable *var = vars[i];
1661 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1662 /* XXX: map loc slots to semantics */
1663 unsigned semantic_name = var->data.location;
1664 unsigned semantic_index = var->data.index;
1665 unsigned loc = var->data.driver_location;
1666
1667 assert(array_len == 1);
1668 (void)array_len;
1669 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1670 (loc + 1) * 4);
1671
1672 if (c->stage == QSTAGE_FRAG) {
1673 if (semantic_name == TGSI_SEMANTIC_POSITION) {
1674 emit_fragcoord_input(c, loc);
1675 } else if (semantic_name == TGSI_SEMANTIC_FACE) {
1676 c->inputs[loc * 4 + 0] = qir_FRAG_REV_FLAG(c);
1677 } else if (semantic_name == TGSI_SEMANTIC_GENERIC &&
1678 (c->fs_key->point_sprite_mask &
1679 (1 << semantic_index))) {
1680 c->inputs[loc * 4 + 0] = c->point_x;
1681 c->inputs[loc * 4 + 1] = c->point_y;
1682 } else {
1683 emit_fragment_input(c, loc,
1684 semantic_name,
1685 semantic_index);
1686 }
1687 } else {
1688 emit_vertex_input(c, loc);
1689 }
1690 }
1691 }
1692
1693 static void
1694 ntq_setup_outputs(struct vc4_compile *c)
1695 {
1696 foreach_list_typed(nir_variable, var, node, &c->s->outputs) {
1697 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1698 /* XXX: map loc slots to semantics */
1699 unsigned semantic_name = var->data.location;
1700 unsigned semantic_index = var->data.index;
1701 unsigned loc = var->data.driver_location * 4;
1702
1703 assert(array_len == 1);
1704 (void)array_len;
1705
1706 /* NIR hack to pass through
1707 * TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS */
1708 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1709 semantic_index == -1)
1710 semantic_index = 0;
1711
1712 for (int i = 0; i < 4; i++) {
1713 add_output(c,
1714 loc + i,
1715 semantic_name,
1716 semantic_index,
1717 i);
1718 }
1719
1720 switch (semantic_name) {
1721 case TGSI_SEMANTIC_POSITION:
1722 c->output_position_index = loc;
1723 break;
1724 case TGSI_SEMANTIC_CLIPVERTEX:
1725 c->output_clipvertex_index = loc;
1726 break;
1727 case TGSI_SEMANTIC_COLOR:
1728 c->output_color_index = loc;
1729 break;
1730 case TGSI_SEMANTIC_PSIZE:
1731 c->output_point_size_index = loc;
1732 break;
1733 }
1734
1735 }
1736 }
1737
1738 static void
1739 ntq_setup_uniforms(struct vc4_compile *c)
1740 {
1741 foreach_list_typed(nir_variable, var, node, &c->s->uniforms) {
1742 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1743 unsigned array_elem_size = 4 * sizeof(float);
1744
1745 declare_uniform_range(c, var->data.driver_location * array_elem_size,
1746 array_len * array_elem_size);
1747
1748 }
1749 }
1750
1751 /**
1752 * Sets up the mapping from nir_register to struct qreg *.
1753 *
1754 * Each nir_register gets a struct qreg per 32-bit component being stored.
1755 */
1756 static void
1757 ntq_setup_registers(struct vc4_compile *c, struct exec_list *list)
1758 {
1759 foreach_list_typed(nir_register, nir_reg, node, list) {
1760 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1761 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1762 array_len *
1763 nir_reg->num_components);
1764
1765 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1766
1767 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1768 qregs[i] = qir_uniform_ui(c, 0);
1769 }
1770 }
1771
1772 static void
1773 ntq_emit_load_const(struct vc4_compile *c, nir_load_const_instr *instr)
1774 {
1775 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1776 instr->def.num_components);
1777 for (int i = 0; i < instr->def.num_components; i++)
1778 qregs[i] = qir_uniform_ui(c, instr->value.u[i]);
1779
1780 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1781 }
1782
1783 static void
1784 ntq_emit_intrinsic(struct vc4_compile *c, nir_intrinsic_instr *instr)
1785 {
1786 const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
1787 struct qreg *dest = NULL;
1788
1789 if (info->has_dest) {
1790 dest = ntq_get_dest(c, instr->dest);
1791 }
1792
1793 switch (instr->intrinsic) {
1794 case nir_intrinsic_load_uniform:
1795 assert(instr->num_components == 1);
1796 *dest = qir_uniform(c, QUNIFORM_UNIFORM, instr->const_index[0]);
1797 break;
1798
1799 case nir_intrinsic_load_uniform_indirect:
1800 *dest = indirect_uniform_load(c, instr);
1801
1802 break;
1803
1804 case nir_intrinsic_load_input:
1805 assert(instr->num_components == 1);
1806 *dest = c->inputs[instr->const_index[0]];
1807
1808 break;
1809
1810 case nir_intrinsic_store_output:
1811 assert(instr->num_components == 1);
1812 c->outputs[instr->const_index[0]] =
1813 qir_MOV(c, ntq_get_src(c, instr->src[0], 0));
1814 c->num_outputs = MAX2(c->num_outputs, instr->const_index[0] + 1);
1815 break;
1816
1817 case nir_intrinsic_discard:
1818 c->discard = qir_uniform_ui(c, ~0);
1819 break;
1820
1821 case nir_intrinsic_discard_if:
1822 if (c->discard.file == QFILE_NULL)
1823 c->discard = qir_uniform_ui(c, 0);
1824 c->discard = qir_OR(c, c->discard,
1825 ntq_get_src(c, instr->src[0], 0));
1826 break;
1827
1828 default:
1829 fprintf(stderr, "Unknown intrinsic: ");
1830 nir_print_instr(&instr->instr, stderr);
1831 fprintf(stderr, "\n");
1832 break;
1833 }
1834 }
1835
1836 static void
1837 ntq_emit_if(struct vc4_compile *c, nir_if *if_stmt)
1838 {
1839 fprintf(stderr, "general IF statements not handled.\n");
1840 }
1841
1842 static void
1843 ntq_emit_instr(struct vc4_compile *c, nir_instr *instr)
1844 {
1845 switch (instr->type) {
1846 case nir_instr_type_alu:
1847 ntq_emit_alu(c, nir_instr_as_alu(instr));
1848 break;
1849
1850 case nir_instr_type_intrinsic:
1851 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
1852 break;
1853
1854 case nir_instr_type_load_const:
1855 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
1856 break;
1857
1858 case nir_instr_type_tex:
1859 ntq_emit_tex(c, nir_instr_as_tex(instr));
1860 break;
1861
1862 default:
1863 fprintf(stderr, "Unknown NIR instr type: ");
1864 nir_print_instr(instr, stderr);
1865 fprintf(stderr, "\n");
1866 abort();
1867 }
1868 }
1869
1870 static void
1871 ntq_emit_block(struct vc4_compile *c, nir_block *block)
1872 {
1873 nir_foreach_instr(block, instr) {
1874 ntq_emit_instr(c, instr);
1875 }
1876 }
1877
1878 static void
1879 ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list)
1880 {
1881 foreach_list_typed(nir_cf_node, node, node, list) {
1882 switch (node->type) {
1883 /* case nir_cf_node_loop: */
1884 case nir_cf_node_block:
1885 ntq_emit_block(c, nir_cf_node_as_block(node));
1886 break;
1887
1888 case nir_cf_node_if:
1889 ntq_emit_if(c, nir_cf_node_as_if(node));
1890 break;
1891
1892 default:
1893 assert(0);
1894 }
1895 }
1896 }
1897
1898 static void
1899 ntq_emit_impl(struct vc4_compile *c, nir_function_impl *impl)
1900 {
1901 ntq_setup_registers(c, &impl->registers);
1902 ntq_emit_cf_list(c, &impl->body);
1903 }
1904
1905 static void
1906 nir_to_qir(struct vc4_compile *c)
1907 {
1908 ntq_setup_inputs(c);
1909 ntq_setup_outputs(c);
1910 ntq_setup_uniforms(c);
1911 ntq_setup_registers(c, &c->s->registers);
1912
1913 /* Find the main function and emit the body. */
1914 nir_foreach_overload(c->s, overload) {
1915 assert(strcmp(overload->function->name, "main") == 0);
1916 assert(overload->impl);
1917 ntq_emit_impl(c, overload->impl);
1918 }
1919 }
1920
1921 static const nir_shader_compiler_options nir_options = {
1922 .lower_ffma = true,
1923 .lower_flrp = true,
1924 .lower_fpow = true,
1925 .lower_fsat = true,
1926 .lower_fsqrt = true,
1927 .lower_negate = true,
1928 };
1929
1930 static bool
1931 count_nir_instrs_in_block(nir_block *block, void *state)
1932 {
1933 int *count = (int *) state;
1934 nir_foreach_instr(block, instr) {
1935 *count = *count + 1;
1936 }
1937 return true;
1938 }
1939
1940 static int
1941 count_nir_instrs(nir_shader *nir)
1942 {
1943 int count = 0;
1944 nir_foreach_overload(nir, overload) {
1945 if (!overload->impl)
1946 continue;
1947 nir_foreach_block(overload->impl, count_nir_instrs_in_block, &count);
1948 }
1949 return count;
1950 }
1951
1952 static struct vc4_compile *
1953 vc4_shader_ntq(struct vc4_context *vc4, enum qstage stage,
1954 struct vc4_key *key)
1955 {
1956 struct vc4_compile *c = qir_compile_init();
1957
1958 c->stage = stage;
1959 c->shader_state = &key->shader_state->base;
1960 c->program_id = key->shader_state->program_id;
1961 c->variant_id = key->shader_state->compiled_variant_count++;
1962
1963 c->key = key;
1964 switch (stage) {
1965 case QSTAGE_FRAG:
1966 c->fs_key = (struct vc4_fs_key *)key;
1967 if (c->fs_key->is_points) {
1968 c->point_x = emit_fragment_varying(c, ~0, ~0, 0);
1969 c->point_y = emit_fragment_varying(c, ~0, ~0, 0);
1970 } else if (c->fs_key->is_lines) {
1971 c->line_x = emit_fragment_varying(c, ~0, ~0, 0);
1972 }
1973 break;
1974 case QSTAGE_VERT:
1975 c->vs_key = (struct vc4_vs_key *)key;
1976 break;
1977 case QSTAGE_COORD:
1978 c->vs_key = (struct vc4_vs_key *)key;
1979 break;
1980 }
1981
1982 const struct tgsi_token *tokens = key->shader_state->base.tokens;
1983 if (c->fs_key && c->fs_key->light_twoside) {
1984 if (!key->shader_state->twoside_tokens) {
1985 const struct tgsi_lowering_config lowering_config = {
1986 .color_two_side = true,
1987 };
1988 struct tgsi_shader_info info;
1989 key->shader_state->twoside_tokens =
1990 tgsi_transform_lowering(&lowering_config,
1991 key->shader_state->base.tokens,
1992 &info);
1993
1994 /* If no transformation occurred, then NULL is
1995 * returned and we just use our original tokens.
1996 */
1997 if (!key->shader_state->twoside_tokens) {
1998 key->shader_state->twoside_tokens =
1999 key->shader_state->base.tokens;
2000 }
2001 }
2002 tokens = key->shader_state->twoside_tokens;
2003 }
2004
2005 if (vc4_debug & VC4_DEBUG_TGSI) {
2006 fprintf(stderr, "%s prog %d/%d TGSI:\n",
2007 qir_get_stage_name(c->stage),
2008 c->program_id, c->variant_id);
2009 tgsi_dump(tokens, 0);
2010 }
2011
2012 c->s = tgsi_to_nir(tokens, &nir_options);
2013 nir_opt_global_to_local(c->s);
2014 nir_convert_to_ssa(c->s);
2015 vc4_nir_lower_io(c);
2016 nir_lower_idiv(c->s);
2017
2018 vc4_optimize_nir(c->s);
2019
2020 nir_remove_dead_variables(c->s);
2021
2022 nir_convert_from_ssa(c->s, false);
2023
2024 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2025 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d NIR instructions\n",
2026 qir_get_stage_name(c->stage),
2027 c->program_id, c->variant_id,
2028 count_nir_instrs(c->s));
2029 }
2030
2031 if (vc4_debug & VC4_DEBUG_NIR) {
2032 fprintf(stderr, "%s prog %d/%d NIR:\n",
2033 qir_get_stage_name(c->stage),
2034 c->program_id, c->variant_id);
2035 nir_print_shader(c->s, stderr);
2036 }
2037
2038 nir_to_qir(c);
2039
2040 switch (stage) {
2041 case QSTAGE_FRAG:
2042 emit_frag_end(c);
2043 break;
2044 case QSTAGE_VERT:
2045 emit_vert_end(c,
2046 vc4->prog.fs->input_semantics,
2047 vc4->prog.fs->num_inputs);
2048 break;
2049 case QSTAGE_COORD:
2050 emit_coord_end(c);
2051 break;
2052 }
2053
2054 if (vc4_debug & VC4_DEBUG_QIR) {
2055 fprintf(stderr, "%s prog %d/%d pre-opt QIR:\n",
2056 qir_get_stage_name(c->stage),
2057 c->program_id, c->variant_id);
2058 qir_dump(c);
2059 }
2060
2061 qir_optimize(c);
2062 qir_lower_uniforms(c);
2063
2064 if (vc4_debug & VC4_DEBUG_QIR) {
2065 fprintf(stderr, "%s prog %d/%d QIR:\n",
2066 qir_get_stage_name(c->stage),
2067 c->program_id, c->variant_id);
2068 qir_dump(c);
2069 }
2070 qir_reorder_uniforms(c);
2071 vc4_generate_code(vc4, c);
2072
2073 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2074 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d instructions\n",
2075 qir_get_stage_name(c->stage),
2076 c->program_id, c->variant_id,
2077 c->qpu_inst_count);
2078 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d uniforms\n",
2079 qir_get_stage_name(c->stage),
2080 c->program_id, c->variant_id,
2081 c->num_uniforms);
2082 }
2083
2084 ralloc_free(c->s);
2085
2086 return c;
2087 }
2088
2089 static void *
2090 vc4_shader_state_create(struct pipe_context *pctx,
2091 const struct pipe_shader_state *cso)
2092 {
2093 struct vc4_context *vc4 = vc4_context(pctx);
2094 struct vc4_uncompiled_shader *so = CALLOC_STRUCT(vc4_uncompiled_shader);
2095 if (!so)
2096 return NULL;
2097
2098 so->base.tokens = tgsi_dup_tokens(cso->tokens);
2099 so->program_id = vc4->next_uncompiled_program_id++;
2100
2101 return so;
2102 }
2103
2104 static void
2105 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
2106 struct vc4_compile *c)
2107 {
2108 int count = c->num_uniforms;
2109 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
2110
2111 uinfo->count = count;
2112 uinfo->data = ralloc_array(shader, uint32_t, count);
2113 memcpy(uinfo->data, c->uniform_data,
2114 count * sizeof(*uinfo->data));
2115 uinfo->contents = ralloc_array(shader, enum quniform_contents, count);
2116 memcpy(uinfo->contents, c->uniform_contents,
2117 count * sizeof(*uinfo->contents));
2118 uinfo->num_texture_samples = c->num_texture_samples;
2119
2120 vc4_set_shader_uniform_dirty_flags(shader);
2121 }
2122
2123 static struct vc4_compiled_shader *
2124 vc4_get_compiled_shader(struct vc4_context *vc4, enum qstage stage,
2125 struct vc4_key *key)
2126 {
2127 struct hash_table *ht;
2128 uint32_t key_size;
2129 if (stage == QSTAGE_FRAG) {
2130 ht = vc4->fs_cache;
2131 key_size = sizeof(struct vc4_fs_key);
2132 } else {
2133 ht = vc4->vs_cache;
2134 key_size = sizeof(struct vc4_vs_key);
2135 }
2136
2137 struct vc4_compiled_shader *shader;
2138 struct hash_entry *entry = _mesa_hash_table_search(ht, key);
2139 if (entry)
2140 return entry->data;
2141
2142 struct vc4_compile *c = vc4_shader_ntq(vc4, stage, key);
2143 shader = rzalloc(NULL, struct vc4_compiled_shader);
2144
2145 shader->program_id = vc4->next_compiled_program_id++;
2146 if (stage == QSTAGE_FRAG) {
2147 bool input_live[c->num_input_semantics];
2148
2149 memset(input_live, 0, sizeof(input_live));
2150 list_for_each_entry(struct qinst, inst, &c->instructions, link) {
2151 for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) {
2152 if (inst->src[i].file == QFILE_VARY)
2153 input_live[inst->src[i].index] = true;
2154 }
2155 }
2156
2157 shader->input_semantics = ralloc_array(shader,
2158 struct vc4_varying_semantic,
2159 c->num_input_semantics);
2160
2161 for (int i = 0; i < c->num_input_semantics; i++) {
2162 struct vc4_varying_semantic *sem = &c->input_semantics[i];
2163
2164 if (!input_live[i])
2165 continue;
2166
2167 /* Skip non-VS-output inputs. */
2168 if (sem->semantic == (uint8_t)~0)
2169 continue;
2170
2171 if (sem->semantic == TGSI_SEMANTIC_COLOR ||
2172 sem->semantic == TGSI_SEMANTIC_BCOLOR) {
2173 shader->color_inputs |= (1 << shader->num_inputs);
2174 }
2175
2176 shader->input_semantics[shader->num_inputs] = *sem;
2177 shader->num_inputs++;
2178 }
2179 } else {
2180 shader->num_inputs = c->num_inputs;
2181
2182 shader->vattr_offsets[0] = 0;
2183 for (int i = 0; i < 8; i++) {
2184 shader->vattr_offsets[i + 1] =
2185 shader->vattr_offsets[i] + c->vattr_sizes[i];
2186
2187 if (c->vattr_sizes[i])
2188 shader->vattrs_live |= (1 << i);
2189 }
2190 }
2191
2192 copy_uniform_state_to_shader(shader, c);
2193 shader->bo = vc4_bo_alloc_shader(vc4->screen, c->qpu_insts,
2194 c->qpu_inst_count * sizeof(uint64_t));
2195
2196 /* Copy the compiler UBO range state to the compiled shader, dropping
2197 * out arrays that were never referenced by an indirect load.
2198 *
2199 * (Note that QIR dead code elimination of an array access still
2200 * leaves that array alive, though)
2201 */
2202 if (c->num_ubo_ranges) {
2203 shader->num_ubo_ranges = c->num_ubo_ranges;
2204 shader->ubo_ranges = ralloc_array(shader, struct vc4_ubo_range,
2205 c->num_ubo_ranges);
2206 uint32_t j = 0;
2207 for (int i = 0; i < c->num_uniform_ranges; i++) {
2208 struct vc4_compiler_ubo_range *range =
2209 &c->ubo_ranges[i];
2210 if (!range->used)
2211 continue;
2212
2213 shader->ubo_ranges[j].dst_offset = range->dst_offset;
2214 shader->ubo_ranges[j].src_offset = range->src_offset;
2215 shader->ubo_ranges[j].size = range->size;
2216 shader->ubo_size += c->ubo_ranges[i].size;
2217 j++;
2218 }
2219 }
2220 if (shader->ubo_size) {
2221 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2222 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d UBO uniforms\n",
2223 qir_get_stage_name(c->stage),
2224 c->program_id, c->variant_id,
2225 shader->ubo_size / 4);
2226 }
2227 }
2228
2229 qir_compile_destroy(c);
2230
2231 struct vc4_key *dup_key;
2232 dup_key = ralloc_size(shader, key_size);
2233 memcpy(dup_key, key, key_size);
2234 _mesa_hash_table_insert(ht, dup_key, shader);
2235
2236 return shader;
2237 }
2238
2239 static void
2240 vc4_setup_shared_key(struct vc4_context *vc4, struct vc4_key *key,
2241 struct vc4_texture_stateobj *texstate)
2242 {
2243 for (int i = 0; i < texstate->num_textures; i++) {
2244 struct pipe_sampler_view *sampler = texstate->textures[i];
2245 struct pipe_sampler_state *sampler_state =
2246 texstate->samplers[i];
2247
2248 if (sampler) {
2249 key->tex[i].format = sampler->format;
2250 key->tex[i].swizzle[0] = sampler->swizzle_r;
2251 key->tex[i].swizzle[1] = sampler->swizzle_g;
2252 key->tex[i].swizzle[2] = sampler->swizzle_b;
2253 key->tex[i].swizzle[3] = sampler->swizzle_a;
2254 key->tex[i].compare_mode = sampler_state->compare_mode;
2255 key->tex[i].compare_func = sampler_state->compare_func;
2256 key->tex[i].wrap_s = sampler_state->wrap_s;
2257 key->tex[i].wrap_t = sampler_state->wrap_t;
2258 }
2259 }
2260
2261 key->ucp_enables = vc4->rasterizer->base.clip_plane_enable;
2262 }
2263
2264 static void
2265 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
2266 {
2267 struct vc4_fs_key local_key;
2268 struct vc4_fs_key *key = &local_key;
2269
2270 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2271 VC4_DIRTY_BLEND |
2272 VC4_DIRTY_FRAMEBUFFER |
2273 VC4_DIRTY_ZSA |
2274 VC4_DIRTY_RASTERIZER |
2275 VC4_DIRTY_FRAGTEX |
2276 VC4_DIRTY_TEXSTATE |
2277 VC4_DIRTY_UNCOMPILED_FS))) {
2278 return;
2279 }
2280
2281 memset(key, 0, sizeof(*key));
2282 vc4_setup_shared_key(vc4, &key->base, &vc4->fragtex);
2283 key->base.shader_state = vc4->prog.bind_fs;
2284 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
2285 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
2286 prim_mode <= PIPE_PRIM_LINE_STRIP);
2287 key->blend = vc4->blend->rt[0];
2288 if (vc4->blend->logicop_enable) {
2289 key->logicop_func = vc4->blend->logicop_func;
2290 } else {
2291 key->logicop_func = PIPE_LOGICOP_COPY;
2292 }
2293 if (vc4->framebuffer.cbufs[0])
2294 key->color_format = vc4->framebuffer.cbufs[0]->format;
2295
2296 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
2297 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
2298 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
2299 key->depth_enabled = (vc4->zsa->base.depth.enabled ||
2300 key->stencil_enabled);
2301 if (vc4->zsa->base.alpha.enabled) {
2302 key->alpha_test = true;
2303 key->alpha_test_func = vc4->zsa->base.alpha.func;
2304 }
2305
2306 if (key->is_points) {
2307 key->point_sprite_mask =
2308 vc4->rasterizer->base.sprite_coord_enable;
2309 key->point_coord_upper_left =
2310 (vc4->rasterizer->base.sprite_coord_mode ==
2311 PIPE_SPRITE_COORD_UPPER_LEFT);
2312 }
2313
2314 key->light_twoside = vc4->rasterizer->base.light_twoside;
2315
2316 struct vc4_compiled_shader *old_fs = vc4->prog.fs;
2317 vc4->prog.fs = vc4_get_compiled_shader(vc4, QSTAGE_FRAG, &key->base);
2318 if (vc4->prog.fs == old_fs)
2319 return;
2320
2321 vc4->dirty |= VC4_DIRTY_COMPILED_FS;
2322 if (vc4->rasterizer->base.flatshade &&
2323 old_fs && vc4->prog.fs->color_inputs != old_fs->color_inputs) {
2324 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
2325 }
2326 }
2327
2328 static void
2329 vc4_update_compiled_vs(struct vc4_context *vc4, uint8_t prim_mode)
2330 {
2331 struct vc4_vs_key local_key;
2332 struct vc4_vs_key *key = &local_key;
2333
2334 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2335 VC4_DIRTY_RASTERIZER |
2336 VC4_DIRTY_VERTTEX |
2337 VC4_DIRTY_TEXSTATE |
2338 VC4_DIRTY_VTXSTATE |
2339 VC4_DIRTY_UNCOMPILED_VS |
2340 VC4_DIRTY_COMPILED_FS))) {
2341 return;
2342 }
2343
2344 memset(key, 0, sizeof(*key));
2345 vc4_setup_shared_key(vc4, &key->base, &vc4->verttex);
2346 key->base.shader_state = vc4->prog.bind_vs;
2347 key->compiled_fs_id = vc4->prog.fs->program_id;
2348
2349 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
2350 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
2351
2352 key->per_vertex_point_size =
2353 (prim_mode == PIPE_PRIM_POINTS &&
2354 vc4->rasterizer->base.point_size_per_vertex);
2355
2356 struct vc4_compiled_shader *vs =
2357 vc4_get_compiled_shader(vc4, QSTAGE_VERT, &key->base);
2358 if (vs != vc4->prog.vs) {
2359 vc4->prog.vs = vs;
2360 vc4->dirty |= VC4_DIRTY_COMPILED_VS;
2361 }
2362
2363 key->is_coord = true;
2364 struct vc4_compiled_shader *cs =
2365 vc4_get_compiled_shader(vc4, QSTAGE_COORD, &key->base);
2366 if (cs != vc4->prog.cs) {
2367 vc4->prog.cs = cs;
2368 vc4->dirty |= VC4_DIRTY_COMPILED_CS;
2369 }
2370 }
2371
2372 void
2373 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
2374 {
2375 vc4_update_compiled_fs(vc4, prim_mode);
2376 vc4_update_compiled_vs(vc4, prim_mode);
2377 }
2378
2379 static uint32_t
2380 fs_cache_hash(const void *key)
2381 {
2382 return _mesa_hash_data(key, sizeof(struct vc4_fs_key));
2383 }
2384
2385 static uint32_t
2386 vs_cache_hash(const void *key)
2387 {
2388 return _mesa_hash_data(key, sizeof(struct vc4_vs_key));
2389 }
2390
2391 static bool
2392 fs_cache_compare(const void *key1, const void *key2)
2393 {
2394 return memcmp(key1, key2, sizeof(struct vc4_fs_key)) == 0;
2395 }
2396
2397 static bool
2398 vs_cache_compare(const void *key1, const void *key2)
2399 {
2400 return memcmp(key1, key2, sizeof(struct vc4_vs_key)) == 0;
2401 }
2402
2403 static void
2404 delete_from_cache_if_matches(struct hash_table *ht,
2405 struct hash_entry *entry,
2406 struct vc4_uncompiled_shader *so)
2407 {
2408 const struct vc4_key *key = entry->key;
2409
2410 if (key->shader_state == so) {
2411 struct vc4_compiled_shader *shader = entry->data;
2412 _mesa_hash_table_remove(ht, entry);
2413 vc4_bo_unreference(&shader->bo);
2414 ralloc_free(shader);
2415 }
2416 }
2417
2418 static void
2419 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
2420 {
2421 struct vc4_context *vc4 = vc4_context(pctx);
2422 struct vc4_uncompiled_shader *so = hwcso;
2423
2424 struct hash_entry *entry;
2425 hash_table_foreach(vc4->fs_cache, entry)
2426 delete_from_cache_if_matches(vc4->fs_cache, entry, so);
2427 hash_table_foreach(vc4->vs_cache, entry)
2428 delete_from_cache_if_matches(vc4->vs_cache, entry, so);
2429
2430 if (so->twoside_tokens != so->base.tokens)
2431 free((void *)so->twoside_tokens);
2432 free((void *)so->base.tokens);
2433 free(so);
2434 }
2435
2436 static void
2437 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
2438 {
2439 struct vc4_context *vc4 = vc4_context(pctx);
2440 vc4->prog.bind_fs = hwcso;
2441 vc4->dirty |= VC4_DIRTY_UNCOMPILED_FS;
2442 }
2443
2444 static void
2445 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
2446 {
2447 struct vc4_context *vc4 = vc4_context(pctx);
2448 vc4->prog.bind_vs = hwcso;
2449 vc4->dirty |= VC4_DIRTY_UNCOMPILED_VS;
2450 }
2451
2452 void
2453 vc4_program_init(struct pipe_context *pctx)
2454 {
2455 struct vc4_context *vc4 = vc4_context(pctx);
2456
2457 pctx->create_vs_state = vc4_shader_state_create;
2458 pctx->delete_vs_state = vc4_shader_state_delete;
2459
2460 pctx->create_fs_state = vc4_shader_state_create;
2461 pctx->delete_fs_state = vc4_shader_state_delete;
2462
2463 pctx->bind_fs_state = vc4_fp_state_bind;
2464 pctx->bind_vs_state = vc4_vp_state_bind;
2465
2466 vc4->fs_cache = _mesa_hash_table_create(pctx, fs_cache_hash,
2467 fs_cache_compare);
2468 vc4->vs_cache = _mesa_hash_table_create(pctx, vs_cache_hash,
2469 vs_cache_compare);
2470 }
2471
2472 void
2473 vc4_program_fini(struct pipe_context *pctx)
2474 {
2475 struct vc4_context *vc4 = vc4_context(pctx);
2476
2477 struct hash_entry *entry;
2478 hash_table_foreach(vc4->fs_cache, entry) {
2479 struct vc4_compiled_shader *shader = entry->data;
2480 vc4_bo_unreference(&shader->bo);
2481 ralloc_free(shader);
2482 _mesa_hash_table_remove(vc4->fs_cache, entry);
2483 }
2484
2485 hash_table_foreach(vc4->vs_cache, entry) {
2486 struct vc4_compiled_shader *shader = entry->data;
2487 vc4_bo_unreference(&shader->bo);
2488 ralloc_free(shader);
2489 _mesa_hash_table_remove(vc4->vs_cache, entry);
2490 }
2491 }