2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "pipe/p_state.h"
27 #include "util/u_format.h"
28 #include "util/u_hash_table.h"
29 #include "util/u_hash.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include "util/format_srgb.h"
33 #include "util/ralloc.h"
34 #include "util/hash_table.h"
35 #include "tgsi/tgsi_dump.h"
36 #include "tgsi/tgsi_info.h"
37 #include "tgsi/tgsi_lowering.h"
39 #include "vc4_context.h"
42 #ifdef USE_VC4_SIMULATOR
43 #include "simpenrose/simpenrose.h"
47 struct vc4_uncompiled_shader
*shader_state
;
49 enum pipe_format format
;
50 unsigned compare_mode
:1;
51 unsigned compare_func
:3;
55 } tex
[VC4_MAX_TEXTURE_SAMPLERS
];
61 enum pipe_format color_format
;
65 bool stencil_full_writemasks
;
69 bool point_coord_upper_left
;
71 uint8_t alpha_test_func
;
72 uint32_t point_sprite_mask
;
74 struct pipe_rt_blend_state blend
;
81 * This is a proxy for the array of FS input semantics, which is
82 * larger than we would want to put in the key.
84 uint64_t compiled_fs_id
;
86 enum pipe_format attr_formats
[8];
88 bool per_vertex_point_size
;
92 resize_qreg_array(struct vc4_compile
*c
,
97 if (*size
>= decl_size
)
100 uint32_t old_size
= *size
;
101 *size
= MAX2(*size
* 2, decl_size
);
102 *regs
= reralloc(c
, *regs
, struct qreg
, *size
);
104 fprintf(stderr
, "Malloc failure\n");
108 for (uint32_t i
= old_size
; i
< *size
; i
++)
109 (*regs
)[i
] = c
->undef
;
113 add_uniform(struct vc4_compile
*c
,
114 enum quniform_contents contents
,
117 uint32_t uniform
= c
->num_uniforms
++;
118 struct qreg u
= { QFILE_UNIF
, uniform
};
120 if (uniform
>= c
->uniform_array_size
) {
121 c
->uniform_array_size
= MAX2(MAX2(16, uniform
+ 1),
122 c
->uniform_array_size
* 2);
124 c
->uniform_data
= reralloc(c
, c
->uniform_data
,
126 c
->uniform_array_size
);
127 c
->uniform_contents
= reralloc(c
, c
->uniform_contents
,
128 enum quniform_contents
,
129 c
->uniform_array_size
);
132 c
->uniform_contents
[uniform
] = contents
;
133 c
->uniform_data
[uniform
] = data
;
139 get_temp_for_uniform(struct vc4_compile
*c
, enum quniform_contents contents
,
142 struct qreg u
= add_uniform(c
, contents
, data
);
143 struct qreg t
= qir_MOV(c
, u
);
148 qir_uniform_ui(struct vc4_compile
*c
, uint32_t ui
)
150 return get_temp_for_uniform(c
, QUNIFORM_CONSTANT
, ui
);
154 qir_uniform_f(struct vc4_compile
*c
, float f
)
156 return qir_uniform_ui(c
, fui(f
));
160 get_src(struct vc4_compile
*c
, unsigned tgsi_op
,
161 struct tgsi_src_register
*src
, int i
)
163 struct qreg r
= c
->undef
;
183 assert(!src
->Indirect
);
188 case TGSI_FILE_TEMPORARY
:
189 r
= c
->temps
[src
->Index
* 4 + s
];
191 case TGSI_FILE_IMMEDIATE
:
192 r
= c
->consts
[src
->Index
* 4 + s
];
194 case TGSI_FILE_CONSTANT
:
195 r
= get_temp_for_uniform(c
, QUNIFORM_UNIFORM
,
198 case TGSI_FILE_INPUT
:
199 r
= c
->inputs
[src
->Index
* 4 + s
];
201 case TGSI_FILE_SAMPLER
:
202 case TGSI_FILE_SAMPLER_VIEW
:
206 fprintf(stderr
, "unknown src file %d\n", src
->File
);
211 r
= qir_FMAXABS(c
, r
, r
);
214 switch (tgsi_opcode_infer_src_type(tgsi_op
)) {
215 case TGSI_TYPE_SIGNED
:
216 case TGSI_TYPE_UNSIGNED
:
217 r
= qir_SUB(c
, qir_uniform_ui(c
, 0), r
);
220 r
= qir_FSUB(c
, qir_uniform_f(c
, 0.0), r
);
230 update_dst(struct vc4_compile
*c
, struct tgsi_full_instruction
*tgsi_inst
,
231 int i
, struct qreg val
)
233 struct tgsi_dst_register
*tgsi_dst
= &tgsi_inst
->Dst
[0].Register
;
235 assert(!tgsi_dst
->Indirect
);
237 switch (tgsi_dst
->File
) {
238 case TGSI_FILE_TEMPORARY
:
239 c
->temps
[tgsi_dst
->Index
* 4 + i
] = val
;
241 case TGSI_FILE_OUTPUT
:
242 c
->outputs
[tgsi_dst
->Index
* 4 + i
] = val
;
243 c
->num_outputs
= MAX2(c
->num_outputs
,
244 tgsi_dst
->Index
* 4 + i
+ 1);
247 fprintf(stderr
, "unknown dst file %d\n", tgsi_dst
->File
);
253 get_swizzled_channel(struct vc4_compile
*c
,
254 struct qreg
*srcs
, int swiz
)
258 case UTIL_FORMAT_SWIZZLE_NONE
:
259 fprintf(stderr
, "warning: unknown swizzle\n");
261 case UTIL_FORMAT_SWIZZLE_0
:
262 return qir_uniform_f(c
, 0.0);
263 case UTIL_FORMAT_SWIZZLE_1
:
264 return qir_uniform_f(c
, 1.0);
265 case UTIL_FORMAT_SWIZZLE_X
:
266 case UTIL_FORMAT_SWIZZLE_Y
:
267 case UTIL_FORMAT_SWIZZLE_Z
:
268 case UTIL_FORMAT_SWIZZLE_W
:
274 tgsi_to_qir_alu(struct vc4_compile
*c
,
275 struct tgsi_full_instruction
*tgsi_inst
,
276 enum qop op
, struct qreg
*src
, int i
)
278 struct qreg dst
= qir_get_temp(c
);
279 qir_emit(c
, qir_inst4(op
, dst
,
288 tgsi_to_qir_scalar(struct vc4_compile
*c
,
289 struct tgsi_full_instruction
*tgsi_inst
,
290 enum qop op
, struct qreg
*src
, int i
)
292 struct qreg dst
= qir_get_temp(c
);
293 qir_emit(c
, qir_inst(op
, dst
,
300 qir_srgb_decode(struct vc4_compile
*c
, struct qreg srgb
)
302 struct qreg low
= qir_FMUL(c
, srgb
, qir_uniform_f(c
, 1.0 / 12.92));
303 struct qreg high
= qir_POW(c
,
307 qir_uniform_f(c
, 0.055)),
308 qir_uniform_f(c
, 1.0 / 1.055)),
309 qir_uniform_f(c
, 2.4));
311 qir_SF(c
, qir_FSUB(c
, srgb
, qir_uniform_f(c
, 0.04045)));
312 return qir_SEL_X_Y_NS(c
, low
, high
);
316 qir_srgb_encode(struct vc4_compile
*c
, struct qreg linear
)
318 struct qreg low
= qir_FMUL(c
, linear
, qir_uniform_f(c
, 12.92));
319 struct qreg high
= qir_FSUB(c
,
321 qir_uniform_f(c
, 1.055),
324 qir_uniform_f(c
, 0.41666))),
325 qir_uniform_f(c
, 0.055));
327 qir_SF(c
, qir_FSUB(c
, linear
, qir_uniform_f(c
, 0.0031308)));
328 return qir_SEL_X_Y_NS(c
, low
, high
);
332 tgsi_to_qir_umul(struct vc4_compile
*c
,
333 struct tgsi_full_instruction
*tgsi_inst
,
334 enum qop op
, struct qreg
*src
, int i
)
336 struct qreg src0_hi
= qir_SHR(c
, src
[0 * 4 + i
],
337 qir_uniform_ui(c
, 16));
338 struct qreg src0_lo
= qir_AND(c
, src
[0 * 4 + i
],
339 qir_uniform_ui(c
, 0xffff));
340 struct qreg src1_hi
= qir_SHR(c
, src
[1 * 4 + i
],
341 qir_uniform_ui(c
, 16));
342 struct qreg src1_lo
= qir_AND(c
, src
[1 * 4 + i
],
343 qir_uniform_ui(c
, 0xffff));
345 struct qreg hilo
= qir_MUL24(c
, src0_hi
, src1_lo
);
346 struct qreg lohi
= qir_MUL24(c
, src0_lo
, src1_hi
);
347 struct qreg lolo
= qir_MUL24(c
, src0_lo
, src1_lo
);
349 return qir_ADD(c
, lolo
, qir_SHL(c
,
350 qir_ADD(c
, hilo
, lohi
),
351 qir_uniform_ui(c
, 16)));
355 tgsi_to_qir_idiv(struct vc4_compile
*c
,
356 struct tgsi_full_instruction
*tgsi_inst
,
357 enum qop op
, struct qreg
*src
, int i
)
359 return qir_FTOI(c
, qir_FMUL(c
,
360 qir_ITOF(c
, src
[0 * 4 + i
]),
361 qir_RCP(c
, qir_ITOF(c
, src
[1 * 4 + i
]))));
365 tgsi_to_qir_ineg(struct vc4_compile
*c
,
366 struct tgsi_full_instruction
*tgsi_inst
,
367 enum qop op
, struct qreg
*src
, int i
)
369 return qir_SUB(c
, qir_uniform_ui(c
, 0), src
[0 * 4 + i
]);
373 tgsi_to_qir_seq(struct vc4_compile
*c
,
374 struct tgsi_full_instruction
*tgsi_inst
,
375 enum qop op
, struct qreg
*src
, int i
)
377 qir_SF(c
, qir_FSUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
378 return qir_SEL_X_0_ZS(c
, qir_uniform_f(c
, 1.0));
382 tgsi_to_qir_sne(struct vc4_compile
*c
,
383 struct tgsi_full_instruction
*tgsi_inst
,
384 enum qop op
, struct qreg
*src
, int i
)
386 qir_SF(c
, qir_FSUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
387 return qir_SEL_X_0_ZC(c
, qir_uniform_f(c
, 1.0));
391 tgsi_to_qir_slt(struct vc4_compile
*c
,
392 struct tgsi_full_instruction
*tgsi_inst
,
393 enum qop op
, struct qreg
*src
, int i
)
395 qir_SF(c
, qir_FSUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
396 return qir_SEL_X_0_NS(c
, qir_uniform_f(c
, 1.0));
400 tgsi_to_qir_sge(struct vc4_compile
*c
,
401 struct tgsi_full_instruction
*tgsi_inst
,
402 enum qop op
, struct qreg
*src
, int i
)
404 qir_SF(c
, qir_FSUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
405 return qir_SEL_X_0_NC(c
, qir_uniform_f(c
, 1.0));
409 tgsi_to_qir_fseq(struct vc4_compile
*c
,
410 struct tgsi_full_instruction
*tgsi_inst
,
411 enum qop op
, struct qreg
*src
, int i
)
413 qir_SF(c
, qir_FSUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
414 return qir_SEL_X_0_ZS(c
, qir_uniform_ui(c
, ~0));
418 tgsi_to_qir_fsne(struct vc4_compile
*c
,
419 struct tgsi_full_instruction
*tgsi_inst
,
420 enum qop op
, struct qreg
*src
, int i
)
422 qir_SF(c
, qir_FSUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
423 return qir_SEL_X_0_ZC(c
, qir_uniform_ui(c
, ~0));
427 tgsi_to_qir_fslt(struct vc4_compile
*c
,
428 struct tgsi_full_instruction
*tgsi_inst
,
429 enum qop op
, struct qreg
*src
, int i
)
431 qir_SF(c
, qir_FSUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
432 return qir_SEL_X_0_NS(c
, qir_uniform_ui(c
, ~0));
436 tgsi_to_qir_fsge(struct vc4_compile
*c
,
437 struct tgsi_full_instruction
*tgsi_inst
,
438 enum qop op
, struct qreg
*src
, int i
)
440 qir_SF(c
, qir_FSUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
441 return qir_SEL_X_0_NC(c
, qir_uniform_ui(c
, ~0));
445 tgsi_to_qir_useq(struct vc4_compile
*c
,
446 struct tgsi_full_instruction
*tgsi_inst
,
447 enum qop op
, struct qreg
*src
, int i
)
449 qir_SF(c
, qir_SUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
450 return qir_SEL_X_0_ZS(c
, qir_uniform_ui(c
, ~0));
454 tgsi_to_qir_usne(struct vc4_compile
*c
,
455 struct tgsi_full_instruction
*tgsi_inst
,
456 enum qop op
, struct qreg
*src
, int i
)
458 qir_SF(c
, qir_SUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
459 return qir_SEL_X_0_ZC(c
, qir_uniform_ui(c
, ~0));
463 tgsi_to_qir_islt(struct vc4_compile
*c
,
464 struct tgsi_full_instruction
*tgsi_inst
,
465 enum qop op
, struct qreg
*src
, int i
)
467 qir_SF(c
, qir_SUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
468 return qir_SEL_X_0_NS(c
, qir_uniform_ui(c
, ~0));
472 tgsi_to_qir_isge(struct vc4_compile
*c
,
473 struct tgsi_full_instruction
*tgsi_inst
,
474 enum qop op
, struct qreg
*src
, int i
)
476 qir_SF(c
, qir_SUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
477 return qir_SEL_X_0_NC(c
, qir_uniform_ui(c
, ~0));
481 tgsi_to_qir_cmp(struct vc4_compile
*c
,
482 struct tgsi_full_instruction
*tgsi_inst
,
483 enum qop op
, struct qreg
*src
, int i
)
485 qir_SF(c
, src
[0 * 4 + i
]);
486 return qir_SEL_X_Y_NS(c
,
492 tgsi_to_qir_mad(struct vc4_compile
*c
,
493 struct tgsi_full_instruction
*tgsi_inst
,
494 enum qop op
, struct qreg
*src
, int i
)
504 tgsi_to_qir_lrp(struct vc4_compile
*c
,
505 struct tgsi_full_instruction
*tgsi_inst
,
506 enum qop op
, struct qreg
*src
, int i
)
508 struct qreg src0
= src
[0 * 4 + i
];
509 struct qreg src1
= src
[1 * 4 + i
];
510 struct qreg src2
= src
[2 * 4 + i
];
513 * src0 * src1 + (1 - src0) * src2.
514 * -> src0 * src1 + src2 - src0 * src2
515 * -> src2 + src0 * (src1 - src2)
517 return qir_FADD(c
, src2
, qir_FMUL(c
, src0
, qir_FSUB(c
, src1
, src2
)));
522 tgsi_to_qir_tex(struct vc4_compile
*c
,
523 struct tgsi_full_instruction
*tgsi_inst
,
524 enum qop op
, struct qreg
*src
)
526 assert(!tgsi_inst
->Instruction
.Saturate
);
528 struct qreg s
= src
[0 * 4 + 0];
529 struct qreg t
= src
[0 * 4 + 1];
530 struct qreg r
= src
[0 * 4 + 2];
531 uint32_t unit
= tgsi_inst
->Src
[1].Register
.Index
;
532 bool is_txl
= tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL
;
534 struct qreg proj
= c
->undef
;
535 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXP
) {
536 proj
= qir_RCP(c
, src
[0 * 4 + 3]);
537 s
= qir_FMUL(c
, s
, proj
);
538 t
= qir_FMUL(c
, t
, proj
);
541 struct qreg texture_u
[] = {
542 add_uniform(c
, QUNIFORM_TEXTURE_CONFIG_P0
, unit
),
543 add_uniform(c
, QUNIFORM_TEXTURE_CONFIG_P1
, unit
),
544 add_uniform(c
, QUNIFORM_CONSTANT
, 0),
545 add_uniform(c
, QUNIFORM_CONSTANT
, 0),
547 uint32_t next_texture_u
= 0;
549 /* There is no native support for GL texture rectangle coordinates, so
550 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
553 if (tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_RECT
||
554 tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWRECT
) {
556 get_temp_for_uniform(c
,
557 QUNIFORM_TEXRECT_SCALE_X
,
560 get_temp_for_uniform(c
,
561 QUNIFORM_TEXRECT_SCALE_Y
,
565 if (tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE
||
566 tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
568 texture_u
[2] = add_uniform(c
, QUNIFORM_TEXTURE_CONFIG_P2
,
569 unit
| (is_txl
<< 16));
572 if (tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE
||
573 tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
) {
574 struct qreg ma
= qir_FMAXABS(c
, qir_FMAXABS(c
, s
, t
), r
);
575 struct qreg rcp_ma
= qir_RCP(c
, ma
);
576 s
= qir_FMUL(c
, s
, rcp_ma
);
577 t
= qir_FMUL(c
, t
, rcp_ma
);
578 r
= qir_FMUL(c
, r
, rcp_ma
);
580 qir_TEX_R(c
, r
, texture_u
[next_texture_u
++]);
581 } else if (c
->key
->tex
[unit
].wrap_s
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
582 c
->key
->tex
[unit
].wrap_s
== PIPE_TEX_WRAP_CLAMP
||
583 c
->key
->tex
[unit
].wrap_t
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
584 c
->key
->tex
[unit
].wrap_t
== PIPE_TEX_WRAP_CLAMP
) {
585 qir_TEX_R(c
, get_temp_for_uniform(c
, QUNIFORM_TEXTURE_BORDER_COLOR
, unit
),
586 texture_u
[next_texture_u
++]);
589 if (c
->key
->tex
[unit
].wrap_s
== PIPE_TEX_WRAP_CLAMP
) {
590 s
= qir_FMIN(c
, qir_FMAX(c
, s
, qir_uniform_f(c
, 0.0)),
591 qir_uniform_f(c
, 1.0));
594 if (c
->key
->tex
[unit
].wrap_t
== PIPE_TEX_WRAP_CLAMP
) {
595 t
= qir_FMIN(c
, qir_FMAX(c
, t
, qir_uniform_f(c
, 0.0)),
596 qir_uniform_f(c
, 1.0));
599 qir_TEX_T(c
, t
, texture_u
[next_texture_u
++]);
601 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB
||
602 tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL
)
603 qir_TEX_B(c
, src
[0 * 4 + 3], texture_u
[next_texture_u
++]);
605 qir_TEX_S(c
, s
, texture_u
[next_texture_u
++]);
607 c
->num_texture_samples
++;
608 struct qreg r4
= qir_TEX_RESULT(c
);
610 enum pipe_format format
= c
->key
->tex
[unit
].format
;
612 struct qreg unpacked
[4];
613 if (util_format_is_depth_or_stencil(format
)) {
614 struct qreg depthf
= qir_ITOF(c
, qir_SHR(c
, r4
,
615 qir_uniform_ui(c
, 8)));
616 struct qreg normalized
= qir_FMUL(c
, depthf
,
617 qir_uniform_f(c
, 1.0f
/0xffffff));
619 struct qreg depth_output
;
621 struct qreg one
= qir_uniform_f(c
, 1.0f
);
622 if (c
->key
->tex
[unit
].compare_mode
) {
623 struct qreg compare
= src
[0 * 4 + 2];
625 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXP
)
626 compare
= qir_FMUL(c
, compare
, proj
);
628 switch (c
->key
->tex
[unit
].compare_func
) {
629 case PIPE_FUNC_NEVER
:
630 depth_output
= qir_uniform_f(c
, 0.0f
);
632 case PIPE_FUNC_ALWAYS
:
635 case PIPE_FUNC_EQUAL
:
636 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
637 depth_output
= qir_SEL_X_0_ZS(c
, one
);
639 case PIPE_FUNC_NOTEQUAL
:
640 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
641 depth_output
= qir_SEL_X_0_ZC(c
, one
);
643 case PIPE_FUNC_GREATER
:
644 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
645 depth_output
= qir_SEL_X_0_NC(c
, one
);
647 case PIPE_FUNC_GEQUAL
:
648 qir_SF(c
, qir_FSUB(c
, normalized
, compare
));
649 depth_output
= qir_SEL_X_0_NS(c
, one
);
652 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
653 depth_output
= qir_SEL_X_0_NS(c
, one
);
655 case PIPE_FUNC_LEQUAL
:
656 qir_SF(c
, qir_FSUB(c
, normalized
, compare
));
657 depth_output
= qir_SEL_X_0_NC(c
, one
);
661 depth_output
= normalized
;
664 for (int i
= 0; i
< 4; i
++)
665 unpacked
[i
] = depth_output
;
667 for (int i
= 0; i
< 4; i
++)
668 unpacked
[i
] = qir_R4_UNPACK(c
, r4
, i
);
671 const uint8_t *format_swiz
= vc4_get_format_swizzle(format
);
672 struct qreg texture_output
[4];
673 for (int i
= 0; i
< 4; i
++) {
674 texture_output
[i
] = get_swizzled_channel(c
, unpacked
,
678 if (util_format_is_srgb(format
)) {
679 for (int i
= 0; i
< 3; i
++)
680 texture_output
[i
] = qir_srgb_decode(c
,
684 for (int i
= 0; i
< 4; i
++) {
685 if (!(tgsi_inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
688 update_dst(c
, tgsi_inst
, i
,
689 get_swizzled_channel(c
, texture_output
,
690 c
->key
->tex
[unit
].swizzle
[i
]));
695 tgsi_to_qir_trunc(struct vc4_compile
*c
,
696 struct tgsi_full_instruction
*tgsi_inst
,
697 enum qop op
, struct qreg
*src
, int i
)
699 return qir_ITOF(c
, qir_FTOI(c
, src
[0 * 4 + i
]));
703 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
707 tgsi_to_qir_frc(struct vc4_compile
*c
,
708 struct tgsi_full_instruction
*tgsi_inst
,
709 enum qop op
, struct qreg
*src
, int i
)
711 struct qreg trunc
= qir_ITOF(c
, qir_FTOI(c
, src
[0 * 4 + i
]));
712 struct qreg diff
= qir_FSUB(c
, src
[0 * 4 + i
], trunc
);
714 return qir_SEL_X_Y_NS(c
,
715 qir_FADD(c
, diff
, qir_uniform_f(c
, 1.0)),
720 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
724 tgsi_to_qir_flr(struct vc4_compile
*c
,
725 struct tgsi_full_instruction
*tgsi_inst
,
726 enum qop op
, struct qreg
*src
, int i
)
728 struct qreg trunc
= qir_ITOF(c
, qir_FTOI(c
, src
[0 * 4 + i
]));
730 /* This will be < 0 if we truncated and the truncation was of a value
731 * that was < 0 in the first place.
733 qir_SF(c
, qir_FSUB(c
, src
[0 * 4 + i
], trunc
));
735 return qir_SEL_X_Y_NS(c
,
736 qir_FSUB(c
, trunc
, qir_uniform_f(c
, 1.0)),
741 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
745 tgsi_to_qir_ceil(struct vc4_compile
*c
,
746 struct tgsi_full_instruction
*tgsi_inst
,
747 enum qop op
, struct qreg
*src
, int i
)
749 struct qreg trunc
= qir_ITOF(c
, qir_FTOI(c
, src
[0 * 4 + i
]));
751 /* This will be < 0 if we truncated and the truncation was of a value
752 * that was > 0 in the first place.
754 qir_SF(c
, qir_FSUB(c
, trunc
, src
[0 * 4 + i
]));
756 return qir_SEL_X_Y_NS(c
,
757 qir_FADD(c
, trunc
, qir_uniform_f(c
, 1.0)),
762 tgsi_to_qir_abs(struct vc4_compile
*c
,
763 struct tgsi_full_instruction
*tgsi_inst
,
764 enum qop op
, struct qreg
*src
, int i
)
766 struct qreg arg
= src
[0 * 4 + i
];
767 return qir_FMAXABS(c
, arg
, arg
);
770 /* Note that this instruction replicates its result from the x channel */
772 tgsi_to_qir_sin(struct vc4_compile
*c
,
773 struct tgsi_full_instruction
*tgsi_inst
,
774 enum qop op
, struct qreg
*src
, int i
)
778 pow(2.0 * M_PI
, 3) / (3 * 2 * 1),
779 -pow(2.0 * M_PI
, 5) / (5 * 4 * 3 * 2 * 1),
780 pow(2.0 * M_PI
, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
781 -pow(2.0 * M_PI
, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
784 struct qreg scaled_x
=
787 qir_uniform_f(c
, 1.0f
/ (M_PI
* 2.0f
)));
789 struct qreg x
= qir_FADD(c
,
790 tgsi_to_qir_frc(c
, NULL
, 0, &scaled_x
, 0),
791 qir_uniform_f(c
, -0.5));
792 struct qreg x2
= qir_FMUL(c
, x
, x
);
793 struct qreg sum
= qir_FMUL(c
, x
, qir_uniform_f(c
, coeff
[0]));
794 for (int i
= 1; i
< ARRAY_SIZE(coeff
); i
++) {
795 x
= qir_FMUL(c
, x
, x2
);
800 qir_uniform_f(c
, coeff
[i
])));
805 /* Note that this instruction replicates its result from the x channel */
807 tgsi_to_qir_cos(struct vc4_compile
*c
,
808 struct tgsi_full_instruction
*tgsi_inst
,
809 enum qop op
, struct qreg
*src
, int i
)
813 pow(2.0 * M_PI
, 2) / (2 * 1),
814 -pow(2.0 * M_PI
, 4) / (4 * 3 * 2 * 1),
815 pow(2.0 * M_PI
, 6) / (6 * 5 * 4 * 3 * 2 * 1),
816 -pow(2.0 * M_PI
, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
817 pow(2.0 * M_PI
, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
820 struct qreg scaled_x
=
821 qir_FMUL(c
, src
[0 * 4 + 0],
822 qir_uniform_f(c
, 1.0f
/ (M_PI
* 2.0f
)));
823 struct qreg x_frac
= qir_FADD(c
,
824 tgsi_to_qir_frc(c
, NULL
, 0, &scaled_x
, 0),
825 qir_uniform_f(c
, -0.5));
827 struct qreg sum
= qir_uniform_f(c
, coeff
[0]);
828 struct qreg x2
= qir_FMUL(c
, x_frac
, x_frac
);
829 struct qreg x
= x2
; /* Current x^2, x^4, or x^6 */
830 for (int i
= 1; i
< ARRAY_SIZE(coeff
); i
++) {
832 x
= qir_FMUL(c
, x
, x2
);
834 struct qreg mul
= qir_FMUL(c
,
836 qir_uniform_f(c
, coeff
[i
]));
840 sum
= qir_FADD(c
, sum
, mul
);
846 tgsi_to_qir_clamp(struct vc4_compile
*c
,
847 struct tgsi_full_instruction
*tgsi_inst
,
848 enum qop op
, struct qreg
*src
, int i
)
850 return qir_FMAX(c
, qir_FMIN(c
,
857 tgsi_to_qir_ssg(struct vc4_compile
*c
,
858 struct tgsi_full_instruction
*tgsi_inst
,
859 enum qop op
, struct qreg
*src
, int i
)
861 qir_SF(c
, src
[0 * 4 + i
]);
862 return qir_SEL_X_Y_NC(c
,
863 qir_SEL_X_0_ZC(c
, qir_uniform_f(c
, 1.0)),
864 qir_uniform_f(c
, -1.0));
868 emit_vertex_input(struct vc4_compile
*c
, int attr
)
870 enum pipe_format format
= c
->vs_key
->attr_formats
[attr
];
871 struct qreg vpm_reads
[4];
873 /* Right now, we're setting the VPM offsets to be 16 bytes wide every
874 * time, so we always read 4 32-bit VPM entries.
876 for (int i
= 0; i
< 4; i
++) {
877 vpm_reads
[i
] = qir_get_temp(c
);
878 qir_emit(c
, qir_inst(QOP_VPM_READ
,
885 bool format_warned
= false;
886 const struct util_format_description
*desc
=
887 util_format_description(format
);
889 for (int i
= 0; i
< 4; i
++) {
890 uint8_t swiz
= desc
->swizzle
[i
];
893 if (swiz
> UTIL_FORMAT_SWIZZLE_W
)
894 result
= get_swizzled_channel(c
, vpm_reads
, swiz
);
895 else if (desc
->channel
[swiz
].size
== 32 &&
896 desc
->channel
[swiz
].type
== UTIL_FORMAT_TYPE_FLOAT
) {
897 result
= get_swizzled_channel(c
, vpm_reads
, swiz
);
898 } else if (desc
->channel
[swiz
].size
== 8 &&
899 (desc
->channel
[swiz
].type
== UTIL_FORMAT_TYPE_UNSIGNED
||
900 desc
->channel
[swiz
].type
== UTIL_FORMAT_TYPE_SIGNED
) &&
901 desc
->channel
[swiz
].normalized
) {
902 struct qreg vpm
= vpm_reads
[0];
903 if (desc
->channel
[swiz
].type
== UTIL_FORMAT_TYPE_SIGNED
)
904 vpm
= qir_XOR(c
, vpm
, qir_uniform_ui(c
, 0x80808080));
905 result
= qir_UNPACK_8(c
, vpm
, swiz
);
907 if (!format_warned
) {
909 "vtx element %d unsupported type: %s\n",
910 attr
, util_format_name(format
));
911 format_warned
= true;
913 result
= qir_uniform_f(c
, 0.0);
916 if (desc
->channel
[swiz
].normalized
&&
917 desc
->channel
[swiz
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
921 qir_uniform_f(c
, 2.0)),
922 qir_uniform_f(c
, 1.0));
925 c
->inputs
[attr
* 4 + i
] = result
;
930 tgsi_to_qir_kill_if(struct vc4_compile
*c
, struct qreg
*src
, int i
)
932 if (c
->discard
.file
== QFILE_NULL
)
933 c
->discard
= qir_uniform_f(c
, 0.0);
934 qir_SF(c
, src
[0 * 4 + i
]);
935 c
->discard
= qir_SEL_X_Y_NS(c
, qir_uniform_f(c
, 1.0),
940 emit_fragcoord_input(struct vc4_compile
*c
, int attr
)
942 c
->inputs
[attr
* 4 + 0] = qir_FRAG_X(c
);
943 c
->inputs
[attr
* 4 + 1] = qir_FRAG_Y(c
);
944 c
->inputs
[attr
* 4 + 2] =
946 qir_ITOF(c
, qir_FRAG_Z(c
)),
947 qir_uniform_f(c
, 1.0 / 0xffffff));
948 c
->inputs
[attr
* 4 + 3] = qir_RCP(c
, qir_FRAG_W(c
));
952 emit_point_coord_input(struct vc4_compile
*c
, int attr
)
954 if (c
->point_x
.file
== QFILE_NULL
) {
955 c
->point_x
= qir_uniform_f(c
, 0.0);
956 c
->point_y
= qir_uniform_f(c
, 0.0);
959 c
->inputs
[attr
* 4 + 0] = c
->point_x
;
960 if (c
->fs_key
->point_coord_upper_left
) {
961 c
->inputs
[attr
* 4 + 1] = qir_FSUB(c
,
962 qir_uniform_f(c
, 1.0),
965 c
->inputs
[attr
* 4 + 1] = c
->point_y
;
967 c
->inputs
[attr
* 4 + 2] = qir_uniform_f(c
, 0.0);
968 c
->inputs
[attr
* 4 + 3] = qir_uniform_f(c
, 1.0);
972 emit_fragment_varying(struct vc4_compile
*c
, uint8_t semantic
,
973 uint8_t index
, uint8_t swizzle
)
975 uint32_t i
= c
->num_input_semantics
++;
981 if (c
->num_input_semantics
>= c
->input_semantics_array_size
) {
982 c
->input_semantics_array_size
=
983 MAX2(4, c
->input_semantics_array_size
* 2);
985 c
->input_semantics
= reralloc(c
, c
->input_semantics
,
986 struct vc4_varying_semantic
,
987 c
->input_semantics_array_size
);
990 c
->input_semantics
[i
].semantic
= semantic
;
991 c
->input_semantics
[i
].index
= index
;
992 c
->input_semantics
[i
].swizzle
= swizzle
;
994 return qir_VARY_ADD_C(c
, qir_FMUL(c
, vary
, qir_FRAG_W(c
)));
998 emit_fragment_input(struct vc4_compile
*c
, int attr
,
999 struct tgsi_full_declaration
*decl
)
1001 for (int i
= 0; i
< 4; i
++) {
1002 c
->inputs
[attr
* 4 + i
] =
1003 emit_fragment_varying(c
,
1004 decl
->Semantic
.Name
,
1005 decl
->Semantic
.Index
,
1012 emit_face_input(struct vc4_compile
*c
, int attr
)
1014 c
->inputs
[attr
* 4 + 0] = qir_FSUB(c
,
1015 qir_uniform_f(c
, 1.0),
1017 qir_ITOF(c
, qir_FRAG_REV_FLAG(c
)),
1018 qir_uniform_f(c
, 2.0)));
1019 c
->inputs
[attr
* 4 + 1] = qir_uniform_f(c
, 0.0);
1020 c
->inputs
[attr
* 4 + 2] = qir_uniform_f(c
, 0.0);
1021 c
->inputs
[attr
* 4 + 3] = qir_uniform_f(c
, 1.0);
1025 add_output(struct vc4_compile
*c
,
1026 uint32_t decl_offset
,
1027 uint8_t semantic_name
,
1028 uint8_t semantic_index
,
1029 uint8_t semantic_swizzle
)
1031 uint32_t old_array_size
= c
->outputs_array_size
;
1032 resize_qreg_array(c
, &c
->outputs
, &c
->outputs_array_size
,
1035 if (old_array_size
!= c
->outputs_array_size
) {
1036 c
->output_semantics
= reralloc(c
,
1037 c
->output_semantics
,
1038 struct vc4_varying_semantic
,
1039 c
->outputs_array_size
);
1042 c
->output_semantics
[decl_offset
].semantic
= semantic_name
;
1043 c
->output_semantics
[decl_offset
].index
= semantic_index
;
1044 c
->output_semantics
[decl_offset
].swizzle
= semantic_swizzle
;
1048 emit_tgsi_declaration(struct vc4_compile
*c
,
1049 struct tgsi_full_declaration
*decl
)
1051 switch (decl
->Declaration
.File
) {
1052 case TGSI_FILE_TEMPORARY
: {
1053 uint32_t old_size
= c
->temps_array_size
;
1054 resize_qreg_array(c
, &c
->temps
, &c
->temps_array_size
,
1055 (decl
->Range
.Last
+ 1) * 4);
1057 for (int i
= old_size
; i
< c
->temps_array_size
; i
++)
1058 c
->temps
[i
] = qir_uniform_ui(c
, 0);
1062 case TGSI_FILE_INPUT
:
1063 resize_qreg_array(c
, &c
->inputs
, &c
->inputs_array_size
,
1064 (decl
->Range
.Last
+ 1) * 4);
1066 for (int i
= decl
->Range
.First
;
1067 i
<= decl
->Range
.Last
;
1069 if (c
->stage
== QSTAGE_FRAG
) {
1070 if (decl
->Semantic
.Name
==
1071 TGSI_SEMANTIC_POSITION
) {
1072 emit_fragcoord_input(c
, i
);
1073 } else if (decl
->Semantic
.Name
== TGSI_SEMANTIC_FACE
) {
1074 emit_face_input(c
, i
);
1075 } else if (decl
->Semantic
.Name
== TGSI_SEMANTIC_GENERIC
&&
1076 (c
->fs_key
->point_sprite_mask
&
1077 (1 << decl
->Semantic
.Index
))) {
1078 emit_point_coord_input(c
, i
);
1080 emit_fragment_input(c
, i
, decl
);
1083 emit_vertex_input(c
, i
);
1088 case TGSI_FILE_OUTPUT
: {
1089 for (int i
= 0; i
< 4; i
++) {
1091 decl
->Range
.First
* 4 + i
,
1092 decl
->Semantic
.Name
,
1093 decl
->Semantic
.Index
,
1097 switch (decl
->Semantic
.Name
) {
1098 case TGSI_SEMANTIC_POSITION
:
1099 c
->output_position_index
= decl
->Range
.First
* 4;
1101 case TGSI_SEMANTIC_CLIPVERTEX
:
1102 c
->output_clipvertex_index
= decl
->Range
.First
* 4;
1104 case TGSI_SEMANTIC_COLOR
:
1105 c
->output_color_index
= decl
->Range
.First
* 4;
1107 case TGSI_SEMANTIC_PSIZE
:
1108 c
->output_point_size_index
= decl
->Range
.First
* 4;
1118 emit_tgsi_instruction(struct vc4_compile
*c
,
1119 struct tgsi_full_instruction
*tgsi_inst
)
1123 struct qreg (*func
)(struct vc4_compile
*c
,
1124 struct tgsi_full_instruction
*tgsi_inst
,
1126 struct qreg
*src
, int i
);
1128 [TGSI_OPCODE_MOV
] = { QOP_MOV
, tgsi_to_qir_alu
},
1129 [TGSI_OPCODE_ABS
] = { 0, tgsi_to_qir_abs
},
1130 [TGSI_OPCODE_MUL
] = { QOP_FMUL
, tgsi_to_qir_alu
},
1131 [TGSI_OPCODE_ADD
] = { QOP_FADD
, tgsi_to_qir_alu
},
1132 [TGSI_OPCODE_SUB
] = { QOP_FSUB
, tgsi_to_qir_alu
},
1133 [TGSI_OPCODE_MIN
] = { QOP_FMIN
, tgsi_to_qir_alu
},
1134 [TGSI_OPCODE_MAX
] = { QOP_FMAX
, tgsi_to_qir_alu
},
1135 [TGSI_OPCODE_F2I
] = { QOP_FTOI
, tgsi_to_qir_alu
},
1136 [TGSI_OPCODE_I2F
] = { QOP_ITOF
, tgsi_to_qir_alu
},
1137 [TGSI_OPCODE_UADD
] = { QOP_ADD
, tgsi_to_qir_alu
},
1138 [TGSI_OPCODE_USHR
] = { QOP_SHR
, tgsi_to_qir_alu
},
1139 [TGSI_OPCODE_ISHR
] = { QOP_ASR
, tgsi_to_qir_alu
},
1140 [TGSI_OPCODE_SHL
] = { QOP_SHL
, tgsi_to_qir_alu
},
1141 [TGSI_OPCODE_IMIN
] = { QOP_MIN
, tgsi_to_qir_alu
},
1142 [TGSI_OPCODE_IMAX
] = { QOP_MAX
, tgsi_to_qir_alu
},
1143 [TGSI_OPCODE_AND
] = { QOP_AND
, tgsi_to_qir_alu
},
1144 [TGSI_OPCODE_OR
] = { QOP_OR
, tgsi_to_qir_alu
},
1145 [TGSI_OPCODE_XOR
] = { QOP_XOR
, tgsi_to_qir_alu
},
1146 [TGSI_OPCODE_NOT
] = { QOP_NOT
, tgsi_to_qir_alu
},
1148 [TGSI_OPCODE_UMUL
] = { 0, tgsi_to_qir_umul
},
1149 [TGSI_OPCODE_IDIV
] = { 0, tgsi_to_qir_idiv
},
1150 [TGSI_OPCODE_INEG
] = { 0, tgsi_to_qir_ineg
},
1152 [TGSI_OPCODE_RSQ
] = { QOP_RSQ
, tgsi_to_qir_alu
},
1153 [TGSI_OPCODE_SEQ
] = { 0, tgsi_to_qir_seq
},
1154 [TGSI_OPCODE_SNE
] = { 0, tgsi_to_qir_sne
},
1155 [TGSI_OPCODE_SGE
] = { 0, tgsi_to_qir_sge
},
1156 [TGSI_OPCODE_SLT
] = { 0, tgsi_to_qir_slt
},
1157 [TGSI_OPCODE_FSEQ
] = { 0, tgsi_to_qir_fseq
},
1158 [TGSI_OPCODE_FSNE
] = { 0, tgsi_to_qir_fsne
},
1159 [TGSI_OPCODE_FSGE
] = { 0, tgsi_to_qir_fsge
},
1160 [TGSI_OPCODE_FSLT
] = { 0, tgsi_to_qir_fslt
},
1161 [TGSI_OPCODE_USEQ
] = { 0, tgsi_to_qir_useq
},
1162 [TGSI_OPCODE_USNE
] = { 0, tgsi_to_qir_usne
},
1163 [TGSI_OPCODE_ISGE
] = { 0, tgsi_to_qir_isge
},
1164 [TGSI_OPCODE_ISLT
] = { 0, tgsi_to_qir_islt
},
1166 [TGSI_OPCODE_CMP
] = { 0, tgsi_to_qir_cmp
},
1167 [TGSI_OPCODE_MAD
] = { 0, tgsi_to_qir_mad
},
1168 [TGSI_OPCODE_RCP
] = { QOP_RCP
, tgsi_to_qir_scalar
},
1169 [TGSI_OPCODE_RSQ
] = { QOP_RSQ
, tgsi_to_qir_scalar
},
1170 [TGSI_OPCODE_EX2
] = { QOP_EXP2
, tgsi_to_qir_scalar
},
1171 [TGSI_OPCODE_LG2
] = { QOP_LOG2
, tgsi_to_qir_scalar
},
1172 [TGSI_OPCODE_LRP
] = { 0, tgsi_to_qir_lrp
},
1173 [TGSI_OPCODE_TRUNC
] = { 0, tgsi_to_qir_trunc
},
1174 [TGSI_OPCODE_CEIL
] = { 0, tgsi_to_qir_ceil
},
1175 [TGSI_OPCODE_FRC
] = { 0, tgsi_to_qir_frc
},
1176 [TGSI_OPCODE_FLR
] = { 0, tgsi_to_qir_flr
},
1177 [TGSI_OPCODE_SIN
] = { 0, tgsi_to_qir_sin
},
1178 [TGSI_OPCODE_COS
] = { 0, tgsi_to_qir_cos
},
1179 [TGSI_OPCODE_CLAMP
] = { 0, tgsi_to_qir_clamp
},
1180 [TGSI_OPCODE_SSG
] = { 0, tgsi_to_qir_ssg
},
1182 static int asdf
= 0;
1183 uint32_t tgsi_op
= tgsi_inst
->Instruction
.Opcode
;
1185 if (tgsi_op
== TGSI_OPCODE_END
)
1188 struct qreg src_regs
[12];
1189 for (int s
= 0; s
< 3; s
++) {
1190 for (int i
= 0; i
< 4; i
++) {
1191 src_regs
[4 * s
+ i
] =
1192 get_src(c
, tgsi_inst
->Instruction
.Opcode
,
1193 &tgsi_inst
->Src
[s
].Register
, i
);
1198 case TGSI_OPCODE_TEX
:
1199 case TGSI_OPCODE_TXP
:
1200 case TGSI_OPCODE_TXB
:
1201 case TGSI_OPCODE_TXL
:
1202 tgsi_to_qir_tex(c
, tgsi_inst
,
1203 op_trans
[tgsi_op
].op
, src_regs
);
1205 case TGSI_OPCODE_KILL
:
1206 c
->discard
= qir_uniform_f(c
, 1.0);
1208 case TGSI_OPCODE_KILL_IF
:
1209 for (int i
= 0; i
< 4; i
++)
1210 tgsi_to_qir_kill_if(c
, src_regs
, i
);
1216 if (tgsi_op
> ARRAY_SIZE(op_trans
) || !(op_trans
[tgsi_op
].func
)) {
1217 fprintf(stderr
, "unknown tgsi inst: ");
1218 tgsi_dump_instruction(tgsi_inst
, asdf
++);
1219 fprintf(stderr
, "\n");
1223 for (int i
= 0; i
< 4; i
++) {
1224 if (!(tgsi_inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
1229 result
= op_trans
[tgsi_op
].func(c
, tgsi_inst
,
1230 op_trans
[tgsi_op
].op
,
1233 if (tgsi_inst
->Instruction
.Saturate
) {
1234 float low
= (tgsi_inst
->Instruction
.Saturate
==
1235 TGSI_SAT_MINUS_PLUS_ONE
? -1.0 : 0.0);
1236 result
= qir_FMAX(c
,
1239 qir_uniform_f(c
, 1.0)),
1240 qir_uniform_f(c
, low
));
1243 update_dst(c
, tgsi_inst
, i
, result
);
1248 parse_tgsi_immediate(struct vc4_compile
*c
, struct tgsi_full_immediate
*imm
)
1250 for (int i
= 0; i
< 4; i
++) {
1251 unsigned n
= c
->num_consts
++;
1252 resize_qreg_array(c
, &c
->consts
, &c
->consts_array_size
, n
+ 1);
1253 c
->consts
[n
] = qir_uniform_ui(c
, imm
->u
[i
].Uint
);
1258 vc4_blend_channel(struct vc4_compile
*c
,
1266 case PIPE_BLENDFACTOR_ONE
:
1268 case PIPE_BLENDFACTOR_SRC_COLOR
:
1269 return qir_FMUL(c
, val
, src
[channel
]);
1270 case PIPE_BLENDFACTOR_SRC_ALPHA
:
1271 return qir_FMUL(c
, val
, src
[3]);
1272 case PIPE_BLENDFACTOR_DST_ALPHA
:
1273 return qir_FMUL(c
, val
, dst
[3]);
1274 case PIPE_BLENDFACTOR_DST_COLOR
:
1275 return qir_FMUL(c
, val
, dst
[channel
]);
1276 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
1277 return qir_FMIN(c
, src
[3], qir_FSUB(c
,
1278 qir_uniform_f(c
, 1.0),
1280 case PIPE_BLENDFACTOR_CONST_COLOR
:
1281 return qir_FMUL(c
, val
,
1282 get_temp_for_uniform(c
,
1283 QUNIFORM_BLEND_CONST_COLOR
,
1285 case PIPE_BLENDFACTOR_CONST_ALPHA
:
1286 return qir_FMUL(c
, val
,
1287 get_temp_for_uniform(c
,
1288 QUNIFORM_BLEND_CONST_COLOR
,
1290 case PIPE_BLENDFACTOR_ZERO
:
1291 return qir_uniform_f(c
, 0.0);
1292 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
1293 return qir_FMUL(c
, val
, qir_FSUB(c
, qir_uniform_f(c
, 1.0),
1295 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
1296 return qir_FMUL(c
, val
, qir_FSUB(c
, qir_uniform_f(c
, 1.0),
1298 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
1299 return qir_FMUL(c
, val
, qir_FSUB(c
, qir_uniform_f(c
, 1.0),
1301 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
1302 return qir_FMUL(c
, val
, qir_FSUB(c
, qir_uniform_f(c
, 1.0),
1304 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
1305 return qir_FMUL(c
, val
,
1306 qir_FSUB(c
, qir_uniform_f(c
, 1.0),
1307 get_temp_for_uniform(c
,
1308 QUNIFORM_BLEND_CONST_COLOR
,
1310 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
1311 return qir_FMUL(c
, val
,
1312 qir_FSUB(c
, qir_uniform_f(c
, 1.0),
1313 get_temp_for_uniform(c
,
1314 QUNIFORM_BLEND_CONST_COLOR
,
1318 case PIPE_BLENDFACTOR_SRC1_COLOR
:
1319 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
1320 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
1321 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
1323 fprintf(stderr
, "Unknown blend factor %d\n", factor
);
1329 vc4_blend_func(struct vc4_compile
*c
,
1330 struct qreg src
, struct qreg dst
,
1334 case PIPE_BLEND_ADD
:
1335 return qir_FADD(c
, src
, dst
);
1336 case PIPE_BLEND_SUBTRACT
:
1337 return qir_FSUB(c
, src
, dst
);
1338 case PIPE_BLEND_REVERSE_SUBTRACT
:
1339 return qir_FSUB(c
, dst
, src
);
1340 case PIPE_BLEND_MIN
:
1341 return qir_FMIN(c
, src
, dst
);
1342 case PIPE_BLEND_MAX
:
1343 return qir_FMAX(c
, src
, dst
);
1347 fprintf(stderr
, "Unknown blend func %d\n", func
);
1354 * Implements fixed function blending in shader code.
1356 * VC4 doesn't have any hardware support for blending. Instead, you read the
1357 * current contents of the destination from the tile buffer after having
1358 * waited for the scoreboard (which is handled by vc4_qpu_emit.c), then do
1359 * math using your output color and that destination value, and update the
1360 * output color appropriately.
1363 vc4_blend(struct vc4_compile
*c
, struct qreg
*result
,
1364 struct qreg
*dst_color
, struct qreg
*src_color
)
1366 struct pipe_rt_blend_state
*blend
= &c
->fs_key
->blend
;
1368 if (!blend
->blend_enable
) {
1369 for (int i
= 0; i
< 4; i
++)
1370 result
[i
] = src_color
[i
];
1374 struct qreg src_blend
[4], dst_blend
[4];
1375 for (int i
= 0; i
< 3; i
++) {
1376 src_blend
[i
] = vc4_blend_channel(c
,
1377 dst_color
, src_color
,
1379 blend
->rgb_src_factor
, i
);
1380 dst_blend
[i
] = vc4_blend_channel(c
,
1381 dst_color
, src_color
,
1383 blend
->rgb_dst_factor
, i
);
1385 src_blend
[3] = vc4_blend_channel(c
,
1386 dst_color
, src_color
,
1388 blend
->alpha_src_factor
, 3);
1389 dst_blend
[3] = vc4_blend_channel(c
,
1390 dst_color
, src_color
,
1392 blend
->alpha_dst_factor
, 3);
1394 for (int i
= 0; i
< 3; i
++) {
1395 result
[i
] = vc4_blend_func(c
,
1396 src_blend
[i
], dst_blend
[i
],
1399 result
[3] = vc4_blend_func(c
,
1400 src_blend
[3], dst_blend
[3],
1405 clip_distance_discard(struct vc4_compile
*c
)
1407 for (int i
= 0; i
< PIPE_MAX_CLIP_PLANES
; i
++) {
1408 if (!(c
->key
->ucp_enables
& (1 << i
)))
1411 struct qreg dist
= emit_fragment_varying(c
,
1412 TGSI_SEMANTIC_CLIPDIST
,
1418 if (c
->discard
.file
== QFILE_NULL
)
1419 c
->discard
= qir_uniform_f(c
, 0.0);
1421 c
->discard
= qir_SEL_X_Y_NS(c
, qir_uniform_f(c
, 1.0),
1427 alpha_test_discard(struct vc4_compile
*c
)
1429 struct qreg src_alpha
;
1430 struct qreg alpha_ref
= get_temp_for_uniform(c
, QUNIFORM_ALPHA_REF
, 0);
1432 if (!c
->fs_key
->alpha_test
)
1435 if (c
->output_color_index
!= -1)
1436 src_alpha
= c
->outputs
[c
->output_color_index
+ 3];
1438 src_alpha
= qir_uniform_f(c
, 1.0);
1440 if (c
->discard
.file
== QFILE_NULL
)
1441 c
->discard
= qir_uniform_f(c
, 0.0);
1443 switch (c
->fs_key
->alpha_test_func
) {
1444 case PIPE_FUNC_NEVER
:
1445 c
->discard
= qir_uniform_f(c
, 1.0);
1447 case PIPE_FUNC_ALWAYS
:
1449 case PIPE_FUNC_EQUAL
:
1450 qir_SF(c
, qir_FSUB(c
, src_alpha
, alpha_ref
));
1451 c
->discard
= qir_SEL_X_Y_ZS(c
, c
->discard
,
1452 qir_uniform_f(c
, 1.0));
1454 case PIPE_FUNC_NOTEQUAL
:
1455 qir_SF(c
, qir_FSUB(c
, src_alpha
, alpha_ref
));
1456 c
->discard
= qir_SEL_X_Y_ZC(c
, c
->discard
,
1457 qir_uniform_f(c
, 1.0));
1459 case PIPE_FUNC_GREATER
:
1460 qir_SF(c
, qir_FSUB(c
, src_alpha
, alpha_ref
));
1461 c
->discard
= qir_SEL_X_Y_NC(c
, c
->discard
,
1462 qir_uniform_f(c
, 1.0));
1464 case PIPE_FUNC_GEQUAL
:
1465 qir_SF(c
, qir_FSUB(c
, alpha_ref
, src_alpha
));
1466 c
->discard
= qir_SEL_X_Y_NS(c
, c
->discard
,
1467 qir_uniform_f(c
, 1.0));
1469 case PIPE_FUNC_LESS
:
1470 qir_SF(c
, qir_FSUB(c
, src_alpha
, alpha_ref
));
1471 c
->discard
= qir_SEL_X_Y_NS(c
, c
->discard
,
1472 qir_uniform_f(c
, 1.0));
1474 case PIPE_FUNC_LEQUAL
:
1475 qir_SF(c
, qir_FSUB(c
, alpha_ref
, src_alpha
));
1476 c
->discard
= qir_SEL_X_Y_NC(c
, c
->discard
,
1477 qir_uniform_f(c
, 1.0));
1483 emit_frag_end(struct vc4_compile
*c
)
1485 clip_distance_discard(c
);
1486 alpha_test_discard(c
);
1488 enum pipe_format color_format
= c
->fs_key
->color_format
;
1489 const uint8_t *format_swiz
= vc4_get_format_swizzle(color_format
);
1490 struct qreg tlb_read_color
[4] = { c
->undef
, c
->undef
, c
->undef
, c
->undef
};
1491 struct qreg dst_color
[4] = { c
->undef
, c
->undef
, c
->undef
, c
->undef
};
1492 struct qreg linear_dst_color
[4] = { c
->undef
, c
->undef
, c
->undef
, c
->undef
};
1493 if (c
->fs_key
->blend
.blend_enable
||
1494 c
->fs_key
->blend
.colormask
!= 0xf) {
1495 struct qreg r4
= qir_TLB_COLOR_READ(c
);
1496 for (int i
= 0; i
< 4; i
++)
1497 tlb_read_color
[i
] = qir_R4_UNPACK(c
, r4
, i
);
1498 for (int i
= 0; i
< 4; i
++) {
1499 dst_color
[i
] = get_swizzled_channel(c
,
1502 if (util_format_is_srgb(color_format
) && i
!= 3) {
1503 linear_dst_color
[i
] =
1504 qir_srgb_decode(c
, dst_color
[i
]);
1506 linear_dst_color
[i
] = dst_color
[i
];
1511 struct qreg blend_color
[4];
1512 struct qreg undef_array
[4] = {
1513 c
->undef
, c
->undef
, c
->undef
, c
->undef
1515 vc4_blend(c
, blend_color
, linear_dst_color
,
1516 (c
->output_color_index
!= -1 ?
1517 c
->outputs
+ c
->output_color_index
:
1520 if (util_format_is_srgb(color_format
)) {
1521 for (int i
= 0; i
< 3; i
++)
1522 blend_color
[i
] = qir_srgb_encode(c
, blend_color
[i
]);
1525 /* If the bit isn't set in the color mask, then just return the
1526 * original dst color, instead.
1528 for (int i
= 0; i
< 4; i
++) {
1529 if (!(c
->fs_key
->blend
.colormask
& (1 << i
))) {
1530 blend_color
[i
] = dst_color
[i
];
1534 /* Debug: Sometimes you're getting a black output and just want to see
1535 * if the FS is getting executed at all. Spam magenta into the color
1539 blend_color
[0] = qir_uniform_f(c
, 1.0);
1540 blend_color
[1] = qir_uniform_f(c
, 0.0);
1541 blend_color
[2] = qir_uniform_f(c
, 1.0);
1542 blend_color
[3] = qir_uniform_f(c
, 0.5);
1545 struct qreg swizzled_outputs
[4];
1546 for (int i
= 0; i
< 4; i
++) {
1547 swizzled_outputs
[i
] = get_swizzled_channel(c
, blend_color
,
1551 if (c
->discard
.file
!= QFILE_NULL
)
1552 qir_TLB_DISCARD_SETUP(c
, c
->discard
);
1554 if (c
->fs_key
->stencil_enabled
) {
1555 qir_TLB_STENCIL_SETUP(c
, add_uniform(c
, QUNIFORM_STENCIL
, 0));
1556 if (c
->fs_key
->stencil_twoside
) {
1557 qir_TLB_STENCIL_SETUP(c
, add_uniform(c
, QUNIFORM_STENCIL
, 1));
1559 if (c
->fs_key
->stencil_full_writemasks
) {
1560 qir_TLB_STENCIL_SETUP(c
, add_uniform(c
, QUNIFORM_STENCIL
, 2));
1564 if (c
->fs_key
->depth_enabled
) {
1566 if (c
->output_position_index
!= -1) {
1567 z
= qir_FTOI(c
, qir_FMUL(c
, c
->outputs
[c
->output_position_index
+ 2],
1568 qir_uniform_f(c
, 0xffffff)));
1572 qir_TLB_Z_WRITE(c
, z
);
1575 bool color_written
= false;
1576 for (int i
= 0; i
< 4; i
++) {
1577 if (swizzled_outputs
[i
].file
!= QFILE_NULL
)
1578 color_written
= true;
1581 struct qreg packed_color
;
1582 if (color_written
) {
1583 /* Fill in any undefined colors. The simulator will assertion
1584 * fail if we read something that wasn't written, and I don't
1585 * know what hardware does.
1587 for (int i
= 0; i
< 4; i
++) {
1588 if (swizzled_outputs
[i
].file
== QFILE_NULL
)
1589 swizzled_outputs
[i
] = qir_uniform_f(c
, 0.0);
1591 packed_color
= qir_get_temp(c
);
1592 qir_emit(c
, qir_inst4(QOP_PACK_COLORS
, packed_color
,
1593 swizzled_outputs
[0],
1594 swizzled_outputs
[1],
1595 swizzled_outputs
[2],
1596 swizzled_outputs
[3]));
1598 packed_color
= qir_uniform_ui(c
, 0);
1601 qir_emit(c
, qir_inst(QOP_TLB_COLOR_WRITE
, c
->undef
,
1602 packed_color
, c
->undef
));
1606 emit_scaled_viewport_write(struct vc4_compile
*c
, struct qreg rcp_w
)
1610 for (int i
= 0; i
< 2; i
++) {
1612 add_uniform(c
, QUNIFORM_VIEWPORT_X_SCALE
+ i
, 0);
1614 xyi
[i
] = qir_FTOI(c
, qir_FMUL(c
,
1621 qir_VPM_WRITE(c
, qir_PACK_SCALED(c
, xyi
[0], xyi
[1]));
1625 emit_zs_write(struct vc4_compile
*c
, struct qreg rcp_w
)
1627 struct qreg zscale
= add_uniform(c
, QUNIFORM_VIEWPORT_Z_SCALE
, 0);
1628 struct qreg zoffset
= add_uniform(c
, QUNIFORM_VIEWPORT_Z_OFFSET
, 0);
1630 qir_VPM_WRITE(c
, qir_FMUL(c
, qir_FADD(c
, qir_FMUL(c
,
1638 emit_rcp_wc_write(struct vc4_compile
*c
, struct qreg rcp_w
)
1640 qir_VPM_WRITE(c
, rcp_w
);
1644 emit_point_size_write(struct vc4_compile
*c
)
1646 struct qreg point_size
;
1648 if (c
->output_point_size_index
)
1649 point_size
= c
->outputs
[c
->output_point_size_index
+ 3];
1651 point_size
= qir_uniform_f(c
, 1.0);
1653 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1656 point_size
= qir_FMAX(c
, point_size
, qir_uniform_f(c
, .125));
1658 qir_VPM_WRITE(c
, point_size
);
1662 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1664 * The simulator insists that there be at least one vertex attribute, so
1665 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also
1666 * insists that all vertex attributes loaded get read by the VS/CS, so we have
1667 * to consume it here.
1670 emit_stub_vpm_read(struct vc4_compile
*c
)
1675 for (int i
= 0; i
< 4; i
++) {
1676 qir_emit(c
, qir_inst(QOP_VPM_READ
,
1685 emit_ucp_clipdistance(struct vc4_compile
*c
)
1687 struct qreg
*clipvertex
;
1689 if (c
->output_clipvertex_index
!= -1)
1690 clipvertex
= &c
->outputs
[c
->output_clipvertex_index
];
1691 else if (c
->output_position_index
!= -1)
1692 clipvertex
= &c
->outputs
[c
->output_position_index
];
1696 for (int plane
= 0; plane
< PIPE_MAX_CLIP_PLANES
; plane
++) {
1697 if (!(c
->key
->ucp_enables
& (1 << plane
)))
1700 /* Pick the next outputs[] that hasn't been written to, since
1701 * there are no other program writes left to be processed at
1702 * this point. If something had been declared but not written
1703 * (like a w component), we'll just smash over the top of it.
1705 uint32_t output_index
= c
->num_outputs
++;
1706 add_output(c
, output_index
,
1707 TGSI_SEMANTIC_CLIPDIST
,
1711 struct qreg dist
= qir_uniform_f(c
, 0.0);
1712 for (int i
= 0; i
< 4; i
++) {
1714 add_uniform(c
, QUNIFORM_USER_CLIP_PLANE
,
1716 dist
= qir_FADD(c
, dist
, qir_FMUL(c
, clipvertex
[i
], ucp
));
1719 c
->outputs
[output_index
] = dist
;
1724 emit_vert_end(struct vc4_compile
*c
,
1725 struct vc4_varying_semantic
*fs_inputs
,
1726 uint32_t num_fs_inputs
)
1728 struct qreg rcp_w
= qir_RCP(c
, c
->outputs
[3]);
1730 emit_stub_vpm_read(c
);
1731 emit_ucp_clipdistance(c
);
1733 emit_scaled_viewport_write(c
, rcp_w
);
1734 emit_zs_write(c
, rcp_w
);
1735 emit_rcp_wc_write(c
, rcp_w
);
1736 if (c
->vs_key
->per_vertex_point_size
)
1737 emit_point_size_write(c
);
1739 for (int i
= 0; i
< num_fs_inputs
; i
++) {
1740 struct vc4_varying_semantic
*input
= &fs_inputs
[i
];
1743 for (j
= 0; j
< c
->num_outputs
; j
++) {
1744 struct vc4_varying_semantic
*output
=
1745 &c
->output_semantics
[j
];
1747 if (input
->semantic
== output
->semantic
&&
1748 input
->index
== output
->index
&&
1749 input
->swizzle
== output
->swizzle
) {
1750 qir_VPM_WRITE(c
, c
->outputs
[j
]);
1754 /* Emit padding if we didn't find a declared VS output for
1757 if (j
== c
->num_outputs
)
1758 qir_VPM_WRITE(c
, qir_uniform_f(c
, 0.0));
1763 emit_coord_end(struct vc4_compile
*c
)
1765 struct qreg rcp_w
= qir_RCP(c
, c
->outputs
[3]);
1767 emit_stub_vpm_read(c
);
1769 for (int i
= 0; i
< 4; i
++)
1770 qir_VPM_WRITE(c
, c
->outputs
[i
]);
1772 emit_scaled_viewport_write(c
, rcp_w
);
1773 emit_zs_write(c
, rcp_w
);
1774 emit_rcp_wc_write(c
, rcp_w
);
1775 if (c
->vs_key
->per_vertex_point_size
)
1776 emit_point_size_write(c
);
1779 static struct vc4_compile
*
1780 vc4_shader_tgsi_to_qir(struct vc4_context
*vc4
, enum qstage stage
,
1781 struct vc4_key
*key
)
1783 struct vc4_compile
*c
= qir_compile_init();
1787 c
->shader_state
= &key
->shader_state
->base
;
1792 c
->fs_key
= (struct vc4_fs_key
*)key
;
1793 if (c
->fs_key
->is_points
) {
1794 c
->point_x
= emit_fragment_varying(c
, ~0, ~0, 0);
1795 c
->point_y
= emit_fragment_varying(c
, ~0, ~0, 0);
1796 } else if (c
->fs_key
->is_lines
) {
1797 c
->line_x
= emit_fragment_varying(c
, ~0, ~0, 0);
1801 c
->vs_key
= (struct vc4_vs_key
*)key
;
1804 c
->vs_key
= (struct vc4_vs_key
*)key
;
1808 const struct tgsi_token
*tokens
= key
->shader_state
->base
.tokens
;
1809 if (c
->fs_key
&& c
->fs_key
->light_twoside
) {
1810 if (!key
->shader_state
->twoside_tokens
) {
1811 const struct tgsi_lowering_config lowering_config
= {
1812 .color_two_side
= true,
1814 struct tgsi_shader_info info
;
1815 key
->shader_state
->twoside_tokens
=
1816 tgsi_transform_lowering(&lowering_config
,
1817 key
->shader_state
->base
.tokens
,
1820 /* If no transformation occurred, then NULL is
1821 * returned and we just use our original tokens.
1823 if (!key
->shader_state
->twoside_tokens
) {
1824 key
->shader_state
->twoside_tokens
=
1825 key
->shader_state
->base
.tokens
;
1828 tokens
= key
->shader_state
->twoside_tokens
;
1831 ret
= tgsi_parse_init(&c
->parser
, tokens
);
1832 assert(ret
== TGSI_PARSE_OK
);
1834 if (vc4_debug
& VC4_DEBUG_TGSI
) {
1835 fprintf(stderr
, "TGSI:\n");
1836 tgsi_dump(tokens
, 0);
1839 while (!tgsi_parse_end_of_tokens(&c
->parser
)) {
1840 tgsi_parse_token(&c
->parser
);
1842 switch (c
->parser
.FullToken
.Token
.Type
) {
1843 case TGSI_TOKEN_TYPE_DECLARATION
:
1844 emit_tgsi_declaration(c
,
1845 &c
->parser
.FullToken
.FullDeclaration
);
1848 case TGSI_TOKEN_TYPE_INSTRUCTION
:
1849 emit_tgsi_instruction(c
,
1850 &c
->parser
.FullToken
.FullInstruction
);
1853 case TGSI_TOKEN_TYPE_IMMEDIATE
:
1854 parse_tgsi_immediate(c
,
1855 &c
->parser
.FullToken
.FullImmediate
);
1866 vc4
->prog
.fs
->input_semantics
,
1867 vc4
->prog
.fs
->num_inputs
);
1874 tgsi_parse_free(&c
->parser
);
1878 if (vc4_debug
& VC4_DEBUG_QIR
) {
1879 fprintf(stderr
, "QIR:\n");
1882 qir_reorder_uniforms(c
);
1883 vc4_generate_code(vc4
, c
);
1885 if (vc4_debug
& VC4_DEBUG_SHADERDB
) {
1886 fprintf(stderr
, "SHADER-DB: %s: %d instructions\n",
1887 qir_get_stage_name(c
->stage
), c
->qpu_inst_count
);
1888 fprintf(stderr
, "SHADER-DB: %s: %d uniforms\n",
1889 qir_get_stage_name(c
->stage
), c
->num_uniforms
);
1896 vc4_shader_state_create(struct pipe_context
*pctx
,
1897 const struct pipe_shader_state
*cso
)
1899 struct vc4_uncompiled_shader
*so
= CALLOC_STRUCT(vc4_uncompiled_shader
);
1903 const struct tgsi_lowering_config lowering_config
= {
1918 struct tgsi_shader_info info
;
1919 so
->base
.tokens
= tgsi_transform_lowering(&lowering_config
, cso
->tokens
, &info
);
1920 if (!so
->base
.tokens
)
1921 so
->base
.tokens
= tgsi_dup_tokens(cso
->tokens
);
1927 copy_uniform_state_to_shader(struct vc4_compiled_shader
*shader
,
1928 struct vc4_compile
*c
)
1930 int count
= c
->num_uniforms
;
1931 struct vc4_shader_uniform_info
*uinfo
= &shader
->uniforms
;
1933 uinfo
->count
= count
;
1934 uinfo
->data
= ralloc_array(shader
, uint32_t, count
);
1935 memcpy(uinfo
->data
, c
->uniform_data
,
1936 count
* sizeof(*uinfo
->data
));
1937 uinfo
->contents
= ralloc_array(shader
, enum quniform_contents
, count
);
1938 memcpy(uinfo
->contents
, c
->uniform_contents
,
1939 count
* sizeof(*uinfo
->contents
));
1940 uinfo
->num_texture_samples
= c
->num_texture_samples
;
1943 static struct vc4_compiled_shader
*
1944 vc4_get_compiled_shader(struct vc4_context
*vc4
, enum qstage stage
,
1945 struct vc4_key
*key
)
1947 struct util_hash_table
*ht
;
1949 if (stage
== QSTAGE_FRAG
) {
1951 key_size
= sizeof(struct vc4_fs_key
);
1954 key_size
= sizeof(struct vc4_vs_key
);
1957 struct vc4_compiled_shader
*shader
;
1958 shader
= util_hash_table_get(ht
, key
);
1962 struct vc4_compile
*c
= vc4_shader_tgsi_to_qir(vc4
, stage
, key
);
1963 shader
= rzalloc(NULL
, struct vc4_compiled_shader
);
1965 shader
->program_id
= vc4
->next_compiled_program_id
++;
1966 if (stage
== QSTAGE_FRAG
) {
1967 shader
->input_semantics
= ralloc_array(shader
,
1968 struct vc4_varying_semantic
,
1969 c
->num_input_semantics
);
1971 for (int i
= 0; i
< c
->num_input_semantics
; i
++) {
1972 struct vc4_varying_semantic
*sem
= &c
->input_semantics
[i
];
1974 /* Skip non-VS-output inputs. */
1975 if (sem
->semantic
== (uint8_t)~0)
1978 if (sem
->semantic
== TGSI_SEMANTIC_COLOR
)
1979 shader
->color_inputs
|= (1 << shader
->num_inputs
);
1980 shader
->input_semantics
[shader
->num_inputs
] = *sem
;
1981 shader
->num_inputs
++;
1984 shader
->num_inputs
= c
->num_inputs
;
1987 copy_uniform_state_to_shader(shader
, c
);
1988 shader
->bo
= vc4_bo_alloc_mem(vc4
->screen
, c
->qpu_insts
,
1989 c
->qpu_inst_count
* sizeof(uint64_t),
1992 qir_compile_destroy(c
);
1994 struct vc4_key
*dup_key
;
1995 dup_key
= malloc(key_size
);
1996 memcpy(dup_key
, key
, key_size
);
1997 util_hash_table_set(ht
, dup_key
, shader
);
2003 vc4_setup_shared_key(struct vc4_context
*vc4
, struct vc4_key
*key
,
2004 struct vc4_texture_stateobj
*texstate
)
2006 for (int i
= 0; i
< texstate
->num_textures
; i
++) {
2007 struct pipe_sampler_view
*sampler
= texstate
->textures
[i
];
2008 struct pipe_sampler_state
*sampler_state
=
2009 texstate
->samplers
[i
];
2012 key
->tex
[i
].format
= sampler
->format
;
2013 key
->tex
[i
].swizzle
[0] = sampler
->swizzle_r
;
2014 key
->tex
[i
].swizzle
[1] = sampler
->swizzle_g
;
2015 key
->tex
[i
].swizzle
[2] = sampler
->swizzle_b
;
2016 key
->tex
[i
].swizzle
[3] = sampler
->swizzle_a
;
2017 key
->tex
[i
].compare_mode
= sampler_state
->compare_mode
;
2018 key
->tex
[i
].compare_func
= sampler_state
->compare_func
;
2019 key
->tex
[i
].wrap_s
= sampler_state
->wrap_s
;
2020 key
->tex
[i
].wrap_t
= sampler_state
->wrap_t
;
2024 key
->ucp_enables
= vc4
->rasterizer
->base
.clip_plane_enable
;
2028 vc4_update_compiled_fs(struct vc4_context
*vc4
, uint8_t prim_mode
)
2030 struct vc4_fs_key local_key
;
2031 struct vc4_fs_key
*key
= &local_key
;
2033 if (!(vc4
->dirty
& (VC4_DIRTY_PRIM_MODE
|
2035 VC4_DIRTY_FRAMEBUFFER
|
2037 VC4_DIRTY_RASTERIZER
|
2039 VC4_DIRTY_TEXSTATE
|
2044 memset(key
, 0, sizeof(*key
));
2045 vc4_setup_shared_key(vc4
, &key
->base
, &vc4
->fragtex
);
2046 key
->base
.shader_state
= vc4
->prog
.bind_fs
;
2047 key
->is_points
= (prim_mode
== PIPE_PRIM_POINTS
);
2048 key
->is_lines
= (prim_mode
>= PIPE_PRIM_LINES
&&
2049 prim_mode
<= PIPE_PRIM_LINE_STRIP
);
2050 key
->blend
= vc4
->blend
->rt
[0];
2052 if (vc4
->framebuffer
.cbufs
[0])
2053 key
->color_format
= vc4
->framebuffer
.cbufs
[0]->format
;
2055 key
->stencil_enabled
= vc4
->zsa
->stencil_uniforms
[0] != 0;
2056 key
->stencil_twoside
= vc4
->zsa
->stencil_uniforms
[1] != 0;
2057 key
->stencil_full_writemasks
= vc4
->zsa
->stencil_uniforms
[2] != 0;
2058 key
->depth_enabled
= (vc4
->zsa
->base
.depth
.enabled
||
2059 key
->stencil_enabled
);
2060 if (vc4
->zsa
->base
.alpha
.enabled
) {
2061 key
->alpha_test
= true;
2062 key
->alpha_test_func
= vc4
->zsa
->base
.alpha
.func
;
2065 if (key
->is_points
) {
2066 key
->point_sprite_mask
=
2067 vc4
->rasterizer
->base
.sprite_coord_enable
;
2068 key
->point_coord_upper_left
=
2069 (vc4
->rasterizer
->base
.sprite_coord_mode
==
2070 PIPE_SPRITE_COORD_UPPER_LEFT
);
2073 key
->light_twoside
= vc4
->rasterizer
->base
.light_twoside
;
2075 struct vc4_compiled_shader
*old_fs
= vc4
->prog
.fs
;
2076 vc4
->prog
.fs
= vc4_get_compiled_shader(vc4
, QSTAGE_FRAG
, &key
->base
);
2077 if (vc4
->prog
.fs
== old_fs
)
2080 if (vc4
->rasterizer
->base
.flatshade
&&
2081 old_fs
&& vc4
->prog
.fs
->color_inputs
!= old_fs
->color_inputs
) {
2082 vc4
->dirty
|= VC4_DIRTY_FLAT_SHADE_FLAGS
;
2087 vc4_update_compiled_vs(struct vc4_context
*vc4
, uint8_t prim_mode
)
2089 struct vc4_vs_key local_key
;
2090 struct vc4_vs_key
*key
= &local_key
;
2092 if (!(vc4
->dirty
& (VC4_DIRTY_PRIM_MODE
|
2093 VC4_DIRTY_RASTERIZER
|
2095 VC4_DIRTY_TEXSTATE
|
2096 VC4_DIRTY_VTXSTATE
|
2101 memset(key
, 0, sizeof(*key
));
2102 vc4_setup_shared_key(vc4
, &key
->base
, &vc4
->verttex
);
2103 key
->base
.shader_state
= vc4
->prog
.bind_vs
;
2104 key
->compiled_fs_id
= vc4
->prog
.fs
->program_id
;
2106 for (int i
= 0; i
< ARRAY_SIZE(key
->attr_formats
); i
++)
2107 key
->attr_formats
[i
] = vc4
->vtx
->pipe
[i
].src_format
;
2109 key
->per_vertex_point_size
=
2110 (prim_mode
== PIPE_PRIM_POINTS
&&
2111 vc4
->rasterizer
->base
.point_size_per_vertex
);
2113 vc4
->prog
.vs
= vc4_get_compiled_shader(vc4
, QSTAGE_VERT
, &key
->base
);
2114 key
->is_coord
= true;
2115 vc4
->prog
.cs
= vc4_get_compiled_shader(vc4
, QSTAGE_COORD
, &key
->base
);
2119 vc4_update_compiled_shaders(struct vc4_context
*vc4
, uint8_t prim_mode
)
2121 vc4_update_compiled_fs(vc4
, prim_mode
);
2122 vc4_update_compiled_vs(vc4
, prim_mode
);
2126 fs_cache_hash(void *key
)
2128 return _mesa_hash_data(key
, sizeof(struct vc4_fs_key
));
2132 vs_cache_hash(void *key
)
2134 return _mesa_hash_data(key
, sizeof(struct vc4_vs_key
));
2138 fs_cache_compare(void *key1
, void *key2
)
2140 return memcmp(key1
, key2
, sizeof(struct vc4_fs_key
));
2144 vs_cache_compare(void *key1
, void *key2
)
2146 return memcmp(key1
, key2
, sizeof(struct vc4_vs_key
));
2149 struct delete_state
{
2150 struct vc4_context
*vc4
;
2151 struct vc4_uncompiled_shader
*shader_state
;
2154 static enum pipe_error
2155 fs_delete_from_cache(void *in_key
, void *in_value
, void *data
)
2157 struct delete_state
*del
= data
;
2158 struct vc4_fs_key
*key
= in_key
;
2159 struct vc4_compiled_shader
*shader
= in_value
;
2161 if (key
->base
.shader_state
== data
) {
2162 util_hash_table_remove(del
->vc4
->fs_cache
, key
);
2163 vc4_bo_unreference(&shader
->bo
);
2164 ralloc_free(shader
);
2170 static enum pipe_error
2171 vs_delete_from_cache(void *in_key
, void *in_value
, void *data
)
2173 struct delete_state
*del
= data
;
2174 struct vc4_vs_key
*key
= in_key
;
2175 struct vc4_compiled_shader
*shader
= in_value
;
2177 if (key
->base
.shader_state
== data
) {
2178 util_hash_table_remove(del
->vc4
->vs_cache
, key
);
2179 vc4_bo_unreference(&shader
->bo
);
2180 ralloc_free(shader
);
2187 vc4_shader_state_delete(struct pipe_context
*pctx
, void *hwcso
)
2189 struct vc4_context
*vc4
= vc4_context(pctx
);
2190 struct vc4_uncompiled_shader
*so
= hwcso
;
2191 struct delete_state del
;
2194 del
.shader_state
= so
;
2195 util_hash_table_foreach(vc4
->fs_cache
, fs_delete_from_cache
, &del
);
2196 util_hash_table_foreach(vc4
->vs_cache
, vs_delete_from_cache
, &del
);
2198 if (so
->twoside_tokens
!= so
->base
.tokens
)
2199 free((void *)so
->twoside_tokens
);
2200 free((void *)so
->base
.tokens
);
2204 static uint32_t translate_wrap(uint32_t p_wrap
, bool using_nearest
)
2207 case PIPE_TEX_WRAP_REPEAT
:
2209 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
2211 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
2213 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
2215 case PIPE_TEX_WRAP_CLAMP
:
2216 return (using_nearest
? 1 : 3);
2218 fprintf(stderr
, "Unknown wrap mode %d\n", p_wrap
);
2219 assert(!"not reached");
2225 write_texture_p0(struct vc4_context
*vc4
,
2226 struct vc4_texture_stateobj
*texstate
,
2229 struct pipe_sampler_view
*texture
= texstate
->textures
[unit
];
2230 struct vc4_resource
*rsc
= vc4_resource(texture
->texture
);
2232 cl_reloc(vc4
, &vc4
->uniforms
, rsc
->bo
,
2233 VC4_SET_FIELD(rsc
->slices
[0].offset
>> 12, VC4_TEX_P0_OFFSET
) |
2234 VC4_SET_FIELD(texture
->u
.tex
.last_level
, VC4_TEX_P0_MIPLVLS
) |
2235 VC4_SET_FIELD(texture
->target
== PIPE_TEXTURE_CUBE
,
2236 VC4_TEX_P0_CMMODE
) |
2237 VC4_SET_FIELD(rsc
->vc4_format
& 7, VC4_TEX_P0_TYPE
));
2241 write_texture_p1(struct vc4_context
*vc4
,
2242 struct vc4_texture_stateobj
*texstate
,
2245 struct pipe_sampler_view
*texture
= texstate
->textures
[unit
];
2246 struct vc4_resource
*rsc
= vc4_resource(texture
->texture
);
2247 struct pipe_sampler_state
*sampler
= texstate
->samplers
[unit
];
2248 static const uint8_t minfilter_map
[6] = {
2249 VC4_TEX_P1_MINFILT_NEAR_MIP_NEAR
,
2250 VC4_TEX_P1_MINFILT_LIN_MIP_NEAR
,
2251 VC4_TEX_P1_MINFILT_NEAR_MIP_LIN
,
2252 VC4_TEX_P1_MINFILT_LIN_MIP_LIN
,
2253 VC4_TEX_P1_MINFILT_NEAREST
,
2254 VC4_TEX_P1_MINFILT_LINEAR
,
2256 static const uint32_t magfilter_map
[] = {
2257 [PIPE_TEX_FILTER_NEAREST
] = VC4_TEX_P1_MAGFILT_NEAREST
,
2258 [PIPE_TEX_FILTER_LINEAR
] = VC4_TEX_P1_MAGFILT_LINEAR
,
2261 bool either_nearest
=
2262 (sampler
->mag_img_filter
== PIPE_TEX_MIPFILTER_NEAREST
||
2263 sampler
->min_img_filter
== PIPE_TEX_MIPFILTER_NEAREST
);
2265 cl_u32(&vc4
->uniforms
,
2266 VC4_SET_FIELD(rsc
->vc4_format
>> 4, VC4_TEX_P1_TYPE4
) |
2267 VC4_SET_FIELD(texture
->texture
->height0
& 2047,
2268 VC4_TEX_P1_HEIGHT
) |
2269 VC4_SET_FIELD(texture
->texture
->width0
& 2047,
2271 VC4_SET_FIELD(magfilter_map
[sampler
->mag_img_filter
],
2272 VC4_TEX_P1_MAGFILT
) |
2273 VC4_SET_FIELD(minfilter_map
[sampler
->min_mip_filter
* 2 +
2274 sampler
->min_img_filter
],
2275 VC4_TEX_P1_MINFILT
) |
2276 VC4_SET_FIELD(translate_wrap(sampler
->wrap_s
, either_nearest
),
2277 VC4_TEX_P1_WRAP_S
) |
2278 VC4_SET_FIELD(translate_wrap(sampler
->wrap_t
, either_nearest
),
2279 VC4_TEX_P1_WRAP_T
));
2283 write_texture_p2(struct vc4_context
*vc4
,
2284 struct vc4_texture_stateobj
*texstate
,
2287 uint32_t unit
= data
& 0xffff;
2288 struct pipe_sampler_view
*texture
= texstate
->textures
[unit
];
2289 struct vc4_resource
*rsc
= vc4_resource(texture
->texture
);
2291 cl_u32(&vc4
->uniforms
,
2292 VC4_SET_FIELD(VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE
,
2294 VC4_SET_FIELD(rsc
->cube_map_stride
>> 12, VC4_TEX_P2_CMST
) |
2295 VC4_SET_FIELD((data
>> 16) & 1, VC4_TEX_P2_BSLOD
));
2299 #define SWIZ(x,y,z,w) { \
2300 UTIL_FORMAT_SWIZZLE_##x, \
2301 UTIL_FORMAT_SWIZZLE_##y, \
2302 UTIL_FORMAT_SWIZZLE_##z, \
2303 UTIL_FORMAT_SWIZZLE_##w \
2307 write_texture_border_color(struct vc4_context
*vc4
,
2308 struct vc4_texture_stateobj
*texstate
,
2311 struct pipe_sampler_state
*sampler
= texstate
->samplers
[unit
];
2312 struct pipe_sampler_view
*texture
= texstate
->textures
[unit
];
2313 struct vc4_resource
*rsc
= vc4_resource(texture
->texture
);
2314 union util_color uc
;
2316 const struct util_format_description
*tex_format_desc
=
2317 util_format_description(texture
->format
);
2319 float border_color
[4];
2320 for (int i
= 0; i
< 4; i
++)
2321 border_color
[i
] = sampler
->border_color
.f
[i
];
2322 if (util_format_is_srgb(texture
->format
)) {
2323 for (int i
= 0; i
< 3; i
++)
2325 util_format_linear_to_srgb_float(border_color
[i
]);
2328 /* Turn the border color into the layout of channels that it would
2329 * have when stored as texture contents.
2331 float storage_color
[4];
2332 util_format_unswizzle_4f(storage_color
,
2334 tex_format_desc
->swizzle
);
2336 /* Now, pack so that when the vc4_format-sampled texture contents are
2337 * replaced with our border color, the vc4_get_format_swizzle()
2338 * swizzling will get the right channels.
2340 if (util_format_is_depth_or_stencil(texture
->format
)) {
2341 uc
.ui
[0] = util_pack_z(PIPE_FORMAT_Z24X8_UNORM
,
2342 sampler
->border_color
.f
[0]) << 8;
2344 switch (rsc
->vc4_format
) {
2346 case VC4_TEXTURE_TYPE_RGBA8888
:
2347 util_pack_color(storage_color
,
2348 PIPE_FORMAT_R8G8B8A8_UNORM
, &uc
);
2350 case VC4_TEXTURE_TYPE_RGBA4444
:
2351 util_pack_color(storage_color
,
2352 PIPE_FORMAT_A8B8G8R8_UNORM
, &uc
);
2354 case VC4_TEXTURE_TYPE_RGB565
:
2355 util_pack_color(storage_color
,
2356 PIPE_FORMAT_B8G8R8A8_UNORM
, &uc
);
2358 case VC4_TEXTURE_TYPE_ALPHA
:
2359 uc
.ui
[0] = float_to_ubyte(storage_color
[0]) << 24;
2361 case VC4_TEXTURE_TYPE_LUMALPHA
:
2362 uc
.ui
[0] = ((float_to_ubyte(storage_color
[1]) << 24) |
2363 (float_to_ubyte(storage_color
[0]) << 0));
2368 cl_u32(&vc4
->uniforms
, uc
.ui
[0]);
2372 get_texrect_scale(struct vc4_texture_stateobj
*texstate
,
2373 enum quniform_contents contents
,
2376 struct pipe_sampler_view
*texture
= texstate
->textures
[data
];
2379 if (contents
== QUNIFORM_TEXRECT_SCALE_X
)
2380 dim
= texture
->texture
->width0
;
2382 dim
= texture
->texture
->height0
;
2384 return fui(1.0f
/ dim
);
2388 vc4_write_uniforms(struct vc4_context
*vc4
, struct vc4_compiled_shader
*shader
,
2389 struct vc4_constbuf_stateobj
*cb
,
2390 struct vc4_texture_stateobj
*texstate
)
2392 struct vc4_shader_uniform_info
*uinfo
= &shader
->uniforms
;
2393 const uint32_t *gallium_uniforms
= cb
->cb
[0].user_buffer
;
2395 cl_start_shader_reloc(&vc4
->uniforms
, uinfo
->num_texture_samples
);
2397 for (int i
= 0; i
< uinfo
->count
; i
++) {
2399 switch (uinfo
->contents
[i
]) {
2400 case QUNIFORM_CONSTANT
:
2401 cl_u32(&vc4
->uniforms
, uinfo
->data
[i
]);
2403 case QUNIFORM_UNIFORM
:
2404 cl_u32(&vc4
->uniforms
,
2405 gallium_uniforms
[uinfo
->data
[i
]]);
2407 case QUNIFORM_VIEWPORT_X_SCALE
:
2408 cl_f(&vc4
->uniforms
, vc4
->viewport
.scale
[0] * 16.0f
);
2410 case QUNIFORM_VIEWPORT_Y_SCALE
:
2411 cl_f(&vc4
->uniforms
, vc4
->viewport
.scale
[1] * 16.0f
);
2414 case QUNIFORM_VIEWPORT_Z_OFFSET
:
2415 cl_f(&vc4
->uniforms
, vc4
->viewport
.translate
[2]);
2417 case QUNIFORM_VIEWPORT_Z_SCALE
:
2418 cl_f(&vc4
->uniforms
, vc4
->viewport
.scale
[2]);
2421 case QUNIFORM_USER_CLIP_PLANE
:
2422 cl_f(&vc4
->uniforms
,
2423 vc4
->clip
.ucp
[uinfo
->data
[i
] / 4][uinfo
->data
[i
] % 4]);
2426 case QUNIFORM_TEXTURE_CONFIG_P0
:
2427 write_texture_p0(vc4
, texstate
, uinfo
->data
[i
]);
2430 case QUNIFORM_TEXTURE_CONFIG_P1
:
2431 write_texture_p1(vc4
, texstate
, uinfo
->data
[i
]);
2434 case QUNIFORM_TEXTURE_CONFIG_P2
:
2435 write_texture_p2(vc4
, texstate
, uinfo
->data
[i
]);
2438 case QUNIFORM_TEXTURE_BORDER_COLOR
:
2439 write_texture_border_color(vc4
, texstate
, uinfo
->data
[i
]);
2442 case QUNIFORM_TEXRECT_SCALE_X
:
2443 case QUNIFORM_TEXRECT_SCALE_Y
:
2444 cl_u32(&vc4
->uniforms
,
2445 get_texrect_scale(texstate
,
2450 case QUNIFORM_BLEND_CONST_COLOR
:
2451 cl_f(&vc4
->uniforms
,
2452 vc4
->blend_color
.color
[uinfo
->data
[i
]]);
2455 case QUNIFORM_STENCIL
:
2456 cl_u32(&vc4
->uniforms
,
2457 vc4
->zsa
->stencil_uniforms
[uinfo
->data
[i
]] |
2458 (uinfo
->data
[i
] <= 1 ?
2459 (vc4
->stencil_ref
.ref_value
[uinfo
->data
[i
]] << 8) :
2463 case QUNIFORM_ALPHA_REF
:
2464 cl_f(&vc4
->uniforms
, vc4
->zsa
->base
.alpha
.ref_value
);
2468 uint32_t written_val
= *(uint32_t *)(vc4
->uniforms
.next
- 4);
2469 fprintf(stderr
, "%p/%d: %d: 0x%08x (%f)\n",
2470 shader
, i
, written_val
, uif(written_val
));
2476 vc4_fp_state_bind(struct pipe_context
*pctx
, void *hwcso
)
2478 struct vc4_context
*vc4
= vc4_context(pctx
);
2479 vc4
->prog
.bind_fs
= hwcso
;
2480 vc4
->prog
.dirty
|= VC4_SHADER_DIRTY_FP
;
2481 vc4
->dirty
|= VC4_DIRTY_PROG
;
2485 vc4_vp_state_bind(struct pipe_context
*pctx
, void *hwcso
)
2487 struct vc4_context
*vc4
= vc4_context(pctx
);
2488 vc4
->prog
.bind_vs
= hwcso
;
2489 vc4
->prog
.dirty
|= VC4_SHADER_DIRTY_VP
;
2490 vc4
->dirty
|= VC4_DIRTY_PROG
;
2494 vc4_program_init(struct pipe_context
*pctx
)
2496 struct vc4_context
*vc4
= vc4_context(pctx
);
2498 pctx
->create_vs_state
= vc4_shader_state_create
;
2499 pctx
->delete_vs_state
= vc4_shader_state_delete
;
2501 pctx
->create_fs_state
= vc4_shader_state_create
;
2502 pctx
->delete_fs_state
= vc4_shader_state_delete
;
2504 pctx
->bind_fs_state
= vc4_fp_state_bind
;
2505 pctx
->bind_vs_state
= vc4_vp_state_bind
;
2507 vc4
->fs_cache
= util_hash_table_create(fs_cache_hash
, fs_cache_compare
);
2508 vc4
->vs_cache
= util_hash_table_create(vs_cache_hash
, vs_cache_compare
);