projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
vc4: Fix handling of non-XYZW swizzles in color outputs.
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <stdio.h>
26 #include <inttypes.h>
27 #include "pipe/p_state.h"
28 #include "util/u_format.h"
29 #include "util/u_hash_table.h"
30 #include "util/u_hash.h"
31 #include "util/u_memory.h"
32 #include "tgsi/tgsi_parse.h"
33 #include "tgsi/tgsi_dump.h"
34
35 #include "vc4_context.h"
36 #include "vc4_qpu.h"
37 #include "vc4_qir.h"
38 #ifdef USE_VC4_SIMULATOR
39 #include "simpenrose/simpenrose.h"
40 #endif
41
42 struct tgsi_to_qir {
43 struct tgsi_parse_context parser;
44 struct qcompile *c;
45 struct qreg *temps;
46 struct qreg *inputs;
47 struct qreg *outputs;
48 struct qreg *uniforms;
49 struct qreg *consts;
50 struct qreg line_x, point_x, point_y;
51
52 uint32_t num_consts;
53
54 struct pipe_shader_state *shader_state;
55 struct vc4_fs_key *fs_key;
56 struct vc4_vs_key *vs_key;
57
58 uint32_t *uniform_data;
59 enum quniform_contents *uniform_contents;
60 uint32_t num_uniforms;
61 uint32_t num_outputs;
62 uint32_t num_texture_samples;
63 };
64
65 struct vc4_key {
66 struct pipe_shader_state *shader_state;
67 };
68
69 struct vc4_fs_key {
70 struct vc4_key base;
71 enum pipe_format color_format;
72 bool depth_enabled;
73 bool is_points;
74 bool is_lines;
75
76 struct pipe_rt_blend_state blend;
77 };
78
79 struct vc4_vs_key {
80 struct vc4_key base;
81 enum pipe_format attr_formats[8];
82 };
83
84 static struct qreg
85 add_uniform(struct tgsi_to_qir *trans,
86 enum quniform_contents contents,
87 uint32_t data)
88 {
89 uint32_t uniform = trans->num_uniforms++;
90 struct qreg u = { QFILE_UNIF, uniform };
91
92 trans->uniform_contents[uniform] = contents;
93 trans->uniform_data[uniform] = data;
94
95 return u;
96 }
97
98 static struct qreg
99 get_temp_for_uniform(struct tgsi_to_qir *trans, enum quniform_contents contents,
100 uint32_t data)
101 {
102 struct qcompile *c = trans->c;
103
104 for (int i = 0; i < trans->num_uniforms; i++) {
105 if (trans->uniform_contents[i] == contents &&
106 trans->uniform_data[i] == data)
107 return trans->uniforms[i];
108 }
109
110 struct qreg u = add_uniform(trans, contents, data);
111 struct qreg t = qir_MOV(c, u);
112
113 trans->uniforms[u.index] = t;
114 return t;
115 }
116
117 static struct qreg
118 qir_uniform_ui(struct tgsi_to_qir *trans, uint32_t ui)
119 {
120 return get_temp_for_uniform(trans, QUNIFORM_CONSTANT, ui);
121 }
122
123 static struct qreg
124 qir_uniform_f(struct tgsi_to_qir *trans, float f)
125 {
126 return qir_uniform_ui(trans, fui(f));
127 }
128
129 static struct qreg
130 get_src(struct tgsi_to_qir *trans, struct tgsi_src_register *src, int i)
131 {
132 struct qcompile *c = trans->c;
133 struct qreg r = c->undef;
134
135 uint32_t s = i;
136 switch (i) {
137 case TGSI_SWIZZLE_X:
138 s = src->SwizzleX;
139 break;
140 case TGSI_SWIZZLE_Y:
141 s = src->SwizzleY;
142 break;
143 case TGSI_SWIZZLE_Z:
144 s = src->SwizzleZ;
145 break;
146 case TGSI_SWIZZLE_W:
147 s = src->SwizzleW;
148 break;
149 default:
150 abort();
151 }
152
153 assert(!src->Indirect);
154
155 switch (src->File) {
156 case TGSI_FILE_NULL:
157 return r;
158 case TGSI_FILE_TEMPORARY:
159 r = trans->temps[src->Index * 4 + s];
160 break;
161 case TGSI_FILE_IMMEDIATE:
162 r = trans->consts[src->Index * 4 + s];
163 break;
164 case TGSI_FILE_CONSTANT:
165 r = get_temp_for_uniform(trans, QUNIFORM_UNIFORM,
166 src->Index * 4 + s);
167 break;
168 case TGSI_FILE_INPUT:
169 r = trans->inputs[src->Index * 4 + s];
170 break;
171 case TGSI_FILE_SAMPLER:
172 case TGSI_FILE_SAMPLER_VIEW:
173 r = c->undef;
174 break;
175 default:
176 fprintf(stderr, "unknown src file %d\n", src->File);
177 abort();
178 }
179
180 if (src->Absolute)
181 r = qir_FMAXABS(c, r, r);
182
183 if (src->Negate)
184 r = qir_FSUB(c, qir_uniform_f(trans, 0), r);
185
186 return r;
187 };
188
189
190 static void
191 update_dst(struct tgsi_to_qir *trans, struct tgsi_full_instruction *tgsi_inst,
192 int i, struct qreg val)
193 {
194 struct tgsi_dst_register *tgsi_dst = &tgsi_inst->Dst[0].Register;
195
196 assert(!tgsi_dst->Indirect);
197
198 switch (tgsi_dst->File) {
199 case TGSI_FILE_TEMPORARY:
200 trans->temps[tgsi_dst->Index * 4 + i] = val;
201 break;
202 case TGSI_FILE_OUTPUT:
203 trans->outputs[tgsi_dst->Index * 4 + i] = val;
204 trans->num_outputs = MAX2(trans->num_outputs,
205 tgsi_dst->Index * 4 + i + 1);
206 break;
207 default:
208 fprintf(stderr, "unknown dst file %d\n", tgsi_dst->File);
209 abort();
210 }
211 };
212
213 static struct qreg
214 get_swizzled_channel(struct tgsi_to_qir *trans,
215 struct qreg *srcs, int swiz)
216 {
217 switch (swiz) {
218 default:
219 case UTIL_FORMAT_SWIZZLE_NONE:
220 fprintf(stderr, "warning: unknown swizzle\n");
221 /* FALLTHROUGH */
222 case UTIL_FORMAT_SWIZZLE_0:
223 return qir_uniform_f(trans, 0.0);
224 case UTIL_FORMAT_SWIZZLE_1:
225 return qir_uniform_f(trans, 1.0);
226 case UTIL_FORMAT_SWIZZLE_X:
227 case UTIL_FORMAT_SWIZZLE_Y:
228 case UTIL_FORMAT_SWIZZLE_Z:
229 case UTIL_FORMAT_SWIZZLE_W:
230 return srcs[swiz];
231 }
232 }
233
234 static struct qreg
235 tgsi_to_qir_alu(struct tgsi_to_qir *trans,
236 struct tgsi_full_instruction *tgsi_inst,
237 enum qop op, struct qreg *src, int i)
238 {
239 struct qcompile *c = trans->c;
240 struct qreg dst = qir_get_temp(c);
241 qir_emit(c, qir_inst4(op, dst,
242 src[0 * 4 + i],
243 src[1 * 4 + i],
244 src[2 * 4 + i],
245 c->undef));
246 return dst;
247 }
248
249 static struct qreg
250 tgsi_to_qir_mad(struct tgsi_to_qir *trans,
251 struct tgsi_full_instruction *tgsi_inst,
252 enum qop op, struct qreg *src, int i)
253 {
254 struct qcompile *c = trans->c;
255 return qir_FADD(c,
256 qir_FMUL(c,
257 src[0 * 4 + i],
258 src[1 * 4 + i]),
259 src[2 * 4 + i]);
260 }
261
262 static struct qreg
263 tgsi_to_qir_lit(struct tgsi_to_qir *trans,
264 struct tgsi_full_instruction *tgsi_inst,
265 enum qop op, struct qreg *src, int i)
266 {
267 struct qcompile *c = trans->c;
268 struct qreg x = src[0 * 4 + 0];
269 struct qreg y = src[0 * 4 + 1];
270 struct qreg w = src[0 * 4 + 3];
271
272 switch (i) {
273 case 0:
274 case 3:
275 return qir_uniform_f(trans, 1.0);
276 case 1:
277 return qir_FMAX(c, src[0 * 4 + 0], qir_uniform_f(trans, 0.0));
278 case 2: {
279 struct qreg zero = qir_uniform_f(trans, 0.0);
280
281 /* XXX: Clamp w to -128..128 */
282 return qir_CMP(c,
283 x,
284 zero,
285 qir_EXP2(c, qir_FMUL(c,
286 w,
287 qir_LOG2(c,
288 qir_FMAX(c,
289 y,
290 zero)))));
291 }
292 default:
293 assert(!"not reached");
294 return c->undef;
295 }
296 }
297
298 static struct qreg
299 tgsi_to_qir_lrp(struct tgsi_to_qir *trans,
300 struct tgsi_full_instruction *tgsi_inst,
301 enum qop op, struct qreg *src, int i)
302 {
303 struct qcompile *c = trans->c;
304 struct qreg src0 = src[0 * 4 + i];
305 struct qreg src1 = src[1 * 4 + i];
306 struct qreg src2 = src[2 * 4 + i];
307
308 /* LRP is:
309 * src0 * src1 + (1 - src0) * src2.
310 * -> src0 * src1 + src2 - src0 * src2
311 * -> src2 + src0 * (src1 - src2)
312 */
313 return qir_FADD(c, src2, qir_FMUL(c, src0, qir_FSUB(c, src1, src2)));
314
315 }
316
317 static void
318 tgsi_to_qir_tex(struct tgsi_to_qir *trans,
319 struct tgsi_full_instruction *tgsi_inst,
320 enum qop op, struct qreg *src)
321 {
322 struct qcompile *c = trans->c;
323
324 assert(!tgsi_inst->Instruction.Saturate);
325
326 struct qreg s = src[0 * 4 + 0];
327 struct qreg t = src[0 * 4 + 1];
328
329 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
330 struct qreg proj = qir_RCP(c, src[0 * 4 + 3]);
331 s = qir_FMUL(c, s, proj);
332 t = qir_FMUL(c, t, proj);
333 }
334
335 /* There is no native support for GL texture rectangle coordinates, so
336 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
337 * 1]).
338 */
339 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_RECT) {
340 uint32_t sampler = 0; /* XXX */
341 s = qir_FMUL(c, s,
342 get_temp_for_uniform(trans,
343 QUNIFORM_TEXRECT_SCALE_X,
344 sampler));
345 t = qir_FMUL(c, t,
346 get_temp_for_uniform(trans,
347 QUNIFORM_TEXRECT_SCALE_Y,
348 sampler));
349 }
350
351 uint32_t tex_and_sampler = 0; /* XXX */
352 qir_TEX_T(c, t, add_uniform(trans, QUNIFORM_TEXTURE_CONFIG_P0,
353 tex_and_sampler));
354
355 struct qreg sampler_p1 = add_uniform(trans, QUNIFORM_TEXTURE_CONFIG_P1,
356 tex_and_sampler);
357 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB) {
358 qir_TEX_B(c, src[0 * 4 + 3], sampler_p1);
359 qir_TEX_S(c, s, add_uniform(trans, QUNIFORM_CONSTANT, 0));
360 } else {
361 qir_TEX_S(c, s, sampler_p1);
362 }
363
364 trans->num_texture_samples++;
365 qir_emit(c, qir_inst(QOP_TEX_RESULT, c->undef, c->undef, c->undef));
366
367 for (int i = 0; i < 4; i++) {
368 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
369 continue;
370
371 struct qreg dst = qir_R4_UNPACK(c, i);
372 update_dst(trans, tgsi_inst, i, dst);
373 }
374 }
375
376 static struct qreg
377 tgsi_to_qir_pow(struct tgsi_to_qir *trans,
378 struct tgsi_full_instruction *tgsi_inst,
379 enum qop op, struct qreg *src, int i)
380 {
381 struct qcompile *c = trans->c;
382
383 /* Note that this instruction replicates its result from the x channel
384 */
385 return qir_EXP2(c, qir_FMUL(c,
386 src[1 * 4 + 0],
387 qir_LOG2(c, src[0 * 4 + 0])));
388 }
389
390 static struct qreg
391 tgsi_to_qir_trunc(struct tgsi_to_qir *trans,
392 struct tgsi_full_instruction *tgsi_inst,
393 enum qop op, struct qreg *src, int i)
394 {
395 struct qcompile *c = trans->c;
396 return qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
397 }
398
399 /**
400 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
401 * to zero).
402 */
403 static struct qreg
404 tgsi_to_qir_frc(struct tgsi_to_qir *trans,
405 struct tgsi_full_instruction *tgsi_inst,
406 enum qop op, struct qreg *src, int i)
407 {
408 struct qcompile *c = trans->c;
409 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
410 struct qreg diff = qir_FSUB(c, src[0 * 4 + i], trunc);
411 return qir_CMP(c,
412 diff,
413 qir_FADD(c, diff, qir_uniform_f(trans, 1.0)),
414 diff);
415 }
416
417 /**
418 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
419 * zero).
420 */
421 static struct qreg
422 tgsi_to_qir_flr(struct tgsi_to_qir *trans,
423 struct tgsi_full_instruction *tgsi_inst,
424 enum qop op, struct qreg *src, int i)
425 {
426 struct qcompile *c = trans->c;
427 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
428 return qir_CMP(c,
429 src[0 * 4 + i],
430 qir_FSUB(c, trunc, qir_uniform_f(trans, 1.0)),
431 trunc);
432 }
433
434 static struct qreg
435 tgsi_to_qir_dp(struct tgsi_to_qir *trans,
436 struct tgsi_full_instruction *tgsi_inst,
437 int num, struct qreg *src, int i)
438 {
439 struct qcompile *c = trans->c;
440
441 struct qreg sum = qir_FMUL(c, src[0 * 4 + 0], src[1 * 4 + 0]);
442 for (int j = 1; j < num; j++) {
443 sum = qir_FADD(c, sum, qir_FMUL(c,
444 src[0 * 4 + j],
445 src[1 * 4 + j]));
446 }
447 return sum;
448 }
449
450 static struct qreg
451 tgsi_to_qir_dp2(struct tgsi_to_qir *trans,
452 struct tgsi_full_instruction *tgsi_inst,
453 enum qop op, struct qreg *src, int i)
454 {
455 return tgsi_to_qir_dp(trans, tgsi_inst, 2, src, i);
456 }
457
458 static struct qreg
459 tgsi_to_qir_dp3(struct tgsi_to_qir *trans,
460 struct tgsi_full_instruction *tgsi_inst,
461 enum qop op, struct qreg *src, int i)
462 {
463 return tgsi_to_qir_dp(trans, tgsi_inst, 3, src, i);
464 }
465
466 static struct qreg
467 tgsi_to_qir_dp4(struct tgsi_to_qir *trans,
468 struct tgsi_full_instruction *tgsi_inst,
469 enum qop op, struct qreg *src, int i)
470 {
471 return tgsi_to_qir_dp(trans, tgsi_inst, 4, src, i);
472 }
473
474 static struct qreg
475 tgsi_to_qir_abs(struct tgsi_to_qir *trans,
476 struct tgsi_full_instruction *tgsi_inst,
477 enum qop op, struct qreg *src, int i)
478 {
479 struct qcompile *c = trans->c;
480 struct qreg arg = src[0 * 4 + i];
481 return qir_FMAXABS(c, arg, arg);
482 }
483
484 /* Note that this instruction replicates its result from the x channel */
485 static struct qreg
486 tgsi_to_qir_sin(struct tgsi_to_qir *trans,
487 struct tgsi_full_instruction *tgsi_inst,
488 enum qop op, struct qreg *src, int i)
489 {
490 struct qcompile *c = trans->c;
491 float coeff[] = {
492 2.0 * M_PI,
493 -pow(2.0 * M_PI, 3) / (3 * 2 * 1),
494 pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
495 -pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
496 };
497
498 struct qreg scaled_x =
499 qir_FMUL(c,
500 src[0 * 4 + 0],
501 qir_uniform_f(trans, 1.0f / (M_PI * 2.0f)));
502
503
504 struct qreg x = tgsi_to_qir_frc(trans, NULL, 0, &scaled_x, 0);
505 struct qreg x2 = qir_FMUL(c, x, x);
506 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(trans, coeff[0]));
507 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
508 x = qir_FMUL(c, x, x2);
509 sum = qir_FADD(c,
510 sum,
511 qir_FMUL(c,
512 x,
513 qir_uniform_f(trans, coeff[i])));
514 }
515 return sum;
516 }
517
518 /* Note that this instruction replicates its result from the x channel */
519 static struct qreg
520 tgsi_to_qir_cos(struct tgsi_to_qir *trans,
521 struct tgsi_full_instruction *tgsi_inst,
522 enum qop op, struct qreg *src, int i)
523 {
524 struct qcompile *c = trans->c;
525 float coeff[] = {
526 1.0f,
527 -pow(2.0 * M_PI, 2) / (2 * 1),
528 pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
529 -pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
530 };
531
532 struct qreg scaled_x =
533 qir_FMUL(c, src[0 * 4 + 0],
534 qir_uniform_f(trans, 1.0f / (M_PI * 2.0f)));
535 struct qreg x_frac = tgsi_to_qir_frc(trans, NULL, 0, &scaled_x, 0);
536
537 struct qreg sum = qir_uniform_f(trans, coeff[0]);
538 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
539 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
540 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
541 if (i != 1)
542 x = qir_FMUL(c, x, x2);
543
544 struct qreg mul = qir_FMUL(c,
545 x,
546 qir_uniform_f(trans, coeff[i]));
547 if (i == 0)
548 sum = mul;
549 else
550 sum = qir_FADD(c, sum, mul);
551 }
552 return sum;
553 }
554
555 static void
556 emit_vertex_input(struct tgsi_to_qir *trans, int attr)
557 {
558 enum pipe_format format = trans->vs_key->attr_formats[attr];
559 struct qcompile *c = trans->c;
560 struct qreg vpm_reads[4];
561
562 /* Right now, we're setting the VPM offsets to be 16 bytes wide every
563 * time, so we always read 4 32-bit VPM entries.
564 */
565 for (int i = 0; i < 4; i++) {
566 vpm_reads[i] = qir_get_temp(c);
567 qir_emit(c, qir_inst(QOP_VPM_READ,
568 vpm_reads[i],
569 c->undef,
570 c->undef));
571 c->num_inputs++;
572 }
573
574 bool format_warned = false;
575 const struct util_format_description *desc =
576 util_format_description(format);
577
578 for (int i = 0; i < 4; i++) {
579 uint8_t swiz = desc->swizzle[i];
580
581 if (swiz <= UTIL_FORMAT_SWIZZLE_W &&
582 !format_warned &&
583 (desc->channel[swiz].type != UTIL_FORMAT_TYPE_FLOAT ||
584 desc->channel[swiz].size != 32)) {
585 fprintf(stderr,
586 "vtx element %d unsupported type: %s\n",
587 attr, util_format_name(format));
588 format_warned = true;
589 }
590
591 trans->inputs[attr * 4 + i] =
592 get_swizzled_channel(trans, vpm_reads, swiz);
593 }
594 }
595
596 static void
597 emit_fragcoord_input(struct tgsi_to_qir *trans, int attr)
598 {
599 struct qcompile *c = trans->c;
600
601 trans->inputs[attr * 4 + 0] = qir_FRAG_X(c);
602 trans->inputs[attr * 4 + 1] = qir_FRAG_Y(c);
603 trans->inputs[attr * 4 + 2] =
604 qir_FMUL(c,
605 qir_FRAG_Z(c),
606 qir_uniform_f(trans, 1.0 / 0xffffff));
607 trans->inputs[attr * 4 + 3] = qir_FRAG_RCP_W(c);
608 }
609
610 static struct qreg
611 emit_fragment_varying(struct tgsi_to_qir *trans, int index)
612 {
613 struct qcompile *c = trans->c;
614
615 struct qreg vary = {
616 QFILE_VARY,
617 index
618 };
619
620 /* XXX: multiply by W */
621 return qir_VARY_ADD_C(c, qir_MOV(c, vary));
622 }
623
624 static void
625 emit_fragment_input(struct tgsi_to_qir *trans, int attr)
626 {
627 struct qcompile *c = trans->c;
628
629 for (int i = 0; i < 4; i++) {
630 trans->inputs[attr * 4 + i] =
631 emit_fragment_varying(trans, attr * 4 + i);
632 c->num_inputs++;
633 }
634 }
635
636 static void
637 emit_tgsi_declaration(struct tgsi_to_qir *trans,
638 struct tgsi_full_declaration *decl)
639 {
640 struct qcompile *c = trans->c;
641
642 switch (decl->Declaration.File) {
643 case TGSI_FILE_INPUT:
644 for (int i = decl->Range.First;
645 i <= decl->Range.Last;
646 i++) {
647 if (c->stage == QSTAGE_FRAG) {
648 if (decl->Semantic.Name ==
649 TGSI_SEMANTIC_POSITION) {
650 emit_fragcoord_input(trans, i);
651 } else {
652 emit_fragment_input(trans, i);
653 }
654 } else {
655 emit_vertex_input(trans, i);
656 }
657 }
658 break;
659 }
660 }
661
662 static void
663 emit_tgsi_instruction(struct tgsi_to_qir *trans,
664 struct tgsi_full_instruction *tgsi_inst)
665 {
666 struct qcompile *c = trans->c;
667 struct {
668 enum qop op;
669 struct qreg (*func)(struct tgsi_to_qir *trans,
670 struct tgsi_full_instruction *tgsi_inst,
671 enum qop op,
672 struct qreg *src, int i);
673 } op_trans[] = {
674 [TGSI_OPCODE_MOV] = { QOP_MOV, tgsi_to_qir_alu },
675 [TGSI_OPCODE_ABS] = { 0, tgsi_to_qir_abs },
676 [TGSI_OPCODE_MUL] = { QOP_FMUL, tgsi_to_qir_alu },
677 [TGSI_OPCODE_ADD] = { QOP_FADD, tgsi_to_qir_alu },
678 [TGSI_OPCODE_SUB] = { QOP_FSUB, tgsi_to_qir_alu },
679 [TGSI_OPCODE_MIN] = { QOP_FMIN, tgsi_to_qir_alu },
680 [TGSI_OPCODE_MAX] = { QOP_FMAX, tgsi_to_qir_alu },
681 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_alu },
682 [TGSI_OPCODE_SEQ] = { QOP_SEQ, tgsi_to_qir_alu },
683 [TGSI_OPCODE_SNE] = { QOP_SNE, tgsi_to_qir_alu },
684 [TGSI_OPCODE_SGE] = { QOP_SGE, tgsi_to_qir_alu },
685 [TGSI_OPCODE_SLT] = { QOP_SLT, tgsi_to_qir_alu },
686 [TGSI_OPCODE_CMP] = { QOP_CMP, tgsi_to_qir_alu },
687 [TGSI_OPCODE_MAD] = { 0, tgsi_to_qir_mad },
688 [TGSI_OPCODE_DP2] = { 0, tgsi_to_qir_dp2 },
689 [TGSI_OPCODE_DP3] = { 0, tgsi_to_qir_dp3 },
690 [TGSI_OPCODE_DP4] = { 0, tgsi_to_qir_dp4 },
691 [TGSI_OPCODE_RCP] = { QOP_RCP, tgsi_to_qir_alu },
692 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_alu },
693 [TGSI_OPCODE_EX2] = { QOP_EXP2, tgsi_to_qir_alu },
694 [TGSI_OPCODE_LG2] = { QOP_LOG2, tgsi_to_qir_alu },
695 [TGSI_OPCODE_LIT] = { 0, tgsi_to_qir_lit },
696 [TGSI_OPCODE_LRP] = { 0, tgsi_to_qir_lrp },
697 [TGSI_OPCODE_POW] = { 0, tgsi_to_qir_pow },
698 [TGSI_OPCODE_TRUNC] = { 0, tgsi_to_qir_trunc },
699 [TGSI_OPCODE_FRC] = { 0, tgsi_to_qir_frc },
700 [TGSI_OPCODE_FLR] = { 0, tgsi_to_qir_flr },
701 [TGSI_OPCODE_SIN] = { 0, tgsi_to_qir_sin },
702 [TGSI_OPCODE_COS] = { 0, tgsi_to_qir_cos },
703 };
704 static int asdf = 0;
705 uint32_t tgsi_op = tgsi_inst->Instruction.Opcode;
706
707 if (tgsi_op == TGSI_OPCODE_END)
708 return;
709
710 struct qreg src_regs[12];
711 for (int s = 0; s < 3; s++) {
712 for (int i = 0; i < 4; i++) {
713 src_regs[4 * s + i] =
714 get_src(trans, &tgsi_inst->Src[s].Register, i);
715 }
716 }
717
718 switch (tgsi_op) {
719 case TGSI_OPCODE_TEX:
720 case TGSI_OPCODE_TXP:
721 case TGSI_OPCODE_TXB:
722 tgsi_to_qir_tex(trans, tgsi_inst,
723 op_trans[tgsi_op].op, src_regs);
724 return;
725 default:
726 break;
727 }
728
729 if (tgsi_op > ARRAY_SIZE(op_trans) || !(op_trans[tgsi_op].func)) {
730 fprintf(stderr, "unknown tgsi inst: ");
731 tgsi_dump_instruction(tgsi_inst, asdf++);
732 fprintf(stderr, "\n");
733 abort();
734 }
735
736 for (int i = 0; i < 4; i++) {
737 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
738 continue;
739
740 struct qreg result;
741
742 result = op_trans[tgsi_op].func(trans, tgsi_inst,
743 op_trans[tgsi_op].op,
744 src_regs, i);
745
746 if (tgsi_inst->Instruction.Saturate) {
747 float low = (tgsi_inst->Instruction.Saturate ==
748 TGSI_SAT_MINUS_PLUS_ONE ? -1.0 : 0.0);
749 result = qir_FMAX(c,
750 qir_FMIN(c,
751 result,
752 qir_uniform_f(trans, 1.0)),
753 qir_uniform_f(trans, low));
754 }
755
756 update_dst(trans, tgsi_inst, i, result);
757 }
758 }
759
760 static void
761 parse_tgsi_immediate(struct tgsi_to_qir *trans, struct tgsi_full_immediate *imm)
762 {
763 for (int i = 0; i < 4; i++) {
764 unsigned n = trans->num_consts++;
765 trans->consts[n] = qir_uniform_ui(trans, imm->u[i].Uint);
766 }
767 }
768
769 static struct qreg
770 vc4_blend_channel(struct tgsi_to_qir *trans,
771 struct qreg *dst,
772 struct qreg *src,
773 struct qreg val,
774 unsigned factor,
775 int channel)
776 {
777 struct qcompile *c = trans->c;
778
779 switch(factor) {
780 case PIPE_BLENDFACTOR_ONE:
781 return val;
782 case PIPE_BLENDFACTOR_SRC_COLOR:
783 return qir_FMUL(c, val, src[channel]);
784 case PIPE_BLENDFACTOR_SRC_ALPHA:
785 return qir_FMUL(c, val, src[3]);
786 case PIPE_BLENDFACTOR_DST_ALPHA:
787 return qir_FMUL(c, val, dst[3]);
788 case PIPE_BLENDFACTOR_DST_COLOR:
789 return qir_FMUL(c, val, dst[channel]);
790 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
791 return qir_FMIN(c, src[3], qir_FSUB(c,
792 qir_uniform_f(trans, 1.0),
793 dst[3]));
794 case PIPE_BLENDFACTOR_CONST_COLOR:
795 return qir_FMUL(c, val,
796 get_temp_for_uniform(trans,
797 QUNIFORM_BLEND_CONST_COLOR,
798 channel));
799 case PIPE_BLENDFACTOR_CONST_ALPHA:
800 return qir_FMUL(c, val,
801 get_temp_for_uniform(trans,
802 QUNIFORM_BLEND_CONST_COLOR,
803 3));
804 case PIPE_BLENDFACTOR_ZERO:
805 return qir_uniform_f(trans, 0.0);
806 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
807 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(trans, 1.0),
808 src[channel]));
809 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
810 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(trans, 1.0),
811 src[3]));
812 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
813 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(trans, 1.0),
814 dst[3]));
815 case PIPE_BLENDFACTOR_INV_DST_COLOR:
816 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(trans, 1.0),
817 dst[channel]));
818 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
819 return qir_FMUL(c, val,
820 qir_FSUB(c, qir_uniform_f(trans, 1.0),
821 get_temp_for_uniform(trans,
822 QUNIFORM_BLEND_CONST_COLOR,
823 channel)));
824 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
825 return qir_FMUL(c, val,
826 qir_FSUB(c, qir_uniform_f(trans, 1.0),
827 get_temp_for_uniform(trans,
828 QUNIFORM_BLEND_CONST_COLOR,
829 3)));
830
831 default:
832 case PIPE_BLENDFACTOR_SRC1_COLOR:
833 case PIPE_BLENDFACTOR_SRC1_ALPHA:
834 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
835 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
836 /* Unsupported. */
837 fprintf(stderr, "Unknown blend factor %d\n", factor);
838 return val;
839 }
840 }
841
842 static struct qreg
843 vc4_blend_func(struct tgsi_to_qir *trans,
844 struct qreg src, struct qreg dst,
845 unsigned func)
846 {
847 struct qcompile *c = trans->c;
848
849 switch (func) {
850 case PIPE_BLEND_ADD:
851 return qir_FADD(c, src, dst);
852 case PIPE_BLEND_SUBTRACT:
853 return qir_FSUB(c, src, dst);
854 case PIPE_BLEND_REVERSE_SUBTRACT:
855 return qir_FSUB(c, dst, src);
856 case PIPE_BLEND_MIN:
857 return qir_FMIN(c, src, dst);
858 case PIPE_BLEND_MAX:
859 return qir_FMAX(c, src, dst);
860
861 default:
862 /* Unsupported. */
863 fprintf(stderr, "Unknown blend func %d\n", func);
864 return src;
865
866 }
867 }
868
869 /**
870 * Implements fixed function blending in shader code.
871 *
872 * VC4 doesn't have any hardware support for blending. Instead, you read the
873 * current contents of the destination from the tile buffer after having
874 * waited for the scoreboard (which is handled by vc4_qpu_emit.c), then do
875 * math using your output color and that destination value, and update the
876 * output color appropriately.
877 */
878 static void
879 vc4_blend(struct tgsi_to_qir *trans, struct qreg *result,
880 struct qreg *dst_color, struct qreg *src_color)
881 {
882 struct pipe_rt_blend_state *blend = &trans->fs_key->blend;
883
884 if (!blend->blend_enable) {
885 for (int i = 0; i < 4; i++)
886 result[i] = src_color[i];
887 return;
888 }
889
890 struct qreg src_blend[4], dst_blend[4];
891 for (int i = 0; i < 3; i++) {
892 src_blend[i] = vc4_blend_channel(trans,
893 dst_color, src_color,
894 src_color[i],
895 blend->rgb_src_factor, i);
896 dst_blend[i] = vc4_blend_channel(trans,
897 dst_color, src_color,
898 dst_color[i],
899 blend->rgb_dst_factor, i);
900 }
901 src_blend[3] = vc4_blend_channel(trans,
902 dst_color, src_color,
903 src_color[3],
904 blend->alpha_src_factor, 3);
905 dst_blend[3] = vc4_blend_channel(trans,
906 dst_color, src_color,
907 dst_color[3],
908 blend->alpha_dst_factor, 3);
909
910 for (int i = 0; i < 3; i++) {
911 result[i] = vc4_blend_func(trans,
912 src_blend[i], dst_blend[i],
913 blend->rgb_func);
914 }
915 result[3] = vc4_blend_func(trans,
916 src_blend[3], dst_blend[3],
917 blend->alpha_func);
918 }
919
920 static void
921 emit_frag_end(struct tgsi_to_qir *trans)
922 {
923 struct qcompile *c = trans->c;
924
925 struct qreg t = qir_get_temp(c);
926
927 const struct util_format_description *format_desc =
928 util_format_description(trans->fs_key->color_format);
929
930 struct qreg src_color[4] = {
931 trans->outputs[0], trans->outputs[1],
932 trans->outputs[2], trans->outputs[3],
933 };
934
935 struct qreg dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
936 if (trans->fs_key->blend.blend_enable ||
937 trans->fs_key->blend.colormask != 0xf) {
938 qir_emit(c, qir_inst(QOP_TLB_COLOR_READ, c->undef,
939 c->undef, c->undef));
940 for (int i = 0; i < 4; i++) {
941 dst_color[i] = qir_R4_UNPACK(c, i);
942
943 /* XXX: Swizzles? */
944 }
945 }
946
947 struct qreg blend_color[4];
948 vc4_blend(trans, blend_color, dst_color, src_color);
949
950 /* If the bit isn't set in the color mask, then just return the
951 * original dst color, instead.
952 */
953 for (int i = 0; i < 4; i++) {
954 if (!(trans->fs_key->blend.colormask & (1 << i))) {
955 blend_color[i] = dst_color[i];
956 }
957 }
958
959 /* Debug: Sometimes you're getting a black output and just want to see
960 * if the FS is getting executed at all. Spam magenta into the color
961 * output.
962 */
963 if (0) {
964 blend_color[0] = qir_uniform_f(trans, 1.0);
965 blend_color[1] = qir_uniform_f(trans, 0.0);
966 blend_color[2] = qir_uniform_f(trans, 1.0);
967 blend_color[3] = qir_uniform_f(trans, 0.5);
968 }
969
970 struct qreg swizzled_outputs[4];
971 for (int i = 0; i < 4; i++) {
972 swizzled_outputs[i] =
973 get_swizzled_channel(trans, blend_color,
974 format_desc->swizzle[i]);
975 }
976
977 if (trans->fs_key->depth_enabled) {
978 qir_emit(c, qir_inst(QOP_TLB_PASSTHROUGH_Z_WRITE, c->undef,
979 c->undef, c->undef));
980 }
981
982 qir_emit(c, qir_inst4(QOP_PACK_COLORS, t,
983 swizzled_outputs[0],
984 swizzled_outputs[1],
985 swizzled_outputs[2],
986 swizzled_outputs[3]));
987 qir_emit(c, qir_inst(QOP_TLB_COLOR_WRITE, c->undef,
988 t, c->undef));
989 }
990
991 static void
992 emit_scaled_viewport_write(struct tgsi_to_qir *trans, struct qreg rcp_w)
993 {
994 struct qcompile *c = trans->c;
995 struct qreg xyi[2];
996
997 for (int i = 0; i < 2; i++) {
998 struct qreg scale =
999 add_uniform(trans, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1000
1001 xyi[i] = qir_FTOI(c, qir_FMUL(c,
1002 qir_FMUL(c,
1003 trans->outputs[i],
1004 scale),
1005 rcp_w));
1006 }
1007
1008 qir_VPM_WRITE(c, qir_PACK_SCALED(c, xyi[0], xyi[1]));
1009 }
1010
1011 static void
1012 emit_zs_write(struct tgsi_to_qir *trans, struct qreg rcp_w)
1013 {
1014 struct qcompile *c = trans->c;
1015
1016 struct qreg zscale = add_uniform(trans, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1017 struct qreg zoffset = add_uniform(trans, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1018
1019 qir_VPM_WRITE(c, qir_FMUL(c, qir_FADD(c, qir_FMUL(c,
1020 trans->outputs[2],
1021 zscale),
1022 zoffset),
1023 rcp_w));
1024 }
1025
1026 static void
1027 emit_rcp_wc_write(struct tgsi_to_qir *trans, struct qreg rcp_w)
1028 {
1029 struct qcompile *c = trans->c;
1030
1031 qir_VPM_WRITE(c, rcp_w);
1032 }
1033
1034 static void
1035 emit_vert_end(struct tgsi_to_qir *trans)
1036 {
1037 struct qcompile *c = trans->c;
1038
1039 struct qreg rcp_w = qir_RCP(c, trans->outputs[3]);
1040
1041 emit_scaled_viewport_write(trans, rcp_w);
1042 emit_zs_write(trans, rcp_w);
1043 emit_rcp_wc_write(trans, rcp_w);
1044
1045 for (int i = 4; i < trans->num_outputs; i++) {
1046 qir_VPM_WRITE(c, trans->outputs[i]);
1047 }
1048 }
1049
1050 static void
1051 emit_coord_end(struct tgsi_to_qir *trans)
1052 {
1053 struct qcompile *c = trans->c;
1054
1055 struct qreg rcp_w = qir_RCP(c, trans->outputs[3]);
1056
1057 for (int i = 0; i < 4; i++)
1058 qir_VPM_WRITE(c, trans->outputs[i]);
1059
1060 emit_scaled_viewport_write(trans, rcp_w);
1061 emit_zs_write(trans, rcp_w);
1062 emit_rcp_wc_write(trans, rcp_w);
1063 }
1064
1065 static struct tgsi_to_qir *
1066 vc4_shader_tgsi_to_qir(struct vc4_compiled_shader *shader, enum qstage stage,
1067 struct vc4_key *key)
1068 {
1069 struct tgsi_to_qir *trans = CALLOC_STRUCT(tgsi_to_qir);
1070 struct qcompile *c;
1071 int ret;
1072
1073 c = qir_compile_init();
1074 c->stage = stage;
1075
1076 memset(trans, 0, sizeof(*trans));
1077 /* XXX sizing */
1078 trans->temps = calloc(sizeof(struct qreg), 1024);
1079 trans->inputs = calloc(sizeof(struct qreg), 8 * 4);
1080 trans->outputs = calloc(sizeof(struct qreg), 1024);
1081 trans->uniforms = calloc(sizeof(struct qreg), 1024);
1082 trans->consts = calloc(sizeof(struct qreg), 1024);
1083
1084 trans->uniform_data = calloc(sizeof(uint32_t), 1024);
1085 trans->uniform_contents = calloc(sizeof(enum quniform_contents), 1024);
1086
1087 trans->shader_state = key->shader_state;
1088 trans->c = c;
1089 ret = tgsi_parse_init(&trans->parser, trans->shader_state->tokens);
1090 assert(ret == TGSI_PARSE_OK);
1091
1092 if (vc4_debug & VC4_DEBUG_TGSI) {
1093 fprintf(stderr, "TGSI:\n");
1094 tgsi_dump(trans->shader_state->tokens, 0);
1095 }
1096
1097 switch (stage) {
1098 case QSTAGE_FRAG:
1099 trans->fs_key = (struct vc4_fs_key *)key;
1100 if (trans->fs_key->is_points) {
1101 trans->point_x = emit_fragment_varying(trans, 0);
1102 trans->point_y = emit_fragment_varying(trans, 0);
1103 } else if (trans->fs_key->is_lines) {
1104 trans->line_x = emit_fragment_varying(trans, 0);
1105 }
1106 break;
1107 case QSTAGE_VERT:
1108 trans->vs_key = (struct vc4_vs_key *)key;
1109 break;
1110 case QSTAGE_COORD:
1111 trans->vs_key = (struct vc4_vs_key *)key;
1112 break;
1113 }
1114
1115 while (!tgsi_parse_end_of_tokens(&trans->parser)) {
1116 tgsi_parse_token(&trans->parser);
1117
1118 switch (trans->parser.FullToken.Token.Type) {
1119 case TGSI_TOKEN_TYPE_DECLARATION:
1120 emit_tgsi_declaration(trans,
1121 &trans->parser.FullToken.FullDeclaration);
1122 break;
1123
1124 case TGSI_TOKEN_TYPE_INSTRUCTION:
1125 emit_tgsi_instruction(trans,
1126 &trans->parser.FullToken.FullInstruction);
1127 break;
1128
1129 case TGSI_TOKEN_TYPE_IMMEDIATE:
1130 parse_tgsi_immediate(trans,
1131 &trans->parser.FullToken.FullImmediate);
1132 break;
1133 }
1134 }
1135
1136 switch (stage) {
1137 case QSTAGE_FRAG:
1138 emit_frag_end(trans);
1139 break;
1140 case QSTAGE_VERT:
1141 emit_vert_end(trans);
1142 break;
1143 case QSTAGE_COORD:
1144 emit_coord_end(trans);
1145 break;
1146 }
1147
1148 tgsi_parse_free(&trans->parser);
1149 free(trans->temps);
1150
1151 qir_optimize(c);
1152
1153 if (vc4_debug & VC4_DEBUG_QIR) {
1154 fprintf(stderr, "QIR:\n");
1155 qir_dump(c);
1156 }
1157 vc4_generate_code(c);
1158
1159 if (vc4_debug & VC4_DEBUG_SHADERDB) {
1160 fprintf(stderr, "SHADER-DB: %s: %d instructions\n",
1161 qir_get_stage_name(c->stage), c->qpu_inst_count);
1162 fprintf(stderr, "SHADER-DB: %s: %d uniforms\n",
1163 qir_get_stage_name(c->stage), trans->num_uniforms);
1164 }
1165
1166 return trans;
1167 }
1168
1169 static void *
1170 vc4_shader_state_create(struct pipe_context *pctx,
1171 const struct pipe_shader_state *cso)
1172 {
1173 struct pipe_shader_state *so = CALLOC_STRUCT(pipe_shader_state);
1174 if (!so)
1175 return NULL;
1176
1177 so->tokens = tgsi_dup_tokens(cso->tokens);
1178
1179 return so;
1180 }
1181
1182 static void
1183 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
1184 int shader_index,
1185 struct tgsi_to_qir *trans)
1186 {
1187 int count = trans->num_uniforms;
1188 struct vc4_shader_uniform_info *uinfo = &shader->uniforms[shader_index];
1189
1190 uinfo->count = count;
1191 uinfo->data = malloc(count * sizeof(*uinfo->data));
1192 memcpy(uinfo->data, trans->uniform_data,
1193 count * sizeof(*uinfo->data));
1194 uinfo->contents = malloc(count * sizeof(*uinfo->contents));
1195 memcpy(uinfo->contents, trans->uniform_contents,
1196 count * sizeof(*uinfo->contents));
1197 uinfo->num_texture_samples = trans->num_texture_samples;
1198 }
1199
1200 static void
1201 vc4_fs_compile(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1202 struct vc4_fs_key *key)
1203 {
1204 struct tgsi_to_qir *trans = vc4_shader_tgsi_to_qir(shader, QSTAGE_FRAG,
1205 &key->base);
1206 shader->num_inputs = trans->c->num_inputs;
1207 copy_uniform_state_to_shader(shader, 0, trans);
1208 shader->bo = vc4_bo_alloc_mem(vc4->screen, trans->c->qpu_insts,
1209 trans->c->qpu_inst_count * sizeof(uint64_t),
1210 "fs_code");
1211
1212 qir_compile_destroy(trans->c);
1213 free(trans);
1214 }
1215
1216 static void
1217 vc4_vs_compile(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1218 struct vc4_vs_key *key)
1219 {
1220 struct tgsi_to_qir *vs_trans = vc4_shader_tgsi_to_qir(shader,
1221 QSTAGE_VERT,
1222 &key->base);
1223 copy_uniform_state_to_shader(shader, 0, vs_trans);
1224
1225 struct tgsi_to_qir *cs_trans = vc4_shader_tgsi_to_qir(shader,
1226 QSTAGE_COORD,
1227 &key->base);
1228 copy_uniform_state_to_shader(shader, 1, cs_trans);
1229
1230 uint32_t vs_size = vs_trans->c->qpu_inst_count * sizeof(uint64_t);
1231 uint32_t cs_size = cs_trans->c->qpu_inst_count * sizeof(uint64_t);
1232 shader->coord_shader_offset = vs_size; /* XXX: alignment? */
1233 shader->bo = vc4_bo_alloc(vc4->screen,
1234 shader->coord_shader_offset + cs_size,
1235 "vs_code");
1236
1237 void *map = vc4_bo_map(shader->bo);
1238 memcpy(map, vs_trans->c->qpu_insts, vs_size);
1239 memcpy(map + shader->coord_shader_offset,
1240 cs_trans->c->qpu_insts, cs_size);
1241
1242 qir_compile_destroy(vs_trans->c);
1243 qir_compile_destroy(cs_trans->c);
1244 }
1245
1246 static void
1247 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
1248 {
1249 struct vc4_fs_key local_key;
1250 struct vc4_fs_key *key = &local_key;
1251
1252 memset(key, 0, sizeof(*key));
1253 key->base.shader_state = vc4->prog.bind_fs;
1254 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
1255 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
1256 prim_mode <= PIPE_PRIM_LINE_STRIP);
1257 key->blend = vc4->blend->rt[0];
1258
1259 if (vc4->framebuffer.cbufs[0])
1260 key->color_format = vc4->framebuffer.cbufs[0]->format;
1261
1262 key->depth_enabled = vc4->zsa->base.depth.enabled;
1263
1264 vc4->prog.fs = util_hash_table_get(vc4->fs_cache, key);
1265 if (vc4->prog.fs)
1266 return;
1267
1268 key = malloc(sizeof(*key));
1269 memcpy(key, &local_key, sizeof(*key));
1270
1271 struct vc4_compiled_shader *shader = CALLOC_STRUCT(vc4_compiled_shader);
1272 vc4_fs_compile(vc4, shader, key);
1273 util_hash_table_set(vc4->fs_cache, key, shader);
1274
1275 vc4->prog.fs = shader;
1276 }
1277
1278 static void
1279 vc4_update_compiled_vs(struct vc4_context *vc4)
1280 {
1281 struct vc4_vs_key local_key;
1282 struct vc4_vs_key *key = &local_key;
1283
1284 memset(key, 0, sizeof(*key));
1285 key->base.shader_state = vc4->prog.bind_vs;
1286
1287 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
1288 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
1289
1290 vc4->prog.vs = util_hash_table_get(vc4->vs_cache, key);
1291 if (vc4->prog.vs)
1292 return;
1293
1294 key = malloc(sizeof(*key));
1295 memcpy(key, &local_key, sizeof(*key));
1296
1297 struct vc4_compiled_shader *shader = CALLOC_STRUCT(vc4_compiled_shader);
1298 vc4_vs_compile(vc4, shader, key);
1299 util_hash_table_set(vc4->vs_cache, key, shader);
1300
1301 vc4->prog.vs = shader;
1302 }
1303
1304 void
1305 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
1306 {
1307 vc4_update_compiled_fs(vc4, prim_mode);
1308 vc4_update_compiled_vs(vc4);
1309 }
1310
1311 static unsigned
1312 fs_cache_hash(void *key)
1313 {
1314 return util_hash_crc32(key, sizeof(struct vc4_fs_key));
1315 }
1316
1317 static unsigned
1318 vs_cache_hash(void *key)
1319 {
1320 return util_hash_crc32(key, sizeof(struct vc4_vs_key));
1321 }
1322
1323 static int
1324 fs_cache_compare(void *key1, void *key2)
1325 {
1326 return memcmp(key1, key2, sizeof(struct vc4_fs_key));
1327 }
1328
1329 static int
1330 vs_cache_compare(void *key1, void *key2)
1331 {
1332 return memcmp(key1, key2, sizeof(struct vc4_vs_key));
1333 }
1334
1335 struct delete_state {
1336 struct vc4_context *vc4;
1337 struct pipe_shader_state *shader_state;
1338 };
1339
1340 static enum pipe_error
1341 fs_delete_from_cache(void *in_key, void *in_value, void *data)
1342 {
1343 struct delete_state *del = data;
1344 struct vc4_fs_key *key = in_key;
1345 struct vc4_compiled_shader *shader = in_value;
1346
1347 if (key->base.shader_state == data) {
1348 util_hash_table_remove(del->vc4->fs_cache, key);
1349 vc4_bo_unreference(&shader->bo);
1350 free(shader);
1351 }
1352
1353 return 0;
1354 }
1355
1356 static enum pipe_error
1357 vs_delete_from_cache(void *in_key, void *in_value, void *data)
1358 {
1359 struct delete_state *del = data;
1360 struct vc4_vs_key *key = in_key;
1361 struct vc4_compiled_shader *shader = in_value;
1362
1363 if (key->base.shader_state == data) {
1364 util_hash_table_remove(del->vc4->vs_cache, key);
1365 vc4_bo_unreference(&shader->bo);
1366 free(shader);
1367 }
1368
1369 return 0;
1370 }
1371
1372 static void
1373 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
1374 {
1375 struct vc4_context *vc4 = vc4_context(pctx);
1376 struct pipe_shader_state *so = hwcso;
1377 struct delete_state del;
1378
1379 del.vc4 = vc4;
1380 del.shader_state = so;
1381 util_hash_table_foreach(vc4->fs_cache, fs_delete_from_cache, &del);
1382 util_hash_table_foreach(vc4->vs_cache, vs_delete_from_cache, &del);
1383
1384 free((void *)so->tokens);
1385 free(so);
1386 }
1387
1388 static uint32_t translate_wrap(uint32_t p_wrap)
1389 {
1390 switch (p_wrap) {
1391 case PIPE_TEX_WRAP_REPEAT:
1392 return 0;
1393 case PIPE_TEX_WRAP_CLAMP:
1394 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1395 return 1;
1396 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1397 return 2;
1398 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1399 return 3;
1400 default:
1401 fprintf(stderr, "Unknown wrap mode %d\n", p_wrap);
1402 assert(!"not reached");
1403 return 0;
1404 }
1405 }
1406
1407 static void
1408 write_texture_p0(struct vc4_context *vc4,
1409 struct vc4_texture_stateobj *texstate,
1410 uint32_t tex_and_sampler)
1411 {
1412 uint32_t texi = (tex_and_sampler >> 0) & 0xff;
1413 struct pipe_sampler_view *texture = texstate->textures[texi];
1414 struct vc4_resource *rsc = vc4_resource(texture->texture);
1415
1416 cl_reloc(vc4, &vc4->uniforms, rsc->bo,
1417 rsc->slices[0].offset | texture->u.tex.last_level);
1418 }
1419
1420 static void
1421 write_texture_p1(struct vc4_context *vc4,
1422 struct vc4_texture_stateobj *texstate,
1423 uint32_t tex_and_sampler)
1424 {
1425 uint32_t texi = (tex_and_sampler >> 0) & 0xff;
1426 uint32_t sampi = (tex_and_sampler >> 8) & 0xff;
1427 struct pipe_sampler_view *texture = texstate->textures[texi];
1428 struct pipe_sampler_state *sampler = texstate->samplers[sampi];
1429 static const uint32_t mipfilter_map[] = {
1430 [PIPE_TEX_MIPFILTER_NEAREST] = 2,
1431 [PIPE_TEX_MIPFILTER_LINEAR] = 4,
1432 [PIPE_TEX_MIPFILTER_NONE] = 0
1433 };
1434 static const uint32_t imgfilter_map[] = {
1435 [PIPE_TEX_FILTER_NEAREST] = 1,
1436 [PIPE_TEX_FILTER_LINEAR] = 0,
1437 };
1438
1439 cl_u32(&vc4->uniforms,
1440 (1 << 31) /* XXX: data type */|
1441 (texture->texture->height0 << 20) |
1442 (texture->texture->width0 << 8) |
1443 (imgfilter_map[sampler->mag_img_filter] << 7) |
1444 ((imgfilter_map[sampler->min_img_filter] +
1445 mipfilter_map[sampler->min_mip_filter]) << 4) |
1446 (translate_wrap(sampler->wrap_t) << 2) |
1447 (translate_wrap(sampler->wrap_s) << 0));
1448 }
1449
1450 static uint32_t
1451 get_texrect_scale(struct vc4_texture_stateobj *texstate,
1452 enum quniform_contents contents,
1453 uint32_t data)
1454 {
1455 struct pipe_sampler_view *texture = texstate->textures[data];
1456 uint32_t dim;
1457
1458 if (contents == QUNIFORM_TEXRECT_SCALE_X)
1459 dim = texture->texture->width0;
1460 else
1461 dim = texture->texture->height0;
1462
1463 return fui(1.0f / dim);
1464 }
1465
1466 void
1467 vc4_write_uniforms(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1468 struct vc4_constbuf_stateobj *cb,
1469 struct vc4_texture_stateobj *texstate,
1470 int shader_index)
1471 {
1472 struct vc4_shader_uniform_info *uinfo = &shader->uniforms[shader_index];
1473 const uint32_t *gallium_uniforms = cb->cb[0].user_buffer;
1474
1475 cl_start_shader_reloc(&vc4->uniforms, uinfo->num_texture_samples);
1476
1477 for (int i = 0; i < uinfo->count; i++) {
1478
1479 switch (uinfo->contents[i]) {
1480 case QUNIFORM_CONSTANT:
1481 cl_u32(&vc4->uniforms, uinfo->data[i]);
1482 break;
1483 case QUNIFORM_UNIFORM:
1484 cl_u32(&vc4->uniforms,
1485 gallium_uniforms[uinfo->data[i]]);
1486 break;
1487 case QUNIFORM_VIEWPORT_X_SCALE:
1488 cl_f(&vc4->uniforms, vc4->viewport.scale[0] * 16.0f);
1489 break;
1490 case QUNIFORM_VIEWPORT_Y_SCALE:
1491 cl_f(&vc4->uniforms, vc4->viewport.scale[1] * 16.0f);
1492 break;
1493
1494 case QUNIFORM_VIEWPORT_Z_OFFSET:
1495 cl_f(&vc4->uniforms, vc4->viewport.translate[2]);
1496 break;
1497 case QUNIFORM_VIEWPORT_Z_SCALE:
1498 cl_f(&vc4->uniforms, vc4->viewport.scale[2]);
1499 break;
1500
1501 case QUNIFORM_TEXTURE_CONFIG_P0:
1502 write_texture_p0(vc4, texstate, uinfo->data[i]);
1503 break;
1504
1505 case QUNIFORM_TEXTURE_CONFIG_P1:
1506 write_texture_p1(vc4, texstate, uinfo->data[i]);
1507 break;
1508
1509 case QUNIFORM_TEXRECT_SCALE_X:
1510 case QUNIFORM_TEXRECT_SCALE_Y:
1511 cl_u32(&vc4->uniforms,
1512 get_texrect_scale(texstate,
1513 uinfo->contents[i],
1514 uinfo->data[i]));
1515 break;
1516
1517 case QUNIFORM_BLEND_CONST_COLOR:
1518 cl_f(&vc4->uniforms,
1519 vc4->blend_color.color[uinfo->data[i]]);
1520 break;
1521 }
1522 #if 0
1523 uint32_t written_val = *(uint32_t *)(vc4->uniforms.next - 4);
1524 fprintf(stderr, "%p/%d: %d: 0x%08x (%f)\n",
1525 shader, shader_index, i, written_val, uif(written_val));
1526 #endif
1527 }
1528 }
1529
1530 static void
1531 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
1532 {
1533 struct vc4_context *vc4 = vc4_context(pctx);
1534 vc4->prog.bind_fs = hwcso;
1535 vc4->prog.dirty |= VC4_SHADER_DIRTY_FP;
1536 vc4->dirty |= VC4_DIRTY_PROG;
1537 }
1538
1539 static void
1540 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
1541 {
1542 struct vc4_context *vc4 = vc4_context(pctx);
1543 vc4->prog.bind_vs = hwcso;
1544 vc4->prog.dirty |= VC4_SHADER_DIRTY_VP;
1545 vc4->dirty |= VC4_DIRTY_PROG;
1546 }
1547
1548 void
1549 vc4_program_init(struct pipe_context *pctx)
1550 {
1551 struct vc4_context *vc4 = vc4_context(pctx);
1552
1553 pctx->create_vs_state = vc4_shader_state_create;
1554 pctx->delete_vs_state = vc4_shader_state_delete;
1555
1556 pctx->create_fs_state = vc4_shader_state_create;
1557 pctx->delete_fs_state = vc4_shader_state_delete;
1558
1559 pctx->bind_fs_state = vc4_fp_state_bind;
1560 pctx->bind_vs_state = vc4_vp_state_bind;
1561
1562 vc4->fs_cache = util_hash_table_create(fs_cache_hash, fs_cache_compare);
1563 vc4->vs_cache = util_hash_table_create(vs_cache_hash, vs_cache_compare);
1564 }