2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "pipe/p_state.h"
28 #include "util/u_format.h"
29 #include "util/u_hash_table.h"
30 #include "util/u_hash.h"
31 #include "util/u_memory.h"
32 #include "tgsi/tgsi_parse.h"
33 #include "tgsi/tgsi_dump.h"
35 #include "vc4_context.h"
38 #ifdef USE_VC4_SIMULATOR
39 #include "simpenrose/simpenrose.h"
43 struct tgsi_parse_context parser
;
48 struct qreg
*uniforms
;
50 struct qreg line_x
, point_x
, point_y
;
54 struct pipe_shader_state
*shader_state
;
55 struct vc4_fs_key
*fs_key
;
56 struct vc4_vs_key
*vs_key
;
58 uint32_t *uniform_data
;
59 enum quniform_contents
*uniform_contents
;
60 uint32_t num_uniforms
;
62 uint32_t num_texture_samples
;
66 struct pipe_shader_state
*shader_state
;
71 enum pipe_format color_format
;
76 struct pipe_rt_blend_state blend
;
81 enum pipe_format attr_formats
[8];
85 add_uniform(struct tgsi_to_qir
*trans
,
86 enum quniform_contents contents
,
89 uint32_t uniform
= trans
->num_uniforms
++;
90 struct qreg u
= { QFILE_UNIF
, uniform
};
92 trans
->uniform_contents
[uniform
] = contents
;
93 trans
->uniform_data
[uniform
] = data
;
99 get_temp_for_uniform(struct tgsi_to_qir
*trans
, enum quniform_contents contents
,
102 struct qcompile
*c
= trans
->c
;
104 for (int i
= 0; i
< trans
->num_uniforms
; i
++) {
105 if (trans
->uniform_contents
[i
] == contents
&&
106 trans
->uniform_data
[i
] == data
)
107 return trans
->uniforms
[i
];
110 struct qreg u
= add_uniform(trans
, contents
, data
);
111 struct qreg t
= qir_MOV(c
, u
);
113 trans
->uniforms
[u
.index
] = t
;
118 qir_uniform_ui(struct tgsi_to_qir
*trans
, uint32_t ui
)
120 return get_temp_for_uniform(trans
, QUNIFORM_CONSTANT
, ui
);
124 qir_uniform_f(struct tgsi_to_qir
*trans
, float f
)
126 return qir_uniform_ui(trans
, fui(f
));
130 get_src(struct tgsi_to_qir
*trans
, struct tgsi_src_register
*src
, int i
)
132 struct qcompile
*c
= trans
->c
;
133 struct qreg r
= c
->undef
;
153 assert(!src
->Indirect
);
158 case TGSI_FILE_TEMPORARY
:
159 r
= trans
->temps
[src
->Index
* 4 + s
];
161 case TGSI_FILE_IMMEDIATE
:
162 r
= trans
->consts
[src
->Index
* 4 + s
];
164 case TGSI_FILE_CONSTANT
:
165 r
= get_temp_for_uniform(trans
, QUNIFORM_UNIFORM
,
168 case TGSI_FILE_INPUT
:
169 r
= trans
->inputs
[src
->Index
* 4 + s
];
171 case TGSI_FILE_SAMPLER
:
172 case TGSI_FILE_SAMPLER_VIEW
:
176 fprintf(stderr
, "unknown src file %d\n", src
->File
);
181 r
= qir_FMAXABS(c
, r
, r
);
184 r
= qir_FSUB(c
, qir_uniform_f(trans
, 0), r
);
191 update_dst(struct tgsi_to_qir
*trans
, struct tgsi_full_instruction
*tgsi_inst
,
192 int i
, struct qreg val
)
194 struct tgsi_dst_register
*tgsi_dst
= &tgsi_inst
->Dst
[0].Register
;
196 assert(!tgsi_dst
->Indirect
);
198 switch (tgsi_dst
->File
) {
199 case TGSI_FILE_TEMPORARY
:
200 trans
->temps
[tgsi_dst
->Index
* 4 + i
] = val
;
202 case TGSI_FILE_OUTPUT
:
203 trans
->outputs
[tgsi_dst
->Index
* 4 + i
] = val
;
204 trans
->num_outputs
= MAX2(trans
->num_outputs
,
205 tgsi_dst
->Index
* 4 + i
+ 1);
208 fprintf(stderr
, "unknown dst file %d\n", tgsi_dst
->File
);
214 get_swizzled_channel(struct tgsi_to_qir
*trans
,
215 struct qreg
*srcs
, int swiz
)
219 case UTIL_FORMAT_SWIZZLE_NONE
:
220 fprintf(stderr
, "warning: unknown swizzle\n");
222 case UTIL_FORMAT_SWIZZLE_0
:
223 return qir_uniform_f(trans
, 0.0);
224 case UTIL_FORMAT_SWIZZLE_1
:
225 return qir_uniform_f(trans
, 1.0);
226 case UTIL_FORMAT_SWIZZLE_X
:
227 case UTIL_FORMAT_SWIZZLE_Y
:
228 case UTIL_FORMAT_SWIZZLE_Z
:
229 case UTIL_FORMAT_SWIZZLE_W
:
235 tgsi_to_qir_alu(struct tgsi_to_qir
*trans
,
236 struct tgsi_full_instruction
*tgsi_inst
,
237 enum qop op
, struct qreg
*src
, int i
)
239 struct qcompile
*c
= trans
->c
;
240 struct qreg dst
= qir_get_temp(c
);
241 qir_emit(c
, qir_inst4(op
, dst
,
250 tgsi_to_qir_mad(struct tgsi_to_qir
*trans
,
251 struct tgsi_full_instruction
*tgsi_inst
,
252 enum qop op
, struct qreg
*src
, int i
)
254 struct qcompile
*c
= trans
->c
;
263 tgsi_to_qir_lit(struct tgsi_to_qir
*trans
,
264 struct tgsi_full_instruction
*tgsi_inst
,
265 enum qop op
, struct qreg
*src
, int i
)
267 struct qcompile
*c
= trans
->c
;
268 struct qreg x
= src
[0 * 4 + 0];
269 struct qreg y
= src
[0 * 4 + 1];
270 struct qreg w
= src
[0 * 4 + 3];
275 return qir_uniform_f(trans
, 1.0);
277 return qir_FMAX(c
, src
[0 * 4 + 0], qir_uniform_f(trans
, 0.0));
279 struct qreg zero
= qir_uniform_f(trans
, 0.0);
281 /* XXX: Clamp w to -128..128 */
285 qir_EXP2(c
, qir_FMUL(c
,
293 assert(!"not reached");
299 tgsi_to_qir_lrp(struct tgsi_to_qir
*trans
,
300 struct tgsi_full_instruction
*tgsi_inst
,
301 enum qop op
, struct qreg
*src
, int i
)
303 struct qcompile
*c
= trans
->c
;
304 struct qreg src0
= src
[0 * 4 + i
];
305 struct qreg src1
= src
[1 * 4 + i
];
306 struct qreg src2
= src
[2 * 4 + i
];
309 * src0 * src1 + (1 - src0) * src2.
310 * -> src0 * src1 + src2 - src0 * src2
311 * -> src2 + src0 * (src1 - src2)
313 return qir_FADD(c
, src2
, qir_FMUL(c
, src0
, qir_FSUB(c
, src1
, src2
)));
318 tgsi_to_qir_tex(struct tgsi_to_qir
*trans
,
319 struct tgsi_full_instruction
*tgsi_inst
,
320 enum qop op
, struct qreg
*src
)
322 struct qcompile
*c
= trans
->c
;
324 assert(!tgsi_inst
->Instruction
.Saturate
);
326 struct qreg s
= src
[0 * 4 + 0];
327 struct qreg t
= src
[0 * 4 + 1];
329 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXP
) {
330 struct qreg proj
= qir_RCP(c
, src
[0 * 4 + 3]);
331 s
= qir_FMUL(c
, s
, proj
);
332 t
= qir_FMUL(c
, t
, proj
);
335 /* There is no native support for GL texture rectangle coordinates, so
336 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
339 if (tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_RECT
) {
340 uint32_t sampler
= 0; /* XXX */
342 get_temp_for_uniform(trans
,
343 QUNIFORM_TEXRECT_SCALE_X
,
346 get_temp_for_uniform(trans
,
347 QUNIFORM_TEXRECT_SCALE_Y
,
351 uint32_t tex_and_sampler
= 0; /* XXX */
352 qir_TEX_T(c
, t
, add_uniform(trans
, QUNIFORM_TEXTURE_CONFIG_P0
,
355 struct qreg sampler_p1
= add_uniform(trans
, QUNIFORM_TEXTURE_CONFIG_P1
,
357 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB
) {
358 qir_TEX_B(c
, src
[0 * 4 + 3], sampler_p1
);
359 qir_TEX_S(c
, s
, add_uniform(trans
, QUNIFORM_CONSTANT
, 0));
361 qir_TEX_S(c
, s
, sampler_p1
);
364 trans
->num_texture_samples
++;
365 qir_emit(c
, qir_inst(QOP_TEX_RESULT
, c
->undef
, c
->undef
, c
->undef
));
367 for (int i
= 0; i
< 4; i
++) {
368 if (!(tgsi_inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
371 struct qreg dst
= qir_R4_UNPACK(c
, i
);
372 update_dst(trans
, tgsi_inst
, i
, dst
);
377 tgsi_to_qir_pow(struct tgsi_to_qir
*trans
,
378 struct tgsi_full_instruction
*tgsi_inst
,
379 enum qop op
, struct qreg
*src
, int i
)
381 struct qcompile
*c
= trans
->c
;
383 /* Note that this instruction replicates its result from the x channel
385 return qir_EXP2(c
, qir_FMUL(c
,
387 qir_LOG2(c
, src
[0 * 4 + 0])));
391 tgsi_to_qir_trunc(struct tgsi_to_qir
*trans
,
392 struct tgsi_full_instruction
*tgsi_inst
,
393 enum qop op
, struct qreg
*src
, int i
)
395 struct qcompile
*c
= trans
->c
;
396 return qir_ITOF(c
, qir_FTOI(c
, src
[0 * 4 + i
]));
400 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
404 tgsi_to_qir_frc(struct tgsi_to_qir
*trans
,
405 struct tgsi_full_instruction
*tgsi_inst
,
406 enum qop op
, struct qreg
*src
, int i
)
408 struct qcompile
*c
= trans
->c
;
409 struct qreg trunc
= qir_ITOF(c
, qir_FTOI(c
, src
[0 * 4 + i
]));
410 struct qreg diff
= qir_FSUB(c
, src
[0 * 4 + i
], trunc
);
413 qir_FADD(c
, diff
, qir_uniform_f(trans
, 1.0)),
418 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
422 tgsi_to_qir_flr(struct tgsi_to_qir
*trans
,
423 struct tgsi_full_instruction
*tgsi_inst
,
424 enum qop op
, struct qreg
*src
, int i
)
426 struct qcompile
*c
= trans
->c
;
427 struct qreg trunc
= qir_ITOF(c
, qir_FTOI(c
, src
[0 * 4 + i
]));
430 qir_FSUB(c
, trunc
, qir_uniform_f(trans
, 1.0)),
435 tgsi_to_qir_dp(struct tgsi_to_qir
*trans
,
436 struct tgsi_full_instruction
*tgsi_inst
,
437 int num
, struct qreg
*src
, int i
)
439 struct qcompile
*c
= trans
->c
;
441 struct qreg sum
= qir_FMUL(c
, src
[0 * 4 + 0], src
[1 * 4 + 0]);
442 for (int j
= 1; j
< num
; j
++) {
443 sum
= qir_FADD(c
, sum
, qir_FMUL(c
,
451 tgsi_to_qir_dp2(struct tgsi_to_qir
*trans
,
452 struct tgsi_full_instruction
*tgsi_inst
,
453 enum qop op
, struct qreg
*src
, int i
)
455 return tgsi_to_qir_dp(trans
, tgsi_inst
, 2, src
, i
);
459 tgsi_to_qir_dp3(struct tgsi_to_qir
*trans
,
460 struct tgsi_full_instruction
*tgsi_inst
,
461 enum qop op
, struct qreg
*src
, int i
)
463 return tgsi_to_qir_dp(trans
, tgsi_inst
, 3, src
, i
);
467 tgsi_to_qir_dp4(struct tgsi_to_qir
*trans
,
468 struct tgsi_full_instruction
*tgsi_inst
,
469 enum qop op
, struct qreg
*src
, int i
)
471 return tgsi_to_qir_dp(trans
, tgsi_inst
, 4, src
, i
);
475 tgsi_to_qir_abs(struct tgsi_to_qir
*trans
,
476 struct tgsi_full_instruction
*tgsi_inst
,
477 enum qop op
, struct qreg
*src
, int i
)
479 struct qcompile
*c
= trans
->c
;
480 struct qreg arg
= src
[0 * 4 + i
];
481 return qir_FMAXABS(c
, arg
, arg
);
484 /* Note that this instruction replicates its result from the x channel */
486 tgsi_to_qir_sin(struct tgsi_to_qir
*trans
,
487 struct tgsi_full_instruction
*tgsi_inst
,
488 enum qop op
, struct qreg
*src
, int i
)
490 struct qcompile
*c
= trans
->c
;
493 -pow(2.0 * M_PI
, 3) / (3 * 2 * 1),
494 pow(2.0 * M_PI
, 5) / (5 * 4 * 3 * 2 * 1),
495 -pow(2.0 * M_PI
, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
498 struct qreg scaled_x
=
501 qir_uniform_f(trans
, 1.0f
/ (M_PI
* 2.0f
)));
504 struct qreg x
= tgsi_to_qir_frc(trans
, NULL
, 0, &scaled_x
, 0);
505 struct qreg x2
= qir_FMUL(c
, x
, x
);
506 struct qreg sum
= qir_FMUL(c
, x
, qir_uniform_f(trans
, coeff
[0]));
507 for (int i
= 1; i
< ARRAY_SIZE(coeff
); i
++) {
508 x
= qir_FMUL(c
, x
, x2
);
513 qir_uniform_f(trans
, coeff
[i
])));
518 /* Note that this instruction replicates its result from the x channel */
520 tgsi_to_qir_cos(struct tgsi_to_qir
*trans
,
521 struct tgsi_full_instruction
*tgsi_inst
,
522 enum qop op
, struct qreg
*src
, int i
)
524 struct qcompile
*c
= trans
->c
;
527 -pow(2.0 * M_PI
, 2) / (2 * 1),
528 pow(2.0 * M_PI
, 4) / (4 * 3 * 2 * 1),
529 -pow(2.0 * M_PI
, 6) / (6 * 5 * 4 * 3 * 2 * 1),
532 struct qreg scaled_x
=
533 qir_FMUL(c
, src
[0 * 4 + 0],
534 qir_uniform_f(trans
, 1.0f
/ (M_PI
* 2.0f
)));
535 struct qreg x_frac
= tgsi_to_qir_frc(trans
, NULL
, 0, &scaled_x
, 0);
537 struct qreg sum
= qir_uniform_f(trans
, coeff
[0]);
538 struct qreg x2
= qir_FMUL(c
, x_frac
, x_frac
);
539 struct qreg x
= x2
; /* Current x^2, x^4, or x^6 */
540 for (int i
= 1; i
< ARRAY_SIZE(coeff
); i
++) {
542 x
= qir_FMUL(c
, x
, x2
);
544 struct qreg mul
= qir_FMUL(c
,
546 qir_uniform_f(trans
, coeff
[i
]));
550 sum
= qir_FADD(c
, sum
, mul
);
556 emit_vertex_input(struct tgsi_to_qir
*trans
, int attr
)
558 enum pipe_format format
= trans
->vs_key
->attr_formats
[attr
];
559 struct qcompile
*c
= trans
->c
;
560 struct qreg vpm_reads
[4];
562 /* Right now, we're setting the VPM offsets to be 16 bytes wide every
563 * time, so we always read 4 32-bit VPM entries.
565 for (int i
= 0; i
< 4; i
++) {
566 vpm_reads
[i
] = qir_get_temp(c
);
567 qir_emit(c
, qir_inst(QOP_VPM_READ
,
574 bool format_warned
= false;
575 const struct util_format_description
*desc
=
576 util_format_description(format
);
578 for (int i
= 0; i
< 4; i
++) {
579 uint8_t swiz
= desc
->swizzle
[i
];
581 if (swiz
<= UTIL_FORMAT_SWIZZLE_W
&&
583 (desc
->channel
[swiz
].type
!= UTIL_FORMAT_TYPE_FLOAT
||
584 desc
->channel
[swiz
].size
!= 32)) {
586 "vtx element %d unsupported type: %s\n",
587 attr
, util_format_name(format
));
588 format_warned
= true;
591 trans
->inputs
[attr
* 4 + i
] =
592 get_swizzled_channel(trans
, vpm_reads
, swiz
);
597 emit_fragcoord_input(struct tgsi_to_qir
*trans
, int attr
)
599 struct qcompile
*c
= trans
->c
;
601 trans
->inputs
[attr
* 4 + 0] = qir_FRAG_X(c
);
602 trans
->inputs
[attr
* 4 + 1] = qir_FRAG_Y(c
);
603 trans
->inputs
[attr
* 4 + 2] =
606 qir_uniform_f(trans
, 1.0 / 0xffffff));
607 trans
->inputs
[attr
* 4 + 3] = qir_FRAG_RCP_W(c
);
611 emit_fragment_varying(struct tgsi_to_qir
*trans
, int index
)
613 struct qcompile
*c
= trans
->c
;
620 /* XXX: multiply by W */
621 return qir_VARY_ADD_C(c
, qir_MOV(c
, vary
));
625 emit_fragment_input(struct tgsi_to_qir
*trans
, int attr
)
627 struct qcompile
*c
= trans
->c
;
629 for (int i
= 0; i
< 4; i
++) {
630 trans
->inputs
[attr
* 4 + i
] =
631 emit_fragment_varying(trans
, attr
* 4 + i
);
637 emit_tgsi_declaration(struct tgsi_to_qir
*trans
,
638 struct tgsi_full_declaration
*decl
)
640 struct qcompile
*c
= trans
->c
;
642 switch (decl
->Declaration
.File
) {
643 case TGSI_FILE_INPUT
:
644 for (int i
= decl
->Range
.First
;
645 i
<= decl
->Range
.Last
;
647 if (c
->stage
== QSTAGE_FRAG
) {
648 if (decl
->Semantic
.Name
==
649 TGSI_SEMANTIC_POSITION
) {
650 emit_fragcoord_input(trans
, i
);
652 emit_fragment_input(trans
, i
);
655 emit_vertex_input(trans
, i
);
663 emit_tgsi_instruction(struct tgsi_to_qir
*trans
,
664 struct tgsi_full_instruction
*tgsi_inst
)
666 struct qcompile
*c
= trans
->c
;
669 struct qreg (*func
)(struct tgsi_to_qir
*trans
,
670 struct tgsi_full_instruction
*tgsi_inst
,
672 struct qreg
*src
, int i
);
674 [TGSI_OPCODE_MOV
] = { QOP_MOV
, tgsi_to_qir_alu
},
675 [TGSI_OPCODE_ABS
] = { 0, tgsi_to_qir_abs
},
676 [TGSI_OPCODE_MUL
] = { QOP_FMUL
, tgsi_to_qir_alu
},
677 [TGSI_OPCODE_ADD
] = { QOP_FADD
, tgsi_to_qir_alu
},
678 [TGSI_OPCODE_SUB
] = { QOP_FSUB
, tgsi_to_qir_alu
},
679 [TGSI_OPCODE_MIN
] = { QOP_FMIN
, tgsi_to_qir_alu
},
680 [TGSI_OPCODE_MAX
] = { QOP_FMAX
, tgsi_to_qir_alu
},
681 [TGSI_OPCODE_RSQ
] = { QOP_RSQ
, tgsi_to_qir_alu
},
682 [TGSI_OPCODE_SEQ
] = { QOP_SEQ
, tgsi_to_qir_alu
},
683 [TGSI_OPCODE_SNE
] = { QOP_SNE
, tgsi_to_qir_alu
},
684 [TGSI_OPCODE_SGE
] = { QOP_SGE
, tgsi_to_qir_alu
},
685 [TGSI_OPCODE_SLT
] = { QOP_SLT
, tgsi_to_qir_alu
},
686 [TGSI_OPCODE_CMP
] = { QOP_CMP
, tgsi_to_qir_alu
},
687 [TGSI_OPCODE_MAD
] = { 0, tgsi_to_qir_mad
},
688 [TGSI_OPCODE_DP2
] = { 0, tgsi_to_qir_dp2
},
689 [TGSI_OPCODE_DP3
] = { 0, tgsi_to_qir_dp3
},
690 [TGSI_OPCODE_DP4
] = { 0, tgsi_to_qir_dp4
},
691 [TGSI_OPCODE_RCP
] = { QOP_RCP
, tgsi_to_qir_alu
},
692 [TGSI_OPCODE_RSQ
] = { QOP_RSQ
, tgsi_to_qir_alu
},
693 [TGSI_OPCODE_EX2
] = { QOP_EXP2
, tgsi_to_qir_alu
},
694 [TGSI_OPCODE_LG2
] = { QOP_LOG2
, tgsi_to_qir_alu
},
695 [TGSI_OPCODE_LIT
] = { 0, tgsi_to_qir_lit
},
696 [TGSI_OPCODE_LRP
] = { 0, tgsi_to_qir_lrp
},
697 [TGSI_OPCODE_POW
] = { 0, tgsi_to_qir_pow
},
698 [TGSI_OPCODE_TRUNC
] = { 0, tgsi_to_qir_trunc
},
699 [TGSI_OPCODE_FRC
] = { 0, tgsi_to_qir_frc
},
700 [TGSI_OPCODE_FLR
] = { 0, tgsi_to_qir_flr
},
701 [TGSI_OPCODE_SIN
] = { 0, tgsi_to_qir_sin
},
702 [TGSI_OPCODE_COS
] = { 0, tgsi_to_qir_cos
},
705 uint32_t tgsi_op
= tgsi_inst
->Instruction
.Opcode
;
707 if (tgsi_op
== TGSI_OPCODE_END
)
710 struct qreg src_regs
[12];
711 for (int s
= 0; s
< 3; s
++) {
712 for (int i
= 0; i
< 4; i
++) {
713 src_regs
[4 * s
+ i
] =
714 get_src(trans
, &tgsi_inst
->Src
[s
].Register
, i
);
719 case TGSI_OPCODE_TEX
:
720 case TGSI_OPCODE_TXP
:
721 case TGSI_OPCODE_TXB
:
722 tgsi_to_qir_tex(trans
, tgsi_inst
,
723 op_trans
[tgsi_op
].op
, src_regs
);
729 if (tgsi_op
> ARRAY_SIZE(op_trans
) || !(op_trans
[tgsi_op
].func
)) {
730 fprintf(stderr
, "unknown tgsi inst: ");
731 tgsi_dump_instruction(tgsi_inst
, asdf
++);
732 fprintf(stderr
, "\n");
736 for (int i
= 0; i
< 4; i
++) {
737 if (!(tgsi_inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
742 result
= op_trans
[tgsi_op
].func(trans
, tgsi_inst
,
743 op_trans
[tgsi_op
].op
,
746 if (tgsi_inst
->Instruction
.Saturate
) {
747 float low
= (tgsi_inst
->Instruction
.Saturate
==
748 TGSI_SAT_MINUS_PLUS_ONE
? -1.0 : 0.0);
752 qir_uniform_f(trans
, 1.0)),
753 qir_uniform_f(trans
, low
));
756 update_dst(trans
, tgsi_inst
, i
, result
);
761 parse_tgsi_immediate(struct tgsi_to_qir
*trans
, struct tgsi_full_immediate
*imm
)
763 for (int i
= 0; i
< 4; i
++) {
764 unsigned n
= trans
->num_consts
++;
765 trans
->consts
[n
] = qir_uniform_ui(trans
, imm
->u
[i
].Uint
);
770 vc4_blend_channel(struct tgsi_to_qir
*trans
,
777 struct qcompile
*c
= trans
->c
;
780 case PIPE_BLENDFACTOR_ONE
:
782 case PIPE_BLENDFACTOR_SRC_COLOR
:
783 return qir_FMUL(c
, val
, src
[channel
]);
784 case PIPE_BLENDFACTOR_SRC_ALPHA
:
785 return qir_FMUL(c
, val
, src
[3]);
786 case PIPE_BLENDFACTOR_DST_ALPHA
:
787 return qir_FMUL(c
, val
, dst
[3]);
788 case PIPE_BLENDFACTOR_DST_COLOR
:
789 return qir_FMUL(c
, val
, dst
[channel
]);
790 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
791 return qir_FMIN(c
, src
[3], qir_FSUB(c
,
792 qir_uniform_f(trans
, 1.0),
794 case PIPE_BLENDFACTOR_CONST_COLOR
:
795 return qir_FMUL(c
, val
,
796 get_temp_for_uniform(trans
,
797 QUNIFORM_BLEND_CONST_COLOR
,
799 case PIPE_BLENDFACTOR_CONST_ALPHA
:
800 return qir_FMUL(c
, val
,
801 get_temp_for_uniform(trans
,
802 QUNIFORM_BLEND_CONST_COLOR
,
804 case PIPE_BLENDFACTOR_ZERO
:
805 return qir_uniform_f(trans
, 0.0);
806 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
807 return qir_FMUL(c
, val
, qir_FSUB(c
, qir_uniform_f(trans
, 1.0),
809 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
810 return qir_FMUL(c
, val
, qir_FSUB(c
, qir_uniform_f(trans
, 1.0),
812 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
813 return qir_FMUL(c
, val
, qir_FSUB(c
, qir_uniform_f(trans
, 1.0),
815 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
816 return qir_FMUL(c
, val
, qir_FSUB(c
, qir_uniform_f(trans
, 1.0),
818 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
819 return qir_FMUL(c
, val
,
820 qir_FSUB(c
, qir_uniform_f(trans
, 1.0),
821 get_temp_for_uniform(trans
,
822 QUNIFORM_BLEND_CONST_COLOR
,
824 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
825 return qir_FMUL(c
, val
,
826 qir_FSUB(c
, qir_uniform_f(trans
, 1.0),
827 get_temp_for_uniform(trans
,
828 QUNIFORM_BLEND_CONST_COLOR
,
832 case PIPE_BLENDFACTOR_SRC1_COLOR
:
833 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
834 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
835 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
837 fprintf(stderr
, "Unknown blend factor %d\n", factor
);
843 vc4_blend_func(struct tgsi_to_qir
*trans
,
844 struct qreg src
, struct qreg dst
,
847 struct qcompile
*c
= trans
->c
;
851 return qir_FADD(c
, src
, dst
);
852 case PIPE_BLEND_SUBTRACT
:
853 return qir_FSUB(c
, src
, dst
);
854 case PIPE_BLEND_REVERSE_SUBTRACT
:
855 return qir_FSUB(c
, dst
, src
);
857 return qir_FMIN(c
, src
, dst
);
859 return qir_FMAX(c
, src
, dst
);
863 fprintf(stderr
, "Unknown blend func %d\n", func
);
870 * Implements fixed function blending in shader code.
872 * VC4 doesn't have any hardware support for blending. Instead, you read the
873 * current contents of the destination from the tile buffer after having
874 * waited for the scoreboard (which is handled by vc4_qpu_emit.c), then do
875 * math using your output color and that destination value, and update the
876 * output color appropriately.
879 vc4_blend(struct tgsi_to_qir
*trans
, struct qreg
*result
,
880 struct qreg
*dst_color
, struct qreg
*src_color
)
882 struct pipe_rt_blend_state
*blend
= &trans
->fs_key
->blend
;
884 if (!blend
->blend_enable
) {
885 for (int i
= 0; i
< 4; i
++)
886 result
[i
] = src_color
[i
];
890 struct qreg src_blend
[4], dst_blend
[4];
891 for (int i
= 0; i
< 3; i
++) {
892 src_blend
[i
] = vc4_blend_channel(trans
,
893 dst_color
, src_color
,
895 blend
->rgb_src_factor
, i
);
896 dst_blend
[i
] = vc4_blend_channel(trans
,
897 dst_color
, src_color
,
899 blend
->rgb_dst_factor
, i
);
901 src_blend
[3] = vc4_blend_channel(trans
,
902 dst_color
, src_color
,
904 blend
->alpha_src_factor
, 3);
905 dst_blend
[3] = vc4_blend_channel(trans
,
906 dst_color
, src_color
,
908 blend
->alpha_dst_factor
, 3);
910 for (int i
= 0; i
< 3; i
++) {
911 result
[i
] = vc4_blend_func(trans
,
912 src_blend
[i
], dst_blend
[i
],
915 result
[3] = vc4_blend_func(trans
,
916 src_blend
[3], dst_blend
[3],
921 emit_frag_end(struct tgsi_to_qir
*trans
)
923 struct qcompile
*c
= trans
->c
;
925 struct qreg t
= qir_get_temp(c
);
927 const struct util_format_description
*format_desc
=
928 util_format_description(trans
->fs_key
->color_format
);
930 struct qreg src_color
[4] = {
931 trans
->outputs
[0], trans
->outputs
[1],
932 trans
->outputs
[2], trans
->outputs
[3],
935 struct qreg dst_color
[4] = { c
->undef
, c
->undef
, c
->undef
, c
->undef
};
936 if (trans
->fs_key
->blend
.blend_enable
||
937 trans
->fs_key
->blend
.colormask
!= 0xf) {
938 qir_emit(c
, qir_inst(QOP_TLB_COLOR_READ
, c
->undef
,
939 c
->undef
, c
->undef
));
940 for (int i
= 0; i
< 4; i
++) {
941 dst_color
[i
] = qir_R4_UNPACK(c
, i
);
947 struct qreg blend_color
[4];
948 vc4_blend(trans
, blend_color
, dst_color
, src_color
);
950 /* If the bit isn't set in the color mask, then just return the
951 * original dst color, instead.
953 for (int i
= 0; i
< 4; i
++) {
954 if (!(trans
->fs_key
->blend
.colormask
& (1 << i
))) {
955 blend_color
[i
] = dst_color
[i
];
959 /* Debug: Sometimes you're getting a black output and just want to see
960 * if the FS is getting executed at all. Spam magenta into the color
964 blend_color
[0] = qir_uniform_f(trans
, 1.0);
965 blend_color
[1] = qir_uniform_f(trans
, 0.0);
966 blend_color
[2] = qir_uniform_f(trans
, 1.0);
967 blend_color
[3] = qir_uniform_f(trans
, 0.5);
970 struct qreg swizzled_outputs
[4];
971 for (int i
= 0; i
< 4; i
++) {
972 swizzled_outputs
[i
] =
973 get_swizzled_channel(trans
, blend_color
,
974 format_desc
->swizzle
[i
]);
977 if (trans
->fs_key
->depth_enabled
) {
978 qir_emit(c
, qir_inst(QOP_TLB_PASSTHROUGH_Z_WRITE
, c
->undef
,
979 c
->undef
, c
->undef
));
982 qir_emit(c
, qir_inst4(QOP_PACK_COLORS
, t
,
986 swizzled_outputs
[3]));
987 qir_emit(c
, qir_inst(QOP_TLB_COLOR_WRITE
, c
->undef
,
992 emit_scaled_viewport_write(struct tgsi_to_qir
*trans
, struct qreg rcp_w
)
994 struct qcompile
*c
= trans
->c
;
997 for (int i
= 0; i
< 2; i
++) {
999 add_uniform(trans
, QUNIFORM_VIEWPORT_X_SCALE
+ i
, 0);
1001 xyi
[i
] = qir_FTOI(c
, qir_FMUL(c
,
1008 qir_VPM_WRITE(c
, qir_PACK_SCALED(c
, xyi
[0], xyi
[1]));
1012 emit_zs_write(struct tgsi_to_qir
*trans
, struct qreg rcp_w
)
1014 struct qcompile
*c
= trans
->c
;
1016 struct qreg zscale
= add_uniform(trans
, QUNIFORM_VIEWPORT_Z_SCALE
, 0);
1017 struct qreg zoffset
= add_uniform(trans
, QUNIFORM_VIEWPORT_Z_OFFSET
, 0);
1019 qir_VPM_WRITE(c
, qir_FMUL(c
, qir_FADD(c
, qir_FMUL(c
,
1027 emit_rcp_wc_write(struct tgsi_to_qir
*trans
, struct qreg rcp_w
)
1029 struct qcompile
*c
= trans
->c
;
1031 qir_VPM_WRITE(c
, rcp_w
);
1035 emit_vert_end(struct tgsi_to_qir
*trans
)
1037 struct qcompile
*c
= trans
->c
;
1039 struct qreg rcp_w
= qir_RCP(c
, trans
->outputs
[3]);
1041 emit_scaled_viewport_write(trans
, rcp_w
);
1042 emit_zs_write(trans
, rcp_w
);
1043 emit_rcp_wc_write(trans
, rcp_w
);
1045 for (int i
= 4; i
< trans
->num_outputs
; i
++) {
1046 qir_VPM_WRITE(c
, trans
->outputs
[i
]);
1051 emit_coord_end(struct tgsi_to_qir
*trans
)
1053 struct qcompile
*c
= trans
->c
;
1055 struct qreg rcp_w
= qir_RCP(c
, trans
->outputs
[3]);
1057 for (int i
= 0; i
< 4; i
++)
1058 qir_VPM_WRITE(c
, trans
->outputs
[i
]);
1060 emit_scaled_viewport_write(trans
, rcp_w
);
1061 emit_zs_write(trans
, rcp_w
);
1062 emit_rcp_wc_write(trans
, rcp_w
);
1065 static struct tgsi_to_qir
*
1066 vc4_shader_tgsi_to_qir(struct vc4_compiled_shader
*shader
, enum qstage stage
,
1067 struct vc4_key
*key
)
1069 struct tgsi_to_qir
*trans
= CALLOC_STRUCT(tgsi_to_qir
);
1073 c
= qir_compile_init();
1076 memset(trans
, 0, sizeof(*trans
));
1078 trans
->temps
= calloc(sizeof(struct qreg
), 1024);
1079 trans
->inputs
= calloc(sizeof(struct qreg
), 8 * 4);
1080 trans
->outputs
= calloc(sizeof(struct qreg
), 1024);
1081 trans
->uniforms
= calloc(sizeof(struct qreg
), 1024);
1082 trans
->consts
= calloc(sizeof(struct qreg
), 1024);
1084 trans
->uniform_data
= calloc(sizeof(uint32_t), 1024);
1085 trans
->uniform_contents
= calloc(sizeof(enum quniform_contents
), 1024);
1087 trans
->shader_state
= key
->shader_state
;
1089 ret
= tgsi_parse_init(&trans
->parser
, trans
->shader_state
->tokens
);
1090 assert(ret
== TGSI_PARSE_OK
);
1092 if (vc4_debug
& VC4_DEBUG_TGSI
) {
1093 fprintf(stderr
, "TGSI:\n");
1094 tgsi_dump(trans
->shader_state
->tokens
, 0);
1099 trans
->fs_key
= (struct vc4_fs_key
*)key
;
1100 if (trans
->fs_key
->is_points
) {
1101 trans
->point_x
= emit_fragment_varying(trans
, 0);
1102 trans
->point_y
= emit_fragment_varying(trans
, 0);
1103 } else if (trans
->fs_key
->is_lines
) {
1104 trans
->line_x
= emit_fragment_varying(trans
, 0);
1108 trans
->vs_key
= (struct vc4_vs_key
*)key
;
1111 trans
->vs_key
= (struct vc4_vs_key
*)key
;
1115 while (!tgsi_parse_end_of_tokens(&trans
->parser
)) {
1116 tgsi_parse_token(&trans
->parser
);
1118 switch (trans
->parser
.FullToken
.Token
.Type
) {
1119 case TGSI_TOKEN_TYPE_DECLARATION
:
1120 emit_tgsi_declaration(trans
,
1121 &trans
->parser
.FullToken
.FullDeclaration
);
1124 case TGSI_TOKEN_TYPE_INSTRUCTION
:
1125 emit_tgsi_instruction(trans
,
1126 &trans
->parser
.FullToken
.FullInstruction
);
1129 case TGSI_TOKEN_TYPE_IMMEDIATE
:
1130 parse_tgsi_immediate(trans
,
1131 &trans
->parser
.FullToken
.FullImmediate
);
1138 emit_frag_end(trans
);
1141 emit_vert_end(trans
);
1144 emit_coord_end(trans
);
1148 tgsi_parse_free(&trans
->parser
);
1153 if (vc4_debug
& VC4_DEBUG_QIR
) {
1154 fprintf(stderr
, "QIR:\n");
1157 vc4_generate_code(c
);
1159 if (vc4_debug
& VC4_DEBUG_SHADERDB
) {
1160 fprintf(stderr
, "SHADER-DB: %s: %d instructions\n",
1161 qir_get_stage_name(c
->stage
), c
->qpu_inst_count
);
1162 fprintf(stderr
, "SHADER-DB: %s: %d uniforms\n",
1163 qir_get_stage_name(c
->stage
), trans
->num_uniforms
);
1170 vc4_shader_state_create(struct pipe_context
*pctx
,
1171 const struct pipe_shader_state
*cso
)
1173 struct pipe_shader_state
*so
= CALLOC_STRUCT(pipe_shader_state
);
1177 so
->tokens
= tgsi_dup_tokens(cso
->tokens
);
1183 copy_uniform_state_to_shader(struct vc4_compiled_shader
*shader
,
1185 struct tgsi_to_qir
*trans
)
1187 int count
= trans
->num_uniforms
;
1188 struct vc4_shader_uniform_info
*uinfo
= &shader
->uniforms
[shader_index
];
1190 uinfo
->count
= count
;
1191 uinfo
->data
= malloc(count
* sizeof(*uinfo
->data
));
1192 memcpy(uinfo
->data
, trans
->uniform_data
,
1193 count
* sizeof(*uinfo
->data
));
1194 uinfo
->contents
= malloc(count
* sizeof(*uinfo
->contents
));
1195 memcpy(uinfo
->contents
, trans
->uniform_contents
,
1196 count
* sizeof(*uinfo
->contents
));
1197 uinfo
->num_texture_samples
= trans
->num_texture_samples
;
1201 vc4_fs_compile(struct vc4_context
*vc4
, struct vc4_compiled_shader
*shader
,
1202 struct vc4_fs_key
*key
)
1204 struct tgsi_to_qir
*trans
= vc4_shader_tgsi_to_qir(shader
, QSTAGE_FRAG
,
1206 shader
->num_inputs
= trans
->c
->num_inputs
;
1207 copy_uniform_state_to_shader(shader
, 0, trans
);
1208 shader
->bo
= vc4_bo_alloc_mem(vc4
->screen
, trans
->c
->qpu_insts
,
1209 trans
->c
->qpu_inst_count
* sizeof(uint64_t),
1212 qir_compile_destroy(trans
->c
);
1217 vc4_vs_compile(struct vc4_context
*vc4
, struct vc4_compiled_shader
*shader
,
1218 struct vc4_vs_key
*key
)
1220 struct tgsi_to_qir
*vs_trans
= vc4_shader_tgsi_to_qir(shader
,
1223 copy_uniform_state_to_shader(shader
, 0, vs_trans
);
1225 struct tgsi_to_qir
*cs_trans
= vc4_shader_tgsi_to_qir(shader
,
1228 copy_uniform_state_to_shader(shader
, 1, cs_trans
);
1230 uint32_t vs_size
= vs_trans
->c
->qpu_inst_count
* sizeof(uint64_t);
1231 uint32_t cs_size
= cs_trans
->c
->qpu_inst_count
* sizeof(uint64_t);
1232 shader
->coord_shader_offset
= vs_size
; /* XXX: alignment? */
1233 shader
->bo
= vc4_bo_alloc(vc4
->screen
,
1234 shader
->coord_shader_offset
+ cs_size
,
1237 void *map
= vc4_bo_map(shader
->bo
);
1238 memcpy(map
, vs_trans
->c
->qpu_insts
, vs_size
);
1239 memcpy(map
+ shader
->coord_shader_offset
,
1240 cs_trans
->c
->qpu_insts
, cs_size
);
1242 qir_compile_destroy(vs_trans
->c
);
1243 qir_compile_destroy(cs_trans
->c
);
1247 vc4_update_compiled_fs(struct vc4_context
*vc4
, uint8_t prim_mode
)
1249 struct vc4_fs_key local_key
;
1250 struct vc4_fs_key
*key
= &local_key
;
1252 memset(key
, 0, sizeof(*key
));
1253 key
->base
.shader_state
= vc4
->prog
.bind_fs
;
1254 key
->is_points
= (prim_mode
== PIPE_PRIM_POINTS
);
1255 key
->is_lines
= (prim_mode
>= PIPE_PRIM_LINES
&&
1256 prim_mode
<= PIPE_PRIM_LINE_STRIP
);
1257 key
->blend
= vc4
->blend
->rt
[0];
1259 if (vc4
->framebuffer
.cbufs
[0])
1260 key
->color_format
= vc4
->framebuffer
.cbufs
[0]->format
;
1262 key
->depth_enabled
= vc4
->zsa
->base
.depth
.enabled
;
1264 vc4
->prog
.fs
= util_hash_table_get(vc4
->fs_cache
, key
);
1268 key
= malloc(sizeof(*key
));
1269 memcpy(key
, &local_key
, sizeof(*key
));
1271 struct vc4_compiled_shader
*shader
= CALLOC_STRUCT(vc4_compiled_shader
);
1272 vc4_fs_compile(vc4
, shader
, key
);
1273 util_hash_table_set(vc4
->fs_cache
, key
, shader
);
1275 vc4
->prog
.fs
= shader
;
1279 vc4_update_compiled_vs(struct vc4_context
*vc4
)
1281 struct vc4_vs_key local_key
;
1282 struct vc4_vs_key
*key
= &local_key
;
1284 memset(key
, 0, sizeof(*key
));
1285 key
->base
.shader_state
= vc4
->prog
.bind_vs
;
1287 for (int i
= 0; i
< ARRAY_SIZE(key
->attr_formats
); i
++)
1288 key
->attr_formats
[i
] = vc4
->vtx
->pipe
[i
].src_format
;
1290 vc4
->prog
.vs
= util_hash_table_get(vc4
->vs_cache
, key
);
1294 key
= malloc(sizeof(*key
));
1295 memcpy(key
, &local_key
, sizeof(*key
));
1297 struct vc4_compiled_shader
*shader
= CALLOC_STRUCT(vc4_compiled_shader
);
1298 vc4_vs_compile(vc4
, shader
, key
);
1299 util_hash_table_set(vc4
->vs_cache
, key
, shader
);
1301 vc4
->prog
.vs
= shader
;
1305 vc4_update_compiled_shaders(struct vc4_context
*vc4
, uint8_t prim_mode
)
1307 vc4_update_compiled_fs(vc4
, prim_mode
);
1308 vc4_update_compiled_vs(vc4
);
1312 fs_cache_hash(void *key
)
1314 return util_hash_crc32(key
, sizeof(struct vc4_fs_key
));
1318 vs_cache_hash(void *key
)
1320 return util_hash_crc32(key
, sizeof(struct vc4_vs_key
));
1324 fs_cache_compare(void *key1
, void *key2
)
1326 return memcmp(key1
, key2
, sizeof(struct vc4_fs_key
));
1330 vs_cache_compare(void *key1
, void *key2
)
1332 return memcmp(key1
, key2
, sizeof(struct vc4_vs_key
));
1335 struct delete_state
{
1336 struct vc4_context
*vc4
;
1337 struct pipe_shader_state
*shader_state
;
1340 static enum pipe_error
1341 fs_delete_from_cache(void *in_key
, void *in_value
, void *data
)
1343 struct delete_state
*del
= data
;
1344 struct vc4_fs_key
*key
= in_key
;
1345 struct vc4_compiled_shader
*shader
= in_value
;
1347 if (key
->base
.shader_state
== data
) {
1348 util_hash_table_remove(del
->vc4
->fs_cache
, key
);
1349 vc4_bo_unreference(&shader
->bo
);
1356 static enum pipe_error
1357 vs_delete_from_cache(void *in_key
, void *in_value
, void *data
)
1359 struct delete_state
*del
= data
;
1360 struct vc4_vs_key
*key
= in_key
;
1361 struct vc4_compiled_shader
*shader
= in_value
;
1363 if (key
->base
.shader_state
== data
) {
1364 util_hash_table_remove(del
->vc4
->vs_cache
, key
);
1365 vc4_bo_unreference(&shader
->bo
);
1373 vc4_shader_state_delete(struct pipe_context
*pctx
, void *hwcso
)
1375 struct vc4_context
*vc4
= vc4_context(pctx
);
1376 struct pipe_shader_state
*so
= hwcso
;
1377 struct delete_state del
;
1380 del
.shader_state
= so
;
1381 util_hash_table_foreach(vc4
->fs_cache
, fs_delete_from_cache
, &del
);
1382 util_hash_table_foreach(vc4
->vs_cache
, vs_delete_from_cache
, &del
);
1384 free((void *)so
->tokens
);
1388 static uint32_t translate_wrap(uint32_t p_wrap
)
1391 case PIPE_TEX_WRAP_REPEAT
:
1393 case PIPE_TEX_WRAP_CLAMP
:
1394 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1396 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1398 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1401 fprintf(stderr
, "Unknown wrap mode %d\n", p_wrap
);
1402 assert(!"not reached");
1408 write_texture_p0(struct vc4_context
*vc4
,
1409 struct vc4_texture_stateobj
*texstate
,
1410 uint32_t tex_and_sampler
)
1412 uint32_t texi
= (tex_and_sampler
>> 0) & 0xff;
1413 struct pipe_sampler_view
*texture
= texstate
->textures
[texi
];
1414 struct vc4_resource
*rsc
= vc4_resource(texture
->texture
);
1416 cl_reloc(vc4
, &vc4
->uniforms
, rsc
->bo
,
1417 rsc
->slices
[0].offset
| texture
->u
.tex
.last_level
);
1421 write_texture_p1(struct vc4_context
*vc4
,
1422 struct vc4_texture_stateobj
*texstate
,
1423 uint32_t tex_and_sampler
)
1425 uint32_t texi
= (tex_and_sampler
>> 0) & 0xff;
1426 uint32_t sampi
= (tex_and_sampler
>> 8) & 0xff;
1427 struct pipe_sampler_view
*texture
= texstate
->textures
[texi
];
1428 struct pipe_sampler_state
*sampler
= texstate
->samplers
[sampi
];
1429 static const uint32_t mipfilter_map
[] = {
1430 [PIPE_TEX_MIPFILTER_NEAREST
] = 2,
1431 [PIPE_TEX_MIPFILTER_LINEAR
] = 4,
1432 [PIPE_TEX_MIPFILTER_NONE
] = 0
1434 static const uint32_t imgfilter_map
[] = {
1435 [PIPE_TEX_FILTER_NEAREST
] = 1,
1436 [PIPE_TEX_FILTER_LINEAR
] = 0,
1439 cl_u32(&vc4
->uniforms
,
1440 (1 << 31) /* XXX: data type */|
1441 (texture
->texture
->height0
<< 20) |
1442 (texture
->texture
->width0
<< 8) |
1443 (imgfilter_map
[sampler
->mag_img_filter
] << 7) |
1444 ((imgfilter_map
[sampler
->min_img_filter
] +
1445 mipfilter_map
[sampler
->min_mip_filter
]) << 4) |
1446 (translate_wrap(sampler
->wrap_t
) << 2) |
1447 (translate_wrap(sampler
->wrap_s
) << 0));
1451 get_texrect_scale(struct vc4_texture_stateobj
*texstate
,
1452 enum quniform_contents contents
,
1455 struct pipe_sampler_view
*texture
= texstate
->textures
[data
];
1458 if (contents
== QUNIFORM_TEXRECT_SCALE_X
)
1459 dim
= texture
->texture
->width0
;
1461 dim
= texture
->texture
->height0
;
1463 return fui(1.0f
/ dim
);
1467 vc4_write_uniforms(struct vc4_context
*vc4
, struct vc4_compiled_shader
*shader
,
1468 struct vc4_constbuf_stateobj
*cb
,
1469 struct vc4_texture_stateobj
*texstate
,
1472 struct vc4_shader_uniform_info
*uinfo
= &shader
->uniforms
[shader_index
];
1473 const uint32_t *gallium_uniforms
= cb
->cb
[0].user_buffer
;
1475 cl_start_shader_reloc(&vc4
->uniforms
, uinfo
->num_texture_samples
);
1477 for (int i
= 0; i
< uinfo
->count
; i
++) {
1479 switch (uinfo
->contents
[i
]) {
1480 case QUNIFORM_CONSTANT
:
1481 cl_u32(&vc4
->uniforms
, uinfo
->data
[i
]);
1483 case QUNIFORM_UNIFORM
:
1484 cl_u32(&vc4
->uniforms
,
1485 gallium_uniforms
[uinfo
->data
[i
]]);
1487 case QUNIFORM_VIEWPORT_X_SCALE
:
1488 cl_f(&vc4
->uniforms
, vc4
->viewport
.scale
[0] * 16.0f
);
1490 case QUNIFORM_VIEWPORT_Y_SCALE
:
1491 cl_f(&vc4
->uniforms
, vc4
->viewport
.scale
[1] * 16.0f
);
1494 case QUNIFORM_VIEWPORT_Z_OFFSET
:
1495 cl_f(&vc4
->uniforms
, vc4
->viewport
.translate
[2]);
1497 case QUNIFORM_VIEWPORT_Z_SCALE
:
1498 cl_f(&vc4
->uniforms
, vc4
->viewport
.scale
[2]);
1501 case QUNIFORM_TEXTURE_CONFIG_P0
:
1502 write_texture_p0(vc4
, texstate
, uinfo
->data
[i
]);
1505 case QUNIFORM_TEXTURE_CONFIG_P1
:
1506 write_texture_p1(vc4
, texstate
, uinfo
->data
[i
]);
1509 case QUNIFORM_TEXRECT_SCALE_X
:
1510 case QUNIFORM_TEXRECT_SCALE_Y
:
1511 cl_u32(&vc4
->uniforms
,
1512 get_texrect_scale(texstate
,
1517 case QUNIFORM_BLEND_CONST_COLOR
:
1518 cl_f(&vc4
->uniforms
,
1519 vc4
->blend_color
.color
[uinfo
->data
[i
]]);
1523 uint32_t written_val
= *(uint32_t *)(vc4
->uniforms
.next
- 4);
1524 fprintf(stderr
, "%p/%d: %d: 0x%08x (%f)\n",
1525 shader
, shader_index
, i
, written_val
, uif(written_val
));
1531 vc4_fp_state_bind(struct pipe_context
*pctx
, void *hwcso
)
1533 struct vc4_context
*vc4
= vc4_context(pctx
);
1534 vc4
->prog
.bind_fs
= hwcso
;
1535 vc4
->prog
.dirty
|= VC4_SHADER_DIRTY_FP
;
1536 vc4
->dirty
|= VC4_DIRTY_PROG
;
1540 vc4_vp_state_bind(struct pipe_context
*pctx
, void *hwcso
)
1542 struct vc4_context
*vc4
= vc4_context(pctx
);
1543 vc4
->prog
.bind_vs
= hwcso
;
1544 vc4
->prog
.dirty
|= VC4_SHADER_DIRTY_VP
;
1545 vc4
->dirty
|= VC4_DIRTY_PROG
;
1549 vc4_program_init(struct pipe_context
*pctx
)
1551 struct vc4_context
*vc4
= vc4_context(pctx
);
1553 pctx
->create_vs_state
= vc4_shader_state_create
;
1554 pctx
->delete_vs_state
= vc4_shader_state_delete
;
1556 pctx
->create_fs_state
= vc4_shader_state_create
;
1557 pctx
->delete_fs_state
= vc4_shader_state_delete
;
1559 pctx
->bind_fs_state
= vc4_fp_state_bind
;
1560 pctx
->bind_vs_state
= vc4_vp_state_bind
;
1562 vc4
->fs_cache
= util_hash_table_create(fs_cache_hash
, fs_cache_compare
);
1563 vc4
->vs_cache
= util_hash_table_create(vs_cache_hash
, vs_cache_compare
);