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vc4: Add a helper for making driver-specific NIR load_uniform for GL state
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "util/u_format.h"
27 #include "util/u_hash.h"
28 #include "util/u_math.h"
29 #include "util/u_memory.h"
30 #include "util/ralloc.h"
31 #include "util/hash_table.h"
32 #include "tgsi/tgsi_dump.h"
33 #include "tgsi/tgsi_info.h"
34 #include "tgsi/tgsi_lowering.h"
35 #include "tgsi/tgsi_parse.h"
36 #include "glsl/nir/nir.h"
37 #include "glsl/nir/nir_builder.h"
38 #include "nir/tgsi_to_nir.h"
39 #include "vc4_context.h"
40 #include "vc4_qpu.h"
41 #include "vc4_qir.h"
42 #ifdef USE_VC4_SIMULATOR
43 #include "simpenrose/simpenrose.h"
44 #endif
45
46 static struct qreg
47 ntq_get_src(struct vc4_compile *c, nir_src src, int i);
48
49 static void
50 resize_qreg_array(struct vc4_compile *c,
51 struct qreg **regs,
52 uint32_t *size,
53 uint32_t decl_size)
54 {
55 if (*size >= decl_size)
56 return;
57
58 uint32_t old_size = *size;
59 *size = MAX2(*size * 2, decl_size);
60 *regs = reralloc(c, *regs, struct qreg, *size);
61 if (!*regs) {
62 fprintf(stderr, "Malloc failure\n");
63 abort();
64 }
65
66 for (uint32_t i = old_size; i < *size; i++)
67 (*regs)[i] = c->undef;
68 }
69
70 static struct qreg
71 indirect_uniform_load(struct vc4_compile *c, nir_intrinsic_instr *intr)
72 {
73 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0);
74 uint32_t offset = intr->const_index[0];
75 struct vc4_compiler_ubo_range *range = NULL;
76 unsigned i;
77 for (i = 0; i < c->num_uniform_ranges; i++) {
78 range = &c->ubo_ranges[i];
79 if (offset >= range->src_offset &&
80 offset < range->src_offset + range->size) {
81 break;
82 }
83 }
84 /* The driver-location-based offset always has to be within a declared
85 * uniform range.
86 */
87 assert(range);
88 if (!range->used) {
89 range->used = true;
90 range->dst_offset = c->next_ubo_dst_offset;
91 c->next_ubo_dst_offset += range->size;
92 c->num_ubo_ranges++;
93 };
94
95 offset -= range->src_offset;
96
97 /* Adjust for where we stored the TGSI register base. */
98 indirect_offset = qir_ADD(c, indirect_offset,
99 qir_uniform_ui(c, (range->dst_offset +
100 offset)));
101
102 /* Clamp to [0, array size). Note that MIN/MAX are signed. */
103 indirect_offset = qir_MAX(c, indirect_offset, qir_uniform_ui(c, 0));
104 indirect_offset = qir_MIN(c, indirect_offset,
105 qir_uniform_ui(c, (range->dst_offset +
106 range->size - 4)));
107
108 qir_TEX_DIRECT(c, indirect_offset, qir_uniform(c, QUNIFORM_UBO_ADDR, 0));
109 c->num_texture_samples++;
110 return qir_TEX_RESULT(c);
111 }
112
113 nir_ssa_def *vc4_nir_get_state_uniform(struct nir_builder *b,
114 enum quniform_contents contents)
115 {
116 nir_intrinsic_instr *intr =
117 nir_intrinsic_instr_create(b->shader,
118 nir_intrinsic_load_uniform);
119 intr->const_index[0] = VC4_NIR_STATE_UNIFORM_OFFSET + contents;
120 intr->num_components = 1;
121 nir_ssa_dest_init(&intr->instr, &intr->dest, 1, NULL);
122 nir_builder_instr_insert(b, &intr->instr);
123 return &intr->dest.ssa;
124 }
125
126 static struct qreg *
127 ntq_init_ssa_def(struct vc4_compile *c, nir_ssa_def *def)
128 {
129 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
130 def->num_components);
131 _mesa_hash_table_insert(c->def_ht, def, qregs);
132 return qregs;
133 }
134
135 static struct qreg *
136 ntq_get_dest(struct vc4_compile *c, nir_dest *dest)
137 {
138 if (dest->is_ssa) {
139 struct qreg *qregs = ntq_init_ssa_def(c, &dest->ssa);
140 for (int i = 0; i < dest->ssa.num_components; i++)
141 qregs[i] = c->undef;
142 return qregs;
143 } else {
144 nir_register *reg = dest->reg.reg;
145 assert(dest->reg.base_offset == 0);
146 assert(reg->num_array_elems == 0);
147 struct hash_entry *entry =
148 _mesa_hash_table_search(c->def_ht, reg);
149 return entry->data;
150 }
151 }
152
153 static struct qreg
154 ntq_get_src(struct vc4_compile *c, nir_src src, int i)
155 {
156 struct hash_entry *entry;
157 if (src.is_ssa) {
158 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
159 assert(i < src.ssa->num_components);
160 } else {
161 nir_register *reg = src.reg.reg;
162 entry = _mesa_hash_table_search(c->def_ht, reg);
163 assert(reg->num_array_elems == 0);
164 assert(src.reg.base_offset == 0);
165 assert(i < reg->num_components);
166 }
167
168 struct qreg *qregs = entry->data;
169 return qregs[i];
170 }
171
172 static struct qreg
173 ntq_get_alu_src(struct vc4_compile *c, nir_alu_instr *instr,
174 unsigned src)
175 {
176 assert(util_is_power_of_two(instr->dest.write_mask));
177 unsigned chan = ffs(instr->dest.write_mask) - 1;
178 struct qreg r = ntq_get_src(c, instr->src[src].src,
179 instr->src[src].swizzle[chan]);
180
181 assert(!instr->src[src].abs);
182 assert(!instr->src[src].negate);
183
184 return r;
185 };
186
187 static struct qreg
188 get_swizzled_channel(struct vc4_compile *c,
189 struct qreg *srcs, int swiz)
190 {
191 switch (swiz) {
192 default:
193 case UTIL_FORMAT_SWIZZLE_NONE:
194 fprintf(stderr, "warning: unknown swizzle\n");
195 /* FALLTHROUGH */
196 case UTIL_FORMAT_SWIZZLE_0:
197 return qir_uniform_f(c, 0.0);
198 case UTIL_FORMAT_SWIZZLE_1:
199 return qir_uniform_f(c, 1.0);
200 case UTIL_FORMAT_SWIZZLE_X:
201 case UTIL_FORMAT_SWIZZLE_Y:
202 case UTIL_FORMAT_SWIZZLE_Z:
203 case UTIL_FORMAT_SWIZZLE_W:
204 return srcs[swiz];
205 }
206 }
207
208 static inline struct qreg
209 qir_SAT(struct vc4_compile *c, struct qreg val)
210 {
211 return qir_FMAX(c,
212 qir_FMIN(c, val, qir_uniform_f(c, 1.0)),
213 qir_uniform_f(c, 0.0));
214 }
215
216 static struct qreg
217 ntq_rcp(struct vc4_compile *c, struct qreg x)
218 {
219 struct qreg r = qir_RCP(c, x);
220
221 /* Apply a Newton-Raphson step to improve the accuracy. */
222 r = qir_FMUL(c, r, qir_FSUB(c,
223 qir_uniform_f(c, 2.0),
224 qir_FMUL(c, x, r)));
225
226 return r;
227 }
228
229 static struct qreg
230 ntq_rsq(struct vc4_compile *c, struct qreg x)
231 {
232 struct qreg r = qir_RSQ(c, x);
233
234 /* Apply a Newton-Raphson step to improve the accuracy. */
235 r = qir_FMUL(c, r, qir_FSUB(c,
236 qir_uniform_f(c, 1.5),
237 qir_FMUL(c,
238 qir_uniform_f(c, 0.5),
239 qir_FMUL(c, x,
240 qir_FMUL(c, r, r)))));
241
242 return r;
243 }
244
245 static struct qreg
246 qir_srgb_decode(struct vc4_compile *c, struct qreg srgb)
247 {
248 struct qreg low = qir_FMUL(c, srgb, qir_uniform_f(c, 1.0 / 12.92));
249 struct qreg high = qir_POW(c,
250 qir_FMUL(c,
251 qir_FADD(c,
252 srgb,
253 qir_uniform_f(c, 0.055)),
254 qir_uniform_f(c, 1.0 / 1.055)),
255 qir_uniform_f(c, 2.4));
256
257 qir_SF(c, qir_FSUB(c, srgb, qir_uniform_f(c, 0.04045)));
258 return qir_SEL_X_Y_NS(c, low, high);
259 }
260
261 static struct qreg
262 qir_srgb_encode(struct vc4_compile *c, struct qreg linear)
263 {
264 struct qreg low = qir_FMUL(c, linear, qir_uniform_f(c, 12.92));
265 struct qreg high = qir_FSUB(c,
266 qir_FMUL(c,
267 qir_uniform_f(c, 1.055),
268 qir_POW(c,
269 linear,
270 qir_uniform_f(c, 0.41666))),
271 qir_uniform_f(c, 0.055));
272
273 qir_SF(c, qir_FSUB(c, linear, qir_uniform_f(c, 0.0031308)));
274 return qir_SEL_X_Y_NS(c, low, high);
275 }
276
277 static struct qreg
278 ntq_umul(struct vc4_compile *c, struct qreg src0, struct qreg src1)
279 {
280 struct qreg src0_hi = qir_SHR(c, src0,
281 qir_uniform_ui(c, 24));
282 struct qreg src1_hi = qir_SHR(c, src1,
283 qir_uniform_ui(c, 24));
284
285 struct qreg hilo = qir_MUL24(c, src0_hi, src1);
286 struct qreg lohi = qir_MUL24(c, src0, src1_hi);
287 struct qreg lolo = qir_MUL24(c, src0, src1);
288
289 return qir_ADD(c, lolo, qir_SHL(c,
290 qir_ADD(c, hilo, lohi),
291 qir_uniform_ui(c, 24)));
292 }
293
294 static void
295 ntq_emit_tex(struct vc4_compile *c, nir_tex_instr *instr)
296 {
297 struct qreg s, t, r, lod, proj, compare;
298 bool is_txb = false, is_txl = false, has_proj = false;
299 unsigned unit = instr->sampler_index;
300
301 for (unsigned i = 0; i < instr->num_srcs; i++) {
302 switch (instr->src[i].src_type) {
303 case nir_tex_src_coord:
304 s = ntq_get_src(c, instr->src[i].src, 0);
305 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D)
306 t = qir_uniform_f(c, 0.5);
307 else
308 t = ntq_get_src(c, instr->src[i].src, 1);
309 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
310 r = ntq_get_src(c, instr->src[i].src, 2);
311 break;
312 case nir_tex_src_bias:
313 lod = ntq_get_src(c, instr->src[i].src, 0);
314 is_txb = true;
315 break;
316 case nir_tex_src_lod:
317 lod = ntq_get_src(c, instr->src[i].src, 0);
318 is_txl = true;
319 break;
320 case nir_tex_src_comparitor:
321 compare = ntq_get_src(c, instr->src[i].src, 0);
322 break;
323 case nir_tex_src_projector:
324 proj = qir_RCP(c, ntq_get_src(c, instr->src[i].src, 0));
325 s = qir_FMUL(c, s, proj);
326 t = qir_FMUL(c, t, proj);
327 has_proj = true;
328 break;
329 default:
330 unreachable("unknown texture source");
331 }
332 }
333
334 struct qreg texture_u[] = {
335 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit),
336 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
337 qir_uniform(c, QUNIFORM_CONSTANT, 0),
338 qir_uniform(c, QUNIFORM_CONSTANT, 0),
339 };
340 uint32_t next_texture_u = 0;
341
342 /* There is no native support for GL texture rectangle coordinates, so
343 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
344 * 1]).
345 */
346 if (instr->sampler_dim == GLSL_SAMPLER_DIM_RECT) {
347 s = qir_FMUL(c, s,
348 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_X, unit));
349 t = qir_FMUL(c, t,
350 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_Y, unit));
351 }
352
353 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE || is_txl) {
354 texture_u[2] = qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P2,
355 unit | (is_txl << 16));
356 }
357
358 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
359 struct qreg ma = qir_FMAXABS(c, qir_FMAXABS(c, s, t), r);
360 struct qreg rcp_ma = qir_RCP(c, ma);
361 s = qir_FMUL(c, s, rcp_ma);
362 t = qir_FMUL(c, t, rcp_ma);
363 r = qir_FMUL(c, r, rcp_ma);
364
365 qir_TEX_R(c, r, texture_u[next_texture_u++]);
366 } else if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
367 c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP ||
368 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
369 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
370 qir_TEX_R(c, qir_uniform(c, QUNIFORM_TEXTURE_BORDER_COLOR, unit),
371 texture_u[next_texture_u++]);
372 }
373
374 if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP) {
375 s = qir_SAT(c, s);
376 }
377
378 if (c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
379 t = qir_SAT(c, t);
380 }
381
382 qir_TEX_T(c, t, texture_u[next_texture_u++]);
383
384 if (is_txl || is_txb)
385 qir_TEX_B(c, lod, texture_u[next_texture_u++]);
386
387 qir_TEX_S(c, s, texture_u[next_texture_u++]);
388
389 c->num_texture_samples++;
390 struct qreg tex = qir_TEX_RESULT(c);
391
392 enum pipe_format format = c->key->tex[unit].format;
393
394 struct qreg unpacked[4];
395 if (util_format_is_depth_or_stencil(format)) {
396 struct qreg depthf = qir_ITOF(c, qir_SHR(c, tex,
397 qir_uniform_ui(c, 8)));
398 struct qreg normalized = qir_FMUL(c, depthf,
399 qir_uniform_f(c, 1.0f/0xffffff));
400
401 struct qreg depth_output;
402
403 struct qreg one = qir_uniform_f(c, 1.0f);
404 if (c->key->tex[unit].compare_mode) {
405 if (has_proj)
406 compare = qir_FMUL(c, compare, proj);
407
408 switch (c->key->tex[unit].compare_func) {
409 case PIPE_FUNC_NEVER:
410 depth_output = qir_uniform_f(c, 0.0f);
411 break;
412 case PIPE_FUNC_ALWAYS:
413 depth_output = one;
414 break;
415 case PIPE_FUNC_EQUAL:
416 qir_SF(c, qir_FSUB(c, compare, normalized));
417 depth_output = qir_SEL_X_0_ZS(c, one);
418 break;
419 case PIPE_FUNC_NOTEQUAL:
420 qir_SF(c, qir_FSUB(c, compare, normalized));
421 depth_output = qir_SEL_X_0_ZC(c, one);
422 break;
423 case PIPE_FUNC_GREATER:
424 qir_SF(c, qir_FSUB(c, compare, normalized));
425 depth_output = qir_SEL_X_0_NC(c, one);
426 break;
427 case PIPE_FUNC_GEQUAL:
428 qir_SF(c, qir_FSUB(c, normalized, compare));
429 depth_output = qir_SEL_X_0_NS(c, one);
430 break;
431 case PIPE_FUNC_LESS:
432 qir_SF(c, qir_FSUB(c, compare, normalized));
433 depth_output = qir_SEL_X_0_NS(c, one);
434 break;
435 case PIPE_FUNC_LEQUAL:
436 qir_SF(c, qir_FSUB(c, normalized, compare));
437 depth_output = qir_SEL_X_0_NC(c, one);
438 break;
439 }
440 } else {
441 depth_output = normalized;
442 }
443
444 for (int i = 0; i < 4; i++)
445 unpacked[i] = depth_output;
446 } else {
447 for (int i = 0; i < 4; i++)
448 unpacked[i] = qir_UNPACK_8_F(c, tex, i);
449 }
450
451 const uint8_t *format_swiz = vc4_get_format_swizzle(format);
452 struct qreg texture_output[4];
453 for (int i = 0; i < 4; i++) {
454 texture_output[i] = get_swizzled_channel(c, unpacked,
455 format_swiz[i]);
456 }
457
458 if (util_format_is_srgb(format)) {
459 for (int i = 0; i < 3; i++)
460 texture_output[i] = qir_srgb_decode(c,
461 texture_output[i]);
462 }
463
464 struct qreg *dest = ntq_get_dest(c, &instr->dest);
465 for (int i = 0; i < 4; i++) {
466 dest[i] = get_swizzled_channel(c, texture_output,
467 c->key->tex[unit].swizzle[i]);
468 }
469 }
470
471 /**
472 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
473 * to zero).
474 */
475 static struct qreg
476 ntq_ffract(struct vc4_compile *c, struct qreg src)
477 {
478 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
479 struct qreg diff = qir_FSUB(c, src, trunc);
480 qir_SF(c, diff);
481 return qir_SEL_X_Y_NS(c,
482 qir_FADD(c, diff, qir_uniform_f(c, 1.0)),
483 diff);
484 }
485
486 /**
487 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
488 * zero).
489 */
490 static struct qreg
491 ntq_ffloor(struct vc4_compile *c, struct qreg src)
492 {
493 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
494
495 /* This will be < 0 if we truncated and the truncation was of a value
496 * that was < 0 in the first place.
497 */
498 qir_SF(c, qir_FSUB(c, src, trunc));
499
500 return qir_SEL_X_Y_NS(c,
501 qir_FSUB(c, trunc, qir_uniform_f(c, 1.0)),
502 trunc);
503 }
504
505 /**
506 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
507 * zero).
508 */
509 static struct qreg
510 ntq_fceil(struct vc4_compile *c, struct qreg src)
511 {
512 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
513
514 /* This will be < 0 if we truncated and the truncation was of a value
515 * that was > 0 in the first place.
516 */
517 qir_SF(c, qir_FSUB(c, trunc, src));
518
519 return qir_SEL_X_Y_NS(c,
520 qir_FADD(c, trunc, qir_uniform_f(c, 1.0)),
521 trunc);
522 }
523
524 static struct qreg
525 ntq_fsin(struct vc4_compile *c, struct qreg src)
526 {
527 float coeff[] = {
528 -2.0 * M_PI,
529 pow(2.0 * M_PI, 3) / (3 * 2 * 1),
530 -pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
531 pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
532 -pow(2.0 * M_PI, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
533 };
534
535 struct qreg scaled_x =
536 qir_FMUL(c,
537 src,
538 qir_uniform_f(c, 1.0 / (M_PI * 2.0)));
539
540 struct qreg x = qir_FADD(c,
541 ntq_ffract(c, scaled_x),
542 qir_uniform_f(c, -0.5));
543 struct qreg x2 = qir_FMUL(c, x, x);
544 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
545 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
546 x = qir_FMUL(c, x, x2);
547 sum = qir_FADD(c,
548 sum,
549 qir_FMUL(c,
550 x,
551 qir_uniform_f(c, coeff[i])));
552 }
553 return sum;
554 }
555
556 static struct qreg
557 ntq_fcos(struct vc4_compile *c, struct qreg src)
558 {
559 float coeff[] = {
560 -1.0f,
561 pow(2.0 * M_PI, 2) / (2 * 1),
562 -pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
563 pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
564 -pow(2.0 * M_PI, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
565 pow(2.0 * M_PI, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
566 };
567
568 struct qreg scaled_x =
569 qir_FMUL(c, src,
570 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
571 struct qreg x_frac = qir_FADD(c,
572 ntq_ffract(c, scaled_x),
573 qir_uniform_f(c, -0.5));
574
575 struct qreg sum = qir_uniform_f(c, coeff[0]);
576 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
577 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
578 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
579 if (i != 1)
580 x = qir_FMUL(c, x, x2);
581
582 struct qreg mul = qir_FMUL(c,
583 x,
584 qir_uniform_f(c, coeff[i]));
585 if (i == 0)
586 sum = mul;
587 else
588 sum = qir_FADD(c, sum, mul);
589 }
590 return sum;
591 }
592
593 static struct qreg
594 ntq_fsign(struct vc4_compile *c, struct qreg src)
595 {
596 qir_SF(c, src);
597 return qir_SEL_X_Y_NC(c,
598 qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0)),
599 qir_uniform_f(c, -1.0));
600 }
601
602 static struct qreg
603 get_channel_from_vpm(struct vc4_compile *c,
604 struct qreg *vpm_reads,
605 uint8_t swiz,
606 const struct util_format_description *desc)
607 {
608 const struct util_format_channel_description *chan =
609 &desc->channel[swiz];
610 struct qreg temp;
611
612 if (swiz > UTIL_FORMAT_SWIZZLE_W)
613 return get_swizzled_channel(c, vpm_reads, swiz);
614 else if (chan->size == 32 &&
615 chan->type == UTIL_FORMAT_TYPE_FLOAT) {
616 return get_swizzled_channel(c, vpm_reads, swiz);
617 } else if (chan->size == 32 &&
618 chan->type == UTIL_FORMAT_TYPE_SIGNED) {
619 if (chan->normalized) {
620 return qir_FMUL(c,
621 qir_ITOF(c, vpm_reads[swiz]),
622 qir_uniform_f(c,
623 1.0 / 0x7fffffff));
624 } else {
625 return qir_ITOF(c, vpm_reads[swiz]);
626 }
627 } else if (chan->size == 8 &&
628 (chan->type == UTIL_FORMAT_TYPE_UNSIGNED ||
629 chan->type == UTIL_FORMAT_TYPE_SIGNED)) {
630 struct qreg vpm = vpm_reads[0];
631 if (chan->type == UTIL_FORMAT_TYPE_SIGNED) {
632 temp = qir_XOR(c, vpm, qir_uniform_ui(c, 0x80808080));
633 if (chan->normalized) {
634 return qir_FSUB(c, qir_FMUL(c,
635 qir_UNPACK_8_F(c, temp, swiz),
636 qir_uniform_f(c, 2.0)),
637 qir_uniform_f(c, 1.0));
638 } else {
639 return qir_FADD(c,
640 qir_ITOF(c,
641 qir_UNPACK_8_I(c, temp,
642 swiz)),
643 qir_uniform_f(c, -128.0));
644 }
645 } else {
646 if (chan->normalized) {
647 return qir_UNPACK_8_F(c, vpm, swiz);
648 } else {
649 return qir_ITOF(c, qir_UNPACK_8_I(c, vpm, swiz));
650 }
651 }
652 } else if (chan->size == 16 &&
653 (chan->type == UTIL_FORMAT_TYPE_UNSIGNED ||
654 chan->type == UTIL_FORMAT_TYPE_SIGNED)) {
655 struct qreg vpm = vpm_reads[swiz / 2];
656
657 /* Note that UNPACK_16F eats a half float, not ints, so we use
658 * UNPACK_16_I for all of these.
659 */
660 if (chan->type == UTIL_FORMAT_TYPE_SIGNED) {
661 temp = qir_ITOF(c, qir_UNPACK_16_I(c, vpm, swiz % 2));
662 if (chan->normalized) {
663 return qir_FMUL(c, temp,
664 qir_uniform_f(c, 1/32768.0f));
665 } else {
666 return temp;
667 }
668 } else {
669 /* UNPACK_16I sign-extends, so we have to emit ANDs. */
670 temp = vpm;
671 if (swiz == 1 || swiz == 3)
672 temp = qir_UNPACK_16_I(c, temp, 1);
673 temp = qir_AND(c, temp, qir_uniform_ui(c, 0xffff));
674 temp = qir_ITOF(c, temp);
675
676 if (chan->normalized) {
677 return qir_FMUL(c, temp,
678 qir_uniform_f(c, 1 / 65535.0));
679 } else {
680 return temp;
681 }
682 }
683 } else {
684 return c->undef;
685 }
686 }
687
688 static void
689 emit_vertex_input(struct vc4_compile *c, int attr)
690 {
691 enum pipe_format format = c->vs_key->attr_formats[attr];
692 uint32_t attr_size = util_format_get_blocksize(format);
693 struct qreg vpm_reads[4];
694
695 c->vattr_sizes[attr] = align(attr_size, 4);
696 for (int i = 0; i < align(attr_size, 4) / 4; i++) {
697 struct qreg vpm = { QFILE_VPM, attr * 4 + i };
698 vpm_reads[i] = qir_MOV(c, vpm);
699 c->num_inputs++;
700 }
701
702 bool format_warned = false;
703 const struct util_format_description *desc =
704 util_format_description(format);
705
706 for (int i = 0; i < 4; i++) {
707 uint8_t swiz = desc->swizzle[i];
708 struct qreg result = get_channel_from_vpm(c, vpm_reads,
709 swiz, desc);
710
711 if (result.file == QFILE_NULL) {
712 if (!format_warned) {
713 fprintf(stderr,
714 "vtx element %d unsupported type: %s\n",
715 attr, util_format_name(format));
716 format_warned = true;
717 }
718 result = qir_uniform_f(c, 0.0);
719 }
720 c->inputs[attr * 4 + i] = result;
721 }
722 }
723
724 static void
725 emit_fragcoord_input(struct vc4_compile *c, int attr)
726 {
727 c->inputs[attr * 4 + 0] = qir_FRAG_X(c);
728 c->inputs[attr * 4 + 1] = qir_FRAG_Y(c);
729 c->inputs[attr * 4 + 2] =
730 qir_FMUL(c,
731 qir_ITOF(c, qir_FRAG_Z(c)),
732 qir_uniform_f(c, 1.0 / 0xffffff));
733 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
734 }
735
736 static struct qreg
737 emit_fragment_varying(struct vc4_compile *c, uint8_t semantic,
738 uint8_t index, uint8_t swizzle)
739 {
740 uint32_t i = c->num_input_semantics++;
741 struct qreg vary = {
742 QFILE_VARY,
743 i
744 };
745
746 if (c->num_input_semantics >= c->input_semantics_array_size) {
747 c->input_semantics_array_size =
748 MAX2(4, c->input_semantics_array_size * 2);
749
750 c->input_semantics = reralloc(c, c->input_semantics,
751 struct vc4_varying_semantic,
752 c->input_semantics_array_size);
753 }
754
755 c->input_semantics[i].semantic = semantic;
756 c->input_semantics[i].index = index;
757 c->input_semantics[i].swizzle = swizzle;
758
759 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
760 }
761
762 static void
763 emit_fragment_input(struct vc4_compile *c, int attr,
764 unsigned semantic_name, unsigned semantic_index)
765 {
766 for (int i = 0; i < 4; i++) {
767 c->inputs[attr * 4 + i] =
768 emit_fragment_varying(c,
769 semantic_name,
770 semantic_index,
771 i);
772 c->num_inputs++;
773 }
774 }
775
776 static void
777 add_output(struct vc4_compile *c,
778 uint32_t decl_offset,
779 uint8_t semantic_name,
780 uint8_t semantic_index,
781 uint8_t semantic_swizzle)
782 {
783 uint32_t old_array_size = c->outputs_array_size;
784 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
785 decl_offset + 1);
786
787 if (old_array_size != c->outputs_array_size) {
788 c->output_semantics = reralloc(c,
789 c->output_semantics,
790 struct vc4_varying_semantic,
791 c->outputs_array_size);
792 }
793
794 c->output_semantics[decl_offset].semantic = semantic_name;
795 c->output_semantics[decl_offset].index = semantic_index;
796 c->output_semantics[decl_offset].swizzle = semantic_swizzle;
797 }
798
799 static void
800 declare_uniform_range(struct vc4_compile *c, uint32_t start, uint32_t size)
801 {
802 unsigned array_id = c->num_uniform_ranges++;
803 if (array_id >= c->ubo_ranges_array_size) {
804 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
805 array_id + 1);
806 c->ubo_ranges = reralloc(c, c->ubo_ranges,
807 struct vc4_compiler_ubo_range,
808 c->ubo_ranges_array_size);
809 }
810
811 c->ubo_ranges[array_id].dst_offset = 0;
812 c->ubo_ranges[array_id].src_offset = start;
813 c->ubo_ranges[array_id].size = size;
814 c->ubo_ranges[array_id].used = false;
815 }
816
817 static void
818 ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr)
819 {
820 /* Vectors are special in that they have non-scalarized writemasks,
821 * and just take the first swizzle channel for each argument in order
822 * into each writemask channel.
823 */
824 if (instr->op == nir_op_vec2 ||
825 instr->op == nir_op_vec3 ||
826 instr->op == nir_op_vec4) {
827 struct qreg srcs[4];
828 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
829 srcs[i] = ntq_get_src(c, instr->src[i].src,
830 instr->src[i].swizzle[0]);
831 struct qreg *dest = ntq_get_dest(c, &instr->dest.dest);
832 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
833 dest[i] = srcs[i];
834 return;
835 }
836
837 /* General case: We can just grab the one used channel per src. */
838 struct qreg src[nir_op_infos[instr->op].num_inputs];
839 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
840 src[i] = ntq_get_alu_src(c, instr, i);
841 }
842
843 /* Pick the channel to store the output in. */
844 assert(!instr->dest.saturate);
845 struct qreg *dest = ntq_get_dest(c, &instr->dest.dest);
846 assert(util_is_power_of_two(instr->dest.write_mask));
847 dest += ffs(instr->dest.write_mask) - 1;
848
849 switch (instr->op) {
850 case nir_op_fmov:
851 case nir_op_imov:
852 *dest = qir_MOV(c, src[0]);
853 break;
854 case nir_op_fmul:
855 *dest = qir_FMUL(c, src[0], src[1]);
856 break;
857 case nir_op_fadd:
858 *dest = qir_FADD(c, src[0], src[1]);
859 break;
860 case nir_op_fsub:
861 *dest = qir_FSUB(c, src[0], src[1]);
862 break;
863 case nir_op_fmin:
864 *dest = qir_FMIN(c, src[0], src[1]);
865 break;
866 case nir_op_fmax:
867 *dest = qir_FMAX(c, src[0], src[1]);
868 break;
869
870 case nir_op_f2i:
871 case nir_op_f2u:
872 *dest = qir_FTOI(c, src[0]);
873 break;
874 case nir_op_i2f:
875 case nir_op_u2f:
876 *dest = qir_ITOF(c, src[0]);
877 break;
878 case nir_op_b2f:
879 *dest = qir_AND(c, src[0], qir_uniform_f(c, 1.0));
880 break;
881 case nir_op_b2i:
882 *dest = qir_AND(c, src[0], qir_uniform_ui(c, 1));
883 break;
884 case nir_op_i2b:
885 case nir_op_f2b:
886 qir_SF(c, src[0]);
887 *dest = qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
888 break;
889
890 case nir_op_iadd:
891 *dest = qir_ADD(c, src[0], src[1]);
892 break;
893 case nir_op_ushr:
894 *dest = qir_SHR(c, src[0], src[1]);
895 break;
896 case nir_op_isub:
897 *dest = qir_SUB(c, src[0], src[1]);
898 break;
899 case nir_op_ishr:
900 *dest = qir_ASR(c, src[0], src[1]);
901 break;
902 case nir_op_ishl:
903 *dest = qir_SHL(c, src[0], src[1]);
904 break;
905 case nir_op_imin:
906 *dest = qir_MIN(c, src[0], src[1]);
907 break;
908 case nir_op_imax:
909 *dest = qir_MAX(c, src[0], src[1]);
910 break;
911 case nir_op_iand:
912 *dest = qir_AND(c, src[0], src[1]);
913 break;
914 case nir_op_ior:
915 *dest = qir_OR(c, src[0], src[1]);
916 break;
917 case nir_op_ixor:
918 *dest = qir_XOR(c, src[0], src[1]);
919 break;
920 case nir_op_inot:
921 *dest = qir_NOT(c, src[0]);
922 break;
923
924 case nir_op_imul:
925 *dest = ntq_umul(c, src[0], src[1]);
926 break;
927
928 case nir_op_seq:
929 qir_SF(c, qir_FSUB(c, src[0], src[1]));
930 *dest = qir_SEL_X_0_ZS(c, qir_uniform_f(c, 1.0));
931 break;
932 case nir_op_sne:
933 qir_SF(c, qir_FSUB(c, src[0], src[1]));
934 *dest = qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0));
935 break;
936 case nir_op_sge:
937 qir_SF(c, qir_FSUB(c, src[0], src[1]));
938 *dest = qir_SEL_X_0_NC(c, qir_uniform_f(c, 1.0));
939 break;
940 case nir_op_slt:
941 qir_SF(c, qir_FSUB(c, src[0], src[1]));
942 *dest = qir_SEL_X_0_NS(c, qir_uniform_f(c, 1.0));
943 break;
944 case nir_op_feq:
945 qir_SF(c, qir_FSUB(c, src[0], src[1]));
946 *dest = qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
947 break;
948 case nir_op_fne:
949 qir_SF(c, qir_FSUB(c, src[0], src[1]));
950 *dest = qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
951 break;
952 case nir_op_fge:
953 qir_SF(c, qir_FSUB(c, src[0], src[1]));
954 *dest = qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
955 break;
956 case nir_op_flt:
957 qir_SF(c, qir_FSUB(c, src[0], src[1]));
958 *dest = qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
959 break;
960 case nir_op_ieq:
961 qir_SF(c, qir_SUB(c, src[0], src[1]));
962 *dest = qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
963 break;
964 case nir_op_ine:
965 qir_SF(c, qir_SUB(c, src[0], src[1]));
966 *dest = qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
967 break;
968 case nir_op_ige:
969 qir_SF(c, qir_SUB(c, src[0], src[1]));
970 *dest = qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
971 break;
972 case nir_op_ilt:
973 qir_SF(c, qir_SUB(c, src[0], src[1]));
974 *dest = qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
975 break;
976
977 case nir_op_bcsel:
978 qir_SF(c, src[0]);
979 *dest = qir_SEL_X_Y_NS(c, src[1], src[2]);
980 break;
981 case nir_op_fcsel:
982 qir_SF(c, src[0]);
983 *dest = qir_SEL_X_Y_ZC(c, src[1], src[2]);
984 break;
985
986 case nir_op_frcp:
987 *dest = ntq_rcp(c, src[0]);
988 break;
989 case nir_op_frsq:
990 *dest = ntq_rsq(c, src[0]);
991 break;
992 case nir_op_fexp2:
993 *dest = qir_EXP2(c, src[0]);
994 break;
995 case nir_op_flog2:
996 *dest = qir_LOG2(c, src[0]);
997 break;
998
999 case nir_op_ftrunc:
1000 *dest = qir_ITOF(c, qir_FTOI(c, src[0]));
1001 break;
1002 case nir_op_fceil:
1003 *dest = ntq_fceil(c, src[0]);
1004 break;
1005 case nir_op_ffract:
1006 *dest = ntq_ffract(c, src[0]);
1007 break;
1008 case nir_op_ffloor:
1009 *dest = ntq_ffloor(c, src[0]);
1010 break;
1011
1012 case nir_op_fsin:
1013 *dest = ntq_fsin(c, src[0]);
1014 break;
1015 case nir_op_fcos:
1016 *dest = ntq_fcos(c, src[0]);
1017 break;
1018
1019 case nir_op_fsign:
1020 *dest = ntq_fsign(c, src[0]);
1021 break;
1022
1023 case nir_op_fabs:
1024 *dest = qir_FMAXABS(c, src[0], src[0]);
1025 break;
1026 case nir_op_iabs:
1027 *dest = qir_MAX(c, src[0],
1028 qir_SUB(c, qir_uniform_ui(c, 0), src[0]));
1029 break;
1030
1031 default:
1032 fprintf(stderr, "unknown NIR ALU inst: ");
1033 nir_print_instr(&instr->instr, stderr);
1034 fprintf(stderr, "\n");
1035 abort();
1036 }
1037 }
1038
1039 static struct qreg
1040 vc4_blend_channel(struct vc4_compile *c,
1041 struct qreg *dst,
1042 struct qreg *src,
1043 struct qreg val,
1044 unsigned factor,
1045 int channel)
1046 {
1047 switch(factor) {
1048 case PIPE_BLENDFACTOR_ONE:
1049 return val;
1050 case PIPE_BLENDFACTOR_SRC_COLOR:
1051 return qir_FMUL(c, val, src[channel]);
1052 case PIPE_BLENDFACTOR_SRC_ALPHA:
1053 return qir_FMUL(c, val, src[3]);
1054 case PIPE_BLENDFACTOR_DST_ALPHA:
1055 return qir_FMUL(c, val, dst[3]);
1056 case PIPE_BLENDFACTOR_DST_COLOR:
1057 return qir_FMUL(c, val, dst[channel]);
1058 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
1059 if (channel != 3) {
1060 return qir_FMUL(c,
1061 val,
1062 qir_FMIN(c,
1063 src[3],
1064 qir_FSUB(c,
1065 qir_uniform_f(c, 1.0),
1066 dst[3])));
1067 } else {
1068 return val;
1069 }
1070 case PIPE_BLENDFACTOR_CONST_COLOR:
1071 return qir_FMUL(c, val,
1072 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR,
1073 channel));
1074 case PIPE_BLENDFACTOR_CONST_ALPHA:
1075 return qir_FMUL(c, val,
1076 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR, 3));
1077 case PIPE_BLENDFACTOR_ZERO:
1078 return qir_uniform_f(c, 0.0);
1079 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
1080 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1081 src[channel]));
1082 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
1083 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1084 src[3]));
1085 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
1086 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1087 dst[3]));
1088 case PIPE_BLENDFACTOR_INV_DST_COLOR:
1089 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1090 dst[channel]));
1091 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
1092 return qir_FMUL(c, val,
1093 qir_FSUB(c, qir_uniform_f(c, 1.0),
1094 qir_uniform(c,
1095 QUNIFORM_BLEND_CONST_COLOR,
1096 channel)));
1097 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
1098 return qir_FMUL(c, val,
1099 qir_FSUB(c, qir_uniform_f(c, 1.0),
1100 qir_uniform(c,
1101 QUNIFORM_BLEND_CONST_COLOR,
1102 3)));
1103
1104 default:
1105 case PIPE_BLENDFACTOR_SRC1_COLOR:
1106 case PIPE_BLENDFACTOR_SRC1_ALPHA:
1107 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
1108 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
1109 /* Unsupported. */
1110 fprintf(stderr, "Unknown blend factor %d\n", factor);
1111 return val;
1112 }
1113 }
1114
1115 static struct qreg
1116 vc4_blend_func(struct vc4_compile *c,
1117 struct qreg src, struct qreg dst,
1118 unsigned func)
1119 {
1120 switch (func) {
1121 case PIPE_BLEND_ADD:
1122 return qir_FADD(c, src, dst);
1123 case PIPE_BLEND_SUBTRACT:
1124 return qir_FSUB(c, src, dst);
1125 case PIPE_BLEND_REVERSE_SUBTRACT:
1126 return qir_FSUB(c, dst, src);
1127 case PIPE_BLEND_MIN:
1128 return qir_FMIN(c, src, dst);
1129 case PIPE_BLEND_MAX:
1130 return qir_FMAX(c, src, dst);
1131
1132 default:
1133 /* Unsupported. */
1134 fprintf(stderr, "Unknown blend func %d\n", func);
1135 return src;
1136
1137 }
1138 }
1139
1140 /**
1141 * Implements fixed function blending in shader code.
1142 *
1143 * VC4 doesn't have any hardware support for blending. Instead, you read the
1144 * current contents of the destination from the tile buffer after having
1145 * waited for the scoreboard (which is handled by vc4_qpu_emit.c), then do
1146 * math using your output color and that destination value, and update the
1147 * output color appropriately.
1148 */
1149 static void
1150 vc4_blend(struct vc4_compile *c, struct qreg *result,
1151 struct qreg *dst_color, struct qreg *src_color)
1152 {
1153 struct pipe_rt_blend_state *blend = &c->fs_key->blend;
1154
1155 if (!blend->blend_enable) {
1156 for (int i = 0; i < 4; i++)
1157 result[i] = src_color[i];
1158 return;
1159 }
1160
1161 for (int i = 0; i < 4; i++)
1162 src_color[i] = qir_SAT(c, src_color[i]);
1163
1164 struct qreg src_blend[4], dst_blend[4];
1165 for (int i = 0; i < 3; i++) {
1166 src_blend[i] = vc4_blend_channel(c,
1167 dst_color, src_color,
1168 src_color[i],
1169 blend->rgb_src_factor, i);
1170 dst_blend[i] = vc4_blend_channel(c,
1171 dst_color, src_color,
1172 dst_color[i],
1173 blend->rgb_dst_factor, i);
1174 }
1175 src_blend[3] = vc4_blend_channel(c,
1176 dst_color, src_color,
1177 src_color[3],
1178 blend->alpha_src_factor, 3);
1179 dst_blend[3] = vc4_blend_channel(c,
1180 dst_color, src_color,
1181 dst_color[3],
1182 blend->alpha_dst_factor, 3);
1183
1184 for (int i = 0; i < 3; i++) {
1185 result[i] = vc4_blend_func(c,
1186 src_blend[i], dst_blend[i],
1187 blend->rgb_func);
1188 }
1189 result[3] = vc4_blend_func(c,
1190 src_blend[3], dst_blend[3],
1191 blend->alpha_func);
1192 }
1193
1194 static void
1195 clip_distance_discard(struct vc4_compile *c)
1196 {
1197 for (int i = 0; i < PIPE_MAX_CLIP_PLANES; i++) {
1198 if (!(c->key->ucp_enables & (1 << i)))
1199 continue;
1200
1201 struct qreg dist = emit_fragment_varying(c,
1202 TGSI_SEMANTIC_CLIPDIST,
1203 i,
1204 TGSI_SWIZZLE_X);
1205
1206 qir_SF(c, dist);
1207
1208 if (c->discard.file == QFILE_NULL)
1209 c->discard = qir_uniform_ui(c, 0);
1210
1211 c->discard = qir_SEL_X_Y_NS(c, qir_uniform_ui(c, ~0),
1212 c->discard);
1213 }
1214 }
1215
1216 static void
1217 alpha_test_discard(struct vc4_compile *c)
1218 {
1219 struct qreg src_alpha;
1220 struct qreg alpha_ref = qir_uniform(c, QUNIFORM_ALPHA_REF, 0);
1221
1222 if (!c->fs_key->alpha_test)
1223 return;
1224
1225 if (c->output_color_index != -1)
1226 src_alpha = c->outputs[c->output_color_index + 3];
1227 else
1228 src_alpha = qir_uniform_f(c, 1.0);
1229
1230 if (c->discard.file == QFILE_NULL)
1231 c->discard = qir_uniform_ui(c, 0);
1232
1233 switch (c->fs_key->alpha_test_func) {
1234 case PIPE_FUNC_NEVER:
1235 c->discard = qir_uniform_ui(c, ~0);
1236 break;
1237 case PIPE_FUNC_ALWAYS:
1238 break;
1239 case PIPE_FUNC_EQUAL:
1240 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1241 c->discard = qir_SEL_X_Y_ZS(c, c->discard,
1242 qir_uniform_ui(c, ~0));
1243 break;
1244 case PIPE_FUNC_NOTEQUAL:
1245 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1246 c->discard = qir_SEL_X_Y_ZC(c, c->discard,
1247 qir_uniform_ui(c, ~0));
1248 break;
1249 case PIPE_FUNC_GREATER:
1250 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1251 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1252 qir_uniform_ui(c, ~0));
1253 break;
1254 case PIPE_FUNC_GEQUAL:
1255 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1256 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1257 qir_uniform_ui(c, ~0));
1258 break;
1259 case PIPE_FUNC_LESS:
1260 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1261 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1262 qir_uniform_ui(c, ~0));
1263 break;
1264 case PIPE_FUNC_LEQUAL:
1265 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1266 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1267 qir_uniform_ui(c, ~0));
1268 break;
1269 }
1270 }
1271
1272 static struct qreg
1273 vc4_logicop(struct vc4_compile *c, struct qreg src, struct qreg dst)
1274 {
1275 switch (c->fs_key->logicop_func) {
1276 case PIPE_LOGICOP_CLEAR:
1277 return qir_uniform_f(c, 0.0);
1278 case PIPE_LOGICOP_NOR:
1279 return qir_NOT(c, qir_OR(c, src, dst));
1280 case PIPE_LOGICOP_AND_INVERTED:
1281 return qir_AND(c, qir_NOT(c, src), dst);
1282 case PIPE_LOGICOP_COPY_INVERTED:
1283 return qir_NOT(c, src);
1284 case PIPE_LOGICOP_AND_REVERSE:
1285 return qir_AND(c, src, qir_NOT(c, dst));
1286 case PIPE_LOGICOP_INVERT:
1287 return qir_NOT(c, dst);
1288 case PIPE_LOGICOP_XOR:
1289 return qir_XOR(c, src, dst);
1290 case PIPE_LOGICOP_NAND:
1291 return qir_NOT(c, qir_AND(c, src, dst));
1292 case PIPE_LOGICOP_AND:
1293 return qir_AND(c, src, dst);
1294 case PIPE_LOGICOP_EQUIV:
1295 return qir_NOT(c, qir_XOR(c, src, dst));
1296 case PIPE_LOGICOP_NOOP:
1297 return dst;
1298 case PIPE_LOGICOP_OR_INVERTED:
1299 return qir_OR(c, qir_NOT(c, src), dst);
1300 case PIPE_LOGICOP_OR_REVERSE:
1301 return qir_OR(c, src, qir_NOT(c, dst));
1302 case PIPE_LOGICOP_OR:
1303 return qir_OR(c, src, dst);
1304 case PIPE_LOGICOP_SET:
1305 return qir_uniform_ui(c, ~0);
1306 case PIPE_LOGICOP_COPY:
1307 default:
1308 return src;
1309 }
1310 }
1311
1312 /**
1313 * Applies the GL blending pipeline and returns the packed (8888) output
1314 * color.
1315 */
1316 static struct qreg
1317 blend_pipeline(struct vc4_compile *c)
1318 {
1319 enum pipe_format color_format = c->fs_key->color_format;
1320 const uint8_t *format_swiz = vc4_get_format_swizzle(color_format);
1321 struct qreg tlb_read_color[4] = { c->undef, c->undef, c->undef, c->undef };
1322 struct qreg dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1323 struct qreg linear_dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1324 struct qreg packed_dst_color = c->undef;
1325
1326 if (c->fs_key->blend.blend_enable ||
1327 c->fs_key->blend.colormask != 0xf ||
1328 c->fs_key->logicop_func != PIPE_LOGICOP_COPY) {
1329 packed_dst_color = qir_TLB_COLOR_READ(c);
1330 for (int i = 0; i < 4; i++)
1331 tlb_read_color[i] = qir_UNPACK_8_F(c,
1332 packed_dst_color, i);
1333 for (int i = 0; i < 4; i++) {
1334 dst_color[i] = get_swizzled_channel(c,
1335 tlb_read_color,
1336 format_swiz[i]);
1337 if (util_format_is_srgb(color_format) && i != 3) {
1338 linear_dst_color[i] =
1339 qir_srgb_decode(c, dst_color[i]);
1340 } else {
1341 linear_dst_color[i] = dst_color[i];
1342 }
1343 }
1344 }
1345
1346 struct qreg undef_array[4] = { c->undef, c->undef, c->undef, c->undef };
1347 const struct qreg *output_colors = (c->output_color_index != -1 ?
1348 c->outputs + c->output_color_index :
1349 undef_array);
1350 struct qreg blend_src_color[4];
1351 for (int i = 0; i < 4; i++)
1352 blend_src_color[i] = output_colors[i];
1353
1354 struct qreg blend_color[4];
1355 vc4_blend(c, blend_color, linear_dst_color, blend_src_color);
1356
1357 if (util_format_is_srgb(color_format)) {
1358 for (int i = 0; i < 3; i++)
1359 blend_color[i] = qir_srgb_encode(c, blend_color[i]);
1360 }
1361
1362 /* Debug: Sometimes you're getting a black output and just want to see
1363 * if the FS is getting executed at all. Spam magenta into the color
1364 * output.
1365 */
1366 if (0) {
1367 blend_color[0] = qir_uniform_f(c, 1.0);
1368 blend_color[1] = qir_uniform_f(c, 0.0);
1369 blend_color[2] = qir_uniform_f(c, 1.0);
1370 blend_color[3] = qir_uniform_f(c, 0.5);
1371 }
1372
1373 struct qreg swizzled_outputs[4];
1374 for (int i = 0; i < 4; i++) {
1375 swizzled_outputs[i] = get_swizzled_channel(c, blend_color,
1376 format_swiz[i]);
1377 }
1378
1379 struct qreg packed_color = c->undef;
1380 for (int i = 0; i < 4; i++) {
1381 if (swizzled_outputs[i].file == QFILE_NULL)
1382 continue;
1383 if (packed_color.file == QFILE_NULL) {
1384 packed_color = qir_PACK_8888_F(c, swizzled_outputs[i]);
1385 } else {
1386 packed_color = qir_PACK_8_F(c,
1387 packed_color,
1388 swizzled_outputs[i],
1389 i);
1390 }
1391 }
1392
1393 if (packed_color.file == QFILE_NULL)
1394 packed_color = qir_uniform_ui(c, 0);
1395
1396 if (c->fs_key->logicop_func != PIPE_LOGICOP_COPY) {
1397 packed_color = vc4_logicop(c, packed_color, packed_dst_color);
1398 }
1399
1400 /* If the bit isn't set in the color mask, then just return the
1401 * original dst color, instead.
1402 */
1403 uint32_t colormask = 0xffffffff;
1404 for (int i = 0; i < 4; i++) {
1405 if (format_swiz[i] < 4 &&
1406 !(c->fs_key->blend.colormask & (1 << format_swiz[i]))) {
1407 colormask &= ~(0xff << (i * 8));
1408 }
1409 }
1410 if (colormask != 0xffffffff) {
1411 packed_color = qir_OR(c,
1412 qir_AND(c, packed_color,
1413 qir_uniform_ui(c, colormask)),
1414 qir_AND(c, packed_dst_color,
1415 qir_uniform_ui(c, ~colormask)));
1416 }
1417
1418 return packed_color;
1419 }
1420
1421 static void
1422 emit_frag_end(struct vc4_compile *c)
1423 {
1424 clip_distance_discard(c);
1425 alpha_test_discard(c);
1426 struct qreg color = blend_pipeline(c);
1427
1428 if (c->discard.file != QFILE_NULL)
1429 qir_TLB_DISCARD_SETUP(c, c->discard);
1430
1431 if (c->fs_key->stencil_enabled) {
1432 qir_TLB_STENCIL_SETUP(c, qir_uniform(c, QUNIFORM_STENCIL, 0));
1433 if (c->fs_key->stencil_twoside) {
1434 qir_TLB_STENCIL_SETUP(c, qir_uniform(c, QUNIFORM_STENCIL, 1));
1435 }
1436 if (c->fs_key->stencil_full_writemasks) {
1437 qir_TLB_STENCIL_SETUP(c, qir_uniform(c, QUNIFORM_STENCIL, 2));
1438 }
1439 }
1440
1441 if (c->fs_key->depth_enabled) {
1442 struct qreg z;
1443 if (c->output_position_index != -1) {
1444 z = qir_FTOI(c, qir_FMUL(c, c->outputs[c->output_position_index + 2],
1445 qir_uniform_f(c, 0xffffff)));
1446 } else {
1447 z = qir_FRAG_Z(c);
1448 }
1449 qir_TLB_Z_WRITE(c, z);
1450 }
1451
1452 qir_TLB_COLOR_WRITE(c, color);
1453 }
1454
1455 static void
1456 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1457 {
1458 struct qreg xyi[2];
1459
1460 for (int i = 0; i < 2; i++) {
1461 struct qreg scale =
1462 qir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1463
1464 xyi[i] = qir_FTOI(c, qir_FMUL(c,
1465 qir_FMUL(c,
1466 c->outputs[c->output_position_index + i],
1467 scale),
1468 rcp_w));
1469 }
1470
1471 qir_VPM_WRITE(c, qir_PACK_SCALED(c, xyi[0], xyi[1]));
1472 }
1473
1474 static void
1475 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1476 {
1477 struct qreg zscale = qir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1478 struct qreg zoffset = qir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1479
1480 qir_VPM_WRITE(c, qir_FADD(c, qir_FMUL(c, qir_FMUL(c,
1481 c->outputs[c->output_position_index + 2],
1482 zscale),
1483 rcp_w),
1484 zoffset));
1485 }
1486
1487 static void
1488 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1489 {
1490 qir_VPM_WRITE(c, rcp_w);
1491 }
1492
1493 static void
1494 emit_point_size_write(struct vc4_compile *c)
1495 {
1496 struct qreg point_size;
1497
1498 if (c->output_point_size_index != -1)
1499 point_size = c->outputs[c->output_point_size_index + 3];
1500 else
1501 point_size = qir_uniform_f(c, 1.0);
1502
1503 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1504 * BCM21553).
1505 */
1506 point_size = qir_FMAX(c, point_size, qir_uniform_f(c, .125));
1507
1508 qir_VPM_WRITE(c, point_size);
1509 }
1510
1511 /**
1512 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1513 *
1514 * The simulator insists that there be at least one vertex attribute, so
1515 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also
1516 * insists that all vertex attributes loaded get read by the VS/CS, so we have
1517 * to consume it here.
1518 */
1519 static void
1520 emit_stub_vpm_read(struct vc4_compile *c)
1521 {
1522 if (c->num_inputs)
1523 return;
1524
1525 c->vattr_sizes[0] = 4;
1526 struct qreg vpm = { QFILE_VPM, 0 };
1527 (void)qir_MOV(c, vpm);
1528 c->num_inputs++;
1529 }
1530
1531 static void
1532 emit_ucp_clipdistance(struct vc4_compile *c)
1533 {
1534 unsigned cv;
1535 if (c->output_clipvertex_index != -1)
1536 cv = c->output_clipvertex_index;
1537 else if (c->output_position_index != -1)
1538 cv = c->output_position_index;
1539 else
1540 return;
1541
1542 for (int plane = 0; plane < PIPE_MAX_CLIP_PLANES; plane++) {
1543 if (!(c->key->ucp_enables & (1 << plane)))
1544 continue;
1545
1546 /* Pick the next outputs[] that hasn't been written to, since
1547 * there are no other program writes left to be processed at
1548 * this point. If something had been declared but not written
1549 * (like a w component), we'll just smash over the top of it.
1550 */
1551 uint32_t output_index = c->num_outputs++;
1552 add_output(c, output_index,
1553 TGSI_SEMANTIC_CLIPDIST,
1554 plane,
1555 TGSI_SWIZZLE_X);
1556
1557
1558 struct qreg dist = qir_uniform_f(c, 0.0);
1559 for (int i = 0; i < 4; i++) {
1560 struct qreg pos_chan = c->outputs[cv + i];
1561 struct qreg ucp =
1562 qir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1563 plane * 4 + i);
1564 dist = qir_FADD(c, dist, qir_FMUL(c, pos_chan, ucp));
1565 }
1566
1567 c->outputs[output_index] = dist;
1568 }
1569 }
1570
1571 static void
1572 emit_vert_end(struct vc4_compile *c,
1573 struct vc4_varying_semantic *fs_inputs,
1574 uint32_t num_fs_inputs)
1575 {
1576 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1577
1578 emit_stub_vpm_read(c);
1579 emit_ucp_clipdistance(c);
1580
1581 emit_scaled_viewport_write(c, rcp_w);
1582 emit_zs_write(c, rcp_w);
1583 emit_rcp_wc_write(c, rcp_w);
1584 if (c->vs_key->per_vertex_point_size)
1585 emit_point_size_write(c);
1586
1587 for (int i = 0; i < num_fs_inputs; i++) {
1588 struct vc4_varying_semantic *input = &fs_inputs[i];
1589 int j;
1590
1591 for (j = 0; j < c->num_outputs; j++) {
1592 struct vc4_varying_semantic *output =
1593 &c->output_semantics[j];
1594
1595 if (input->semantic == output->semantic &&
1596 input->index == output->index &&
1597 input->swizzle == output->swizzle) {
1598 qir_VPM_WRITE(c, c->outputs[j]);
1599 break;
1600 }
1601 }
1602 /* Emit padding if we didn't find a declared VS output for
1603 * this FS input.
1604 */
1605 if (j == c->num_outputs)
1606 qir_VPM_WRITE(c, qir_uniform_f(c, 0.0));
1607 }
1608 }
1609
1610 static void
1611 emit_coord_end(struct vc4_compile *c)
1612 {
1613 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1614
1615 emit_stub_vpm_read(c);
1616
1617 for (int i = 0; i < 4; i++)
1618 qir_VPM_WRITE(c, c->outputs[c->output_position_index + i]);
1619
1620 emit_scaled_viewport_write(c, rcp_w);
1621 emit_zs_write(c, rcp_w);
1622 emit_rcp_wc_write(c, rcp_w);
1623 if (c->vs_key->per_vertex_point_size)
1624 emit_point_size_write(c);
1625 }
1626
1627 static void
1628 vc4_optimize_nir(struct nir_shader *s)
1629 {
1630 bool progress;
1631
1632 do {
1633 progress = false;
1634
1635 nir_lower_vars_to_ssa(s);
1636 nir_lower_alu_to_scalar(s);
1637
1638 progress = nir_copy_prop(s) || progress;
1639 progress = nir_opt_dce(s) || progress;
1640 progress = nir_opt_cse(s) || progress;
1641 progress = nir_opt_peephole_select(s) || progress;
1642 progress = nir_opt_algebraic(s) || progress;
1643 progress = nir_opt_constant_folding(s) || progress;
1644 progress = nir_opt_undef(s) || progress;
1645 } while (progress);
1646 }
1647
1648 static int
1649 driver_location_compare(const void *in_a, const void *in_b)
1650 {
1651 const nir_variable *const *a = in_a;
1652 const nir_variable *const *b = in_b;
1653
1654 return (*a)->data.driver_location - (*b)->data.driver_location;
1655 }
1656
1657 static void
1658 ntq_setup_inputs(struct vc4_compile *c)
1659 {
1660 unsigned num_entries = 0;
1661 foreach_list_typed(nir_variable, var, node, &c->s->inputs)
1662 num_entries++;
1663
1664 nir_variable *vars[num_entries];
1665
1666 unsigned i = 0;
1667 foreach_list_typed(nir_variable, var, node, &c->s->inputs)
1668 vars[i++] = var;
1669
1670 /* Sort the variables so that we emit the input setup in
1671 * driver_location order. This is required for VPM reads, whose data
1672 * is fetched into the VPM in driver_location (TGSI register index)
1673 * order.
1674 */
1675 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1676
1677 for (unsigned i = 0; i < num_entries; i++) {
1678 nir_variable *var = vars[i];
1679 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1680 /* XXX: map loc slots to semantics */
1681 unsigned semantic_name = var->data.location;
1682 unsigned semantic_index = var->data.index;
1683 unsigned loc = var->data.driver_location;
1684
1685 assert(array_len == 1);
1686 (void)array_len;
1687 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1688 (loc + 1) * 4);
1689
1690 if (c->stage == QSTAGE_FRAG) {
1691 if (semantic_name == TGSI_SEMANTIC_POSITION) {
1692 emit_fragcoord_input(c, loc);
1693 } else if (semantic_name == TGSI_SEMANTIC_FACE) {
1694 c->inputs[loc * 4 + 0] = qir_FRAG_REV_FLAG(c);
1695 } else if (semantic_name == TGSI_SEMANTIC_GENERIC &&
1696 (c->fs_key->point_sprite_mask &
1697 (1 << semantic_index))) {
1698 c->inputs[loc * 4 + 0] = c->point_x;
1699 c->inputs[loc * 4 + 1] = c->point_y;
1700 } else {
1701 emit_fragment_input(c, loc,
1702 semantic_name,
1703 semantic_index);
1704 }
1705 } else {
1706 emit_vertex_input(c, loc);
1707 }
1708 }
1709 }
1710
1711 static void
1712 ntq_setup_outputs(struct vc4_compile *c)
1713 {
1714 foreach_list_typed(nir_variable, var, node, &c->s->outputs) {
1715 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1716 /* XXX: map loc slots to semantics */
1717 unsigned semantic_name = var->data.location;
1718 unsigned semantic_index = var->data.index;
1719 unsigned loc = var->data.driver_location * 4;
1720
1721 assert(array_len == 1);
1722 (void)array_len;
1723
1724 /* NIR hack to pass through
1725 * TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS */
1726 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1727 semantic_index == -1)
1728 semantic_index = 0;
1729
1730 for (int i = 0; i < 4; i++) {
1731 add_output(c,
1732 loc + i,
1733 semantic_name,
1734 semantic_index,
1735 i);
1736 }
1737
1738 switch (semantic_name) {
1739 case TGSI_SEMANTIC_POSITION:
1740 c->output_position_index = loc;
1741 break;
1742 case TGSI_SEMANTIC_CLIPVERTEX:
1743 c->output_clipvertex_index = loc;
1744 break;
1745 case TGSI_SEMANTIC_COLOR:
1746 c->output_color_index = loc;
1747 break;
1748 case TGSI_SEMANTIC_PSIZE:
1749 c->output_point_size_index = loc;
1750 break;
1751 }
1752
1753 }
1754 }
1755
1756 static void
1757 ntq_setup_uniforms(struct vc4_compile *c)
1758 {
1759 foreach_list_typed(nir_variable, var, node, &c->s->uniforms) {
1760 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1761 unsigned array_elem_size = 4 * sizeof(float);
1762
1763 declare_uniform_range(c, var->data.driver_location * array_elem_size,
1764 array_len * array_elem_size);
1765
1766 }
1767 }
1768
1769 /**
1770 * Sets up the mapping from nir_register to struct qreg *.
1771 *
1772 * Each nir_register gets a struct qreg per 32-bit component being stored.
1773 */
1774 static void
1775 ntq_setup_registers(struct vc4_compile *c, struct exec_list *list)
1776 {
1777 foreach_list_typed(nir_register, nir_reg, node, list) {
1778 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1779 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1780 array_len *
1781 nir_reg->num_components);
1782
1783 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1784
1785 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1786 qregs[i] = qir_uniform_ui(c, 0);
1787 }
1788 }
1789
1790 static void
1791 ntq_emit_load_const(struct vc4_compile *c, nir_load_const_instr *instr)
1792 {
1793 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1794 for (int i = 0; i < instr->def.num_components; i++)
1795 qregs[i] = qir_uniform_ui(c, instr->value.u[i]);
1796
1797 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1798 }
1799
1800 static void
1801 ntq_emit_ssa_undef(struct vc4_compile *c, nir_ssa_undef_instr *instr)
1802 {
1803 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1804
1805 /* QIR needs there to be *some* value, so pick 0 (same as for
1806 * ntq_setup_registers().
1807 */
1808 for (int i = 0; i < instr->def.num_components; i++)
1809 qregs[i] = qir_uniform_ui(c, 0);
1810 }
1811
1812 static void
1813 ntq_emit_intrinsic(struct vc4_compile *c, nir_intrinsic_instr *instr)
1814 {
1815 const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
1816 struct qreg *dest = NULL;
1817
1818 if (info->has_dest) {
1819 dest = ntq_get_dest(c, &instr->dest);
1820 }
1821
1822 switch (instr->intrinsic) {
1823 case nir_intrinsic_load_uniform:
1824 assert(instr->num_components == 1);
1825 if (instr->const_index[0] < VC4_NIR_STATE_UNIFORM_OFFSET) {
1826 *dest = qir_uniform(c, QUNIFORM_UNIFORM,
1827 instr->const_index[0]);
1828 } else {
1829 *dest = qir_uniform(c, instr->const_index[0] -
1830 VC4_NIR_STATE_UNIFORM_OFFSET,
1831 0);
1832 }
1833 break;
1834
1835 case nir_intrinsic_load_uniform_indirect:
1836 *dest = indirect_uniform_load(c, instr);
1837
1838 break;
1839
1840 case nir_intrinsic_load_input:
1841 assert(instr->num_components == 1);
1842 *dest = c->inputs[instr->const_index[0]];
1843
1844 break;
1845
1846 case nir_intrinsic_store_output:
1847 assert(instr->num_components == 1);
1848 c->outputs[instr->const_index[0]] =
1849 qir_MOV(c, ntq_get_src(c, instr->src[0], 0));
1850 c->num_outputs = MAX2(c->num_outputs, instr->const_index[0] + 1);
1851 break;
1852
1853 case nir_intrinsic_discard:
1854 c->discard = qir_uniform_ui(c, ~0);
1855 break;
1856
1857 case nir_intrinsic_discard_if:
1858 if (c->discard.file == QFILE_NULL)
1859 c->discard = qir_uniform_ui(c, 0);
1860 c->discard = qir_OR(c, c->discard,
1861 ntq_get_src(c, instr->src[0], 0));
1862 break;
1863
1864 default:
1865 fprintf(stderr, "Unknown intrinsic: ");
1866 nir_print_instr(&instr->instr, stderr);
1867 fprintf(stderr, "\n");
1868 break;
1869 }
1870 }
1871
1872 static void
1873 ntq_emit_if(struct vc4_compile *c, nir_if *if_stmt)
1874 {
1875 fprintf(stderr, "general IF statements not handled.\n");
1876 }
1877
1878 static void
1879 ntq_emit_instr(struct vc4_compile *c, nir_instr *instr)
1880 {
1881 switch (instr->type) {
1882 case nir_instr_type_alu:
1883 ntq_emit_alu(c, nir_instr_as_alu(instr));
1884 break;
1885
1886 case nir_instr_type_intrinsic:
1887 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
1888 break;
1889
1890 case nir_instr_type_load_const:
1891 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
1892 break;
1893
1894 case nir_instr_type_ssa_undef:
1895 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
1896 break;
1897
1898 case nir_instr_type_tex:
1899 ntq_emit_tex(c, nir_instr_as_tex(instr));
1900 break;
1901
1902 default:
1903 fprintf(stderr, "Unknown NIR instr type: ");
1904 nir_print_instr(instr, stderr);
1905 fprintf(stderr, "\n");
1906 abort();
1907 }
1908 }
1909
1910 static void
1911 ntq_emit_block(struct vc4_compile *c, nir_block *block)
1912 {
1913 nir_foreach_instr(block, instr) {
1914 ntq_emit_instr(c, instr);
1915 }
1916 }
1917
1918 static void
1919 ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list)
1920 {
1921 foreach_list_typed(nir_cf_node, node, node, list) {
1922 switch (node->type) {
1923 /* case nir_cf_node_loop: */
1924 case nir_cf_node_block:
1925 ntq_emit_block(c, nir_cf_node_as_block(node));
1926 break;
1927
1928 case nir_cf_node_if:
1929 ntq_emit_if(c, nir_cf_node_as_if(node));
1930 break;
1931
1932 default:
1933 assert(0);
1934 }
1935 }
1936 }
1937
1938 static void
1939 ntq_emit_impl(struct vc4_compile *c, nir_function_impl *impl)
1940 {
1941 ntq_setup_registers(c, &impl->registers);
1942 ntq_emit_cf_list(c, &impl->body);
1943 }
1944
1945 static void
1946 nir_to_qir(struct vc4_compile *c)
1947 {
1948 ntq_setup_inputs(c);
1949 ntq_setup_outputs(c);
1950 ntq_setup_uniforms(c);
1951 ntq_setup_registers(c, &c->s->registers);
1952
1953 /* Find the main function and emit the body. */
1954 nir_foreach_overload(c->s, overload) {
1955 assert(strcmp(overload->function->name, "main") == 0);
1956 assert(overload->impl);
1957 ntq_emit_impl(c, overload->impl);
1958 }
1959 }
1960
1961 static const nir_shader_compiler_options nir_options = {
1962 .lower_ffma = true,
1963 .lower_flrp = true,
1964 .lower_fpow = true,
1965 .lower_fsat = true,
1966 .lower_fsqrt = true,
1967 .lower_negate = true,
1968 };
1969
1970 static bool
1971 count_nir_instrs_in_block(nir_block *block, void *state)
1972 {
1973 int *count = (int *) state;
1974 nir_foreach_instr(block, instr) {
1975 *count = *count + 1;
1976 }
1977 return true;
1978 }
1979
1980 static int
1981 count_nir_instrs(nir_shader *nir)
1982 {
1983 int count = 0;
1984 nir_foreach_overload(nir, overload) {
1985 if (!overload->impl)
1986 continue;
1987 nir_foreach_block(overload->impl, count_nir_instrs_in_block, &count);
1988 }
1989 return count;
1990 }
1991
1992 static struct vc4_compile *
1993 vc4_shader_ntq(struct vc4_context *vc4, enum qstage stage,
1994 struct vc4_key *key)
1995 {
1996 struct vc4_compile *c = qir_compile_init();
1997
1998 c->stage = stage;
1999 c->shader_state = &key->shader_state->base;
2000 c->program_id = key->shader_state->program_id;
2001 c->variant_id = key->shader_state->compiled_variant_count++;
2002
2003 c->key = key;
2004 switch (stage) {
2005 case QSTAGE_FRAG:
2006 c->fs_key = (struct vc4_fs_key *)key;
2007 if (c->fs_key->is_points) {
2008 c->point_x = emit_fragment_varying(c, ~0, ~0, 0);
2009 c->point_y = emit_fragment_varying(c, ~0, ~0, 0);
2010 } else if (c->fs_key->is_lines) {
2011 c->line_x = emit_fragment_varying(c, ~0, ~0, 0);
2012 }
2013 break;
2014 case QSTAGE_VERT:
2015 c->vs_key = (struct vc4_vs_key *)key;
2016 break;
2017 case QSTAGE_COORD:
2018 c->vs_key = (struct vc4_vs_key *)key;
2019 break;
2020 }
2021
2022 const struct tgsi_token *tokens = key->shader_state->base.tokens;
2023 if (c->fs_key && c->fs_key->light_twoside) {
2024 if (!key->shader_state->twoside_tokens) {
2025 const struct tgsi_lowering_config lowering_config = {
2026 .color_two_side = true,
2027 };
2028 struct tgsi_shader_info info;
2029 key->shader_state->twoside_tokens =
2030 tgsi_transform_lowering(&lowering_config,
2031 key->shader_state->base.tokens,
2032 &info);
2033
2034 /* If no transformation occurred, then NULL is
2035 * returned and we just use our original tokens.
2036 */
2037 if (!key->shader_state->twoside_tokens) {
2038 key->shader_state->twoside_tokens =
2039 key->shader_state->base.tokens;
2040 }
2041 }
2042 tokens = key->shader_state->twoside_tokens;
2043 }
2044
2045 if (vc4_debug & VC4_DEBUG_TGSI) {
2046 fprintf(stderr, "%s prog %d/%d TGSI:\n",
2047 qir_get_stage_name(c->stage),
2048 c->program_id, c->variant_id);
2049 tgsi_dump(tokens, 0);
2050 }
2051
2052 c->s = tgsi_to_nir(tokens, &nir_options);
2053 nir_opt_global_to_local(c->s);
2054 nir_convert_to_ssa(c->s);
2055 vc4_nir_lower_io(c);
2056 nir_lower_idiv(c->s);
2057 nir_lower_load_const_to_scalar(c->s);
2058
2059 vc4_optimize_nir(c->s);
2060
2061 nir_remove_dead_variables(c->s);
2062
2063 nir_convert_from_ssa(c->s, true);
2064
2065 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2066 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d NIR instructions\n",
2067 qir_get_stage_name(c->stage),
2068 c->program_id, c->variant_id,
2069 count_nir_instrs(c->s));
2070 }
2071
2072 if (vc4_debug & VC4_DEBUG_NIR) {
2073 fprintf(stderr, "%s prog %d/%d NIR:\n",
2074 qir_get_stage_name(c->stage),
2075 c->program_id, c->variant_id);
2076 nir_print_shader(c->s, stderr);
2077 }
2078
2079 nir_to_qir(c);
2080
2081 switch (stage) {
2082 case QSTAGE_FRAG:
2083 emit_frag_end(c);
2084 break;
2085 case QSTAGE_VERT:
2086 emit_vert_end(c,
2087 vc4->prog.fs->input_semantics,
2088 vc4->prog.fs->num_inputs);
2089 break;
2090 case QSTAGE_COORD:
2091 emit_coord_end(c);
2092 break;
2093 }
2094
2095 if (vc4_debug & VC4_DEBUG_QIR) {
2096 fprintf(stderr, "%s prog %d/%d pre-opt QIR:\n",
2097 qir_get_stage_name(c->stage),
2098 c->program_id, c->variant_id);
2099 qir_dump(c);
2100 }
2101
2102 qir_optimize(c);
2103 qir_lower_uniforms(c);
2104
2105 if (vc4_debug & VC4_DEBUG_QIR) {
2106 fprintf(stderr, "%s prog %d/%d QIR:\n",
2107 qir_get_stage_name(c->stage),
2108 c->program_id, c->variant_id);
2109 qir_dump(c);
2110 }
2111 qir_reorder_uniforms(c);
2112 vc4_generate_code(vc4, c);
2113
2114 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2115 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d instructions\n",
2116 qir_get_stage_name(c->stage),
2117 c->program_id, c->variant_id,
2118 c->qpu_inst_count);
2119 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d uniforms\n",
2120 qir_get_stage_name(c->stage),
2121 c->program_id, c->variant_id,
2122 c->num_uniforms);
2123 }
2124
2125 ralloc_free(c->s);
2126
2127 return c;
2128 }
2129
2130 static void *
2131 vc4_shader_state_create(struct pipe_context *pctx,
2132 const struct pipe_shader_state *cso)
2133 {
2134 struct vc4_context *vc4 = vc4_context(pctx);
2135 struct vc4_uncompiled_shader *so = CALLOC_STRUCT(vc4_uncompiled_shader);
2136 if (!so)
2137 return NULL;
2138
2139 so->base.tokens = tgsi_dup_tokens(cso->tokens);
2140 so->program_id = vc4->next_uncompiled_program_id++;
2141
2142 return so;
2143 }
2144
2145 static void
2146 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
2147 struct vc4_compile *c)
2148 {
2149 int count = c->num_uniforms;
2150 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
2151
2152 uinfo->count = count;
2153 uinfo->data = ralloc_array(shader, uint32_t, count);
2154 memcpy(uinfo->data, c->uniform_data,
2155 count * sizeof(*uinfo->data));
2156 uinfo->contents = ralloc_array(shader, enum quniform_contents, count);
2157 memcpy(uinfo->contents, c->uniform_contents,
2158 count * sizeof(*uinfo->contents));
2159 uinfo->num_texture_samples = c->num_texture_samples;
2160
2161 vc4_set_shader_uniform_dirty_flags(shader);
2162 }
2163
2164 static struct vc4_compiled_shader *
2165 vc4_get_compiled_shader(struct vc4_context *vc4, enum qstage stage,
2166 struct vc4_key *key)
2167 {
2168 struct hash_table *ht;
2169 uint32_t key_size;
2170 if (stage == QSTAGE_FRAG) {
2171 ht = vc4->fs_cache;
2172 key_size = sizeof(struct vc4_fs_key);
2173 } else {
2174 ht = vc4->vs_cache;
2175 key_size = sizeof(struct vc4_vs_key);
2176 }
2177
2178 struct vc4_compiled_shader *shader;
2179 struct hash_entry *entry = _mesa_hash_table_search(ht, key);
2180 if (entry)
2181 return entry->data;
2182
2183 struct vc4_compile *c = vc4_shader_ntq(vc4, stage, key);
2184 shader = rzalloc(NULL, struct vc4_compiled_shader);
2185
2186 shader->program_id = vc4->next_compiled_program_id++;
2187 if (stage == QSTAGE_FRAG) {
2188 bool input_live[c->num_input_semantics];
2189
2190 memset(input_live, 0, sizeof(input_live));
2191 list_for_each_entry(struct qinst, inst, &c->instructions, link) {
2192 for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) {
2193 if (inst->src[i].file == QFILE_VARY)
2194 input_live[inst->src[i].index] = true;
2195 }
2196 }
2197
2198 shader->input_semantics = ralloc_array(shader,
2199 struct vc4_varying_semantic,
2200 c->num_input_semantics);
2201
2202 for (int i = 0; i < c->num_input_semantics; i++) {
2203 struct vc4_varying_semantic *sem = &c->input_semantics[i];
2204
2205 if (!input_live[i])
2206 continue;
2207
2208 /* Skip non-VS-output inputs. */
2209 if (sem->semantic == (uint8_t)~0)
2210 continue;
2211
2212 if (sem->semantic == TGSI_SEMANTIC_COLOR ||
2213 sem->semantic == TGSI_SEMANTIC_BCOLOR) {
2214 shader->color_inputs |= (1 << shader->num_inputs);
2215 }
2216
2217 shader->input_semantics[shader->num_inputs] = *sem;
2218 shader->num_inputs++;
2219 }
2220 } else {
2221 shader->num_inputs = c->num_inputs;
2222
2223 shader->vattr_offsets[0] = 0;
2224 for (int i = 0; i < 8; i++) {
2225 shader->vattr_offsets[i + 1] =
2226 shader->vattr_offsets[i] + c->vattr_sizes[i];
2227
2228 if (c->vattr_sizes[i])
2229 shader->vattrs_live |= (1 << i);
2230 }
2231 }
2232
2233 copy_uniform_state_to_shader(shader, c);
2234 shader->bo = vc4_bo_alloc_shader(vc4->screen, c->qpu_insts,
2235 c->qpu_inst_count * sizeof(uint64_t));
2236
2237 /* Copy the compiler UBO range state to the compiled shader, dropping
2238 * out arrays that were never referenced by an indirect load.
2239 *
2240 * (Note that QIR dead code elimination of an array access still
2241 * leaves that array alive, though)
2242 */
2243 if (c->num_ubo_ranges) {
2244 shader->num_ubo_ranges = c->num_ubo_ranges;
2245 shader->ubo_ranges = ralloc_array(shader, struct vc4_ubo_range,
2246 c->num_ubo_ranges);
2247 uint32_t j = 0;
2248 for (int i = 0; i < c->num_uniform_ranges; i++) {
2249 struct vc4_compiler_ubo_range *range =
2250 &c->ubo_ranges[i];
2251 if (!range->used)
2252 continue;
2253
2254 shader->ubo_ranges[j].dst_offset = range->dst_offset;
2255 shader->ubo_ranges[j].src_offset = range->src_offset;
2256 shader->ubo_ranges[j].size = range->size;
2257 shader->ubo_size += c->ubo_ranges[i].size;
2258 j++;
2259 }
2260 }
2261 if (shader->ubo_size) {
2262 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2263 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d UBO uniforms\n",
2264 qir_get_stage_name(c->stage),
2265 c->program_id, c->variant_id,
2266 shader->ubo_size / 4);
2267 }
2268 }
2269
2270 qir_compile_destroy(c);
2271
2272 struct vc4_key *dup_key;
2273 dup_key = ralloc_size(shader, key_size);
2274 memcpy(dup_key, key, key_size);
2275 _mesa_hash_table_insert(ht, dup_key, shader);
2276
2277 return shader;
2278 }
2279
2280 static void
2281 vc4_setup_shared_key(struct vc4_context *vc4, struct vc4_key *key,
2282 struct vc4_texture_stateobj *texstate)
2283 {
2284 for (int i = 0; i < texstate->num_textures; i++) {
2285 struct pipe_sampler_view *sampler = texstate->textures[i];
2286 struct pipe_sampler_state *sampler_state =
2287 texstate->samplers[i];
2288
2289 if (sampler) {
2290 key->tex[i].format = sampler->format;
2291 key->tex[i].swizzle[0] = sampler->swizzle_r;
2292 key->tex[i].swizzle[1] = sampler->swizzle_g;
2293 key->tex[i].swizzle[2] = sampler->swizzle_b;
2294 key->tex[i].swizzle[3] = sampler->swizzle_a;
2295 key->tex[i].compare_mode = sampler_state->compare_mode;
2296 key->tex[i].compare_func = sampler_state->compare_func;
2297 key->tex[i].wrap_s = sampler_state->wrap_s;
2298 key->tex[i].wrap_t = sampler_state->wrap_t;
2299 }
2300 }
2301
2302 key->ucp_enables = vc4->rasterizer->base.clip_plane_enable;
2303 }
2304
2305 static void
2306 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
2307 {
2308 struct vc4_fs_key local_key;
2309 struct vc4_fs_key *key = &local_key;
2310
2311 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2312 VC4_DIRTY_BLEND |
2313 VC4_DIRTY_FRAMEBUFFER |
2314 VC4_DIRTY_ZSA |
2315 VC4_DIRTY_RASTERIZER |
2316 VC4_DIRTY_FRAGTEX |
2317 VC4_DIRTY_TEXSTATE |
2318 VC4_DIRTY_UNCOMPILED_FS))) {
2319 return;
2320 }
2321
2322 memset(key, 0, sizeof(*key));
2323 vc4_setup_shared_key(vc4, &key->base, &vc4->fragtex);
2324 key->base.shader_state = vc4->prog.bind_fs;
2325 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
2326 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
2327 prim_mode <= PIPE_PRIM_LINE_STRIP);
2328 key->blend = vc4->blend->rt[0];
2329 if (vc4->blend->logicop_enable) {
2330 key->logicop_func = vc4->blend->logicop_func;
2331 } else {
2332 key->logicop_func = PIPE_LOGICOP_COPY;
2333 }
2334 if (vc4->framebuffer.cbufs[0])
2335 key->color_format = vc4->framebuffer.cbufs[0]->format;
2336
2337 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
2338 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
2339 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
2340 key->depth_enabled = (vc4->zsa->base.depth.enabled ||
2341 key->stencil_enabled);
2342 if (vc4->zsa->base.alpha.enabled) {
2343 key->alpha_test = true;
2344 key->alpha_test_func = vc4->zsa->base.alpha.func;
2345 }
2346
2347 if (key->is_points) {
2348 key->point_sprite_mask =
2349 vc4->rasterizer->base.sprite_coord_enable;
2350 key->point_coord_upper_left =
2351 (vc4->rasterizer->base.sprite_coord_mode ==
2352 PIPE_SPRITE_COORD_UPPER_LEFT);
2353 }
2354
2355 key->light_twoside = vc4->rasterizer->base.light_twoside;
2356
2357 struct vc4_compiled_shader *old_fs = vc4->prog.fs;
2358 vc4->prog.fs = vc4_get_compiled_shader(vc4, QSTAGE_FRAG, &key->base);
2359 if (vc4->prog.fs == old_fs)
2360 return;
2361
2362 vc4->dirty |= VC4_DIRTY_COMPILED_FS;
2363 if (vc4->rasterizer->base.flatshade &&
2364 old_fs && vc4->prog.fs->color_inputs != old_fs->color_inputs) {
2365 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
2366 }
2367 }
2368
2369 static void
2370 vc4_update_compiled_vs(struct vc4_context *vc4, uint8_t prim_mode)
2371 {
2372 struct vc4_vs_key local_key;
2373 struct vc4_vs_key *key = &local_key;
2374
2375 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2376 VC4_DIRTY_RASTERIZER |
2377 VC4_DIRTY_VERTTEX |
2378 VC4_DIRTY_TEXSTATE |
2379 VC4_DIRTY_VTXSTATE |
2380 VC4_DIRTY_UNCOMPILED_VS |
2381 VC4_DIRTY_COMPILED_FS))) {
2382 return;
2383 }
2384
2385 memset(key, 0, sizeof(*key));
2386 vc4_setup_shared_key(vc4, &key->base, &vc4->verttex);
2387 key->base.shader_state = vc4->prog.bind_vs;
2388 key->compiled_fs_id = vc4->prog.fs->program_id;
2389
2390 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
2391 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
2392
2393 key->per_vertex_point_size =
2394 (prim_mode == PIPE_PRIM_POINTS &&
2395 vc4->rasterizer->base.point_size_per_vertex);
2396
2397 struct vc4_compiled_shader *vs =
2398 vc4_get_compiled_shader(vc4, QSTAGE_VERT, &key->base);
2399 if (vs != vc4->prog.vs) {
2400 vc4->prog.vs = vs;
2401 vc4->dirty |= VC4_DIRTY_COMPILED_VS;
2402 }
2403
2404 key->is_coord = true;
2405 struct vc4_compiled_shader *cs =
2406 vc4_get_compiled_shader(vc4, QSTAGE_COORD, &key->base);
2407 if (cs != vc4->prog.cs) {
2408 vc4->prog.cs = cs;
2409 vc4->dirty |= VC4_DIRTY_COMPILED_CS;
2410 }
2411 }
2412
2413 void
2414 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
2415 {
2416 vc4_update_compiled_fs(vc4, prim_mode);
2417 vc4_update_compiled_vs(vc4, prim_mode);
2418 }
2419
2420 static uint32_t
2421 fs_cache_hash(const void *key)
2422 {
2423 return _mesa_hash_data(key, sizeof(struct vc4_fs_key));
2424 }
2425
2426 static uint32_t
2427 vs_cache_hash(const void *key)
2428 {
2429 return _mesa_hash_data(key, sizeof(struct vc4_vs_key));
2430 }
2431
2432 static bool
2433 fs_cache_compare(const void *key1, const void *key2)
2434 {
2435 return memcmp(key1, key2, sizeof(struct vc4_fs_key)) == 0;
2436 }
2437
2438 static bool
2439 vs_cache_compare(const void *key1, const void *key2)
2440 {
2441 return memcmp(key1, key2, sizeof(struct vc4_vs_key)) == 0;
2442 }
2443
2444 static void
2445 delete_from_cache_if_matches(struct hash_table *ht,
2446 struct hash_entry *entry,
2447 struct vc4_uncompiled_shader *so)
2448 {
2449 const struct vc4_key *key = entry->key;
2450
2451 if (key->shader_state == so) {
2452 struct vc4_compiled_shader *shader = entry->data;
2453 _mesa_hash_table_remove(ht, entry);
2454 vc4_bo_unreference(&shader->bo);
2455 ralloc_free(shader);
2456 }
2457 }
2458
2459 static void
2460 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
2461 {
2462 struct vc4_context *vc4 = vc4_context(pctx);
2463 struct vc4_uncompiled_shader *so = hwcso;
2464
2465 struct hash_entry *entry;
2466 hash_table_foreach(vc4->fs_cache, entry)
2467 delete_from_cache_if_matches(vc4->fs_cache, entry, so);
2468 hash_table_foreach(vc4->vs_cache, entry)
2469 delete_from_cache_if_matches(vc4->vs_cache, entry, so);
2470
2471 if (so->twoside_tokens != so->base.tokens)
2472 free((void *)so->twoside_tokens);
2473 free((void *)so->base.tokens);
2474 free(so);
2475 }
2476
2477 static void
2478 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
2479 {
2480 struct vc4_context *vc4 = vc4_context(pctx);
2481 vc4->prog.bind_fs = hwcso;
2482 vc4->dirty |= VC4_DIRTY_UNCOMPILED_FS;
2483 }
2484
2485 static void
2486 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
2487 {
2488 struct vc4_context *vc4 = vc4_context(pctx);
2489 vc4->prog.bind_vs = hwcso;
2490 vc4->dirty |= VC4_DIRTY_UNCOMPILED_VS;
2491 }
2492
2493 void
2494 vc4_program_init(struct pipe_context *pctx)
2495 {
2496 struct vc4_context *vc4 = vc4_context(pctx);
2497
2498 pctx->create_vs_state = vc4_shader_state_create;
2499 pctx->delete_vs_state = vc4_shader_state_delete;
2500
2501 pctx->create_fs_state = vc4_shader_state_create;
2502 pctx->delete_fs_state = vc4_shader_state_delete;
2503
2504 pctx->bind_fs_state = vc4_fp_state_bind;
2505 pctx->bind_vs_state = vc4_vp_state_bind;
2506
2507 vc4->fs_cache = _mesa_hash_table_create(pctx, fs_cache_hash,
2508 fs_cache_compare);
2509 vc4->vs_cache = _mesa_hash_table_create(pctx, vs_cache_hash,
2510 vs_cache_compare);
2511 }
2512
2513 void
2514 vc4_program_fini(struct pipe_context *pctx)
2515 {
2516 struct vc4_context *vc4 = vc4_context(pctx);
2517
2518 struct hash_entry *entry;
2519 hash_table_foreach(vc4->fs_cache, entry) {
2520 struct vc4_compiled_shader *shader = entry->data;
2521 vc4_bo_unreference(&shader->bo);
2522 ralloc_free(shader);
2523 _mesa_hash_table_remove(vc4->fs_cache, entry);
2524 }
2525
2526 hash_table_foreach(vc4->vs_cache, entry) {
2527 struct vc4_compiled_shader *shader = entry->data;
2528 vc4_bo_unreference(&shader->bo);
2529 ralloc_free(shader);
2530 _mesa_hash_table_remove(vc4->vs_cache, entry);
2531 }
2532 }