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vc4: Stop complaining about unknown texture channel types.
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "pipe/p_state.h"
27 #include "util/u_format.h"
28 #include "util/u_hash_table.h"
29 #include "util/u_hash.h"
30 #include "util/u_memory.h"
31 #include "tgsi/tgsi_parse.h"
32 #include "tgsi/tgsi_dump.h"
33
34 #include "vc4_context.h"
35 #include "vc4_qpu.h"
36 #include "vc4_qir.h"
37 #ifdef USE_VC4_SIMULATOR
38 #include "simpenrose/simpenrose.h"
39 #endif
40
41 struct tgsi_to_qir {
42 struct tgsi_parse_context parser;
43 struct qcompile *c;
44 struct qreg *temps;
45 struct qreg *inputs;
46 struct qreg *outputs;
47 struct qreg *uniforms;
48 struct qreg *consts;
49 struct qreg line_x, point_x, point_y;
50
51 uint32_t num_consts;
52
53 struct pipe_shader_state *shader_state;
54 struct vc4_key *key;
55 struct vc4_fs_key *fs_key;
56 struct vc4_vs_key *vs_key;
57
58 uint32_t *uniform_data;
59 enum quniform_contents *uniform_contents;
60 uint32_t num_uniforms;
61 uint32_t num_outputs;
62 uint32_t num_texture_samples;
63 };
64
65 struct vc4_key {
66 struct pipe_shader_state *shader_state;
67 enum pipe_format tex_format[VC4_MAX_TEXTURE_SAMPLERS];
68 };
69
70 struct vc4_fs_key {
71 struct vc4_key base;
72 enum pipe_format color_format;
73 bool depth_enabled;
74 bool is_points;
75 bool is_lines;
76
77 struct pipe_rt_blend_state blend;
78 };
79
80 struct vc4_vs_key {
81 struct vc4_key base;
82 enum pipe_format attr_formats[8];
83 };
84
85 static struct qreg
86 add_uniform(struct tgsi_to_qir *trans,
87 enum quniform_contents contents,
88 uint32_t data)
89 {
90 uint32_t uniform = trans->num_uniforms++;
91 struct qreg u = { QFILE_UNIF, uniform };
92
93 trans->uniform_contents[uniform] = contents;
94 trans->uniform_data[uniform] = data;
95
96 return u;
97 }
98
99 static struct qreg
100 get_temp_for_uniform(struct tgsi_to_qir *trans, enum quniform_contents contents,
101 uint32_t data)
102 {
103 struct qcompile *c = trans->c;
104
105 for (int i = 0; i < trans->num_uniforms; i++) {
106 if (trans->uniform_contents[i] == contents &&
107 trans->uniform_data[i] == data)
108 return trans->uniforms[i];
109 }
110
111 struct qreg u = add_uniform(trans, contents, data);
112 struct qreg t = qir_MOV(c, u);
113
114 trans->uniforms[u.index] = t;
115 return t;
116 }
117
118 static struct qreg
119 qir_uniform_ui(struct tgsi_to_qir *trans, uint32_t ui)
120 {
121 return get_temp_for_uniform(trans, QUNIFORM_CONSTANT, ui);
122 }
123
124 static struct qreg
125 qir_uniform_f(struct tgsi_to_qir *trans, float f)
126 {
127 return qir_uniform_ui(trans, fui(f));
128 }
129
130 static struct qreg
131 get_src(struct tgsi_to_qir *trans, struct tgsi_src_register *src, int i)
132 {
133 struct qcompile *c = trans->c;
134 struct qreg r = c->undef;
135
136 uint32_t s = i;
137 switch (i) {
138 case TGSI_SWIZZLE_X:
139 s = src->SwizzleX;
140 break;
141 case TGSI_SWIZZLE_Y:
142 s = src->SwizzleY;
143 break;
144 case TGSI_SWIZZLE_Z:
145 s = src->SwizzleZ;
146 break;
147 case TGSI_SWIZZLE_W:
148 s = src->SwizzleW;
149 break;
150 default:
151 abort();
152 }
153
154 assert(!src->Indirect);
155
156 switch (src->File) {
157 case TGSI_FILE_NULL:
158 return r;
159 case TGSI_FILE_TEMPORARY:
160 r = trans->temps[src->Index * 4 + s];
161 break;
162 case TGSI_FILE_IMMEDIATE:
163 r = trans->consts[src->Index * 4 + s];
164 break;
165 case TGSI_FILE_CONSTANT:
166 r = get_temp_for_uniform(trans, QUNIFORM_UNIFORM,
167 src->Index * 4 + s);
168 break;
169 case TGSI_FILE_INPUT:
170 r = trans->inputs[src->Index * 4 + s];
171 break;
172 case TGSI_FILE_SAMPLER:
173 case TGSI_FILE_SAMPLER_VIEW:
174 r = c->undef;
175 break;
176 default:
177 fprintf(stderr, "unknown src file %d\n", src->File);
178 abort();
179 }
180
181 if (src->Absolute)
182 r = qir_FMAXABS(c, r, r);
183
184 if (src->Negate)
185 r = qir_FSUB(c, qir_uniform_f(trans, 0), r);
186
187 return r;
188 };
189
190
191 static void
192 update_dst(struct tgsi_to_qir *trans, struct tgsi_full_instruction *tgsi_inst,
193 int i, struct qreg val)
194 {
195 struct tgsi_dst_register *tgsi_dst = &tgsi_inst->Dst[0].Register;
196
197 assert(!tgsi_dst->Indirect);
198
199 switch (tgsi_dst->File) {
200 case TGSI_FILE_TEMPORARY:
201 trans->temps[tgsi_dst->Index * 4 + i] = val;
202 break;
203 case TGSI_FILE_OUTPUT:
204 trans->outputs[tgsi_dst->Index * 4 + i] = val;
205 trans->num_outputs = MAX2(trans->num_outputs,
206 tgsi_dst->Index * 4 + i + 1);
207 break;
208 default:
209 fprintf(stderr, "unknown dst file %d\n", tgsi_dst->File);
210 abort();
211 }
212 };
213
214 static struct qreg
215 get_swizzled_channel(struct tgsi_to_qir *trans,
216 struct qreg *srcs, int swiz)
217 {
218 switch (swiz) {
219 default:
220 case UTIL_FORMAT_SWIZZLE_NONE:
221 fprintf(stderr, "warning: unknown swizzle\n");
222 /* FALLTHROUGH */
223 case UTIL_FORMAT_SWIZZLE_0:
224 return qir_uniform_f(trans, 0.0);
225 case UTIL_FORMAT_SWIZZLE_1:
226 return qir_uniform_f(trans, 1.0);
227 case UTIL_FORMAT_SWIZZLE_X:
228 case UTIL_FORMAT_SWIZZLE_Y:
229 case UTIL_FORMAT_SWIZZLE_Z:
230 case UTIL_FORMAT_SWIZZLE_W:
231 return srcs[swiz];
232 }
233 }
234
235 static struct qreg
236 tgsi_to_qir_alu(struct tgsi_to_qir *trans,
237 struct tgsi_full_instruction *tgsi_inst,
238 enum qop op, struct qreg *src, int i)
239 {
240 struct qcompile *c = trans->c;
241 struct qreg dst = qir_get_temp(c);
242 qir_emit(c, qir_inst4(op, dst,
243 src[0 * 4 + i],
244 src[1 * 4 + i],
245 src[2 * 4 + i],
246 c->undef));
247 return dst;
248 }
249
250 static struct qreg
251 tgsi_to_qir_mad(struct tgsi_to_qir *trans,
252 struct tgsi_full_instruction *tgsi_inst,
253 enum qop op, struct qreg *src, int i)
254 {
255 struct qcompile *c = trans->c;
256 return qir_FADD(c,
257 qir_FMUL(c,
258 src[0 * 4 + i],
259 src[1 * 4 + i]),
260 src[2 * 4 + i]);
261 }
262
263 static struct qreg
264 tgsi_to_qir_lit(struct tgsi_to_qir *trans,
265 struct tgsi_full_instruction *tgsi_inst,
266 enum qop op, struct qreg *src, int i)
267 {
268 struct qcompile *c = trans->c;
269 struct qreg x = src[0 * 4 + 0];
270 struct qreg y = src[0 * 4 + 1];
271 struct qreg w = src[0 * 4 + 3];
272
273 switch (i) {
274 case 0:
275 case 3:
276 return qir_uniform_f(trans, 1.0);
277 case 1:
278 return qir_FMAX(c, src[0 * 4 + 0], qir_uniform_f(trans, 0.0));
279 case 2: {
280 struct qreg zero = qir_uniform_f(trans, 0.0);
281
282 /* XXX: Clamp w to -128..128 */
283 return qir_CMP(c,
284 x,
285 zero,
286 qir_EXP2(c, qir_FMUL(c,
287 w,
288 qir_LOG2(c,
289 qir_FMAX(c,
290 y,
291 zero)))));
292 }
293 default:
294 assert(!"not reached");
295 return c->undef;
296 }
297 }
298
299 static struct qreg
300 tgsi_to_qir_lrp(struct tgsi_to_qir *trans,
301 struct tgsi_full_instruction *tgsi_inst,
302 enum qop op, struct qreg *src, int i)
303 {
304 struct qcompile *c = trans->c;
305 struct qreg src0 = src[0 * 4 + i];
306 struct qreg src1 = src[1 * 4 + i];
307 struct qreg src2 = src[2 * 4 + i];
308
309 /* LRP is:
310 * src0 * src1 + (1 - src0) * src2.
311 * -> src0 * src1 + src2 - src0 * src2
312 * -> src2 + src0 * (src1 - src2)
313 */
314 return qir_FADD(c, src2, qir_FMUL(c, src0, qir_FSUB(c, src1, src2)));
315
316 }
317
318 static void
319 tgsi_to_qir_tex(struct tgsi_to_qir *trans,
320 struct tgsi_full_instruction *tgsi_inst,
321 enum qop op, struct qreg *src)
322 {
323 struct qcompile *c = trans->c;
324
325 assert(!tgsi_inst->Instruction.Saturate);
326
327 struct qreg s = src[0 * 4 + 0];
328 struct qreg t = src[0 * 4 + 1];
329 uint32_t unit = tgsi_inst->Src[1].Register.Index;
330
331 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
332 struct qreg proj = qir_RCP(c, src[0 * 4 + 3]);
333 s = qir_FMUL(c, s, proj);
334 t = qir_FMUL(c, t, proj);
335 }
336
337 /* There is no native support for GL texture rectangle coordinates, so
338 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
339 * 1]).
340 */
341 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_RECT) {
342 s = qir_FMUL(c, s,
343 get_temp_for_uniform(trans,
344 QUNIFORM_TEXRECT_SCALE_X,
345 unit));
346 t = qir_FMUL(c, t,
347 get_temp_for_uniform(trans,
348 QUNIFORM_TEXRECT_SCALE_Y,
349 unit));
350 }
351
352 qir_TEX_T(c, t, add_uniform(trans, QUNIFORM_TEXTURE_CONFIG_P0,
353 unit));
354
355 struct qreg sampler_p1 = add_uniform(trans, QUNIFORM_TEXTURE_CONFIG_P1,
356 unit);
357 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB) {
358 qir_TEX_B(c, src[0 * 4 + 3], sampler_p1);
359 qir_TEX_S(c, s, add_uniform(trans, QUNIFORM_CONSTANT, 0));
360 } else {
361 qir_TEX_S(c, s, sampler_p1);
362 }
363
364 trans->num_texture_samples++;
365 qir_emit(c, qir_inst(QOP_TEX_RESULT, c->undef, c->undef, c->undef));
366
367 struct qreg unpacked[4];
368 for (int i = 0; i < 4; i++)
369 unpacked[i] = qir_R4_UNPACK(c, i);
370
371 for (int i = 0; i < 4; i++) {
372 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
373 continue;
374
375 enum pipe_format format = trans->key->tex_format[unit];
376 const struct util_format_description *desc =
377 util_format_description(format);
378
379 uint8_t swiz = desc->swizzle[i];
380
381 update_dst(trans, tgsi_inst, i,
382 get_swizzled_channel(trans, unpacked, swiz));
383 }
384 }
385
386 static struct qreg
387 tgsi_to_qir_pow(struct tgsi_to_qir *trans,
388 struct tgsi_full_instruction *tgsi_inst,
389 enum qop op, struct qreg *src, int i)
390 {
391 struct qcompile *c = trans->c;
392
393 /* Note that this instruction replicates its result from the x channel
394 */
395 return qir_EXP2(c, qir_FMUL(c,
396 src[1 * 4 + 0],
397 qir_LOG2(c, src[0 * 4 + 0])));
398 }
399
400 static struct qreg
401 tgsi_to_qir_trunc(struct tgsi_to_qir *trans,
402 struct tgsi_full_instruction *tgsi_inst,
403 enum qop op, struct qreg *src, int i)
404 {
405 struct qcompile *c = trans->c;
406 return qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
407 }
408
409 /**
410 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
411 * to zero).
412 */
413 static struct qreg
414 tgsi_to_qir_frc(struct tgsi_to_qir *trans,
415 struct tgsi_full_instruction *tgsi_inst,
416 enum qop op, struct qreg *src, int i)
417 {
418 struct qcompile *c = trans->c;
419 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
420 struct qreg diff = qir_FSUB(c, src[0 * 4 + i], trunc);
421 return qir_CMP(c,
422 diff,
423 qir_FADD(c, diff, qir_uniform_f(trans, 1.0)),
424 diff);
425 }
426
427 /**
428 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
429 * zero).
430 */
431 static struct qreg
432 tgsi_to_qir_flr(struct tgsi_to_qir *trans,
433 struct tgsi_full_instruction *tgsi_inst,
434 enum qop op, struct qreg *src, int i)
435 {
436 struct qcompile *c = trans->c;
437 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
438 return qir_CMP(c,
439 src[0 * 4 + i],
440 qir_FSUB(c, trunc, qir_uniform_f(trans, 1.0)),
441 trunc);
442 }
443
444 static struct qreg
445 tgsi_to_qir_dp(struct tgsi_to_qir *trans,
446 struct tgsi_full_instruction *tgsi_inst,
447 int num, struct qreg *src, int i)
448 {
449 struct qcompile *c = trans->c;
450
451 struct qreg sum = qir_FMUL(c, src[0 * 4 + 0], src[1 * 4 + 0]);
452 for (int j = 1; j < num; j++) {
453 sum = qir_FADD(c, sum, qir_FMUL(c,
454 src[0 * 4 + j],
455 src[1 * 4 + j]));
456 }
457 return sum;
458 }
459
460 static struct qreg
461 tgsi_to_qir_dp2(struct tgsi_to_qir *trans,
462 struct tgsi_full_instruction *tgsi_inst,
463 enum qop op, struct qreg *src, int i)
464 {
465 return tgsi_to_qir_dp(trans, tgsi_inst, 2, src, i);
466 }
467
468 static struct qreg
469 tgsi_to_qir_dp3(struct tgsi_to_qir *trans,
470 struct tgsi_full_instruction *tgsi_inst,
471 enum qop op, struct qreg *src, int i)
472 {
473 return tgsi_to_qir_dp(trans, tgsi_inst, 3, src, i);
474 }
475
476 static struct qreg
477 tgsi_to_qir_dp4(struct tgsi_to_qir *trans,
478 struct tgsi_full_instruction *tgsi_inst,
479 enum qop op, struct qreg *src, int i)
480 {
481 return tgsi_to_qir_dp(trans, tgsi_inst, 4, src, i);
482 }
483
484 static struct qreg
485 tgsi_to_qir_abs(struct tgsi_to_qir *trans,
486 struct tgsi_full_instruction *tgsi_inst,
487 enum qop op, struct qreg *src, int i)
488 {
489 struct qcompile *c = trans->c;
490 struct qreg arg = src[0 * 4 + i];
491 return qir_FMAXABS(c, arg, arg);
492 }
493
494 /* Note that this instruction replicates its result from the x channel */
495 static struct qreg
496 tgsi_to_qir_sin(struct tgsi_to_qir *trans,
497 struct tgsi_full_instruction *tgsi_inst,
498 enum qop op, struct qreg *src, int i)
499 {
500 struct qcompile *c = trans->c;
501 float coeff[] = {
502 2.0 * M_PI,
503 -pow(2.0 * M_PI, 3) / (3 * 2 * 1),
504 pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
505 -pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
506 };
507
508 struct qreg scaled_x =
509 qir_FMUL(c,
510 src[0 * 4 + 0],
511 qir_uniform_f(trans, 1.0f / (M_PI * 2.0f)));
512
513
514 struct qreg x = tgsi_to_qir_frc(trans, NULL, 0, &scaled_x, 0);
515 struct qreg x2 = qir_FMUL(c, x, x);
516 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(trans, coeff[0]));
517 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
518 x = qir_FMUL(c, x, x2);
519 sum = qir_FADD(c,
520 sum,
521 qir_FMUL(c,
522 x,
523 qir_uniform_f(trans, coeff[i])));
524 }
525 return sum;
526 }
527
528 /* Note that this instruction replicates its result from the x channel */
529 static struct qreg
530 tgsi_to_qir_cos(struct tgsi_to_qir *trans,
531 struct tgsi_full_instruction *tgsi_inst,
532 enum qop op, struct qreg *src, int i)
533 {
534 struct qcompile *c = trans->c;
535 float coeff[] = {
536 1.0f,
537 -pow(2.0 * M_PI, 2) / (2 * 1),
538 pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
539 -pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
540 };
541
542 struct qreg scaled_x =
543 qir_FMUL(c, src[0 * 4 + 0],
544 qir_uniform_f(trans, 1.0f / (M_PI * 2.0f)));
545 struct qreg x_frac = tgsi_to_qir_frc(trans, NULL, 0, &scaled_x, 0);
546
547 struct qreg sum = qir_uniform_f(trans, coeff[0]);
548 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
549 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
550 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
551 if (i != 1)
552 x = qir_FMUL(c, x, x2);
553
554 struct qreg mul = qir_FMUL(c,
555 x,
556 qir_uniform_f(trans, coeff[i]));
557 if (i == 0)
558 sum = mul;
559 else
560 sum = qir_FADD(c, sum, mul);
561 }
562 return sum;
563 }
564
565 static void
566 emit_vertex_input(struct tgsi_to_qir *trans, int attr)
567 {
568 enum pipe_format format = trans->vs_key->attr_formats[attr];
569 struct qcompile *c = trans->c;
570 struct qreg vpm_reads[4];
571
572 /* Right now, we're setting the VPM offsets to be 16 bytes wide every
573 * time, so we always read 4 32-bit VPM entries.
574 */
575 for (int i = 0; i < 4; i++) {
576 vpm_reads[i] = qir_get_temp(c);
577 qir_emit(c, qir_inst(QOP_VPM_READ,
578 vpm_reads[i],
579 c->undef,
580 c->undef));
581 c->num_inputs++;
582 }
583
584 bool format_warned = false;
585 const struct util_format_description *desc =
586 util_format_description(format);
587
588 for (int i = 0; i < 4; i++) {
589 uint8_t swiz = desc->swizzle[i];
590
591 if (swiz <= UTIL_FORMAT_SWIZZLE_W &&
592 !format_warned &&
593 (desc->channel[swiz].type != UTIL_FORMAT_TYPE_FLOAT ||
594 desc->channel[swiz].size != 32)) {
595 fprintf(stderr,
596 "vtx element %d unsupported type: %s\n",
597 attr, util_format_name(format));
598 format_warned = true;
599 }
600
601 trans->inputs[attr * 4 + i] =
602 get_swizzled_channel(trans, vpm_reads, swiz);
603 }
604 }
605
606 static void
607 emit_fragcoord_input(struct tgsi_to_qir *trans, int attr)
608 {
609 struct qcompile *c = trans->c;
610
611 trans->inputs[attr * 4 + 0] = qir_FRAG_X(c);
612 trans->inputs[attr * 4 + 1] = qir_FRAG_Y(c);
613 trans->inputs[attr * 4 + 2] =
614 qir_FMUL(c,
615 qir_FRAG_Z(c),
616 qir_uniform_f(trans, 1.0 / 0xffffff));
617 trans->inputs[attr * 4 + 3] = qir_FRAG_RCP_W(c);
618 }
619
620 static struct qreg
621 emit_fragment_varying(struct tgsi_to_qir *trans, int index)
622 {
623 struct qcompile *c = trans->c;
624
625 struct qreg vary = {
626 QFILE_VARY,
627 index
628 };
629
630 /* XXX: multiply by W */
631 return qir_VARY_ADD_C(c, qir_MOV(c, vary));
632 }
633
634 static void
635 emit_fragment_input(struct tgsi_to_qir *trans, int attr)
636 {
637 struct qcompile *c = trans->c;
638
639 for (int i = 0; i < 4; i++) {
640 trans->inputs[attr * 4 + i] =
641 emit_fragment_varying(trans, attr * 4 + i);
642 c->num_inputs++;
643 }
644 }
645
646 static void
647 emit_tgsi_declaration(struct tgsi_to_qir *trans,
648 struct tgsi_full_declaration *decl)
649 {
650 struct qcompile *c = trans->c;
651
652 switch (decl->Declaration.File) {
653 case TGSI_FILE_INPUT:
654 for (int i = decl->Range.First;
655 i <= decl->Range.Last;
656 i++) {
657 if (c->stage == QSTAGE_FRAG) {
658 if (decl->Semantic.Name ==
659 TGSI_SEMANTIC_POSITION) {
660 emit_fragcoord_input(trans, i);
661 } else {
662 emit_fragment_input(trans, i);
663 }
664 } else {
665 emit_vertex_input(trans, i);
666 }
667 }
668 break;
669 }
670 }
671
672 static void
673 emit_tgsi_instruction(struct tgsi_to_qir *trans,
674 struct tgsi_full_instruction *tgsi_inst)
675 {
676 struct qcompile *c = trans->c;
677 struct {
678 enum qop op;
679 struct qreg (*func)(struct tgsi_to_qir *trans,
680 struct tgsi_full_instruction *tgsi_inst,
681 enum qop op,
682 struct qreg *src, int i);
683 } op_trans[] = {
684 [TGSI_OPCODE_MOV] = { QOP_MOV, tgsi_to_qir_alu },
685 [TGSI_OPCODE_ABS] = { 0, tgsi_to_qir_abs },
686 [TGSI_OPCODE_MUL] = { QOP_FMUL, tgsi_to_qir_alu },
687 [TGSI_OPCODE_ADD] = { QOP_FADD, tgsi_to_qir_alu },
688 [TGSI_OPCODE_SUB] = { QOP_FSUB, tgsi_to_qir_alu },
689 [TGSI_OPCODE_MIN] = { QOP_FMIN, tgsi_to_qir_alu },
690 [TGSI_OPCODE_MAX] = { QOP_FMAX, tgsi_to_qir_alu },
691 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_alu },
692 [TGSI_OPCODE_SEQ] = { QOP_SEQ, tgsi_to_qir_alu },
693 [TGSI_OPCODE_SNE] = { QOP_SNE, tgsi_to_qir_alu },
694 [TGSI_OPCODE_SGE] = { QOP_SGE, tgsi_to_qir_alu },
695 [TGSI_OPCODE_SLT] = { QOP_SLT, tgsi_to_qir_alu },
696 [TGSI_OPCODE_CMP] = { QOP_CMP, tgsi_to_qir_alu },
697 [TGSI_OPCODE_MAD] = { 0, tgsi_to_qir_mad },
698 [TGSI_OPCODE_DP2] = { 0, tgsi_to_qir_dp2 },
699 [TGSI_OPCODE_DP3] = { 0, tgsi_to_qir_dp3 },
700 [TGSI_OPCODE_DP4] = { 0, tgsi_to_qir_dp4 },
701 [TGSI_OPCODE_RCP] = { QOP_RCP, tgsi_to_qir_alu },
702 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_alu },
703 [TGSI_OPCODE_EX2] = { QOP_EXP2, tgsi_to_qir_alu },
704 [TGSI_OPCODE_LG2] = { QOP_LOG2, tgsi_to_qir_alu },
705 [TGSI_OPCODE_LIT] = { 0, tgsi_to_qir_lit },
706 [TGSI_OPCODE_LRP] = { 0, tgsi_to_qir_lrp },
707 [TGSI_OPCODE_POW] = { 0, tgsi_to_qir_pow },
708 [TGSI_OPCODE_TRUNC] = { 0, tgsi_to_qir_trunc },
709 [TGSI_OPCODE_FRC] = { 0, tgsi_to_qir_frc },
710 [TGSI_OPCODE_FLR] = { 0, tgsi_to_qir_flr },
711 [TGSI_OPCODE_SIN] = { 0, tgsi_to_qir_sin },
712 [TGSI_OPCODE_COS] = { 0, tgsi_to_qir_cos },
713 };
714 static int asdf = 0;
715 uint32_t tgsi_op = tgsi_inst->Instruction.Opcode;
716
717 if (tgsi_op == TGSI_OPCODE_END)
718 return;
719
720 struct qreg src_regs[12];
721 for (int s = 0; s < 3; s++) {
722 for (int i = 0; i < 4; i++) {
723 src_regs[4 * s + i] =
724 get_src(trans, &tgsi_inst->Src[s].Register, i);
725 }
726 }
727
728 switch (tgsi_op) {
729 case TGSI_OPCODE_TEX:
730 case TGSI_OPCODE_TXP:
731 case TGSI_OPCODE_TXB:
732 tgsi_to_qir_tex(trans, tgsi_inst,
733 op_trans[tgsi_op].op, src_regs);
734 return;
735 default:
736 break;
737 }
738
739 if (tgsi_op > ARRAY_SIZE(op_trans) || !(op_trans[tgsi_op].func)) {
740 fprintf(stderr, "unknown tgsi inst: ");
741 tgsi_dump_instruction(tgsi_inst, asdf++);
742 fprintf(stderr, "\n");
743 abort();
744 }
745
746 for (int i = 0; i < 4; i++) {
747 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
748 continue;
749
750 struct qreg result;
751
752 result = op_trans[tgsi_op].func(trans, tgsi_inst,
753 op_trans[tgsi_op].op,
754 src_regs, i);
755
756 if (tgsi_inst->Instruction.Saturate) {
757 float low = (tgsi_inst->Instruction.Saturate ==
758 TGSI_SAT_MINUS_PLUS_ONE ? -1.0 : 0.0);
759 result = qir_FMAX(c,
760 qir_FMIN(c,
761 result,
762 qir_uniform_f(trans, 1.0)),
763 qir_uniform_f(trans, low));
764 }
765
766 update_dst(trans, tgsi_inst, i, result);
767 }
768 }
769
770 static void
771 parse_tgsi_immediate(struct tgsi_to_qir *trans, struct tgsi_full_immediate *imm)
772 {
773 for (int i = 0; i < 4; i++) {
774 unsigned n = trans->num_consts++;
775 trans->consts[n] = qir_uniform_ui(trans, imm->u[i].Uint);
776 }
777 }
778
779 static struct qreg
780 vc4_blend_channel(struct tgsi_to_qir *trans,
781 struct qreg *dst,
782 struct qreg *src,
783 struct qreg val,
784 unsigned factor,
785 int channel)
786 {
787 struct qcompile *c = trans->c;
788
789 switch(factor) {
790 case PIPE_BLENDFACTOR_ONE:
791 return val;
792 case PIPE_BLENDFACTOR_SRC_COLOR:
793 return qir_FMUL(c, val, src[channel]);
794 case PIPE_BLENDFACTOR_SRC_ALPHA:
795 return qir_FMUL(c, val, src[3]);
796 case PIPE_BLENDFACTOR_DST_ALPHA:
797 return qir_FMUL(c, val, dst[3]);
798 case PIPE_BLENDFACTOR_DST_COLOR:
799 return qir_FMUL(c, val, dst[channel]);
800 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
801 return qir_FMIN(c, src[3], qir_FSUB(c,
802 qir_uniform_f(trans, 1.0),
803 dst[3]));
804 case PIPE_BLENDFACTOR_CONST_COLOR:
805 return qir_FMUL(c, val,
806 get_temp_for_uniform(trans,
807 QUNIFORM_BLEND_CONST_COLOR,
808 channel));
809 case PIPE_BLENDFACTOR_CONST_ALPHA:
810 return qir_FMUL(c, val,
811 get_temp_for_uniform(trans,
812 QUNIFORM_BLEND_CONST_COLOR,
813 3));
814 case PIPE_BLENDFACTOR_ZERO:
815 return qir_uniform_f(trans, 0.0);
816 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
817 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(trans, 1.0),
818 src[channel]));
819 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
820 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(trans, 1.0),
821 src[3]));
822 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
823 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(trans, 1.0),
824 dst[3]));
825 case PIPE_BLENDFACTOR_INV_DST_COLOR:
826 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(trans, 1.0),
827 dst[channel]));
828 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
829 return qir_FMUL(c, val,
830 qir_FSUB(c, qir_uniform_f(trans, 1.0),
831 get_temp_for_uniform(trans,
832 QUNIFORM_BLEND_CONST_COLOR,
833 channel)));
834 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
835 return qir_FMUL(c, val,
836 qir_FSUB(c, qir_uniform_f(trans, 1.0),
837 get_temp_for_uniform(trans,
838 QUNIFORM_BLEND_CONST_COLOR,
839 3)));
840
841 default:
842 case PIPE_BLENDFACTOR_SRC1_COLOR:
843 case PIPE_BLENDFACTOR_SRC1_ALPHA:
844 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
845 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
846 /* Unsupported. */
847 fprintf(stderr, "Unknown blend factor %d\n", factor);
848 return val;
849 }
850 }
851
852 static struct qreg
853 vc4_blend_func(struct tgsi_to_qir *trans,
854 struct qreg src, struct qreg dst,
855 unsigned func)
856 {
857 struct qcompile *c = trans->c;
858
859 switch (func) {
860 case PIPE_BLEND_ADD:
861 return qir_FADD(c, src, dst);
862 case PIPE_BLEND_SUBTRACT:
863 return qir_FSUB(c, src, dst);
864 case PIPE_BLEND_REVERSE_SUBTRACT:
865 return qir_FSUB(c, dst, src);
866 case PIPE_BLEND_MIN:
867 return qir_FMIN(c, src, dst);
868 case PIPE_BLEND_MAX:
869 return qir_FMAX(c, src, dst);
870
871 default:
872 /* Unsupported. */
873 fprintf(stderr, "Unknown blend func %d\n", func);
874 return src;
875
876 }
877 }
878
879 /**
880 * Implements fixed function blending in shader code.
881 *
882 * VC4 doesn't have any hardware support for blending. Instead, you read the
883 * current contents of the destination from the tile buffer after having
884 * waited for the scoreboard (which is handled by vc4_qpu_emit.c), then do
885 * math using your output color and that destination value, and update the
886 * output color appropriately.
887 */
888 static void
889 vc4_blend(struct tgsi_to_qir *trans, struct qreg *result,
890 struct qreg *dst_color, struct qreg *src_color)
891 {
892 struct pipe_rt_blend_state *blend = &trans->fs_key->blend;
893
894 if (!blend->blend_enable) {
895 for (int i = 0; i < 4; i++)
896 result[i] = src_color[i];
897 return;
898 }
899
900 struct qreg src_blend[4], dst_blend[4];
901 for (int i = 0; i < 3; i++) {
902 src_blend[i] = vc4_blend_channel(trans,
903 dst_color, src_color,
904 src_color[i],
905 blend->rgb_src_factor, i);
906 dst_blend[i] = vc4_blend_channel(trans,
907 dst_color, src_color,
908 dst_color[i],
909 blend->rgb_dst_factor, i);
910 }
911 src_blend[3] = vc4_blend_channel(trans,
912 dst_color, src_color,
913 src_color[3],
914 blend->alpha_src_factor, 3);
915 dst_blend[3] = vc4_blend_channel(trans,
916 dst_color, src_color,
917 dst_color[3],
918 blend->alpha_dst_factor, 3);
919
920 for (int i = 0; i < 3; i++) {
921 result[i] = vc4_blend_func(trans,
922 src_blend[i], dst_blend[i],
923 blend->rgb_func);
924 }
925 result[3] = vc4_blend_func(trans,
926 src_blend[3], dst_blend[3],
927 blend->alpha_func);
928 }
929
930 static void
931 emit_frag_end(struct tgsi_to_qir *trans)
932 {
933 struct qcompile *c = trans->c;
934
935 struct qreg t = qir_get_temp(c);
936
937 const struct util_format_description *format_desc =
938 util_format_description(trans->fs_key->color_format);
939
940 struct qreg src_color[4] = {
941 trans->outputs[0], trans->outputs[1],
942 trans->outputs[2], trans->outputs[3],
943 };
944
945 struct qreg dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
946 if (trans->fs_key->blend.blend_enable ||
947 trans->fs_key->blend.colormask != 0xf) {
948 qir_emit(c, qir_inst(QOP_TLB_COLOR_READ, c->undef,
949 c->undef, c->undef));
950 for (int i = 0; i < 4; i++) {
951 dst_color[i] = qir_R4_UNPACK(c, i);
952
953 /* XXX: Swizzles? */
954 }
955 }
956
957 struct qreg blend_color[4];
958 vc4_blend(trans, blend_color, dst_color, src_color);
959
960 /* If the bit isn't set in the color mask, then just return the
961 * original dst color, instead.
962 */
963 for (int i = 0; i < 4; i++) {
964 if (!(trans->fs_key->blend.colormask & (1 << i))) {
965 blend_color[i] = dst_color[i];
966 }
967 }
968
969 /* Debug: Sometimes you're getting a black output and just want to see
970 * if the FS is getting executed at all. Spam magenta into the color
971 * output.
972 */
973 if (0) {
974 blend_color[0] = qir_uniform_f(trans, 1.0);
975 blend_color[1] = qir_uniform_f(trans, 0.0);
976 blend_color[2] = qir_uniform_f(trans, 1.0);
977 blend_color[3] = qir_uniform_f(trans, 0.5);
978 }
979
980 struct qreg swizzled_outputs[4];
981 for (int i = 0; i < 4; i++) {
982 swizzled_outputs[i] =
983 get_swizzled_channel(trans, blend_color,
984 format_desc->swizzle[i]);
985 }
986
987 if (trans->fs_key->depth_enabled) {
988 qir_emit(c, qir_inst(QOP_TLB_PASSTHROUGH_Z_WRITE, c->undef,
989 c->undef, c->undef));
990 }
991
992 qir_emit(c, qir_inst4(QOP_PACK_COLORS, t,
993 swizzled_outputs[0],
994 swizzled_outputs[1],
995 swizzled_outputs[2],
996 swizzled_outputs[3]));
997 qir_emit(c, qir_inst(QOP_TLB_COLOR_WRITE, c->undef,
998 t, c->undef));
999 }
1000
1001 static void
1002 emit_scaled_viewport_write(struct tgsi_to_qir *trans, struct qreg rcp_w)
1003 {
1004 struct qcompile *c = trans->c;
1005 struct qreg xyi[2];
1006
1007 for (int i = 0; i < 2; i++) {
1008 struct qreg scale =
1009 add_uniform(trans, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1010
1011 xyi[i] = qir_FTOI(c, qir_FMUL(c,
1012 qir_FMUL(c,
1013 trans->outputs[i],
1014 scale),
1015 rcp_w));
1016 }
1017
1018 qir_VPM_WRITE(c, qir_PACK_SCALED(c, xyi[0], xyi[1]));
1019 }
1020
1021 static void
1022 emit_zs_write(struct tgsi_to_qir *trans, struct qreg rcp_w)
1023 {
1024 struct qcompile *c = trans->c;
1025
1026 struct qreg zscale = add_uniform(trans, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1027 struct qreg zoffset = add_uniform(trans, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1028
1029 qir_VPM_WRITE(c, qir_FMUL(c, qir_FADD(c, qir_FMUL(c,
1030 trans->outputs[2],
1031 zscale),
1032 zoffset),
1033 rcp_w));
1034 }
1035
1036 static void
1037 emit_rcp_wc_write(struct tgsi_to_qir *trans, struct qreg rcp_w)
1038 {
1039 struct qcompile *c = trans->c;
1040
1041 qir_VPM_WRITE(c, rcp_w);
1042 }
1043
1044 static void
1045 emit_vert_end(struct tgsi_to_qir *trans)
1046 {
1047 struct qcompile *c = trans->c;
1048
1049 struct qreg rcp_w = qir_RCP(c, trans->outputs[3]);
1050
1051 emit_scaled_viewport_write(trans, rcp_w);
1052 emit_zs_write(trans, rcp_w);
1053 emit_rcp_wc_write(trans, rcp_w);
1054
1055 for (int i = 4; i < trans->num_outputs; i++) {
1056 qir_VPM_WRITE(c, trans->outputs[i]);
1057 }
1058 }
1059
1060 static void
1061 emit_coord_end(struct tgsi_to_qir *trans)
1062 {
1063 struct qcompile *c = trans->c;
1064
1065 struct qreg rcp_w = qir_RCP(c, trans->outputs[3]);
1066
1067 for (int i = 0; i < 4; i++)
1068 qir_VPM_WRITE(c, trans->outputs[i]);
1069
1070 emit_scaled_viewport_write(trans, rcp_w);
1071 emit_zs_write(trans, rcp_w);
1072 emit_rcp_wc_write(trans, rcp_w);
1073 }
1074
1075 static struct tgsi_to_qir *
1076 vc4_shader_tgsi_to_qir(struct vc4_compiled_shader *shader, enum qstage stage,
1077 struct vc4_key *key)
1078 {
1079 struct tgsi_to_qir *trans = CALLOC_STRUCT(tgsi_to_qir);
1080 struct qcompile *c;
1081 int ret;
1082
1083 c = qir_compile_init();
1084 c->stage = stage;
1085
1086 memset(trans, 0, sizeof(*trans));
1087 /* XXX sizing */
1088 trans->temps = calloc(sizeof(struct qreg), 1024);
1089 trans->inputs = calloc(sizeof(struct qreg), 8 * 4);
1090 trans->outputs = calloc(sizeof(struct qreg), 1024);
1091 trans->uniforms = calloc(sizeof(struct qreg), 1024);
1092 trans->consts = calloc(sizeof(struct qreg), 1024);
1093
1094 trans->uniform_data = calloc(sizeof(uint32_t), 1024);
1095 trans->uniform_contents = calloc(sizeof(enum quniform_contents), 1024);
1096
1097 trans->shader_state = key->shader_state;
1098 trans->c = c;
1099 ret = tgsi_parse_init(&trans->parser, trans->shader_state->tokens);
1100 assert(ret == TGSI_PARSE_OK);
1101
1102 if (vc4_debug & VC4_DEBUG_TGSI) {
1103 fprintf(stderr, "TGSI:\n");
1104 tgsi_dump(trans->shader_state->tokens, 0);
1105 }
1106
1107 trans->key = key;
1108 switch (stage) {
1109 case QSTAGE_FRAG:
1110 trans->fs_key = (struct vc4_fs_key *)key;
1111 if (trans->fs_key->is_points) {
1112 trans->point_x = emit_fragment_varying(trans, 0);
1113 trans->point_y = emit_fragment_varying(trans, 0);
1114 } else if (trans->fs_key->is_lines) {
1115 trans->line_x = emit_fragment_varying(trans, 0);
1116 }
1117 break;
1118 case QSTAGE_VERT:
1119 trans->vs_key = (struct vc4_vs_key *)key;
1120 break;
1121 case QSTAGE_COORD:
1122 trans->vs_key = (struct vc4_vs_key *)key;
1123 break;
1124 }
1125
1126 while (!tgsi_parse_end_of_tokens(&trans->parser)) {
1127 tgsi_parse_token(&trans->parser);
1128
1129 switch (trans->parser.FullToken.Token.Type) {
1130 case TGSI_TOKEN_TYPE_DECLARATION:
1131 emit_tgsi_declaration(trans,
1132 &trans->parser.FullToken.FullDeclaration);
1133 break;
1134
1135 case TGSI_TOKEN_TYPE_INSTRUCTION:
1136 emit_tgsi_instruction(trans,
1137 &trans->parser.FullToken.FullInstruction);
1138 break;
1139
1140 case TGSI_TOKEN_TYPE_IMMEDIATE:
1141 parse_tgsi_immediate(trans,
1142 &trans->parser.FullToken.FullImmediate);
1143 break;
1144 }
1145 }
1146
1147 switch (stage) {
1148 case QSTAGE_FRAG:
1149 emit_frag_end(trans);
1150 break;
1151 case QSTAGE_VERT:
1152 emit_vert_end(trans);
1153 break;
1154 case QSTAGE_COORD:
1155 emit_coord_end(trans);
1156 break;
1157 }
1158
1159 tgsi_parse_free(&trans->parser);
1160 free(trans->temps);
1161
1162 qir_optimize(c);
1163
1164 if (vc4_debug & VC4_DEBUG_QIR) {
1165 fprintf(stderr, "QIR:\n");
1166 qir_dump(c);
1167 }
1168 vc4_generate_code(c);
1169
1170 if (vc4_debug & VC4_DEBUG_SHADERDB) {
1171 fprintf(stderr, "SHADER-DB: %s: %d instructions\n",
1172 qir_get_stage_name(c->stage), c->qpu_inst_count);
1173 fprintf(stderr, "SHADER-DB: %s: %d uniforms\n",
1174 qir_get_stage_name(c->stage), trans->num_uniforms);
1175 }
1176
1177 return trans;
1178 }
1179
1180 static void *
1181 vc4_shader_state_create(struct pipe_context *pctx,
1182 const struct pipe_shader_state *cso)
1183 {
1184 struct pipe_shader_state *so = CALLOC_STRUCT(pipe_shader_state);
1185 if (!so)
1186 return NULL;
1187
1188 so->tokens = tgsi_dup_tokens(cso->tokens);
1189
1190 return so;
1191 }
1192
1193 static void
1194 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
1195 int shader_index,
1196 struct tgsi_to_qir *trans)
1197 {
1198 int count = trans->num_uniforms;
1199 struct vc4_shader_uniform_info *uinfo = &shader->uniforms[shader_index];
1200
1201 uinfo->count = count;
1202 uinfo->data = malloc(count * sizeof(*uinfo->data));
1203 memcpy(uinfo->data, trans->uniform_data,
1204 count * sizeof(*uinfo->data));
1205 uinfo->contents = malloc(count * sizeof(*uinfo->contents));
1206 memcpy(uinfo->contents, trans->uniform_contents,
1207 count * sizeof(*uinfo->contents));
1208 uinfo->num_texture_samples = trans->num_texture_samples;
1209 }
1210
1211 static void
1212 vc4_fs_compile(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1213 struct vc4_fs_key *key)
1214 {
1215 struct tgsi_to_qir *trans = vc4_shader_tgsi_to_qir(shader, QSTAGE_FRAG,
1216 &key->base);
1217 shader->num_inputs = trans->c->num_inputs;
1218 copy_uniform_state_to_shader(shader, 0, trans);
1219 shader->bo = vc4_bo_alloc_mem(vc4->screen, trans->c->qpu_insts,
1220 trans->c->qpu_inst_count * sizeof(uint64_t),
1221 "fs_code");
1222
1223 qir_compile_destroy(trans->c);
1224 free(trans);
1225 }
1226
1227 static void
1228 vc4_vs_compile(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1229 struct vc4_vs_key *key)
1230 {
1231 struct tgsi_to_qir *vs_trans = vc4_shader_tgsi_to_qir(shader,
1232 QSTAGE_VERT,
1233 &key->base);
1234 copy_uniform_state_to_shader(shader, 0, vs_trans);
1235
1236 struct tgsi_to_qir *cs_trans = vc4_shader_tgsi_to_qir(shader,
1237 QSTAGE_COORD,
1238 &key->base);
1239 copy_uniform_state_to_shader(shader, 1, cs_trans);
1240
1241 uint32_t vs_size = vs_trans->c->qpu_inst_count * sizeof(uint64_t);
1242 uint32_t cs_size = cs_trans->c->qpu_inst_count * sizeof(uint64_t);
1243 shader->coord_shader_offset = vs_size; /* XXX: alignment? */
1244 shader->bo = vc4_bo_alloc(vc4->screen,
1245 shader->coord_shader_offset + cs_size,
1246 "vs_code");
1247
1248 void *map = vc4_bo_map(shader->bo);
1249 memcpy(map, vs_trans->c->qpu_insts, vs_size);
1250 memcpy(map + shader->coord_shader_offset,
1251 cs_trans->c->qpu_insts, cs_size);
1252
1253 qir_compile_destroy(vs_trans->c);
1254 qir_compile_destroy(cs_trans->c);
1255 }
1256
1257 static void
1258 vc4_setup_shared_key(struct vc4_key *key, struct vc4_texture_stateobj *texstate)
1259 {
1260 for (int i = 0; i < texstate->num_textures; i++) {
1261 struct pipe_sampler_view *sampler = texstate->textures[i];
1262 if (sampler) {
1263 struct pipe_resource *prsc = sampler->texture;
1264 key->tex_format[i] = prsc->format;
1265 }
1266 }
1267 }
1268
1269 static void
1270 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
1271 {
1272 struct vc4_fs_key local_key;
1273 struct vc4_fs_key *key = &local_key;
1274
1275 memset(key, 0, sizeof(*key));
1276 vc4_setup_shared_key(&key->base, &vc4->fragtex);
1277 key->base.shader_state = vc4->prog.bind_fs;
1278 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
1279 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
1280 prim_mode <= PIPE_PRIM_LINE_STRIP);
1281 key->blend = vc4->blend->rt[0];
1282
1283 if (vc4->framebuffer.cbufs[0])
1284 key->color_format = vc4->framebuffer.cbufs[0]->format;
1285
1286 key->depth_enabled = vc4->zsa->base.depth.enabled;
1287
1288 vc4->prog.fs = util_hash_table_get(vc4->fs_cache, key);
1289 if (vc4->prog.fs)
1290 return;
1291
1292 key = malloc(sizeof(*key));
1293 memcpy(key, &local_key, sizeof(*key));
1294
1295 struct vc4_compiled_shader *shader = CALLOC_STRUCT(vc4_compiled_shader);
1296 vc4_fs_compile(vc4, shader, key);
1297 util_hash_table_set(vc4->fs_cache, key, shader);
1298
1299 vc4->prog.fs = shader;
1300 }
1301
1302 static void
1303 vc4_update_compiled_vs(struct vc4_context *vc4)
1304 {
1305 struct vc4_vs_key local_key;
1306 struct vc4_vs_key *key = &local_key;
1307
1308 memset(key, 0, sizeof(*key));
1309 vc4_setup_shared_key(&key->base, &vc4->verttex);
1310 key->base.shader_state = vc4->prog.bind_vs;
1311
1312 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
1313 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
1314
1315 vc4->prog.vs = util_hash_table_get(vc4->vs_cache, key);
1316 if (vc4->prog.vs)
1317 return;
1318
1319 key = malloc(sizeof(*key));
1320 memcpy(key, &local_key, sizeof(*key));
1321
1322 struct vc4_compiled_shader *shader = CALLOC_STRUCT(vc4_compiled_shader);
1323 vc4_vs_compile(vc4, shader, key);
1324 util_hash_table_set(vc4->vs_cache, key, shader);
1325
1326 vc4->prog.vs = shader;
1327 }
1328
1329 void
1330 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
1331 {
1332 vc4_update_compiled_fs(vc4, prim_mode);
1333 vc4_update_compiled_vs(vc4);
1334 }
1335
1336 static unsigned
1337 fs_cache_hash(void *key)
1338 {
1339 return util_hash_crc32(key, sizeof(struct vc4_fs_key));
1340 }
1341
1342 static unsigned
1343 vs_cache_hash(void *key)
1344 {
1345 return util_hash_crc32(key, sizeof(struct vc4_vs_key));
1346 }
1347
1348 static int
1349 fs_cache_compare(void *key1, void *key2)
1350 {
1351 return memcmp(key1, key2, sizeof(struct vc4_fs_key));
1352 }
1353
1354 static int
1355 vs_cache_compare(void *key1, void *key2)
1356 {
1357 return memcmp(key1, key2, sizeof(struct vc4_vs_key));
1358 }
1359
1360 struct delete_state {
1361 struct vc4_context *vc4;
1362 struct pipe_shader_state *shader_state;
1363 };
1364
1365 static enum pipe_error
1366 fs_delete_from_cache(void *in_key, void *in_value, void *data)
1367 {
1368 struct delete_state *del = data;
1369 struct vc4_fs_key *key = in_key;
1370 struct vc4_compiled_shader *shader = in_value;
1371
1372 if (key->base.shader_state == data) {
1373 util_hash_table_remove(del->vc4->fs_cache, key);
1374 vc4_bo_unreference(&shader->bo);
1375 free(shader);
1376 }
1377
1378 return 0;
1379 }
1380
1381 static enum pipe_error
1382 vs_delete_from_cache(void *in_key, void *in_value, void *data)
1383 {
1384 struct delete_state *del = data;
1385 struct vc4_vs_key *key = in_key;
1386 struct vc4_compiled_shader *shader = in_value;
1387
1388 if (key->base.shader_state == data) {
1389 util_hash_table_remove(del->vc4->vs_cache, key);
1390 vc4_bo_unreference(&shader->bo);
1391 free(shader);
1392 }
1393
1394 return 0;
1395 }
1396
1397 static void
1398 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
1399 {
1400 struct vc4_context *vc4 = vc4_context(pctx);
1401 struct pipe_shader_state *so = hwcso;
1402 struct delete_state del;
1403
1404 del.vc4 = vc4;
1405 del.shader_state = so;
1406 util_hash_table_foreach(vc4->fs_cache, fs_delete_from_cache, &del);
1407 util_hash_table_foreach(vc4->vs_cache, vs_delete_from_cache, &del);
1408
1409 free((void *)so->tokens);
1410 free(so);
1411 }
1412
1413 static uint32_t translate_wrap(uint32_t p_wrap)
1414 {
1415 switch (p_wrap) {
1416 case PIPE_TEX_WRAP_REPEAT:
1417 return 0;
1418 case PIPE_TEX_WRAP_CLAMP:
1419 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1420 return 1;
1421 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1422 return 2;
1423 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1424 return 3;
1425 default:
1426 fprintf(stderr, "Unknown wrap mode %d\n", p_wrap);
1427 assert(!"not reached");
1428 return 0;
1429 }
1430 }
1431
1432 static void
1433 write_texture_p0(struct vc4_context *vc4,
1434 struct vc4_texture_stateobj *texstate,
1435 uint32_t unit)
1436 {
1437 struct pipe_sampler_view *texture = texstate->textures[unit];
1438 struct vc4_resource *rsc = vc4_resource(texture->texture);
1439
1440 cl_reloc(vc4, &vc4->uniforms, rsc->bo,
1441 rsc->slices[0].offset | texture->u.tex.last_level);
1442 }
1443
1444 static void
1445 write_texture_p1(struct vc4_context *vc4,
1446 struct vc4_texture_stateobj *texstate,
1447 uint32_t unit)
1448 {
1449 struct pipe_sampler_view *texture = texstate->textures[unit];
1450 struct pipe_sampler_state *sampler = texstate->samplers[unit];
1451 static const uint32_t mipfilter_map[] = {
1452 [PIPE_TEX_MIPFILTER_NEAREST] = 2,
1453 [PIPE_TEX_MIPFILTER_LINEAR] = 4,
1454 [PIPE_TEX_MIPFILTER_NONE] = 0
1455 };
1456 static const uint32_t imgfilter_map[] = {
1457 [PIPE_TEX_FILTER_NEAREST] = 1,
1458 [PIPE_TEX_FILTER_LINEAR] = 0,
1459 };
1460
1461 cl_u32(&vc4->uniforms,
1462 (1 << 31) /* XXX: data type */|
1463 (texture->texture->height0 << 20) |
1464 (texture->texture->width0 << 8) |
1465 (imgfilter_map[sampler->mag_img_filter] << 7) |
1466 ((imgfilter_map[sampler->min_img_filter] +
1467 mipfilter_map[sampler->min_mip_filter]) << 4) |
1468 (translate_wrap(sampler->wrap_t) << 2) |
1469 (translate_wrap(sampler->wrap_s) << 0));
1470 }
1471
1472 static uint32_t
1473 get_texrect_scale(struct vc4_texture_stateobj *texstate,
1474 enum quniform_contents contents,
1475 uint32_t data)
1476 {
1477 struct pipe_sampler_view *texture = texstate->textures[data];
1478 uint32_t dim;
1479
1480 if (contents == QUNIFORM_TEXRECT_SCALE_X)
1481 dim = texture->texture->width0;
1482 else
1483 dim = texture->texture->height0;
1484
1485 return fui(1.0f / dim);
1486 }
1487
1488 void
1489 vc4_write_uniforms(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1490 struct vc4_constbuf_stateobj *cb,
1491 struct vc4_texture_stateobj *texstate,
1492 int shader_index)
1493 {
1494 struct vc4_shader_uniform_info *uinfo = &shader->uniforms[shader_index];
1495 const uint32_t *gallium_uniforms = cb->cb[0].user_buffer;
1496
1497 cl_start_shader_reloc(&vc4->uniforms, uinfo->num_texture_samples);
1498
1499 for (int i = 0; i < uinfo->count; i++) {
1500
1501 switch (uinfo->contents[i]) {
1502 case QUNIFORM_CONSTANT:
1503 cl_u32(&vc4->uniforms, uinfo->data[i]);
1504 break;
1505 case QUNIFORM_UNIFORM:
1506 cl_u32(&vc4->uniforms,
1507 gallium_uniforms[uinfo->data[i]]);
1508 break;
1509 case QUNIFORM_VIEWPORT_X_SCALE:
1510 cl_f(&vc4->uniforms, vc4->viewport.scale[0] * 16.0f);
1511 break;
1512 case QUNIFORM_VIEWPORT_Y_SCALE:
1513 cl_f(&vc4->uniforms, vc4->viewport.scale[1] * 16.0f);
1514 break;
1515
1516 case QUNIFORM_VIEWPORT_Z_OFFSET:
1517 cl_f(&vc4->uniforms, vc4->viewport.translate[2]);
1518 break;
1519 case QUNIFORM_VIEWPORT_Z_SCALE:
1520 cl_f(&vc4->uniforms, vc4->viewport.scale[2]);
1521 break;
1522
1523 case QUNIFORM_TEXTURE_CONFIG_P0:
1524 write_texture_p0(vc4, texstate, uinfo->data[i]);
1525 break;
1526
1527 case QUNIFORM_TEXTURE_CONFIG_P1:
1528 write_texture_p1(vc4, texstate, uinfo->data[i]);
1529 break;
1530
1531 case QUNIFORM_TEXRECT_SCALE_X:
1532 case QUNIFORM_TEXRECT_SCALE_Y:
1533 cl_u32(&vc4->uniforms,
1534 get_texrect_scale(texstate,
1535 uinfo->contents[i],
1536 uinfo->data[i]));
1537 break;
1538
1539 case QUNIFORM_BLEND_CONST_COLOR:
1540 cl_f(&vc4->uniforms,
1541 vc4->blend_color.color[uinfo->data[i]]);
1542 break;
1543 }
1544 #if 0
1545 uint32_t written_val = *(uint32_t *)(vc4->uniforms.next - 4);
1546 fprintf(stderr, "%p/%d: %d: 0x%08x (%f)\n",
1547 shader, shader_index, i, written_val, uif(written_val));
1548 #endif
1549 }
1550 }
1551
1552 static void
1553 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
1554 {
1555 struct vc4_context *vc4 = vc4_context(pctx);
1556 vc4->prog.bind_fs = hwcso;
1557 vc4->prog.dirty |= VC4_SHADER_DIRTY_FP;
1558 vc4->dirty |= VC4_DIRTY_PROG;
1559 }
1560
1561 static void
1562 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
1563 {
1564 struct vc4_context *vc4 = vc4_context(pctx);
1565 vc4->prog.bind_vs = hwcso;
1566 vc4->prog.dirty |= VC4_SHADER_DIRTY_VP;
1567 vc4->dirty |= VC4_DIRTY_PROG;
1568 }
1569
1570 void
1571 vc4_program_init(struct pipe_context *pctx)
1572 {
1573 struct vc4_context *vc4 = vc4_context(pctx);
1574
1575 pctx->create_vs_state = vc4_shader_state_create;
1576 pctx->delete_vs_state = vc4_shader_state_delete;
1577
1578 pctx->create_fs_state = vc4_shader_state_create;
1579 pctx->delete_fs_state = vc4_shader_state_delete;
1580
1581 pctx->bind_fs_state = vc4_fp_state_bind;
1582 pctx->bind_vs_state = vc4_vp_state_bind;
1583
1584 vc4->fs_cache = util_hash_table_create(fs_cache_hash, fs_cache_compare);
1585 vc4->vs_cache = util_hash_table_create(vs_cache_hash, vs_cache_compare);
1586 }