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vc4: Apply a Newton-Raphson step to improve RCP.
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "pipe/p_state.h"
27 #include "util/u_format.h"
28 #include "util/u_hash_table.h"
29 #include "util/u_hash.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include "util/format_srgb.h"
33 #include "util/ralloc.h"
34 #include "util/hash_table.h"
35 #include "tgsi/tgsi_dump.h"
36 #include "tgsi/tgsi_info.h"
37 #include "tgsi/tgsi_lowering.h"
38
39 #include "vc4_context.h"
40 #include "vc4_qpu.h"
41 #include "vc4_qir.h"
42 #ifdef USE_VC4_SIMULATOR
43 #include "simpenrose/simpenrose.h"
44 #endif
45
46 struct vc4_key {
47 struct vc4_uncompiled_shader *shader_state;
48 struct {
49 enum pipe_format format;
50 unsigned compare_mode:1;
51 unsigned compare_func:3;
52 unsigned wrap_s:3;
53 unsigned wrap_t:3;
54 uint8_t swizzle[4];
55 } tex[VC4_MAX_TEXTURE_SAMPLERS];
56 uint8_t ucp_enables;
57 };
58
59 struct vc4_fs_key {
60 struct vc4_key base;
61 enum pipe_format color_format;
62 bool depth_enabled;
63 bool stencil_enabled;
64 bool stencil_twoside;
65 bool stencil_full_writemasks;
66 bool is_points;
67 bool is_lines;
68 bool alpha_test;
69 bool point_coord_upper_left;
70 bool light_twoside;
71 uint8_t alpha_test_func;
72 uint32_t point_sprite_mask;
73
74 struct pipe_rt_blend_state blend;
75 };
76
77 struct vc4_vs_key {
78 struct vc4_key base;
79
80 /**
81 * This is a proxy for the array of FS input semantics, which is
82 * larger than we would want to put in the key.
83 */
84 uint64_t compiled_fs_id;
85
86 enum pipe_format attr_formats[8];
87 bool is_coord;
88 bool per_vertex_point_size;
89 };
90
91 static void
92 resize_qreg_array(struct vc4_compile *c,
93 struct qreg **regs,
94 uint32_t *size,
95 uint32_t decl_size)
96 {
97 if (*size >= decl_size)
98 return;
99
100 uint32_t old_size = *size;
101 *size = MAX2(*size * 2, decl_size);
102 *regs = reralloc(c, *regs, struct qreg, *size);
103 if (!*regs) {
104 fprintf(stderr, "Malloc failure\n");
105 abort();
106 }
107
108 for (uint32_t i = old_size; i < *size; i++)
109 (*regs)[i] = c->undef;
110 }
111
112 static struct qreg
113 add_uniform(struct vc4_compile *c,
114 enum quniform_contents contents,
115 uint32_t data)
116 {
117 uint32_t uniform = c->num_uniforms++;
118 struct qreg u = { QFILE_UNIF, uniform };
119
120 if (uniform >= c->uniform_array_size) {
121 c->uniform_array_size = MAX2(MAX2(16, uniform + 1),
122 c->uniform_array_size * 2);
123
124 c->uniform_data = reralloc(c, c->uniform_data,
125 uint32_t,
126 c->uniform_array_size);
127 c->uniform_contents = reralloc(c, c->uniform_contents,
128 enum quniform_contents,
129 c->uniform_array_size);
130 }
131
132 c->uniform_contents[uniform] = contents;
133 c->uniform_data[uniform] = data;
134
135 return u;
136 }
137
138 static struct qreg
139 get_temp_for_uniform(struct vc4_compile *c, enum quniform_contents contents,
140 uint32_t data)
141 {
142 struct qreg u = add_uniform(c, contents, data);
143 struct qreg t = qir_MOV(c, u);
144 return t;
145 }
146
147 static struct qreg
148 qir_uniform_ui(struct vc4_compile *c, uint32_t ui)
149 {
150 return get_temp_for_uniform(c, QUNIFORM_CONSTANT, ui);
151 }
152
153 static struct qreg
154 qir_uniform_f(struct vc4_compile *c, float f)
155 {
156 return qir_uniform_ui(c, fui(f));
157 }
158
159 static struct qreg
160 get_src(struct vc4_compile *c, unsigned tgsi_op,
161 struct tgsi_src_register *src, int i)
162 {
163 struct qreg r = c->undef;
164
165 uint32_t s = i;
166 switch (i) {
167 case TGSI_SWIZZLE_X:
168 s = src->SwizzleX;
169 break;
170 case TGSI_SWIZZLE_Y:
171 s = src->SwizzleY;
172 break;
173 case TGSI_SWIZZLE_Z:
174 s = src->SwizzleZ;
175 break;
176 case TGSI_SWIZZLE_W:
177 s = src->SwizzleW;
178 break;
179 default:
180 abort();
181 }
182
183 assert(!src->Indirect);
184
185 switch (src->File) {
186 case TGSI_FILE_NULL:
187 return r;
188 case TGSI_FILE_TEMPORARY:
189 r = c->temps[src->Index * 4 + s];
190 break;
191 case TGSI_FILE_IMMEDIATE:
192 r = c->consts[src->Index * 4 + s];
193 break;
194 case TGSI_FILE_CONSTANT:
195 r = get_temp_for_uniform(c, QUNIFORM_UNIFORM,
196 src->Index * 4 + s);
197 break;
198 case TGSI_FILE_INPUT:
199 r = c->inputs[src->Index * 4 + s];
200 break;
201 case TGSI_FILE_SAMPLER:
202 case TGSI_FILE_SAMPLER_VIEW:
203 r = c->undef;
204 break;
205 default:
206 fprintf(stderr, "unknown src file %d\n", src->File);
207 abort();
208 }
209
210 if (src->Absolute)
211 r = qir_FMAXABS(c, r, r);
212
213 if (src->Negate) {
214 switch (tgsi_opcode_infer_src_type(tgsi_op)) {
215 case TGSI_TYPE_SIGNED:
216 case TGSI_TYPE_UNSIGNED:
217 r = qir_SUB(c, qir_uniform_ui(c, 0), r);
218 break;
219 default:
220 r = qir_FSUB(c, qir_uniform_f(c, 0.0), r);
221 break;
222 }
223 }
224
225 return r;
226 };
227
228
229 static void
230 update_dst(struct vc4_compile *c, struct tgsi_full_instruction *tgsi_inst,
231 int i, struct qreg val)
232 {
233 struct tgsi_dst_register *tgsi_dst = &tgsi_inst->Dst[0].Register;
234
235 assert(!tgsi_dst->Indirect);
236
237 switch (tgsi_dst->File) {
238 case TGSI_FILE_TEMPORARY:
239 c->temps[tgsi_dst->Index * 4 + i] = val;
240 break;
241 case TGSI_FILE_OUTPUT:
242 c->outputs[tgsi_dst->Index * 4 + i] = val;
243 c->num_outputs = MAX2(c->num_outputs,
244 tgsi_dst->Index * 4 + i + 1);
245 break;
246 default:
247 fprintf(stderr, "unknown dst file %d\n", tgsi_dst->File);
248 abort();
249 }
250 };
251
252 static struct qreg
253 get_swizzled_channel(struct vc4_compile *c,
254 struct qreg *srcs, int swiz)
255 {
256 switch (swiz) {
257 default:
258 case UTIL_FORMAT_SWIZZLE_NONE:
259 fprintf(stderr, "warning: unknown swizzle\n");
260 /* FALLTHROUGH */
261 case UTIL_FORMAT_SWIZZLE_0:
262 return qir_uniform_f(c, 0.0);
263 case UTIL_FORMAT_SWIZZLE_1:
264 return qir_uniform_f(c, 1.0);
265 case UTIL_FORMAT_SWIZZLE_X:
266 case UTIL_FORMAT_SWIZZLE_Y:
267 case UTIL_FORMAT_SWIZZLE_Z:
268 case UTIL_FORMAT_SWIZZLE_W:
269 return srcs[swiz];
270 }
271 }
272
273 static struct qreg
274 tgsi_to_qir_alu(struct vc4_compile *c,
275 struct tgsi_full_instruction *tgsi_inst,
276 enum qop op, struct qreg *src, int i)
277 {
278 struct qreg dst = qir_get_temp(c);
279 qir_emit(c, qir_inst4(op, dst,
280 src[0 * 4 + i],
281 src[1 * 4 + i],
282 src[2 * 4 + i],
283 c->undef));
284 return dst;
285 }
286
287 static struct qreg
288 tgsi_to_qir_scalar(struct vc4_compile *c,
289 struct tgsi_full_instruction *tgsi_inst,
290 enum qop op, struct qreg *src, int i)
291 {
292 struct qreg dst = qir_get_temp(c);
293 qir_emit(c, qir_inst(op, dst,
294 src[0 * 4 + 0],
295 c->undef));
296 return dst;
297 }
298
299 static struct qreg
300 tgsi_to_qir_rcp(struct vc4_compile *c,
301 struct tgsi_full_instruction *tgsi_inst,
302 enum qop op, struct qreg *src, int i)
303 {
304 struct qreg x = src[0 * 4 + 0];
305 struct qreg r = qir_RCP(c, x);
306
307 /* Apply a Newton-Raphson step to improve the accuracy. */
308 r = qir_FMUL(c, r, qir_FSUB(c,
309 qir_uniform_f(c, 2.0),
310 qir_FMUL(c, x, r)));
311
312 return r;
313 }
314
315 static struct qreg
316 qir_srgb_decode(struct vc4_compile *c, struct qreg srgb)
317 {
318 struct qreg low = qir_FMUL(c, srgb, qir_uniform_f(c, 1.0 / 12.92));
319 struct qreg high = qir_POW(c,
320 qir_FMUL(c,
321 qir_FADD(c,
322 srgb,
323 qir_uniform_f(c, 0.055)),
324 qir_uniform_f(c, 1.0 / 1.055)),
325 qir_uniform_f(c, 2.4));
326
327 qir_SF(c, qir_FSUB(c, srgb, qir_uniform_f(c, 0.04045)));
328 return qir_SEL_X_Y_NS(c, low, high);
329 }
330
331 static struct qreg
332 qir_srgb_encode(struct vc4_compile *c, struct qreg linear)
333 {
334 struct qreg low = qir_FMUL(c, linear, qir_uniform_f(c, 12.92));
335 struct qreg high = qir_FSUB(c,
336 qir_FMUL(c,
337 qir_uniform_f(c, 1.055),
338 qir_POW(c,
339 linear,
340 qir_uniform_f(c, 0.41666))),
341 qir_uniform_f(c, 0.055));
342
343 qir_SF(c, qir_FSUB(c, linear, qir_uniform_f(c, 0.0031308)));
344 return qir_SEL_X_Y_NS(c, low, high);
345 }
346
347 static struct qreg
348 tgsi_to_qir_umul(struct vc4_compile *c,
349 struct tgsi_full_instruction *tgsi_inst,
350 enum qop op, struct qreg *src, int i)
351 {
352 struct qreg src0_hi = qir_SHR(c, src[0 * 4 + i],
353 qir_uniform_ui(c, 16));
354 struct qreg src0_lo = qir_AND(c, src[0 * 4 + i],
355 qir_uniform_ui(c, 0xffff));
356 struct qreg src1_hi = qir_SHR(c, src[1 * 4 + i],
357 qir_uniform_ui(c, 16));
358 struct qreg src1_lo = qir_AND(c, src[1 * 4 + i],
359 qir_uniform_ui(c, 0xffff));
360
361 struct qreg hilo = qir_MUL24(c, src0_hi, src1_lo);
362 struct qreg lohi = qir_MUL24(c, src0_lo, src1_hi);
363 struct qreg lolo = qir_MUL24(c, src0_lo, src1_lo);
364
365 return qir_ADD(c, lolo, qir_SHL(c,
366 qir_ADD(c, hilo, lohi),
367 qir_uniform_ui(c, 16)));
368 }
369
370 static struct qreg
371 tgsi_to_qir_idiv(struct vc4_compile *c,
372 struct tgsi_full_instruction *tgsi_inst,
373 enum qop op, struct qreg *src, int i)
374 {
375 return qir_FTOI(c, qir_FMUL(c,
376 qir_ITOF(c, src[0 * 4 + i]),
377 qir_RCP(c, qir_ITOF(c, src[1 * 4 + i]))));
378 }
379
380 static struct qreg
381 tgsi_to_qir_ineg(struct vc4_compile *c,
382 struct tgsi_full_instruction *tgsi_inst,
383 enum qop op, struct qreg *src, int i)
384 {
385 return qir_SUB(c, qir_uniform_ui(c, 0), src[0 * 4 + i]);
386 }
387
388 static struct qreg
389 tgsi_to_qir_seq(struct vc4_compile *c,
390 struct tgsi_full_instruction *tgsi_inst,
391 enum qop op, struct qreg *src, int i)
392 {
393 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
394 return qir_SEL_X_0_ZS(c, qir_uniform_f(c, 1.0));
395 }
396
397 static struct qreg
398 tgsi_to_qir_sne(struct vc4_compile *c,
399 struct tgsi_full_instruction *tgsi_inst,
400 enum qop op, struct qreg *src, int i)
401 {
402 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
403 return qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0));
404 }
405
406 static struct qreg
407 tgsi_to_qir_slt(struct vc4_compile *c,
408 struct tgsi_full_instruction *tgsi_inst,
409 enum qop op, struct qreg *src, int i)
410 {
411 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
412 return qir_SEL_X_0_NS(c, qir_uniform_f(c, 1.0));
413 }
414
415 static struct qreg
416 tgsi_to_qir_sge(struct vc4_compile *c,
417 struct tgsi_full_instruction *tgsi_inst,
418 enum qop op, struct qreg *src, int i)
419 {
420 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
421 return qir_SEL_X_0_NC(c, qir_uniform_f(c, 1.0));
422 }
423
424 static struct qreg
425 tgsi_to_qir_fseq(struct vc4_compile *c,
426 struct tgsi_full_instruction *tgsi_inst,
427 enum qop op, struct qreg *src, int i)
428 {
429 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
430 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
431 }
432
433 static struct qreg
434 tgsi_to_qir_fsne(struct vc4_compile *c,
435 struct tgsi_full_instruction *tgsi_inst,
436 enum qop op, struct qreg *src, int i)
437 {
438 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
439 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
440 }
441
442 static struct qreg
443 tgsi_to_qir_fslt(struct vc4_compile *c,
444 struct tgsi_full_instruction *tgsi_inst,
445 enum qop op, struct qreg *src, int i)
446 {
447 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
448 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
449 }
450
451 static struct qreg
452 tgsi_to_qir_fsge(struct vc4_compile *c,
453 struct tgsi_full_instruction *tgsi_inst,
454 enum qop op, struct qreg *src, int i)
455 {
456 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
457 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
458 }
459
460 static struct qreg
461 tgsi_to_qir_useq(struct vc4_compile *c,
462 struct tgsi_full_instruction *tgsi_inst,
463 enum qop op, struct qreg *src, int i)
464 {
465 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
466 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
467 }
468
469 static struct qreg
470 tgsi_to_qir_usne(struct vc4_compile *c,
471 struct tgsi_full_instruction *tgsi_inst,
472 enum qop op, struct qreg *src, int i)
473 {
474 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
475 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
476 }
477
478 static struct qreg
479 tgsi_to_qir_islt(struct vc4_compile *c,
480 struct tgsi_full_instruction *tgsi_inst,
481 enum qop op, struct qreg *src, int i)
482 {
483 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
484 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
485 }
486
487 static struct qreg
488 tgsi_to_qir_isge(struct vc4_compile *c,
489 struct tgsi_full_instruction *tgsi_inst,
490 enum qop op, struct qreg *src, int i)
491 {
492 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
493 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
494 }
495
496 static struct qreg
497 tgsi_to_qir_cmp(struct vc4_compile *c,
498 struct tgsi_full_instruction *tgsi_inst,
499 enum qop op, struct qreg *src, int i)
500 {
501 qir_SF(c, src[0 * 4 + i]);
502 return qir_SEL_X_Y_NS(c,
503 src[1 * 4 + i],
504 src[2 * 4 + i]);
505 }
506
507 static struct qreg
508 tgsi_to_qir_mad(struct vc4_compile *c,
509 struct tgsi_full_instruction *tgsi_inst,
510 enum qop op, struct qreg *src, int i)
511 {
512 return qir_FADD(c,
513 qir_FMUL(c,
514 src[0 * 4 + i],
515 src[1 * 4 + i]),
516 src[2 * 4 + i]);
517 }
518
519 static struct qreg
520 tgsi_to_qir_lrp(struct vc4_compile *c,
521 struct tgsi_full_instruction *tgsi_inst,
522 enum qop op, struct qreg *src, int i)
523 {
524 struct qreg src0 = src[0 * 4 + i];
525 struct qreg src1 = src[1 * 4 + i];
526 struct qreg src2 = src[2 * 4 + i];
527
528 /* LRP is:
529 * src0 * src1 + (1 - src0) * src2.
530 * -> src0 * src1 + src2 - src0 * src2
531 * -> src2 + src0 * (src1 - src2)
532 */
533 return qir_FADD(c, src2, qir_FMUL(c, src0, qir_FSUB(c, src1, src2)));
534
535 }
536
537 static void
538 tgsi_to_qir_tex(struct vc4_compile *c,
539 struct tgsi_full_instruction *tgsi_inst,
540 enum qop op, struct qreg *src)
541 {
542 assert(!tgsi_inst->Instruction.Saturate);
543
544 struct qreg s = src[0 * 4 + 0];
545 struct qreg t = src[0 * 4 + 1];
546 struct qreg r = src[0 * 4 + 2];
547 uint32_t unit = tgsi_inst->Src[1].Register.Index;
548 bool is_txl = tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL;
549
550 struct qreg proj = c->undef;
551 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
552 proj = qir_RCP(c, src[0 * 4 + 3]);
553 s = qir_FMUL(c, s, proj);
554 t = qir_FMUL(c, t, proj);
555 }
556
557 struct qreg texture_u[] = {
558 add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit),
559 add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
560 add_uniform(c, QUNIFORM_CONSTANT, 0),
561 add_uniform(c, QUNIFORM_CONSTANT, 0),
562 };
563 uint32_t next_texture_u = 0;
564
565 /* There is no native support for GL texture rectangle coordinates, so
566 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
567 * 1]).
568 */
569 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_RECT ||
570 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT) {
571 s = qir_FMUL(c, s,
572 get_temp_for_uniform(c,
573 QUNIFORM_TEXRECT_SCALE_X,
574 unit));
575 t = qir_FMUL(c, t,
576 get_temp_for_uniform(c,
577 QUNIFORM_TEXRECT_SCALE_Y,
578 unit));
579 }
580
581 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
582 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
583 is_txl) {
584 texture_u[2] = add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P2,
585 unit | (is_txl << 16));
586 }
587
588 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
589 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE) {
590 struct qreg ma = qir_FMAXABS(c, qir_FMAXABS(c, s, t), r);
591 struct qreg rcp_ma = qir_RCP(c, ma);
592 s = qir_FMUL(c, s, rcp_ma);
593 t = qir_FMUL(c, t, rcp_ma);
594 r = qir_FMUL(c, r, rcp_ma);
595
596 qir_TEX_R(c, r, texture_u[next_texture_u++]);
597 } else if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
598 c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP ||
599 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
600 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
601 qir_TEX_R(c, get_temp_for_uniform(c, QUNIFORM_TEXTURE_BORDER_COLOR, unit),
602 texture_u[next_texture_u++]);
603 }
604
605 if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP) {
606 s = qir_FMIN(c, qir_FMAX(c, s, qir_uniform_f(c, 0.0)),
607 qir_uniform_f(c, 1.0));
608 }
609
610 if (c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
611 t = qir_FMIN(c, qir_FMAX(c, t, qir_uniform_f(c, 0.0)),
612 qir_uniform_f(c, 1.0));
613 }
614
615 qir_TEX_T(c, t, texture_u[next_texture_u++]);
616
617 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
618 tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL)
619 qir_TEX_B(c, src[0 * 4 + 3], texture_u[next_texture_u++]);
620
621 qir_TEX_S(c, s, texture_u[next_texture_u++]);
622
623 c->num_texture_samples++;
624 struct qreg r4 = qir_TEX_RESULT(c);
625
626 enum pipe_format format = c->key->tex[unit].format;
627
628 struct qreg unpacked[4];
629 if (util_format_is_depth_or_stencil(format)) {
630 struct qreg depthf = qir_ITOF(c, qir_SHR(c, r4,
631 qir_uniform_ui(c, 8)));
632 struct qreg normalized = qir_FMUL(c, depthf,
633 qir_uniform_f(c, 1.0f/0xffffff));
634
635 struct qreg depth_output;
636
637 struct qreg one = qir_uniform_f(c, 1.0f);
638 if (c->key->tex[unit].compare_mode) {
639 struct qreg compare = src[0 * 4 + 2];
640
641 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP)
642 compare = qir_FMUL(c, compare, proj);
643
644 switch (c->key->tex[unit].compare_func) {
645 case PIPE_FUNC_NEVER:
646 depth_output = qir_uniform_f(c, 0.0f);
647 break;
648 case PIPE_FUNC_ALWAYS:
649 depth_output = one;
650 break;
651 case PIPE_FUNC_EQUAL:
652 qir_SF(c, qir_FSUB(c, compare, normalized));
653 depth_output = qir_SEL_X_0_ZS(c, one);
654 break;
655 case PIPE_FUNC_NOTEQUAL:
656 qir_SF(c, qir_FSUB(c, compare, normalized));
657 depth_output = qir_SEL_X_0_ZC(c, one);
658 break;
659 case PIPE_FUNC_GREATER:
660 qir_SF(c, qir_FSUB(c, compare, normalized));
661 depth_output = qir_SEL_X_0_NC(c, one);
662 break;
663 case PIPE_FUNC_GEQUAL:
664 qir_SF(c, qir_FSUB(c, normalized, compare));
665 depth_output = qir_SEL_X_0_NS(c, one);
666 break;
667 case PIPE_FUNC_LESS:
668 qir_SF(c, qir_FSUB(c, compare, normalized));
669 depth_output = qir_SEL_X_0_NS(c, one);
670 break;
671 case PIPE_FUNC_LEQUAL:
672 qir_SF(c, qir_FSUB(c, normalized, compare));
673 depth_output = qir_SEL_X_0_NC(c, one);
674 break;
675 }
676 } else {
677 depth_output = normalized;
678 }
679
680 for (int i = 0; i < 4; i++)
681 unpacked[i] = depth_output;
682 } else {
683 for (int i = 0; i < 4; i++)
684 unpacked[i] = qir_R4_UNPACK(c, r4, i);
685 }
686
687 const uint8_t *format_swiz = vc4_get_format_swizzle(format);
688 struct qreg texture_output[4];
689 for (int i = 0; i < 4; i++) {
690 texture_output[i] = get_swizzled_channel(c, unpacked,
691 format_swiz[i]);
692 }
693
694 if (util_format_is_srgb(format)) {
695 for (int i = 0; i < 3; i++)
696 texture_output[i] = qir_srgb_decode(c,
697 texture_output[i]);
698 }
699
700 for (int i = 0; i < 4; i++) {
701 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
702 continue;
703
704 update_dst(c, tgsi_inst, i,
705 get_swizzled_channel(c, texture_output,
706 c->key->tex[unit].swizzle[i]));
707 }
708 }
709
710 static struct qreg
711 tgsi_to_qir_trunc(struct vc4_compile *c,
712 struct tgsi_full_instruction *tgsi_inst,
713 enum qop op, struct qreg *src, int i)
714 {
715 return qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
716 }
717
718 /**
719 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
720 * to zero).
721 */
722 static struct qreg
723 tgsi_to_qir_frc(struct vc4_compile *c,
724 struct tgsi_full_instruction *tgsi_inst,
725 enum qop op, struct qreg *src, int i)
726 {
727 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
728 struct qreg diff = qir_FSUB(c, src[0 * 4 + i], trunc);
729 qir_SF(c, diff);
730 return qir_SEL_X_Y_NS(c,
731 qir_FADD(c, diff, qir_uniform_f(c, 1.0)),
732 diff);
733 }
734
735 /**
736 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
737 * zero).
738 */
739 static struct qreg
740 tgsi_to_qir_flr(struct vc4_compile *c,
741 struct tgsi_full_instruction *tgsi_inst,
742 enum qop op, struct qreg *src, int i)
743 {
744 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
745
746 /* This will be < 0 if we truncated and the truncation was of a value
747 * that was < 0 in the first place.
748 */
749 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], trunc));
750
751 return qir_SEL_X_Y_NS(c,
752 qir_FSUB(c, trunc, qir_uniform_f(c, 1.0)),
753 trunc);
754 }
755
756 /**
757 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
758 * zero).
759 */
760 static struct qreg
761 tgsi_to_qir_ceil(struct vc4_compile *c,
762 struct tgsi_full_instruction *tgsi_inst,
763 enum qop op, struct qreg *src, int i)
764 {
765 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
766
767 /* This will be < 0 if we truncated and the truncation was of a value
768 * that was > 0 in the first place.
769 */
770 qir_SF(c, qir_FSUB(c, trunc, src[0 * 4 + i]));
771
772 return qir_SEL_X_Y_NS(c,
773 qir_FADD(c, trunc, qir_uniform_f(c, 1.0)),
774 trunc);
775 }
776
777 static struct qreg
778 tgsi_to_qir_abs(struct vc4_compile *c,
779 struct tgsi_full_instruction *tgsi_inst,
780 enum qop op, struct qreg *src, int i)
781 {
782 struct qreg arg = src[0 * 4 + i];
783 return qir_FMAXABS(c, arg, arg);
784 }
785
786 /* Note that this instruction replicates its result from the x channel */
787 static struct qreg
788 tgsi_to_qir_sin(struct vc4_compile *c,
789 struct tgsi_full_instruction *tgsi_inst,
790 enum qop op, struct qreg *src, int i)
791 {
792 float coeff[] = {
793 -2.0 * M_PI,
794 pow(2.0 * M_PI, 3) / (3 * 2 * 1),
795 -pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
796 pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
797 -pow(2.0 * M_PI, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
798 };
799
800 struct qreg scaled_x =
801 qir_FMUL(c,
802 src[0 * 4 + 0],
803 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
804
805 struct qreg x = qir_FADD(c,
806 tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0),
807 qir_uniform_f(c, -0.5));
808 struct qreg x2 = qir_FMUL(c, x, x);
809 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
810 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
811 x = qir_FMUL(c, x, x2);
812 sum = qir_FADD(c,
813 sum,
814 qir_FMUL(c,
815 x,
816 qir_uniform_f(c, coeff[i])));
817 }
818 return sum;
819 }
820
821 /* Note that this instruction replicates its result from the x channel */
822 static struct qreg
823 tgsi_to_qir_cos(struct vc4_compile *c,
824 struct tgsi_full_instruction *tgsi_inst,
825 enum qop op, struct qreg *src, int i)
826 {
827 float coeff[] = {
828 -1.0f,
829 pow(2.0 * M_PI, 2) / (2 * 1),
830 -pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
831 pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
832 -pow(2.0 * M_PI, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
833 pow(2.0 * M_PI, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
834 };
835
836 struct qreg scaled_x =
837 qir_FMUL(c, src[0 * 4 + 0],
838 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
839 struct qreg x_frac = qir_FADD(c,
840 tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0),
841 qir_uniform_f(c, -0.5));
842
843 struct qreg sum = qir_uniform_f(c, coeff[0]);
844 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
845 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
846 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
847 if (i != 1)
848 x = qir_FMUL(c, x, x2);
849
850 struct qreg mul = qir_FMUL(c,
851 x,
852 qir_uniform_f(c, coeff[i]));
853 if (i == 0)
854 sum = mul;
855 else
856 sum = qir_FADD(c, sum, mul);
857 }
858 return sum;
859 }
860
861 static struct qreg
862 tgsi_to_qir_clamp(struct vc4_compile *c,
863 struct tgsi_full_instruction *tgsi_inst,
864 enum qop op, struct qreg *src, int i)
865 {
866 return qir_FMAX(c, qir_FMIN(c,
867 src[0 * 4 + i],
868 src[2 * 4 + i]),
869 src[1 * 4 + i]);
870 }
871
872 static struct qreg
873 tgsi_to_qir_ssg(struct vc4_compile *c,
874 struct tgsi_full_instruction *tgsi_inst,
875 enum qop op, struct qreg *src, int i)
876 {
877 qir_SF(c, src[0 * 4 + i]);
878 return qir_SEL_X_Y_NC(c,
879 qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0)),
880 qir_uniform_f(c, -1.0));
881 }
882
883 static void
884 emit_vertex_input(struct vc4_compile *c, int attr)
885 {
886 enum pipe_format format = c->vs_key->attr_formats[attr];
887 struct qreg vpm_reads[4];
888
889 /* Right now, we're setting the VPM offsets to be 16 bytes wide every
890 * time, so we always read 4 32-bit VPM entries.
891 */
892 for (int i = 0; i < 4; i++) {
893 vpm_reads[i] = qir_get_temp(c);
894 qir_emit(c, qir_inst(QOP_VPM_READ,
895 vpm_reads[i],
896 c->undef,
897 c->undef));
898 c->num_inputs++;
899 }
900
901 bool format_warned = false;
902 const struct util_format_description *desc =
903 util_format_description(format);
904
905 for (int i = 0; i < 4; i++) {
906 uint8_t swiz = desc->swizzle[i];
907 struct qreg result;
908
909 if (swiz > UTIL_FORMAT_SWIZZLE_W)
910 result = get_swizzled_channel(c, vpm_reads, swiz);
911 else if (desc->channel[swiz].size == 32 &&
912 desc->channel[swiz].type == UTIL_FORMAT_TYPE_FLOAT) {
913 result = get_swizzled_channel(c, vpm_reads, swiz);
914 } else if (desc->channel[swiz].size == 8 &&
915 (desc->channel[swiz].type == UTIL_FORMAT_TYPE_UNSIGNED ||
916 desc->channel[swiz].type == UTIL_FORMAT_TYPE_SIGNED) &&
917 desc->channel[swiz].normalized) {
918 struct qreg vpm = vpm_reads[0];
919 if (desc->channel[swiz].type == UTIL_FORMAT_TYPE_SIGNED)
920 vpm = qir_XOR(c, vpm, qir_uniform_ui(c, 0x80808080));
921 result = qir_UNPACK_8(c, vpm, swiz);
922 } else {
923 if (!format_warned) {
924 fprintf(stderr,
925 "vtx element %d unsupported type: %s\n",
926 attr, util_format_name(format));
927 format_warned = true;
928 }
929 result = qir_uniform_f(c, 0.0);
930 }
931
932 if (desc->channel[swiz].normalized &&
933 desc->channel[swiz].type == UTIL_FORMAT_TYPE_SIGNED) {
934 result = qir_FSUB(c,
935 qir_FMUL(c,
936 result,
937 qir_uniform_f(c, 2.0)),
938 qir_uniform_f(c, 1.0));
939 }
940
941 c->inputs[attr * 4 + i] = result;
942 }
943 }
944
945 static void
946 tgsi_to_qir_kill_if(struct vc4_compile *c, struct qreg *src, int i)
947 {
948 if (c->discard.file == QFILE_NULL)
949 c->discard = qir_uniform_f(c, 0.0);
950 qir_SF(c, src[0 * 4 + i]);
951 c->discard = qir_SEL_X_Y_NS(c, qir_uniform_f(c, 1.0),
952 c->discard);
953 }
954
955 static void
956 emit_fragcoord_input(struct vc4_compile *c, int attr)
957 {
958 c->inputs[attr * 4 + 0] = qir_FRAG_X(c);
959 c->inputs[attr * 4 + 1] = qir_FRAG_Y(c);
960 c->inputs[attr * 4 + 2] =
961 qir_FMUL(c,
962 qir_ITOF(c, qir_FRAG_Z(c)),
963 qir_uniform_f(c, 1.0 / 0xffffff));
964 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
965 }
966
967 static void
968 emit_point_coord_input(struct vc4_compile *c, int attr)
969 {
970 if (c->point_x.file == QFILE_NULL) {
971 c->point_x = qir_uniform_f(c, 0.0);
972 c->point_y = qir_uniform_f(c, 0.0);
973 }
974
975 c->inputs[attr * 4 + 0] = c->point_x;
976 if (c->fs_key->point_coord_upper_left) {
977 c->inputs[attr * 4 + 1] = qir_FSUB(c,
978 qir_uniform_f(c, 1.0),
979 c->point_y);
980 } else {
981 c->inputs[attr * 4 + 1] = c->point_y;
982 }
983 c->inputs[attr * 4 + 2] = qir_uniform_f(c, 0.0);
984 c->inputs[attr * 4 + 3] = qir_uniform_f(c, 1.0);
985 }
986
987 static struct qreg
988 emit_fragment_varying(struct vc4_compile *c, uint8_t semantic,
989 uint8_t index, uint8_t swizzle)
990 {
991 uint32_t i = c->num_input_semantics++;
992 struct qreg vary = {
993 QFILE_VARY,
994 i
995 };
996
997 if (c->num_input_semantics >= c->input_semantics_array_size) {
998 c->input_semantics_array_size =
999 MAX2(4, c->input_semantics_array_size * 2);
1000
1001 c->input_semantics = reralloc(c, c->input_semantics,
1002 struct vc4_varying_semantic,
1003 c->input_semantics_array_size);
1004 }
1005
1006 c->input_semantics[i].semantic = semantic;
1007 c->input_semantics[i].index = index;
1008 c->input_semantics[i].swizzle = swizzle;
1009
1010 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
1011 }
1012
1013 static void
1014 emit_fragment_input(struct vc4_compile *c, int attr,
1015 struct tgsi_full_declaration *decl)
1016 {
1017 for (int i = 0; i < 4; i++) {
1018 c->inputs[attr * 4 + i] =
1019 emit_fragment_varying(c,
1020 decl->Semantic.Name,
1021 decl->Semantic.Index,
1022 i);
1023 c->num_inputs++;
1024 }
1025 }
1026
1027 static void
1028 emit_face_input(struct vc4_compile *c, int attr)
1029 {
1030 c->inputs[attr * 4 + 0] = qir_FSUB(c,
1031 qir_uniform_f(c, 1.0),
1032 qir_FMUL(c,
1033 qir_ITOF(c, qir_FRAG_REV_FLAG(c)),
1034 qir_uniform_f(c, 2.0)));
1035 c->inputs[attr * 4 + 1] = qir_uniform_f(c, 0.0);
1036 c->inputs[attr * 4 + 2] = qir_uniform_f(c, 0.0);
1037 c->inputs[attr * 4 + 3] = qir_uniform_f(c, 1.0);
1038 }
1039
1040 static void
1041 add_output(struct vc4_compile *c,
1042 uint32_t decl_offset,
1043 uint8_t semantic_name,
1044 uint8_t semantic_index,
1045 uint8_t semantic_swizzle)
1046 {
1047 uint32_t old_array_size = c->outputs_array_size;
1048 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
1049 decl_offset + 1);
1050
1051 if (old_array_size != c->outputs_array_size) {
1052 c->output_semantics = reralloc(c,
1053 c->output_semantics,
1054 struct vc4_varying_semantic,
1055 c->outputs_array_size);
1056 }
1057
1058 c->output_semantics[decl_offset].semantic = semantic_name;
1059 c->output_semantics[decl_offset].index = semantic_index;
1060 c->output_semantics[decl_offset].swizzle = semantic_swizzle;
1061 }
1062
1063 static void
1064 emit_tgsi_declaration(struct vc4_compile *c,
1065 struct tgsi_full_declaration *decl)
1066 {
1067 switch (decl->Declaration.File) {
1068 case TGSI_FILE_TEMPORARY: {
1069 uint32_t old_size = c->temps_array_size;
1070 resize_qreg_array(c, &c->temps, &c->temps_array_size,
1071 (decl->Range.Last + 1) * 4);
1072
1073 for (int i = old_size; i < c->temps_array_size; i++)
1074 c->temps[i] = qir_uniform_ui(c, 0);
1075 break;
1076 }
1077
1078 case TGSI_FILE_INPUT:
1079 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1080 (decl->Range.Last + 1) * 4);
1081
1082 for (int i = decl->Range.First;
1083 i <= decl->Range.Last;
1084 i++) {
1085 if (c->stage == QSTAGE_FRAG) {
1086 if (decl->Semantic.Name ==
1087 TGSI_SEMANTIC_POSITION) {
1088 emit_fragcoord_input(c, i);
1089 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
1090 emit_face_input(c, i);
1091 } else if (decl->Semantic.Name == TGSI_SEMANTIC_GENERIC &&
1092 (c->fs_key->point_sprite_mask &
1093 (1 << decl->Semantic.Index))) {
1094 emit_point_coord_input(c, i);
1095 } else {
1096 emit_fragment_input(c, i, decl);
1097 }
1098 } else {
1099 emit_vertex_input(c, i);
1100 }
1101 }
1102 break;
1103
1104 case TGSI_FILE_OUTPUT: {
1105 for (int i = 0; i < 4; i++) {
1106 add_output(c,
1107 decl->Range.First * 4 + i,
1108 decl->Semantic.Name,
1109 decl->Semantic.Index,
1110 i);
1111 }
1112
1113 switch (decl->Semantic.Name) {
1114 case TGSI_SEMANTIC_POSITION:
1115 c->output_position_index = decl->Range.First * 4;
1116 break;
1117 case TGSI_SEMANTIC_CLIPVERTEX:
1118 c->output_clipvertex_index = decl->Range.First * 4;
1119 break;
1120 case TGSI_SEMANTIC_COLOR:
1121 c->output_color_index = decl->Range.First * 4;
1122 break;
1123 case TGSI_SEMANTIC_PSIZE:
1124 c->output_point_size_index = decl->Range.First * 4;
1125 break;
1126 }
1127
1128 break;
1129 }
1130 }
1131 }
1132
1133 static void
1134 emit_tgsi_instruction(struct vc4_compile *c,
1135 struct tgsi_full_instruction *tgsi_inst)
1136 {
1137 struct {
1138 enum qop op;
1139 struct qreg (*func)(struct vc4_compile *c,
1140 struct tgsi_full_instruction *tgsi_inst,
1141 enum qop op,
1142 struct qreg *src, int i);
1143 } op_trans[] = {
1144 [TGSI_OPCODE_MOV] = { QOP_MOV, tgsi_to_qir_alu },
1145 [TGSI_OPCODE_ABS] = { 0, tgsi_to_qir_abs },
1146 [TGSI_OPCODE_MUL] = { QOP_FMUL, tgsi_to_qir_alu },
1147 [TGSI_OPCODE_ADD] = { QOP_FADD, tgsi_to_qir_alu },
1148 [TGSI_OPCODE_SUB] = { QOP_FSUB, tgsi_to_qir_alu },
1149 [TGSI_OPCODE_MIN] = { QOP_FMIN, tgsi_to_qir_alu },
1150 [TGSI_OPCODE_MAX] = { QOP_FMAX, tgsi_to_qir_alu },
1151 [TGSI_OPCODE_F2I] = { QOP_FTOI, tgsi_to_qir_alu },
1152 [TGSI_OPCODE_I2F] = { QOP_ITOF, tgsi_to_qir_alu },
1153 [TGSI_OPCODE_UADD] = { QOP_ADD, tgsi_to_qir_alu },
1154 [TGSI_OPCODE_USHR] = { QOP_SHR, tgsi_to_qir_alu },
1155 [TGSI_OPCODE_ISHR] = { QOP_ASR, tgsi_to_qir_alu },
1156 [TGSI_OPCODE_SHL] = { QOP_SHL, tgsi_to_qir_alu },
1157 [TGSI_OPCODE_IMIN] = { QOP_MIN, tgsi_to_qir_alu },
1158 [TGSI_OPCODE_IMAX] = { QOP_MAX, tgsi_to_qir_alu },
1159 [TGSI_OPCODE_AND] = { QOP_AND, tgsi_to_qir_alu },
1160 [TGSI_OPCODE_OR] = { QOP_OR, tgsi_to_qir_alu },
1161 [TGSI_OPCODE_XOR] = { QOP_XOR, tgsi_to_qir_alu },
1162 [TGSI_OPCODE_NOT] = { QOP_NOT, tgsi_to_qir_alu },
1163
1164 [TGSI_OPCODE_UMUL] = { 0, tgsi_to_qir_umul },
1165 [TGSI_OPCODE_IDIV] = { 0, tgsi_to_qir_idiv },
1166 [TGSI_OPCODE_INEG] = { 0, tgsi_to_qir_ineg },
1167
1168 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_alu },
1169 [TGSI_OPCODE_SEQ] = { 0, tgsi_to_qir_seq },
1170 [TGSI_OPCODE_SNE] = { 0, tgsi_to_qir_sne },
1171 [TGSI_OPCODE_SGE] = { 0, tgsi_to_qir_sge },
1172 [TGSI_OPCODE_SLT] = { 0, tgsi_to_qir_slt },
1173 [TGSI_OPCODE_FSEQ] = { 0, tgsi_to_qir_fseq },
1174 [TGSI_OPCODE_FSNE] = { 0, tgsi_to_qir_fsne },
1175 [TGSI_OPCODE_FSGE] = { 0, tgsi_to_qir_fsge },
1176 [TGSI_OPCODE_FSLT] = { 0, tgsi_to_qir_fslt },
1177 [TGSI_OPCODE_USEQ] = { 0, tgsi_to_qir_useq },
1178 [TGSI_OPCODE_USNE] = { 0, tgsi_to_qir_usne },
1179 [TGSI_OPCODE_ISGE] = { 0, tgsi_to_qir_isge },
1180 [TGSI_OPCODE_ISLT] = { 0, tgsi_to_qir_islt },
1181
1182 [TGSI_OPCODE_CMP] = { 0, tgsi_to_qir_cmp },
1183 [TGSI_OPCODE_MAD] = { 0, tgsi_to_qir_mad },
1184 [TGSI_OPCODE_RCP] = { QOP_RCP, tgsi_to_qir_rcp },
1185 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_scalar },
1186 [TGSI_OPCODE_EX2] = { QOP_EXP2, tgsi_to_qir_scalar },
1187 [TGSI_OPCODE_LG2] = { QOP_LOG2, tgsi_to_qir_scalar },
1188 [TGSI_OPCODE_LRP] = { 0, tgsi_to_qir_lrp },
1189 [TGSI_OPCODE_TRUNC] = { 0, tgsi_to_qir_trunc },
1190 [TGSI_OPCODE_CEIL] = { 0, tgsi_to_qir_ceil },
1191 [TGSI_OPCODE_FRC] = { 0, tgsi_to_qir_frc },
1192 [TGSI_OPCODE_FLR] = { 0, tgsi_to_qir_flr },
1193 [TGSI_OPCODE_SIN] = { 0, tgsi_to_qir_sin },
1194 [TGSI_OPCODE_COS] = { 0, tgsi_to_qir_cos },
1195 [TGSI_OPCODE_CLAMP] = { 0, tgsi_to_qir_clamp },
1196 [TGSI_OPCODE_SSG] = { 0, tgsi_to_qir_ssg },
1197 };
1198 static int asdf = 0;
1199 uint32_t tgsi_op = tgsi_inst->Instruction.Opcode;
1200
1201 if (tgsi_op == TGSI_OPCODE_END)
1202 return;
1203
1204 struct qreg src_regs[12];
1205 for (int s = 0; s < 3; s++) {
1206 for (int i = 0; i < 4; i++) {
1207 src_regs[4 * s + i] =
1208 get_src(c, tgsi_inst->Instruction.Opcode,
1209 &tgsi_inst->Src[s].Register, i);
1210 }
1211 }
1212
1213 switch (tgsi_op) {
1214 case TGSI_OPCODE_TEX:
1215 case TGSI_OPCODE_TXP:
1216 case TGSI_OPCODE_TXB:
1217 case TGSI_OPCODE_TXL:
1218 tgsi_to_qir_tex(c, tgsi_inst,
1219 op_trans[tgsi_op].op, src_regs);
1220 return;
1221 case TGSI_OPCODE_KILL:
1222 c->discard = qir_uniform_f(c, 1.0);
1223 return;
1224 case TGSI_OPCODE_KILL_IF:
1225 for (int i = 0; i < 4; i++)
1226 tgsi_to_qir_kill_if(c, src_regs, i);
1227 return;
1228 default:
1229 break;
1230 }
1231
1232 if (tgsi_op > ARRAY_SIZE(op_trans) || !(op_trans[tgsi_op].func)) {
1233 fprintf(stderr, "unknown tgsi inst: ");
1234 tgsi_dump_instruction(tgsi_inst, asdf++);
1235 fprintf(stderr, "\n");
1236 abort();
1237 }
1238
1239 for (int i = 0; i < 4; i++) {
1240 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
1241 continue;
1242
1243 struct qreg result;
1244
1245 result = op_trans[tgsi_op].func(c, tgsi_inst,
1246 op_trans[tgsi_op].op,
1247 src_regs, i);
1248
1249 if (tgsi_inst->Instruction.Saturate) {
1250 float low = (tgsi_inst->Instruction.Saturate ==
1251 TGSI_SAT_MINUS_PLUS_ONE ? -1.0 : 0.0);
1252 result = qir_FMAX(c,
1253 qir_FMIN(c,
1254 result,
1255 qir_uniform_f(c, 1.0)),
1256 qir_uniform_f(c, low));
1257 }
1258
1259 update_dst(c, tgsi_inst, i, result);
1260 }
1261 }
1262
1263 static void
1264 parse_tgsi_immediate(struct vc4_compile *c, struct tgsi_full_immediate *imm)
1265 {
1266 for (int i = 0; i < 4; i++) {
1267 unsigned n = c->num_consts++;
1268 resize_qreg_array(c, &c->consts, &c->consts_array_size, n + 1);
1269 c->consts[n] = qir_uniform_ui(c, imm->u[i].Uint);
1270 }
1271 }
1272
1273 static struct qreg
1274 vc4_blend_channel(struct vc4_compile *c,
1275 struct qreg *dst,
1276 struct qreg *src,
1277 struct qreg val,
1278 unsigned factor,
1279 int channel)
1280 {
1281 switch(factor) {
1282 case PIPE_BLENDFACTOR_ONE:
1283 return val;
1284 case PIPE_BLENDFACTOR_SRC_COLOR:
1285 return qir_FMUL(c, val, src[channel]);
1286 case PIPE_BLENDFACTOR_SRC_ALPHA:
1287 return qir_FMUL(c, val, src[3]);
1288 case PIPE_BLENDFACTOR_DST_ALPHA:
1289 return qir_FMUL(c, val, dst[3]);
1290 case PIPE_BLENDFACTOR_DST_COLOR:
1291 return qir_FMUL(c, val, dst[channel]);
1292 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
1293 return qir_FMIN(c, src[3], qir_FSUB(c,
1294 qir_uniform_f(c, 1.0),
1295 dst[3]));
1296 case PIPE_BLENDFACTOR_CONST_COLOR:
1297 return qir_FMUL(c, val,
1298 get_temp_for_uniform(c,
1299 QUNIFORM_BLEND_CONST_COLOR,
1300 channel));
1301 case PIPE_BLENDFACTOR_CONST_ALPHA:
1302 return qir_FMUL(c, val,
1303 get_temp_for_uniform(c,
1304 QUNIFORM_BLEND_CONST_COLOR,
1305 3));
1306 case PIPE_BLENDFACTOR_ZERO:
1307 return qir_uniform_f(c, 0.0);
1308 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
1309 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1310 src[channel]));
1311 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
1312 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1313 src[3]));
1314 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
1315 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1316 dst[3]));
1317 case PIPE_BLENDFACTOR_INV_DST_COLOR:
1318 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1319 dst[channel]));
1320 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
1321 return qir_FMUL(c, val,
1322 qir_FSUB(c, qir_uniform_f(c, 1.0),
1323 get_temp_for_uniform(c,
1324 QUNIFORM_BLEND_CONST_COLOR,
1325 channel)));
1326 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
1327 return qir_FMUL(c, val,
1328 qir_FSUB(c, qir_uniform_f(c, 1.0),
1329 get_temp_for_uniform(c,
1330 QUNIFORM_BLEND_CONST_COLOR,
1331 3)));
1332
1333 default:
1334 case PIPE_BLENDFACTOR_SRC1_COLOR:
1335 case PIPE_BLENDFACTOR_SRC1_ALPHA:
1336 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
1337 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
1338 /* Unsupported. */
1339 fprintf(stderr, "Unknown blend factor %d\n", factor);
1340 return val;
1341 }
1342 }
1343
1344 static struct qreg
1345 vc4_blend_func(struct vc4_compile *c,
1346 struct qreg src, struct qreg dst,
1347 unsigned func)
1348 {
1349 switch (func) {
1350 case PIPE_BLEND_ADD:
1351 return qir_FADD(c, src, dst);
1352 case PIPE_BLEND_SUBTRACT:
1353 return qir_FSUB(c, src, dst);
1354 case PIPE_BLEND_REVERSE_SUBTRACT:
1355 return qir_FSUB(c, dst, src);
1356 case PIPE_BLEND_MIN:
1357 return qir_FMIN(c, src, dst);
1358 case PIPE_BLEND_MAX:
1359 return qir_FMAX(c, src, dst);
1360
1361 default:
1362 /* Unsupported. */
1363 fprintf(stderr, "Unknown blend func %d\n", func);
1364 return src;
1365
1366 }
1367 }
1368
1369 /**
1370 * Implements fixed function blending in shader code.
1371 *
1372 * VC4 doesn't have any hardware support for blending. Instead, you read the
1373 * current contents of the destination from the tile buffer after having
1374 * waited for the scoreboard (which is handled by vc4_qpu_emit.c), then do
1375 * math using your output color and that destination value, and update the
1376 * output color appropriately.
1377 */
1378 static void
1379 vc4_blend(struct vc4_compile *c, struct qreg *result,
1380 struct qreg *dst_color, struct qreg *src_color)
1381 {
1382 struct pipe_rt_blend_state *blend = &c->fs_key->blend;
1383
1384 if (!blend->blend_enable) {
1385 for (int i = 0; i < 4; i++)
1386 result[i] = src_color[i];
1387 return;
1388 }
1389
1390 struct qreg src_blend[4], dst_blend[4];
1391 for (int i = 0; i < 3; i++) {
1392 src_blend[i] = vc4_blend_channel(c,
1393 dst_color, src_color,
1394 src_color[i],
1395 blend->rgb_src_factor, i);
1396 dst_blend[i] = vc4_blend_channel(c,
1397 dst_color, src_color,
1398 dst_color[i],
1399 blend->rgb_dst_factor, i);
1400 }
1401 src_blend[3] = vc4_blend_channel(c,
1402 dst_color, src_color,
1403 src_color[3],
1404 blend->alpha_src_factor, 3);
1405 dst_blend[3] = vc4_blend_channel(c,
1406 dst_color, src_color,
1407 dst_color[3],
1408 blend->alpha_dst_factor, 3);
1409
1410 for (int i = 0; i < 3; i++) {
1411 result[i] = vc4_blend_func(c,
1412 src_blend[i], dst_blend[i],
1413 blend->rgb_func);
1414 }
1415 result[3] = vc4_blend_func(c,
1416 src_blend[3], dst_blend[3],
1417 blend->alpha_func);
1418 }
1419
1420 static void
1421 clip_distance_discard(struct vc4_compile *c)
1422 {
1423 for (int i = 0; i < PIPE_MAX_CLIP_PLANES; i++) {
1424 if (!(c->key->ucp_enables & (1 << i)))
1425 continue;
1426
1427 struct qreg dist = emit_fragment_varying(c,
1428 TGSI_SEMANTIC_CLIPDIST,
1429 i,
1430 TGSI_SWIZZLE_X);
1431
1432 qir_SF(c, dist);
1433
1434 if (c->discard.file == QFILE_NULL)
1435 c->discard = qir_uniform_f(c, 0.0);
1436
1437 c->discard = qir_SEL_X_Y_NS(c, qir_uniform_f(c, 1.0),
1438 c->discard);
1439 }
1440 }
1441
1442 static void
1443 alpha_test_discard(struct vc4_compile *c)
1444 {
1445 struct qreg src_alpha;
1446 struct qreg alpha_ref = get_temp_for_uniform(c, QUNIFORM_ALPHA_REF, 0);
1447
1448 if (!c->fs_key->alpha_test)
1449 return;
1450
1451 if (c->output_color_index != -1)
1452 src_alpha = c->outputs[c->output_color_index + 3];
1453 else
1454 src_alpha = qir_uniform_f(c, 1.0);
1455
1456 if (c->discard.file == QFILE_NULL)
1457 c->discard = qir_uniform_f(c, 0.0);
1458
1459 switch (c->fs_key->alpha_test_func) {
1460 case PIPE_FUNC_NEVER:
1461 c->discard = qir_uniform_f(c, 1.0);
1462 break;
1463 case PIPE_FUNC_ALWAYS:
1464 break;
1465 case PIPE_FUNC_EQUAL:
1466 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1467 c->discard = qir_SEL_X_Y_ZS(c, c->discard,
1468 qir_uniform_f(c, 1.0));
1469 break;
1470 case PIPE_FUNC_NOTEQUAL:
1471 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1472 c->discard = qir_SEL_X_Y_ZC(c, c->discard,
1473 qir_uniform_f(c, 1.0));
1474 break;
1475 case PIPE_FUNC_GREATER:
1476 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1477 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1478 qir_uniform_f(c, 1.0));
1479 break;
1480 case PIPE_FUNC_GEQUAL:
1481 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1482 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1483 qir_uniform_f(c, 1.0));
1484 break;
1485 case PIPE_FUNC_LESS:
1486 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1487 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1488 qir_uniform_f(c, 1.0));
1489 break;
1490 case PIPE_FUNC_LEQUAL:
1491 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1492 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1493 qir_uniform_f(c, 1.0));
1494 break;
1495 }
1496 }
1497
1498 static void
1499 emit_frag_end(struct vc4_compile *c)
1500 {
1501 clip_distance_discard(c);
1502 alpha_test_discard(c);
1503
1504 enum pipe_format color_format = c->fs_key->color_format;
1505 const uint8_t *format_swiz = vc4_get_format_swizzle(color_format);
1506 struct qreg tlb_read_color[4] = { c->undef, c->undef, c->undef, c->undef };
1507 struct qreg dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1508 struct qreg linear_dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1509 if (c->fs_key->blend.blend_enable ||
1510 c->fs_key->blend.colormask != 0xf) {
1511 struct qreg r4 = qir_TLB_COLOR_READ(c);
1512 for (int i = 0; i < 4; i++)
1513 tlb_read_color[i] = qir_R4_UNPACK(c, r4, i);
1514 for (int i = 0; i < 4; i++) {
1515 dst_color[i] = get_swizzled_channel(c,
1516 tlb_read_color,
1517 format_swiz[i]);
1518 if (util_format_is_srgb(color_format) && i != 3) {
1519 linear_dst_color[i] =
1520 qir_srgb_decode(c, dst_color[i]);
1521 } else {
1522 linear_dst_color[i] = dst_color[i];
1523 }
1524 }
1525 }
1526
1527 struct qreg blend_color[4];
1528 struct qreg undef_array[4] = {
1529 c->undef, c->undef, c->undef, c->undef
1530 };
1531 vc4_blend(c, blend_color, linear_dst_color,
1532 (c->output_color_index != -1 ?
1533 c->outputs + c->output_color_index :
1534 undef_array));
1535
1536 if (util_format_is_srgb(color_format)) {
1537 for (int i = 0; i < 3; i++)
1538 blend_color[i] = qir_srgb_encode(c, blend_color[i]);
1539 }
1540
1541 /* If the bit isn't set in the color mask, then just return the
1542 * original dst color, instead.
1543 */
1544 for (int i = 0; i < 4; i++) {
1545 if (!(c->fs_key->blend.colormask & (1 << i))) {
1546 blend_color[i] = dst_color[i];
1547 }
1548 }
1549
1550 /* Debug: Sometimes you're getting a black output and just want to see
1551 * if the FS is getting executed at all. Spam magenta into the color
1552 * output.
1553 */
1554 if (0) {
1555 blend_color[0] = qir_uniform_f(c, 1.0);
1556 blend_color[1] = qir_uniform_f(c, 0.0);
1557 blend_color[2] = qir_uniform_f(c, 1.0);
1558 blend_color[3] = qir_uniform_f(c, 0.5);
1559 }
1560
1561 struct qreg swizzled_outputs[4];
1562 for (int i = 0; i < 4; i++) {
1563 swizzled_outputs[i] = get_swizzled_channel(c, blend_color,
1564 format_swiz[i]);
1565 }
1566
1567 if (c->discard.file != QFILE_NULL)
1568 qir_TLB_DISCARD_SETUP(c, c->discard);
1569
1570 if (c->fs_key->stencil_enabled) {
1571 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 0));
1572 if (c->fs_key->stencil_twoside) {
1573 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 1));
1574 }
1575 if (c->fs_key->stencil_full_writemasks) {
1576 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 2));
1577 }
1578 }
1579
1580 if (c->fs_key->depth_enabled) {
1581 struct qreg z;
1582 if (c->output_position_index != -1) {
1583 z = qir_FTOI(c, qir_FMUL(c, c->outputs[c->output_position_index + 2],
1584 qir_uniform_f(c, 0xffffff)));
1585 } else {
1586 z = qir_FRAG_Z(c);
1587 }
1588 qir_TLB_Z_WRITE(c, z);
1589 }
1590
1591 bool color_written = false;
1592 for (int i = 0; i < 4; i++) {
1593 if (swizzled_outputs[i].file != QFILE_NULL)
1594 color_written = true;
1595 }
1596
1597 struct qreg packed_color;
1598 if (color_written) {
1599 /* Fill in any undefined colors. The simulator will assertion
1600 * fail if we read something that wasn't written, and I don't
1601 * know what hardware does.
1602 */
1603 for (int i = 0; i < 4; i++) {
1604 if (swizzled_outputs[i].file == QFILE_NULL)
1605 swizzled_outputs[i] = qir_uniform_f(c, 0.0);
1606 }
1607 packed_color = qir_get_temp(c);
1608 qir_emit(c, qir_inst4(QOP_PACK_COLORS, packed_color,
1609 swizzled_outputs[0],
1610 swizzled_outputs[1],
1611 swizzled_outputs[2],
1612 swizzled_outputs[3]));
1613 } else {
1614 packed_color = qir_uniform_ui(c, 0);
1615 }
1616
1617 qir_emit(c, qir_inst(QOP_TLB_COLOR_WRITE, c->undef,
1618 packed_color, c->undef));
1619 }
1620
1621 static void
1622 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1623 {
1624 struct qreg xyi[2];
1625
1626 for (int i = 0; i < 2; i++) {
1627 struct qreg scale =
1628 add_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1629
1630 xyi[i] = qir_FTOI(c, qir_FMUL(c,
1631 qir_FMUL(c,
1632 c->outputs[i],
1633 scale),
1634 rcp_w));
1635 }
1636
1637 qir_VPM_WRITE(c, qir_PACK_SCALED(c, xyi[0], xyi[1]));
1638 }
1639
1640 static void
1641 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1642 {
1643 struct qreg zscale = add_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1644 struct qreg zoffset = add_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1645
1646 qir_VPM_WRITE(c, qir_FMUL(c, qir_FADD(c, qir_FMUL(c,
1647 c->outputs[2],
1648 zscale),
1649 zoffset),
1650 rcp_w));
1651 }
1652
1653 static void
1654 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1655 {
1656 qir_VPM_WRITE(c, rcp_w);
1657 }
1658
1659 static void
1660 emit_point_size_write(struct vc4_compile *c)
1661 {
1662 struct qreg point_size;
1663
1664 if (c->output_point_size_index)
1665 point_size = c->outputs[c->output_point_size_index + 3];
1666 else
1667 point_size = qir_uniform_f(c, 1.0);
1668
1669 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1670 * BCM21553).
1671 */
1672 point_size = qir_FMAX(c, point_size, qir_uniform_f(c, .125));
1673
1674 qir_VPM_WRITE(c, point_size);
1675 }
1676
1677 /**
1678 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1679 *
1680 * The simulator insists that there be at least one vertex attribute, so
1681 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also
1682 * insists that all vertex attributes loaded get read by the VS/CS, so we have
1683 * to consume it here.
1684 */
1685 static void
1686 emit_stub_vpm_read(struct vc4_compile *c)
1687 {
1688 if (c->num_inputs)
1689 return;
1690
1691 for (int i = 0; i < 4; i++) {
1692 qir_emit(c, qir_inst(QOP_VPM_READ,
1693 qir_get_temp(c),
1694 c->undef,
1695 c->undef));
1696 c->num_inputs++;
1697 }
1698 }
1699
1700 static void
1701 emit_ucp_clipdistance(struct vc4_compile *c)
1702 {
1703 struct qreg *clipvertex;
1704
1705 if (c->output_clipvertex_index != -1)
1706 clipvertex = &c->outputs[c->output_clipvertex_index];
1707 else if (c->output_position_index != -1)
1708 clipvertex = &c->outputs[c->output_position_index];
1709 else
1710 return;
1711
1712 for (int plane = 0; plane < PIPE_MAX_CLIP_PLANES; plane++) {
1713 if (!(c->key->ucp_enables & (1 << plane)))
1714 continue;
1715
1716 /* Pick the next outputs[] that hasn't been written to, since
1717 * there are no other program writes left to be processed at
1718 * this point. If something had been declared but not written
1719 * (like a w component), we'll just smash over the top of it.
1720 */
1721 uint32_t output_index = c->num_outputs++;
1722 add_output(c, output_index,
1723 TGSI_SEMANTIC_CLIPDIST,
1724 plane,
1725 TGSI_SWIZZLE_X);
1726
1727 struct qreg dist = qir_uniform_f(c, 0.0);
1728 for (int i = 0; i < 4; i++) {
1729 struct qreg ucp =
1730 add_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1731 plane * 4 + i);
1732 dist = qir_FADD(c, dist, qir_FMUL(c, clipvertex[i], ucp));
1733 }
1734
1735 c->outputs[output_index] = dist;
1736 }
1737 }
1738
1739 static void
1740 emit_vert_end(struct vc4_compile *c,
1741 struct vc4_varying_semantic *fs_inputs,
1742 uint32_t num_fs_inputs)
1743 {
1744 struct qreg rcp_w = qir_RCP(c, c->outputs[3]);
1745
1746 emit_stub_vpm_read(c);
1747 emit_ucp_clipdistance(c);
1748
1749 emit_scaled_viewport_write(c, rcp_w);
1750 emit_zs_write(c, rcp_w);
1751 emit_rcp_wc_write(c, rcp_w);
1752 if (c->vs_key->per_vertex_point_size)
1753 emit_point_size_write(c);
1754
1755 for (int i = 0; i < num_fs_inputs; i++) {
1756 struct vc4_varying_semantic *input = &fs_inputs[i];
1757 int j;
1758
1759 for (j = 0; j < c->num_outputs; j++) {
1760 struct vc4_varying_semantic *output =
1761 &c->output_semantics[j];
1762
1763 if (input->semantic == output->semantic &&
1764 input->index == output->index &&
1765 input->swizzle == output->swizzle) {
1766 qir_VPM_WRITE(c, c->outputs[j]);
1767 break;
1768 }
1769 }
1770 /* Emit padding if we didn't find a declared VS output for
1771 * this FS input.
1772 */
1773 if (j == c->num_outputs)
1774 qir_VPM_WRITE(c, qir_uniform_f(c, 0.0));
1775 }
1776 }
1777
1778 static void
1779 emit_coord_end(struct vc4_compile *c)
1780 {
1781 struct qreg rcp_w = qir_RCP(c, c->outputs[3]);
1782
1783 emit_stub_vpm_read(c);
1784
1785 for (int i = 0; i < 4; i++)
1786 qir_VPM_WRITE(c, c->outputs[i]);
1787
1788 emit_scaled_viewport_write(c, rcp_w);
1789 emit_zs_write(c, rcp_w);
1790 emit_rcp_wc_write(c, rcp_w);
1791 if (c->vs_key->per_vertex_point_size)
1792 emit_point_size_write(c);
1793 }
1794
1795 static struct vc4_compile *
1796 vc4_shader_tgsi_to_qir(struct vc4_context *vc4, enum qstage stage,
1797 struct vc4_key *key)
1798 {
1799 struct vc4_compile *c = qir_compile_init();
1800 int ret;
1801
1802 c->stage = stage;
1803 c->shader_state = &key->shader_state->base;
1804
1805 c->key = key;
1806 switch (stage) {
1807 case QSTAGE_FRAG:
1808 c->fs_key = (struct vc4_fs_key *)key;
1809 if (c->fs_key->is_points) {
1810 c->point_x = emit_fragment_varying(c, ~0, ~0, 0);
1811 c->point_y = emit_fragment_varying(c, ~0, ~0, 0);
1812 } else if (c->fs_key->is_lines) {
1813 c->line_x = emit_fragment_varying(c, ~0, ~0, 0);
1814 }
1815 break;
1816 case QSTAGE_VERT:
1817 c->vs_key = (struct vc4_vs_key *)key;
1818 break;
1819 case QSTAGE_COORD:
1820 c->vs_key = (struct vc4_vs_key *)key;
1821 break;
1822 }
1823
1824 const struct tgsi_token *tokens = key->shader_state->base.tokens;
1825 if (c->fs_key && c->fs_key->light_twoside) {
1826 if (!key->shader_state->twoside_tokens) {
1827 const struct tgsi_lowering_config lowering_config = {
1828 .color_two_side = true,
1829 };
1830 struct tgsi_shader_info info;
1831 key->shader_state->twoside_tokens =
1832 tgsi_transform_lowering(&lowering_config,
1833 key->shader_state->base.tokens,
1834 &info);
1835
1836 /* If no transformation occurred, then NULL is
1837 * returned and we just use our original tokens.
1838 */
1839 if (!key->shader_state->twoside_tokens) {
1840 key->shader_state->twoside_tokens =
1841 key->shader_state->base.tokens;
1842 }
1843 }
1844 tokens = key->shader_state->twoside_tokens;
1845 }
1846
1847 ret = tgsi_parse_init(&c->parser, tokens);
1848 assert(ret == TGSI_PARSE_OK);
1849
1850 if (vc4_debug & VC4_DEBUG_TGSI) {
1851 fprintf(stderr, "TGSI:\n");
1852 tgsi_dump(tokens, 0);
1853 }
1854
1855 while (!tgsi_parse_end_of_tokens(&c->parser)) {
1856 tgsi_parse_token(&c->parser);
1857
1858 switch (c->parser.FullToken.Token.Type) {
1859 case TGSI_TOKEN_TYPE_DECLARATION:
1860 emit_tgsi_declaration(c,
1861 &c->parser.FullToken.FullDeclaration);
1862 break;
1863
1864 case TGSI_TOKEN_TYPE_INSTRUCTION:
1865 emit_tgsi_instruction(c,
1866 &c->parser.FullToken.FullInstruction);
1867 break;
1868
1869 case TGSI_TOKEN_TYPE_IMMEDIATE:
1870 parse_tgsi_immediate(c,
1871 &c->parser.FullToken.FullImmediate);
1872 break;
1873 }
1874 }
1875
1876 switch (stage) {
1877 case QSTAGE_FRAG:
1878 emit_frag_end(c);
1879 break;
1880 case QSTAGE_VERT:
1881 emit_vert_end(c,
1882 vc4->prog.fs->input_semantics,
1883 vc4->prog.fs->num_inputs);
1884 break;
1885 case QSTAGE_COORD:
1886 emit_coord_end(c);
1887 break;
1888 }
1889
1890 tgsi_parse_free(&c->parser);
1891
1892 qir_optimize(c);
1893
1894 if (vc4_debug & VC4_DEBUG_QIR) {
1895 fprintf(stderr, "QIR:\n");
1896 qir_dump(c);
1897 }
1898 qir_reorder_uniforms(c);
1899 vc4_generate_code(vc4, c);
1900
1901 if (vc4_debug & VC4_DEBUG_SHADERDB) {
1902 fprintf(stderr, "SHADER-DB: %s: %d instructions\n",
1903 qir_get_stage_name(c->stage), c->qpu_inst_count);
1904 fprintf(stderr, "SHADER-DB: %s: %d uniforms\n",
1905 qir_get_stage_name(c->stage), c->num_uniforms);
1906 }
1907
1908 return c;
1909 }
1910
1911 static void *
1912 vc4_shader_state_create(struct pipe_context *pctx,
1913 const struct pipe_shader_state *cso)
1914 {
1915 struct vc4_uncompiled_shader *so = CALLOC_STRUCT(vc4_uncompiled_shader);
1916 if (!so)
1917 return NULL;
1918
1919 const struct tgsi_lowering_config lowering_config = {
1920 .lower_DST = true,
1921 .lower_XPD = true,
1922 .lower_SCS = true,
1923 .lower_POW = true,
1924 .lower_LIT = true,
1925 .lower_EXP = true,
1926 .lower_LOG = true,
1927 .lower_DP4 = true,
1928 .lower_DP3 = true,
1929 .lower_DPH = true,
1930 .lower_DP2 = true,
1931 .lower_DP2A = true,
1932 };
1933
1934 struct tgsi_shader_info info;
1935 so->base.tokens = tgsi_transform_lowering(&lowering_config, cso->tokens, &info);
1936 if (!so->base.tokens)
1937 so->base.tokens = tgsi_dup_tokens(cso->tokens);
1938
1939 return so;
1940 }
1941
1942 static void
1943 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
1944 struct vc4_compile *c)
1945 {
1946 int count = c->num_uniforms;
1947 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
1948
1949 uinfo->count = count;
1950 uinfo->data = ralloc_array(shader, uint32_t, count);
1951 memcpy(uinfo->data, c->uniform_data,
1952 count * sizeof(*uinfo->data));
1953 uinfo->contents = ralloc_array(shader, enum quniform_contents, count);
1954 memcpy(uinfo->contents, c->uniform_contents,
1955 count * sizeof(*uinfo->contents));
1956 uinfo->num_texture_samples = c->num_texture_samples;
1957 }
1958
1959 static struct vc4_compiled_shader *
1960 vc4_get_compiled_shader(struct vc4_context *vc4, enum qstage stage,
1961 struct vc4_key *key)
1962 {
1963 struct util_hash_table *ht;
1964 uint32_t key_size;
1965 if (stage == QSTAGE_FRAG) {
1966 ht = vc4->fs_cache;
1967 key_size = sizeof(struct vc4_fs_key);
1968 } else {
1969 ht = vc4->vs_cache;
1970 key_size = sizeof(struct vc4_vs_key);
1971 }
1972
1973 struct vc4_compiled_shader *shader;
1974 shader = util_hash_table_get(ht, key);
1975 if (shader)
1976 return shader;
1977
1978 struct vc4_compile *c = vc4_shader_tgsi_to_qir(vc4, stage, key);
1979 shader = rzalloc(NULL, struct vc4_compiled_shader);
1980
1981 shader->program_id = vc4->next_compiled_program_id++;
1982 if (stage == QSTAGE_FRAG) {
1983 shader->input_semantics = ralloc_array(shader,
1984 struct vc4_varying_semantic,
1985 c->num_input_semantics);
1986
1987 for (int i = 0; i < c->num_input_semantics; i++) {
1988 struct vc4_varying_semantic *sem = &c->input_semantics[i];
1989
1990 /* Skip non-VS-output inputs. */
1991 if (sem->semantic == (uint8_t)~0)
1992 continue;
1993
1994 if (sem->semantic == TGSI_SEMANTIC_COLOR)
1995 shader->color_inputs |= (1 << shader->num_inputs);
1996 shader->input_semantics[shader->num_inputs] = *sem;
1997 shader->num_inputs++;
1998 }
1999 } else {
2000 shader->num_inputs = c->num_inputs;
2001 }
2002
2003 copy_uniform_state_to_shader(shader, c);
2004 shader->bo = vc4_bo_alloc_mem(vc4->screen, c->qpu_insts,
2005 c->qpu_inst_count * sizeof(uint64_t),
2006 "code");
2007
2008 qir_compile_destroy(c);
2009
2010 struct vc4_key *dup_key;
2011 dup_key = malloc(key_size);
2012 memcpy(dup_key, key, key_size);
2013 util_hash_table_set(ht, dup_key, shader);
2014
2015 return shader;
2016 }
2017
2018 static void
2019 vc4_setup_shared_key(struct vc4_context *vc4, struct vc4_key *key,
2020 struct vc4_texture_stateobj *texstate)
2021 {
2022 for (int i = 0; i < texstate->num_textures; i++) {
2023 struct pipe_sampler_view *sampler = texstate->textures[i];
2024 struct pipe_sampler_state *sampler_state =
2025 texstate->samplers[i];
2026
2027 if (sampler) {
2028 key->tex[i].format = sampler->format;
2029 key->tex[i].swizzle[0] = sampler->swizzle_r;
2030 key->tex[i].swizzle[1] = sampler->swizzle_g;
2031 key->tex[i].swizzle[2] = sampler->swizzle_b;
2032 key->tex[i].swizzle[3] = sampler->swizzle_a;
2033 key->tex[i].compare_mode = sampler_state->compare_mode;
2034 key->tex[i].compare_func = sampler_state->compare_func;
2035 key->tex[i].wrap_s = sampler_state->wrap_s;
2036 key->tex[i].wrap_t = sampler_state->wrap_t;
2037 }
2038 }
2039
2040 key->ucp_enables = vc4->rasterizer->base.clip_plane_enable;
2041 }
2042
2043 static void
2044 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
2045 {
2046 struct vc4_fs_key local_key;
2047 struct vc4_fs_key *key = &local_key;
2048
2049 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2050 VC4_DIRTY_BLEND |
2051 VC4_DIRTY_FRAMEBUFFER |
2052 VC4_DIRTY_ZSA |
2053 VC4_DIRTY_RASTERIZER |
2054 VC4_DIRTY_FRAGTEX |
2055 VC4_DIRTY_TEXSTATE |
2056 VC4_DIRTY_PROG))) {
2057 return;
2058 }
2059
2060 memset(key, 0, sizeof(*key));
2061 vc4_setup_shared_key(vc4, &key->base, &vc4->fragtex);
2062 key->base.shader_state = vc4->prog.bind_fs;
2063 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
2064 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
2065 prim_mode <= PIPE_PRIM_LINE_STRIP);
2066 key->blend = vc4->blend->rt[0];
2067
2068 if (vc4->framebuffer.cbufs[0])
2069 key->color_format = vc4->framebuffer.cbufs[0]->format;
2070
2071 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
2072 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
2073 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
2074 key->depth_enabled = (vc4->zsa->base.depth.enabled ||
2075 key->stencil_enabled);
2076 if (vc4->zsa->base.alpha.enabled) {
2077 key->alpha_test = true;
2078 key->alpha_test_func = vc4->zsa->base.alpha.func;
2079 }
2080
2081 if (key->is_points) {
2082 key->point_sprite_mask =
2083 vc4->rasterizer->base.sprite_coord_enable;
2084 key->point_coord_upper_left =
2085 (vc4->rasterizer->base.sprite_coord_mode ==
2086 PIPE_SPRITE_COORD_UPPER_LEFT);
2087 }
2088
2089 key->light_twoside = vc4->rasterizer->base.light_twoside;
2090
2091 struct vc4_compiled_shader *old_fs = vc4->prog.fs;
2092 vc4->prog.fs = vc4_get_compiled_shader(vc4, QSTAGE_FRAG, &key->base);
2093 if (vc4->prog.fs == old_fs)
2094 return;
2095
2096 if (vc4->rasterizer->base.flatshade &&
2097 old_fs && vc4->prog.fs->color_inputs != old_fs->color_inputs) {
2098 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
2099 }
2100 }
2101
2102 static void
2103 vc4_update_compiled_vs(struct vc4_context *vc4, uint8_t prim_mode)
2104 {
2105 struct vc4_vs_key local_key;
2106 struct vc4_vs_key *key = &local_key;
2107
2108 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2109 VC4_DIRTY_RASTERIZER |
2110 VC4_DIRTY_VERTTEX |
2111 VC4_DIRTY_TEXSTATE |
2112 VC4_DIRTY_VTXSTATE |
2113 VC4_DIRTY_PROG))) {
2114 return;
2115 }
2116
2117 memset(key, 0, sizeof(*key));
2118 vc4_setup_shared_key(vc4, &key->base, &vc4->verttex);
2119 key->base.shader_state = vc4->prog.bind_vs;
2120 key->compiled_fs_id = vc4->prog.fs->program_id;
2121
2122 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
2123 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
2124
2125 key->per_vertex_point_size =
2126 (prim_mode == PIPE_PRIM_POINTS &&
2127 vc4->rasterizer->base.point_size_per_vertex);
2128
2129 vc4->prog.vs = vc4_get_compiled_shader(vc4, QSTAGE_VERT, &key->base);
2130 key->is_coord = true;
2131 vc4->prog.cs = vc4_get_compiled_shader(vc4, QSTAGE_COORD, &key->base);
2132 }
2133
2134 void
2135 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
2136 {
2137 vc4_update_compiled_fs(vc4, prim_mode);
2138 vc4_update_compiled_vs(vc4, prim_mode);
2139 }
2140
2141 static unsigned
2142 fs_cache_hash(void *key)
2143 {
2144 return _mesa_hash_data(key, sizeof(struct vc4_fs_key));
2145 }
2146
2147 static unsigned
2148 vs_cache_hash(void *key)
2149 {
2150 return _mesa_hash_data(key, sizeof(struct vc4_vs_key));
2151 }
2152
2153 static int
2154 fs_cache_compare(void *key1, void *key2)
2155 {
2156 return memcmp(key1, key2, sizeof(struct vc4_fs_key));
2157 }
2158
2159 static int
2160 vs_cache_compare(void *key1, void *key2)
2161 {
2162 return memcmp(key1, key2, sizeof(struct vc4_vs_key));
2163 }
2164
2165 struct delete_state {
2166 struct vc4_context *vc4;
2167 struct vc4_uncompiled_shader *shader_state;
2168 };
2169
2170 static enum pipe_error
2171 fs_delete_from_cache(void *in_key, void *in_value, void *data)
2172 {
2173 struct delete_state *del = data;
2174 struct vc4_fs_key *key = in_key;
2175 struct vc4_compiled_shader *shader = in_value;
2176
2177 if (key->base.shader_state == data) {
2178 util_hash_table_remove(del->vc4->fs_cache, key);
2179 vc4_bo_unreference(&shader->bo);
2180 ralloc_free(shader);
2181 }
2182
2183 return 0;
2184 }
2185
2186 static enum pipe_error
2187 vs_delete_from_cache(void *in_key, void *in_value, void *data)
2188 {
2189 struct delete_state *del = data;
2190 struct vc4_vs_key *key = in_key;
2191 struct vc4_compiled_shader *shader = in_value;
2192
2193 if (key->base.shader_state == data) {
2194 util_hash_table_remove(del->vc4->vs_cache, key);
2195 vc4_bo_unreference(&shader->bo);
2196 ralloc_free(shader);
2197 }
2198
2199 return 0;
2200 }
2201
2202 static void
2203 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
2204 {
2205 struct vc4_context *vc4 = vc4_context(pctx);
2206 struct vc4_uncompiled_shader *so = hwcso;
2207 struct delete_state del;
2208
2209 del.vc4 = vc4;
2210 del.shader_state = so;
2211 util_hash_table_foreach(vc4->fs_cache, fs_delete_from_cache, &del);
2212 util_hash_table_foreach(vc4->vs_cache, vs_delete_from_cache, &del);
2213
2214 if (so->twoside_tokens != so->base.tokens)
2215 free((void *)so->twoside_tokens);
2216 free((void *)so->base.tokens);
2217 free(so);
2218 }
2219
2220 static uint32_t translate_wrap(uint32_t p_wrap, bool using_nearest)
2221 {
2222 switch (p_wrap) {
2223 case PIPE_TEX_WRAP_REPEAT:
2224 return 0;
2225 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
2226 return 1;
2227 case PIPE_TEX_WRAP_MIRROR_REPEAT:
2228 return 2;
2229 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
2230 return 3;
2231 case PIPE_TEX_WRAP_CLAMP:
2232 return (using_nearest ? 1 : 3);
2233 default:
2234 fprintf(stderr, "Unknown wrap mode %d\n", p_wrap);
2235 assert(!"not reached");
2236 return 0;
2237 }
2238 }
2239
2240 static void
2241 write_texture_p0(struct vc4_context *vc4,
2242 struct vc4_texture_stateobj *texstate,
2243 uint32_t unit)
2244 {
2245 struct pipe_sampler_view *texture = texstate->textures[unit];
2246 struct vc4_resource *rsc = vc4_resource(texture->texture);
2247
2248 cl_reloc(vc4, &vc4->uniforms, rsc->bo,
2249 VC4_SET_FIELD(rsc->slices[0].offset >> 12, VC4_TEX_P0_OFFSET) |
2250 VC4_SET_FIELD(texture->u.tex.last_level, VC4_TEX_P0_MIPLVLS) |
2251 VC4_SET_FIELD(texture->target == PIPE_TEXTURE_CUBE,
2252 VC4_TEX_P0_CMMODE) |
2253 VC4_SET_FIELD(rsc->vc4_format & 7, VC4_TEX_P0_TYPE));
2254 }
2255
2256 static void
2257 write_texture_p1(struct vc4_context *vc4,
2258 struct vc4_texture_stateobj *texstate,
2259 uint32_t unit)
2260 {
2261 struct pipe_sampler_view *texture = texstate->textures[unit];
2262 struct vc4_resource *rsc = vc4_resource(texture->texture);
2263 struct pipe_sampler_state *sampler = texstate->samplers[unit];
2264 static const uint8_t minfilter_map[6] = {
2265 VC4_TEX_P1_MINFILT_NEAR_MIP_NEAR,
2266 VC4_TEX_P1_MINFILT_LIN_MIP_NEAR,
2267 VC4_TEX_P1_MINFILT_NEAR_MIP_LIN,
2268 VC4_TEX_P1_MINFILT_LIN_MIP_LIN,
2269 VC4_TEX_P1_MINFILT_NEAREST,
2270 VC4_TEX_P1_MINFILT_LINEAR,
2271 };
2272 static const uint32_t magfilter_map[] = {
2273 [PIPE_TEX_FILTER_NEAREST] = VC4_TEX_P1_MAGFILT_NEAREST,
2274 [PIPE_TEX_FILTER_LINEAR] = VC4_TEX_P1_MAGFILT_LINEAR,
2275 };
2276
2277 bool either_nearest =
2278 (sampler->mag_img_filter == PIPE_TEX_MIPFILTER_NEAREST ||
2279 sampler->min_img_filter == PIPE_TEX_MIPFILTER_NEAREST);
2280
2281 cl_u32(&vc4->uniforms,
2282 VC4_SET_FIELD(rsc->vc4_format >> 4, VC4_TEX_P1_TYPE4) |
2283 VC4_SET_FIELD(texture->texture->height0 & 2047,
2284 VC4_TEX_P1_HEIGHT) |
2285 VC4_SET_FIELD(texture->texture->width0 & 2047,
2286 VC4_TEX_P1_WIDTH) |
2287 VC4_SET_FIELD(magfilter_map[sampler->mag_img_filter],
2288 VC4_TEX_P1_MAGFILT) |
2289 VC4_SET_FIELD(minfilter_map[sampler->min_mip_filter * 2 +
2290 sampler->min_img_filter],
2291 VC4_TEX_P1_MINFILT) |
2292 VC4_SET_FIELD(translate_wrap(sampler->wrap_s, either_nearest),
2293 VC4_TEX_P1_WRAP_S) |
2294 VC4_SET_FIELD(translate_wrap(sampler->wrap_t, either_nearest),
2295 VC4_TEX_P1_WRAP_T));
2296 }
2297
2298 static void
2299 write_texture_p2(struct vc4_context *vc4,
2300 struct vc4_texture_stateobj *texstate,
2301 uint32_t data)
2302 {
2303 uint32_t unit = data & 0xffff;
2304 struct pipe_sampler_view *texture = texstate->textures[unit];
2305 struct vc4_resource *rsc = vc4_resource(texture->texture);
2306
2307 cl_u32(&vc4->uniforms,
2308 VC4_SET_FIELD(VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE,
2309 VC4_TEX_P2_PTYPE) |
2310 VC4_SET_FIELD(rsc->cube_map_stride >> 12, VC4_TEX_P2_CMST) |
2311 VC4_SET_FIELD((data >> 16) & 1, VC4_TEX_P2_BSLOD));
2312 }
2313
2314
2315 #define SWIZ(x,y,z,w) { \
2316 UTIL_FORMAT_SWIZZLE_##x, \
2317 UTIL_FORMAT_SWIZZLE_##y, \
2318 UTIL_FORMAT_SWIZZLE_##z, \
2319 UTIL_FORMAT_SWIZZLE_##w \
2320 }
2321
2322 static void
2323 write_texture_border_color(struct vc4_context *vc4,
2324 struct vc4_texture_stateobj *texstate,
2325 uint32_t unit)
2326 {
2327 struct pipe_sampler_state *sampler = texstate->samplers[unit];
2328 struct pipe_sampler_view *texture = texstate->textures[unit];
2329 struct vc4_resource *rsc = vc4_resource(texture->texture);
2330 union util_color uc;
2331
2332 const struct util_format_description *tex_format_desc =
2333 util_format_description(texture->format);
2334
2335 float border_color[4];
2336 for (int i = 0; i < 4; i++)
2337 border_color[i] = sampler->border_color.f[i];
2338 if (util_format_is_srgb(texture->format)) {
2339 for (int i = 0; i < 3; i++)
2340 border_color[i] =
2341 util_format_linear_to_srgb_float(border_color[i]);
2342 }
2343
2344 /* Turn the border color into the layout of channels that it would
2345 * have when stored as texture contents.
2346 */
2347 float storage_color[4];
2348 util_format_unswizzle_4f(storage_color,
2349 border_color,
2350 tex_format_desc->swizzle);
2351
2352 /* Now, pack so that when the vc4_format-sampled texture contents are
2353 * replaced with our border color, the vc4_get_format_swizzle()
2354 * swizzling will get the right channels.
2355 */
2356 if (util_format_is_depth_or_stencil(texture->format)) {
2357 uc.ui[0] = util_pack_z(PIPE_FORMAT_Z24X8_UNORM,
2358 sampler->border_color.f[0]) << 8;
2359 } else {
2360 switch (rsc->vc4_format) {
2361 default:
2362 case VC4_TEXTURE_TYPE_RGBA8888:
2363 util_pack_color(storage_color,
2364 PIPE_FORMAT_R8G8B8A8_UNORM, &uc);
2365 break;
2366 case VC4_TEXTURE_TYPE_RGBA4444:
2367 util_pack_color(storage_color,
2368 PIPE_FORMAT_A8B8G8R8_UNORM, &uc);
2369 break;
2370 case VC4_TEXTURE_TYPE_RGB565:
2371 util_pack_color(storage_color,
2372 PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
2373 break;
2374 case VC4_TEXTURE_TYPE_ALPHA:
2375 uc.ui[0] = float_to_ubyte(storage_color[0]) << 24;
2376 break;
2377 case VC4_TEXTURE_TYPE_LUMALPHA:
2378 uc.ui[0] = ((float_to_ubyte(storage_color[1]) << 24) |
2379 (float_to_ubyte(storage_color[0]) << 0));
2380 break;
2381 }
2382 }
2383
2384 cl_u32(&vc4->uniforms, uc.ui[0]);
2385 }
2386
2387 static uint32_t
2388 get_texrect_scale(struct vc4_texture_stateobj *texstate,
2389 enum quniform_contents contents,
2390 uint32_t data)
2391 {
2392 struct pipe_sampler_view *texture = texstate->textures[data];
2393 uint32_t dim;
2394
2395 if (contents == QUNIFORM_TEXRECT_SCALE_X)
2396 dim = texture->texture->width0;
2397 else
2398 dim = texture->texture->height0;
2399
2400 return fui(1.0f / dim);
2401 }
2402
2403 void
2404 vc4_write_uniforms(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
2405 struct vc4_constbuf_stateobj *cb,
2406 struct vc4_texture_stateobj *texstate)
2407 {
2408 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
2409 const uint32_t *gallium_uniforms = cb->cb[0].user_buffer;
2410
2411 cl_start_shader_reloc(&vc4->uniforms, uinfo->num_texture_samples);
2412
2413 for (int i = 0; i < uinfo->count; i++) {
2414
2415 switch (uinfo->contents[i]) {
2416 case QUNIFORM_CONSTANT:
2417 cl_u32(&vc4->uniforms, uinfo->data[i]);
2418 break;
2419 case QUNIFORM_UNIFORM:
2420 cl_u32(&vc4->uniforms,
2421 gallium_uniforms[uinfo->data[i]]);
2422 break;
2423 case QUNIFORM_VIEWPORT_X_SCALE:
2424 cl_f(&vc4->uniforms, vc4->viewport.scale[0] * 16.0f);
2425 break;
2426 case QUNIFORM_VIEWPORT_Y_SCALE:
2427 cl_f(&vc4->uniforms, vc4->viewport.scale[1] * 16.0f);
2428 break;
2429
2430 case QUNIFORM_VIEWPORT_Z_OFFSET:
2431 cl_f(&vc4->uniforms, vc4->viewport.translate[2]);
2432 break;
2433 case QUNIFORM_VIEWPORT_Z_SCALE:
2434 cl_f(&vc4->uniforms, vc4->viewport.scale[2]);
2435 break;
2436
2437 case QUNIFORM_USER_CLIP_PLANE:
2438 cl_f(&vc4->uniforms,
2439 vc4->clip.ucp[uinfo->data[i] / 4][uinfo->data[i] % 4]);
2440 break;
2441
2442 case QUNIFORM_TEXTURE_CONFIG_P0:
2443 write_texture_p0(vc4, texstate, uinfo->data[i]);
2444 break;
2445
2446 case QUNIFORM_TEXTURE_CONFIG_P1:
2447 write_texture_p1(vc4, texstate, uinfo->data[i]);
2448 break;
2449
2450 case QUNIFORM_TEXTURE_CONFIG_P2:
2451 write_texture_p2(vc4, texstate, uinfo->data[i]);
2452 break;
2453
2454 case QUNIFORM_TEXTURE_BORDER_COLOR:
2455 write_texture_border_color(vc4, texstate, uinfo->data[i]);
2456 break;
2457
2458 case QUNIFORM_TEXRECT_SCALE_X:
2459 case QUNIFORM_TEXRECT_SCALE_Y:
2460 cl_u32(&vc4->uniforms,
2461 get_texrect_scale(texstate,
2462 uinfo->contents[i],
2463 uinfo->data[i]));
2464 break;
2465
2466 case QUNIFORM_BLEND_CONST_COLOR:
2467 cl_f(&vc4->uniforms,
2468 vc4->blend_color.color[uinfo->data[i]]);
2469 break;
2470
2471 case QUNIFORM_STENCIL:
2472 cl_u32(&vc4->uniforms,
2473 vc4->zsa->stencil_uniforms[uinfo->data[i]] |
2474 (uinfo->data[i] <= 1 ?
2475 (vc4->stencil_ref.ref_value[uinfo->data[i]] << 8) :
2476 0));
2477 break;
2478
2479 case QUNIFORM_ALPHA_REF:
2480 cl_f(&vc4->uniforms, vc4->zsa->base.alpha.ref_value);
2481 break;
2482 }
2483 #if 0
2484 uint32_t written_val = *(uint32_t *)(vc4->uniforms.next - 4);
2485 fprintf(stderr, "%p: %d / 0x%08x (%f)\n",
2486 shader, i, written_val, uif(written_val));
2487 #endif
2488 }
2489 }
2490
2491 static void
2492 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
2493 {
2494 struct vc4_context *vc4 = vc4_context(pctx);
2495 vc4->prog.bind_fs = hwcso;
2496 vc4->prog.dirty |= VC4_SHADER_DIRTY_FP;
2497 vc4->dirty |= VC4_DIRTY_PROG;
2498 }
2499
2500 static void
2501 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
2502 {
2503 struct vc4_context *vc4 = vc4_context(pctx);
2504 vc4->prog.bind_vs = hwcso;
2505 vc4->prog.dirty |= VC4_SHADER_DIRTY_VP;
2506 vc4->dirty |= VC4_DIRTY_PROG;
2507 }
2508
2509 void
2510 vc4_program_init(struct pipe_context *pctx)
2511 {
2512 struct vc4_context *vc4 = vc4_context(pctx);
2513
2514 pctx->create_vs_state = vc4_shader_state_create;
2515 pctx->delete_vs_state = vc4_shader_state_delete;
2516
2517 pctx->create_fs_state = vc4_shader_state_create;
2518 pctx->delete_fs_state = vc4_shader_state_delete;
2519
2520 pctx->bind_fs_state = vc4_fp_state_bind;
2521 pctx->bind_vs_state = vc4_vp_state_bind;
2522
2523 vc4->fs_cache = util_hash_table_create(fs_cache_hash, fs_cache_compare);
2524 vc4->vs_cache = util_hash_table_create(vs_cache_hash, vs_cache_compare);
2525 }