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vc4: Refactor vertex attribute conversions a bit.
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "pipe/p_state.h"
27 #include "util/u_format.h"
28 #include "util/u_hash.h"
29 #include "util/u_memory.h"
30 #include "util/u_pack_color.h"
31 #include "util/format_srgb.h"
32 #include "util/ralloc.h"
33 #include "util/hash_table.h"
34 #include "tgsi/tgsi_dump.h"
35 #include "tgsi/tgsi_info.h"
36 #include "tgsi/tgsi_lowering.h"
37
38 #include "vc4_context.h"
39 #include "vc4_qpu.h"
40 #include "vc4_qir.h"
41 #ifdef USE_VC4_SIMULATOR
42 #include "simpenrose/simpenrose.h"
43 #endif
44
45 struct vc4_key {
46 struct vc4_uncompiled_shader *shader_state;
47 struct {
48 enum pipe_format format;
49 unsigned compare_mode:1;
50 unsigned compare_func:3;
51 unsigned wrap_s:3;
52 unsigned wrap_t:3;
53 uint8_t swizzle[4];
54 } tex[VC4_MAX_TEXTURE_SAMPLERS];
55 uint8_t ucp_enables;
56 };
57
58 struct vc4_fs_key {
59 struct vc4_key base;
60 enum pipe_format color_format;
61 bool depth_enabled;
62 bool stencil_enabled;
63 bool stencil_twoside;
64 bool stencil_full_writemasks;
65 bool is_points;
66 bool is_lines;
67 bool alpha_test;
68 bool point_coord_upper_left;
69 bool light_twoside;
70 uint8_t alpha_test_func;
71 uint8_t logicop_func;
72 uint32_t point_sprite_mask;
73
74 struct pipe_rt_blend_state blend;
75 };
76
77 struct vc4_vs_key {
78 struct vc4_key base;
79
80 /**
81 * This is a proxy for the array of FS input semantics, which is
82 * larger than we would want to put in the key.
83 */
84 uint64_t compiled_fs_id;
85
86 enum pipe_format attr_formats[8];
87 bool is_coord;
88 bool per_vertex_point_size;
89 };
90
91 static void
92 resize_qreg_array(struct vc4_compile *c,
93 struct qreg **regs,
94 uint32_t *size,
95 uint32_t decl_size)
96 {
97 if (*size >= decl_size)
98 return;
99
100 uint32_t old_size = *size;
101 *size = MAX2(*size * 2, decl_size);
102 *regs = reralloc(c, *regs, struct qreg, *size);
103 if (!*regs) {
104 fprintf(stderr, "Malloc failure\n");
105 abort();
106 }
107
108 for (uint32_t i = old_size; i < *size; i++)
109 (*regs)[i] = c->undef;
110 }
111
112 static struct qreg
113 add_uniform(struct vc4_compile *c,
114 enum quniform_contents contents,
115 uint32_t data)
116 {
117 for (int i = 0; i < c->num_uniforms; i++) {
118 if (c->uniform_contents[i] == contents &&
119 c->uniform_data[i] == data) {
120 return (struct qreg) { QFILE_UNIF, i };
121 }
122 }
123
124 uint32_t uniform = c->num_uniforms++;
125 struct qreg u = { QFILE_UNIF, uniform };
126
127 if (uniform >= c->uniform_array_size) {
128 c->uniform_array_size = MAX2(MAX2(16, uniform + 1),
129 c->uniform_array_size * 2);
130
131 c->uniform_data = reralloc(c, c->uniform_data,
132 uint32_t,
133 c->uniform_array_size);
134 c->uniform_contents = reralloc(c, c->uniform_contents,
135 enum quniform_contents,
136 c->uniform_array_size);
137 }
138
139 c->uniform_contents[uniform] = contents;
140 c->uniform_data[uniform] = data;
141
142 return u;
143 }
144
145 static struct qreg
146 get_temp_for_uniform(struct vc4_compile *c, enum quniform_contents contents,
147 uint32_t data)
148 {
149 struct qreg u = add_uniform(c, contents, data);
150 struct qreg t = qir_MOV(c, u);
151 return t;
152 }
153
154 static struct qreg
155 qir_uniform_ui(struct vc4_compile *c, uint32_t ui)
156 {
157 return get_temp_for_uniform(c, QUNIFORM_CONSTANT, ui);
158 }
159
160 static struct qreg
161 qir_uniform_f(struct vc4_compile *c, float f)
162 {
163 return qir_uniform_ui(c, fui(f));
164 }
165
166 static struct qreg
167 indirect_uniform_load(struct vc4_compile *c,
168 struct tgsi_full_src_register *src, int swiz)
169 {
170 struct tgsi_ind_register *indirect = &src->Indirect;
171 struct vc4_compiler_ubo_range *range = &c->ubo_ranges[indirect->ArrayID];
172 if (!range->used) {
173 range->used = true;
174 range->dst_offset = c->next_ubo_dst_offset;
175 c->next_ubo_dst_offset += range->size;
176 c->num_ubo_ranges++;
177 };
178
179 assert(src->Register.Indirect);
180 assert(indirect->File == TGSI_FILE_ADDRESS);
181
182 struct qreg addr_val = c->addr[indirect->Swizzle];
183 struct qreg indirect_offset =
184 qir_ADD(c, addr_val, qir_uniform_ui(c,
185 range->dst_offset +
186 (src->Register.Index * 16)+
187 swiz * 4));
188 indirect_offset = qir_MIN(c, indirect_offset, qir_uniform_ui(c, (range->dst_offset +
189 range->size - 4)));
190
191 qir_TEX_DIRECT(c, indirect_offset, add_uniform(c, QUNIFORM_UBO_ADDR, 0));
192 struct qreg r4 = qir_TEX_RESULT(c);
193 c->num_texture_samples++;
194 return qir_MOV(c, r4);
195 }
196
197 static struct qreg
198 get_src(struct vc4_compile *c, unsigned tgsi_op,
199 struct tgsi_full_src_register *full_src, int i)
200 {
201 struct tgsi_src_register *src = &full_src->Register;
202 struct qreg r = c->undef;
203
204 uint32_t s = i;
205 switch (i) {
206 case TGSI_SWIZZLE_X:
207 s = src->SwizzleX;
208 break;
209 case TGSI_SWIZZLE_Y:
210 s = src->SwizzleY;
211 break;
212 case TGSI_SWIZZLE_Z:
213 s = src->SwizzleZ;
214 break;
215 case TGSI_SWIZZLE_W:
216 s = src->SwizzleW;
217 break;
218 default:
219 abort();
220 }
221
222 switch (src->File) {
223 case TGSI_FILE_NULL:
224 return r;
225 case TGSI_FILE_TEMPORARY:
226 r = c->temps[src->Index * 4 + s];
227 break;
228 case TGSI_FILE_IMMEDIATE:
229 r = c->consts[src->Index * 4 + s];
230 break;
231 case TGSI_FILE_CONSTANT:
232 if (src->Indirect) {
233 r = indirect_uniform_load(c, full_src, s);
234 } else {
235 r = get_temp_for_uniform(c, QUNIFORM_UNIFORM,
236 src->Index * 4 + s);
237 }
238 break;
239 case TGSI_FILE_INPUT:
240 r = c->inputs[src->Index * 4 + s];
241 break;
242 case TGSI_FILE_SAMPLER:
243 case TGSI_FILE_SAMPLER_VIEW:
244 r = c->undef;
245 break;
246 default:
247 fprintf(stderr, "unknown src file %d\n", src->File);
248 abort();
249 }
250
251 if (src->Absolute)
252 r = qir_FMAXABS(c, r, r);
253
254 if (src->Negate) {
255 switch (tgsi_opcode_infer_src_type(tgsi_op)) {
256 case TGSI_TYPE_SIGNED:
257 case TGSI_TYPE_UNSIGNED:
258 r = qir_SUB(c, qir_uniform_ui(c, 0), r);
259 break;
260 default:
261 r = qir_FSUB(c, qir_uniform_f(c, 0.0), r);
262 break;
263 }
264 }
265
266 return r;
267 };
268
269
270 static void
271 update_dst(struct vc4_compile *c, struct tgsi_full_instruction *tgsi_inst,
272 int i, struct qreg val)
273 {
274 struct tgsi_dst_register *tgsi_dst = &tgsi_inst->Dst[0].Register;
275
276 assert(!tgsi_dst->Indirect);
277
278 switch (tgsi_dst->File) {
279 case TGSI_FILE_TEMPORARY:
280 c->temps[tgsi_dst->Index * 4 + i] = val;
281 break;
282 case TGSI_FILE_OUTPUT:
283 c->outputs[tgsi_dst->Index * 4 + i] = val;
284 c->num_outputs = MAX2(c->num_outputs,
285 tgsi_dst->Index * 4 + i + 1);
286 break;
287 case TGSI_FILE_ADDRESS:
288 assert(tgsi_dst->Index == 0);
289 c->addr[i] = val;
290 break;
291 default:
292 fprintf(stderr, "unknown dst file %d\n", tgsi_dst->File);
293 abort();
294 }
295 };
296
297 static struct qreg
298 get_swizzled_channel(struct vc4_compile *c,
299 struct qreg *srcs, int swiz)
300 {
301 switch (swiz) {
302 default:
303 case UTIL_FORMAT_SWIZZLE_NONE:
304 fprintf(stderr, "warning: unknown swizzle\n");
305 /* FALLTHROUGH */
306 case UTIL_FORMAT_SWIZZLE_0:
307 return qir_uniform_f(c, 0.0);
308 case UTIL_FORMAT_SWIZZLE_1:
309 return qir_uniform_f(c, 1.0);
310 case UTIL_FORMAT_SWIZZLE_X:
311 case UTIL_FORMAT_SWIZZLE_Y:
312 case UTIL_FORMAT_SWIZZLE_Z:
313 case UTIL_FORMAT_SWIZZLE_W:
314 return srcs[swiz];
315 }
316 }
317
318 static struct qreg
319 tgsi_to_qir_alu(struct vc4_compile *c,
320 struct tgsi_full_instruction *tgsi_inst,
321 enum qop op, struct qreg *src, int i)
322 {
323 struct qreg dst = qir_get_temp(c);
324 qir_emit(c, qir_inst4(op, dst,
325 src[0 * 4 + i],
326 src[1 * 4 + i],
327 src[2 * 4 + i],
328 c->undef));
329 return dst;
330 }
331
332 static struct qreg
333 tgsi_to_qir_scalar(struct vc4_compile *c,
334 struct tgsi_full_instruction *tgsi_inst,
335 enum qop op, struct qreg *src, int i)
336 {
337 struct qreg dst = qir_get_temp(c);
338 qir_emit(c, qir_inst(op, dst,
339 src[0 * 4 + 0],
340 c->undef));
341 return dst;
342 }
343
344 static struct qreg
345 tgsi_to_qir_rcp(struct vc4_compile *c,
346 struct tgsi_full_instruction *tgsi_inst,
347 enum qop op, struct qreg *src, int i)
348 {
349 struct qreg x = src[0 * 4 + 0];
350 struct qreg r = qir_RCP(c, x);
351
352 /* Apply a Newton-Raphson step to improve the accuracy. */
353 r = qir_FMUL(c, r, qir_FSUB(c,
354 qir_uniform_f(c, 2.0),
355 qir_FMUL(c, x, r)));
356
357 return r;
358 }
359
360 static struct qreg
361 tgsi_to_qir_rsq(struct vc4_compile *c,
362 struct tgsi_full_instruction *tgsi_inst,
363 enum qop op, struct qreg *src, int i)
364 {
365 struct qreg x = src[0 * 4 + 0];
366 struct qreg r = qir_RSQ(c, x);
367
368 /* Apply a Newton-Raphson step to improve the accuracy. */
369 r = qir_FMUL(c, r, qir_FSUB(c,
370 qir_uniform_f(c, 1.5),
371 qir_FMUL(c,
372 qir_uniform_f(c, 0.5),
373 qir_FMUL(c, x,
374 qir_FMUL(c, r, r)))));
375
376 return r;
377 }
378
379 static struct qreg
380 qir_srgb_decode(struct vc4_compile *c, struct qreg srgb)
381 {
382 struct qreg low = qir_FMUL(c, srgb, qir_uniform_f(c, 1.0 / 12.92));
383 struct qreg high = qir_POW(c,
384 qir_FMUL(c,
385 qir_FADD(c,
386 srgb,
387 qir_uniform_f(c, 0.055)),
388 qir_uniform_f(c, 1.0 / 1.055)),
389 qir_uniform_f(c, 2.4));
390
391 qir_SF(c, qir_FSUB(c, srgb, qir_uniform_f(c, 0.04045)));
392 return qir_SEL_X_Y_NS(c, low, high);
393 }
394
395 static struct qreg
396 qir_srgb_encode(struct vc4_compile *c, struct qreg linear)
397 {
398 struct qreg low = qir_FMUL(c, linear, qir_uniform_f(c, 12.92));
399 struct qreg high = qir_FSUB(c,
400 qir_FMUL(c,
401 qir_uniform_f(c, 1.055),
402 qir_POW(c,
403 linear,
404 qir_uniform_f(c, 0.41666))),
405 qir_uniform_f(c, 0.055));
406
407 qir_SF(c, qir_FSUB(c, linear, qir_uniform_f(c, 0.0031308)));
408 return qir_SEL_X_Y_NS(c, low, high);
409 }
410
411 static struct qreg
412 tgsi_to_qir_umul(struct vc4_compile *c,
413 struct tgsi_full_instruction *tgsi_inst,
414 enum qop op, struct qreg *src, int i)
415 {
416 struct qreg src0_hi = qir_SHR(c, src[0 * 4 + i],
417 qir_uniform_ui(c, 16));
418 struct qreg src0_lo = qir_AND(c, src[0 * 4 + i],
419 qir_uniform_ui(c, 0xffff));
420 struct qreg src1_hi = qir_SHR(c, src[1 * 4 + i],
421 qir_uniform_ui(c, 16));
422 struct qreg src1_lo = qir_AND(c, src[1 * 4 + i],
423 qir_uniform_ui(c, 0xffff));
424
425 struct qreg hilo = qir_MUL24(c, src0_hi, src1_lo);
426 struct qreg lohi = qir_MUL24(c, src0_lo, src1_hi);
427 struct qreg lolo = qir_MUL24(c, src0_lo, src1_lo);
428
429 return qir_ADD(c, lolo, qir_SHL(c,
430 qir_ADD(c, hilo, lohi),
431 qir_uniform_ui(c, 16)));
432 }
433
434 static struct qreg
435 tgsi_to_qir_umad(struct vc4_compile *c,
436 struct tgsi_full_instruction *tgsi_inst,
437 enum qop op, struct qreg *src, int i)
438 {
439 return qir_ADD(c, tgsi_to_qir_umul(c, NULL, 0, src, i), src[2 * 4 + i]);
440 }
441
442 static struct qreg
443 tgsi_to_qir_idiv(struct vc4_compile *c,
444 struct tgsi_full_instruction *tgsi_inst,
445 enum qop op, struct qreg *src, int i)
446 {
447 return qir_FTOI(c, qir_FMUL(c,
448 qir_ITOF(c, src[0 * 4 + i]),
449 qir_RCP(c, qir_ITOF(c, src[1 * 4 + i]))));
450 }
451
452 static struct qreg
453 tgsi_to_qir_ineg(struct vc4_compile *c,
454 struct tgsi_full_instruction *tgsi_inst,
455 enum qop op, struct qreg *src, int i)
456 {
457 return qir_SUB(c, qir_uniform_ui(c, 0), src[0 * 4 + i]);
458 }
459
460 static struct qreg
461 tgsi_to_qir_seq(struct vc4_compile *c,
462 struct tgsi_full_instruction *tgsi_inst,
463 enum qop op, struct qreg *src, int i)
464 {
465 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
466 return qir_SEL_X_0_ZS(c, qir_uniform_f(c, 1.0));
467 }
468
469 static struct qreg
470 tgsi_to_qir_sne(struct vc4_compile *c,
471 struct tgsi_full_instruction *tgsi_inst,
472 enum qop op, struct qreg *src, int i)
473 {
474 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
475 return qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0));
476 }
477
478 static struct qreg
479 tgsi_to_qir_slt(struct vc4_compile *c,
480 struct tgsi_full_instruction *tgsi_inst,
481 enum qop op, struct qreg *src, int i)
482 {
483 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
484 return qir_SEL_X_0_NS(c, qir_uniform_f(c, 1.0));
485 }
486
487 static struct qreg
488 tgsi_to_qir_sge(struct vc4_compile *c,
489 struct tgsi_full_instruction *tgsi_inst,
490 enum qop op, struct qreg *src, int i)
491 {
492 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
493 return qir_SEL_X_0_NC(c, qir_uniform_f(c, 1.0));
494 }
495
496 static struct qreg
497 tgsi_to_qir_fseq(struct vc4_compile *c,
498 struct tgsi_full_instruction *tgsi_inst,
499 enum qop op, struct qreg *src, int i)
500 {
501 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
502 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
503 }
504
505 static struct qreg
506 tgsi_to_qir_fsne(struct vc4_compile *c,
507 struct tgsi_full_instruction *tgsi_inst,
508 enum qop op, struct qreg *src, int i)
509 {
510 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
511 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
512 }
513
514 static struct qreg
515 tgsi_to_qir_fslt(struct vc4_compile *c,
516 struct tgsi_full_instruction *tgsi_inst,
517 enum qop op, struct qreg *src, int i)
518 {
519 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
520 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
521 }
522
523 static struct qreg
524 tgsi_to_qir_fsge(struct vc4_compile *c,
525 struct tgsi_full_instruction *tgsi_inst,
526 enum qop op, struct qreg *src, int i)
527 {
528 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
529 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
530 }
531
532 static struct qreg
533 tgsi_to_qir_useq(struct vc4_compile *c,
534 struct tgsi_full_instruction *tgsi_inst,
535 enum qop op, struct qreg *src, int i)
536 {
537 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
538 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
539 }
540
541 static struct qreg
542 tgsi_to_qir_usne(struct vc4_compile *c,
543 struct tgsi_full_instruction *tgsi_inst,
544 enum qop op, struct qreg *src, int i)
545 {
546 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
547 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
548 }
549
550 static struct qreg
551 tgsi_to_qir_islt(struct vc4_compile *c,
552 struct tgsi_full_instruction *tgsi_inst,
553 enum qop op, struct qreg *src, int i)
554 {
555 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
556 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
557 }
558
559 static struct qreg
560 tgsi_to_qir_isge(struct vc4_compile *c,
561 struct tgsi_full_instruction *tgsi_inst,
562 enum qop op, struct qreg *src, int i)
563 {
564 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
565 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
566 }
567
568 static struct qreg
569 tgsi_to_qir_cmp(struct vc4_compile *c,
570 struct tgsi_full_instruction *tgsi_inst,
571 enum qop op, struct qreg *src, int i)
572 {
573 qir_SF(c, src[0 * 4 + i]);
574 return qir_SEL_X_Y_NS(c,
575 src[1 * 4 + i],
576 src[2 * 4 + i]);
577 }
578
579 static struct qreg
580 tgsi_to_qir_ucmp(struct vc4_compile *c,
581 struct tgsi_full_instruction *tgsi_inst,
582 enum qop op, struct qreg *src, int i)
583 {
584 qir_SF(c, src[0 * 4 + i]);
585 return qir_SEL_X_Y_ZC(c,
586 src[1 * 4 + i],
587 src[2 * 4 + i]);
588 }
589
590 static struct qreg
591 tgsi_to_qir_mad(struct vc4_compile *c,
592 struct tgsi_full_instruction *tgsi_inst,
593 enum qop op, struct qreg *src, int i)
594 {
595 return qir_FADD(c,
596 qir_FMUL(c,
597 src[0 * 4 + i],
598 src[1 * 4 + i]),
599 src[2 * 4 + i]);
600 }
601
602 static struct qreg
603 tgsi_to_qir_lrp(struct vc4_compile *c,
604 struct tgsi_full_instruction *tgsi_inst,
605 enum qop op, struct qreg *src, int i)
606 {
607 struct qreg src0 = src[0 * 4 + i];
608 struct qreg src1 = src[1 * 4 + i];
609 struct qreg src2 = src[2 * 4 + i];
610
611 /* LRP is:
612 * src0 * src1 + (1 - src0) * src2.
613 * -> src0 * src1 + src2 - src0 * src2
614 * -> src2 + src0 * (src1 - src2)
615 */
616 return qir_FADD(c, src2, qir_FMUL(c, src0, qir_FSUB(c, src1, src2)));
617
618 }
619
620 static void
621 tgsi_to_qir_tex(struct vc4_compile *c,
622 struct tgsi_full_instruction *tgsi_inst,
623 enum qop op, struct qreg *src)
624 {
625 assert(!tgsi_inst->Instruction.Saturate);
626
627 struct qreg s = src[0 * 4 + 0];
628 struct qreg t = src[0 * 4 + 1];
629 struct qreg r = src[0 * 4 + 2];
630 uint32_t unit = tgsi_inst->Src[1].Register.Index;
631 bool is_txl = tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL;
632
633 struct qreg proj = c->undef;
634 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
635 proj = qir_RCP(c, src[0 * 4 + 3]);
636 s = qir_FMUL(c, s, proj);
637 t = qir_FMUL(c, t, proj);
638 }
639
640 struct qreg texture_u[] = {
641 add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit),
642 add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
643 add_uniform(c, QUNIFORM_CONSTANT, 0),
644 add_uniform(c, QUNIFORM_CONSTANT, 0),
645 };
646 uint32_t next_texture_u = 0;
647
648 /* There is no native support for GL texture rectangle coordinates, so
649 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
650 * 1]).
651 */
652 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_RECT ||
653 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT) {
654 s = qir_FMUL(c, s,
655 get_temp_for_uniform(c,
656 QUNIFORM_TEXRECT_SCALE_X,
657 unit));
658 t = qir_FMUL(c, t,
659 get_temp_for_uniform(c,
660 QUNIFORM_TEXRECT_SCALE_Y,
661 unit));
662 }
663
664 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
665 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
666 is_txl) {
667 texture_u[2] = add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P2,
668 unit | (is_txl << 16));
669 }
670
671 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
672 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE) {
673 struct qreg ma = qir_FMAXABS(c, qir_FMAXABS(c, s, t), r);
674 struct qreg rcp_ma = qir_RCP(c, ma);
675 s = qir_FMUL(c, s, rcp_ma);
676 t = qir_FMUL(c, t, rcp_ma);
677 r = qir_FMUL(c, r, rcp_ma);
678
679 qir_TEX_R(c, r, texture_u[next_texture_u++]);
680 } else if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
681 c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP ||
682 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
683 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
684 qir_TEX_R(c, get_temp_for_uniform(c, QUNIFORM_TEXTURE_BORDER_COLOR, unit),
685 texture_u[next_texture_u++]);
686 }
687
688 if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP) {
689 s = qir_FMIN(c, qir_FMAX(c, s, qir_uniform_f(c, 0.0)),
690 qir_uniform_f(c, 1.0));
691 }
692
693 if (c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
694 t = qir_FMIN(c, qir_FMAX(c, t, qir_uniform_f(c, 0.0)),
695 qir_uniform_f(c, 1.0));
696 }
697
698 qir_TEX_T(c, t, texture_u[next_texture_u++]);
699
700 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
701 tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL)
702 qir_TEX_B(c, src[0 * 4 + 3], texture_u[next_texture_u++]);
703
704 qir_TEX_S(c, s, texture_u[next_texture_u++]);
705
706 c->num_texture_samples++;
707 struct qreg r4 = qir_TEX_RESULT(c);
708
709 enum pipe_format format = c->key->tex[unit].format;
710
711 struct qreg unpacked[4];
712 if (util_format_is_depth_or_stencil(format)) {
713 struct qreg depthf = qir_ITOF(c, qir_SHR(c, r4,
714 qir_uniform_ui(c, 8)));
715 struct qreg normalized = qir_FMUL(c, depthf,
716 qir_uniform_f(c, 1.0f/0xffffff));
717
718 struct qreg depth_output;
719
720 struct qreg one = qir_uniform_f(c, 1.0f);
721 if (c->key->tex[unit].compare_mode) {
722 struct qreg compare = src[0 * 4 + 2];
723
724 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP)
725 compare = qir_FMUL(c, compare, proj);
726
727 switch (c->key->tex[unit].compare_func) {
728 case PIPE_FUNC_NEVER:
729 depth_output = qir_uniform_f(c, 0.0f);
730 break;
731 case PIPE_FUNC_ALWAYS:
732 depth_output = one;
733 break;
734 case PIPE_FUNC_EQUAL:
735 qir_SF(c, qir_FSUB(c, compare, normalized));
736 depth_output = qir_SEL_X_0_ZS(c, one);
737 break;
738 case PIPE_FUNC_NOTEQUAL:
739 qir_SF(c, qir_FSUB(c, compare, normalized));
740 depth_output = qir_SEL_X_0_ZC(c, one);
741 break;
742 case PIPE_FUNC_GREATER:
743 qir_SF(c, qir_FSUB(c, compare, normalized));
744 depth_output = qir_SEL_X_0_NC(c, one);
745 break;
746 case PIPE_FUNC_GEQUAL:
747 qir_SF(c, qir_FSUB(c, normalized, compare));
748 depth_output = qir_SEL_X_0_NS(c, one);
749 break;
750 case PIPE_FUNC_LESS:
751 qir_SF(c, qir_FSUB(c, compare, normalized));
752 depth_output = qir_SEL_X_0_NS(c, one);
753 break;
754 case PIPE_FUNC_LEQUAL:
755 qir_SF(c, qir_FSUB(c, normalized, compare));
756 depth_output = qir_SEL_X_0_NC(c, one);
757 break;
758 }
759 } else {
760 depth_output = normalized;
761 }
762
763 for (int i = 0; i < 4; i++)
764 unpacked[i] = depth_output;
765 } else {
766 for (int i = 0; i < 4; i++)
767 unpacked[i] = qir_R4_UNPACK(c, r4, i);
768 }
769
770 const uint8_t *format_swiz = vc4_get_format_swizzle(format);
771 struct qreg texture_output[4];
772 for (int i = 0; i < 4; i++) {
773 texture_output[i] = get_swizzled_channel(c, unpacked,
774 format_swiz[i]);
775 }
776
777 if (util_format_is_srgb(format)) {
778 for (int i = 0; i < 3; i++)
779 texture_output[i] = qir_srgb_decode(c,
780 texture_output[i]);
781 }
782
783 for (int i = 0; i < 4; i++) {
784 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
785 continue;
786
787 update_dst(c, tgsi_inst, i,
788 get_swizzled_channel(c, texture_output,
789 c->key->tex[unit].swizzle[i]));
790 }
791 }
792
793 static struct qreg
794 tgsi_to_qir_trunc(struct vc4_compile *c,
795 struct tgsi_full_instruction *tgsi_inst,
796 enum qop op, struct qreg *src, int i)
797 {
798 return qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
799 }
800
801 /**
802 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
803 * to zero).
804 */
805 static struct qreg
806 tgsi_to_qir_frc(struct vc4_compile *c,
807 struct tgsi_full_instruction *tgsi_inst,
808 enum qop op, struct qreg *src, int i)
809 {
810 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
811 struct qreg diff = qir_FSUB(c, src[0 * 4 + i], trunc);
812 qir_SF(c, diff);
813 return qir_SEL_X_Y_NS(c,
814 qir_FADD(c, diff, qir_uniform_f(c, 1.0)),
815 diff);
816 }
817
818 /**
819 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
820 * zero).
821 */
822 static struct qreg
823 tgsi_to_qir_flr(struct vc4_compile *c,
824 struct tgsi_full_instruction *tgsi_inst,
825 enum qop op, struct qreg *src, int i)
826 {
827 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
828
829 /* This will be < 0 if we truncated and the truncation was of a value
830 * that was < 0 in the first place.
831 */
832 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], trunc));
833
834 return qir_SEL_X_Y_NS(c,
835 qir_FSUB(c, trunc, qir_uniform_f(c, 1.0)),
836 trunc);
837 }
838
839 /**
840 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
841 * zero).
842 */
843 static struct qreg
844 tgsi_to_qir_ceil(struct vc4_compile *c,
845 struct tgsi_full_instruction *tgsi_inst,
846 enum qop op, struct qreg *src, int i)
847 {
848 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
849
850 /* This will be < 0 if we truncated and the truncation was of a value
851 * that was > 0 in the first place.
852 */
853 qir_SF(c, qir_FSUB(c, trunc, src[0 * 4 + i]));
854
855 return qir_SEL_X_Y_NS(c,
856 qir_FADD(c, trunc, qir_uniform_f(c, 1.0)),
857 trunc);
858 }
859
860 static struct qreg
861 tgsi_to_qir_abs(struct vc4_compile *c,
862 struct tgsi_full_instruction *tgsi_inst,
863 enum qop op, struct qreg *src, int i)
864 {
865 struct qreg arg = src[0 * 4 + i];
866 return qir_FMAXABS(c, arg, arg);
867 }
868
869 /* Note that this instruction replicates its result from the x channel */
870 static struct qreg
871 tgsi_to_qir_sin(struct vc4_compile *c,
872 struct tgsi_full_instruction *tgsi_inst,
873 enum qop op, struct qreg *src, int i)
874 {
875 float coeff[] = {
876 -2.0 * M_PI,
877 pow(2.0 * M_PI, 3) / (3 * 2 * 1),
878 -pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
879 pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
880 -pow(2.0 * M_PI, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
881 };
882
883 struct qreg scaled_x =
884 qir_FMUL(c,
885 src[0 * 4 + 0],
886 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
887
888 struct qreg x = qir_FADD(c,
889 tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0),
890 qir_uniform_f(c, -0.5));
891 struct qreg x2 = qir_FMUL(c, x, x);
892 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
893 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
894 x = qir_FMUL(c, x, x2);
895 sum = qir_FADD(c,
896 sum,
897 qir_FMUL(c,
898 x,
899 qir_uniform_f(c, coeff[i])));
900 }
901 return sum;
902 }
903
904 /* Note that this instruction replicates its result from the x channel */
905 static struct qreg
906 tgsi_to_qir_cos(struct vc4_compile *c,
907 struct tgsi_full_instruction *tgsi_inst,
908 enum qop op, struct qreg *src, int i)
909 {
910 float coeff[] = {
911 -1.0f,
912 pow(2.0 * M_PI, 2) / (2 * 1),
913 -pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
914 pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
915 -pow(2.0 * M_PI, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
916 pow(2.0 * M_PI, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
917 };
918
919 struct qreg scaled_x =
920 qir_FMUL(c, src[0 * 4 + 0],
921 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
922 struct qreg x_frac = qir_FADD(c,
923 tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0),
924 qir_uniform_f(c, -0.5));
925
926 struct qreg sum = qir_uniform_f(c, coeff[0]);
927 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
928 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
929 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
930 if (i != 1)
931 x = qir_FMUL(c, x, x2);
932
933 struct qreg mul = qir_FMUL(c,
934 x,
935 qir_uniform_f(c, coeff[i]));
936 if (i == 0)
937 sum = mul;
938 else
939 sum = qir_FADD(c, sum, mul);
940 }
941 return sum;
942 }
943
944 static struct qreg
945 tgsi_to_qir_clamp(struct vc4_compile *c,
946 struct tgsi_full_instruction *tgsi_inst,
947 enum qop op, struct qreg *src, int i)
948 {
949 return qir_FMAX(c, qir_FMIN(c,
950 src[0 * 4 + i],
951 src[2 * 4 + i]),
952 src[1 * 4 + i]);
953 }
954
955 static struct qreg
956 tgsi_to_qir_ssg(struct vc4_compile *c,
957 struct tgsi_full_instruction *tgsi_inst,
958 enum qop op, struct qreg *src, int i)
959 {
960 qir_SF(c, src[0 * 4 + i]);
961 return qir_SEL_X_Y_NC(c,
962 qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0)),
963 qir_uniform_f(c, -1.0));
964 }
965
966 /* Compare to tgsi_to_qir_flr() for the floor logic. */
967 static struct qreg
968 tgsi_to_qir_arl(struct vc4_compile *c,
969 struct tgsi_full_instruction *tgsi_inst,
970 enum qop op, struct qreg *src, int i)
971 {
972 struct qreg trunc = qir_FTOI(c, src[0 * 4 + i]);
973 struct qreg scaled = qir_SHL(c, trunc, qir_uniform_ui(c, 4));
974
975 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], qir_ITOF(c, trunc)));
976
977 return qir_SEL_X_Y_NS(c, qir_SUB(c, scaled, qir_uniform_ui(c, 4)),
978 scaled);
979 }
980
981 static struct qreg
982 tgsi_to_qir_uarl(struct vc4_compile *c,
983 struct tgsi_full_instruction *tgsi_inst,
984 enum qop op, struct qreg *src, int i)
985 {
986 return qir_SHL(c, src[0 * 4 + i], qir_uniform_ui(c, 4));
987 }
988
989 static struct qreg
990 get_channel_from_vpm(struct vc4_compile *c,
991 struct qreg *vpm_reads,
992 uint8_t swiz,
993 const struct util_format_description *desc)
994 {
995 const struct util_format_channel_description *chan =
996 &desc->channel[swiz];
997 struct qreg temp;
998
999 if (swiz > UTIL_FORMAT_SWIZZLE_W)
1000 return get_swizzled_channel(c, vpm_reads, swiz);
1001 else if (chan->size == 32 &&
1002 chan->type == UTIL_FORMAT_TYPE_FLOAT) {
1003 return get_swizzled_channel(c, vpm_reads, swiz);
1004 } else if (chan->size == 8 &&
1005 (chan->type == UTIL_FORMAT_TYPE_UNSIGNED ||
1006 chan->type == UTIL_FORMAT_TYPE_SIGNED) &&
1007 chan->normalized) {
1008 struct qreg vpm = vpm_reads[0];
1009 if (chan->type == UTIL_FORMAT_TYPE_SIGNED)
1010 vpm = qir_XOR(c, vpm, qir_uniform_ui(c, 0x80808080));
1011 temp = qir_UNPACK_8_F(c, vpm, swiz);
1012
1013 if (chan->type == UTIL_FORMAT_TYPE_SIGNED) {
1014 return qir_FSUB(c, qir_FMUL(c,
1015 temp,
1016 qir_uniform_f(c, 2.0)),
1017 qir_uniform_f(c, 1.0));
1018 } else {
1019 return temp;
1020 }
1021 } else {
1022 return c->undef;
1023 }
1024 }
1025
1026 static void
1027 emit_vertex_input(struct vc4_compile *c, int attr)
1028 {
1029 enum pipe_format format = c->vs_key->attr_formats[attr];
1030 struct qreg vpm_reads[4];
1031
1032 /* Right now, we're setting the VPM offsets to be 16 bytes wide every
1033 * time, so we always read 4 32-bit VPM entries.
1034 */
1035 for (int i = 0; i < 4; i++) {
1036 vpm_reads[i] = qir_get_temp(c);
1037 qir_emit(c, qir_inst(QOP_VPM_READ,
1038 vpm_reads[i],
1039 c->undef,
1040 c->undef));
1041 c->num_inputs++;
1042 }
1043
1044 bool format_warned = false;
1045 const struct util_format_description *desc =
1046 util_format_description(format);
1047
1048 for (int i = 0; i < 4; i++) {
1049 uint8_t swiz = desc->swizzle[i];
1050 struct qreg result = get_channel_from_vpm(c, vpm_reads,
1051 swiz, desc);
1052
1053 if (result.file == QFILE_NULL) {
1054 if (!format_warned) {
1055 fprintf(stderr,
1056 "vtx element %d unsupported type: %s\n",
1057 attr, util_format_name(format));
1058 format_warned = true;
1059 }
1060 result = qir_uniform_f(c, 0.0);
1061 }
1062 c->inputs[attr * 4 + i] = result;
1063 }
1064 }
1065
1066 static void
1067 tgsi_to_qir_kill_if(struct vc4_compile *c, struct qreg *src, int i)
1068 {
1069 if (c->discard.file == QFILE_NULL)
1070 c->discard = qir_uniform_f(c, 0.0);
1071 qir_SF(c, src[0 * 4 + i]);
1072 c->discard = qir_SEL_X_Y_NS(c, qir_uniform_f(c, 1.0),
1073 c->discard);
1074 }
1075
1076 static void
1077 emit_fragcoord_input(struct vc4_compile *c, int attr)
1078 {
1079 c->inputs[attr * 4 + 0] = qir_FRAG_X(c);
1080 c->inputs[attr * 4 + 1] = qir_FRAG_Y(c);
1081 c->inputs[attr * 4 + 2] =
1082 qir_FMUL(c,
1083 qir_ITOF(c, qir_FRAG_Z(c)),
1084 qir_uniform_f(c, 1.0 / 0xffffff));
1085 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
1086 }
1087
1088 static void
1089 emit_point_coord_input(struct vc4_compile *c, int attr)
1090 {
1091 if (c->point_x.file == QFILE_NULL) {
1092 c->point_x = qir_uniform_f(c, 0.0);
1093 c->point_y = qir_uniform_f(c, 0.0);
1094 }
1095
1096 c->inputs[attr * 4 + 0] = c->point_x;
1097 if (c->fs_key->point_coord_upper_left) {
1098 c->inputs[attr * 4 + 1] = qir_FSUB(c,
1099 qir_uniform_f(c, 1.0),
1100 c->point_y);
1101 } else {
1102 c->inputs[attr * 4 + 1] = c->point_y;
1103 }
1104 c->inputs[attr * 4 + 2] = qir_uniform_f(c, 0.0);
1105 c->inputs[attr * 4 + 3] = qir_uniform_f(c, 1.0);
1106 }
1107
1108 static struct qreg
1109 emit_fragment_varying(struct vc4_compile *c, uint8_t semantic,
1110 uint8_t index, uint8_t swizzle)
1111 {
1112 uint32_t i = c->num_input_semantics++;
1113 struct qreg vary = {
1114 QFILE_VARY,
1115 i
1116 };
1117
1118 if (c->num_input_semantics >= c->input_semantics_array_size) {
1119 c->input_semantics_array_size =
1120 MAX2(4, c->input_semantics_array_size * 2);
1121
1122 c->input_semantics = reralloc(c, c->input_semantics,
1123 struct vc4_varying_semantic,
1124 c->input_semantics_array_size);
1125 }
1126
1127 c->input_semantics[i].semantic = semantic;
1128 c->input_semantics[i].index = index;
1129 c->input_semantics[i].swizzle = swizzle;
1130
1131 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
1132 }
1133
1134 static void
1135 emit_fragment_input(struct vc4_compile *c, int attr,
1136 struct tgsi_full_declaration *decl)
1137 {
1138 for (int i = 0; i < 4; i++) {
1139 c->inputs[attr * 4 + i] =
1140 emit_fragment_varying(c,
1141 decl->Semantic.Name,
1142 decl->Semantic.Index,
1143 i);
1144 c->num_inputs++;
1145 }
1146 }
1147
1148 static void
1149 emit_face_input(struct vc4_compile *c, int attr)
1150 {
1151 c->inputs[attr * 4 + 0] = qir_FSUB(c,
1152 qir_uniform_f(c, 1.0),
1153 qir_FMUL(c,
1154 qir_ITOF(c, qir_FRAG_REV_FLAG(c)),
1155 qir_uniform_f(c, 2.0)));
1156 c->inputs[attr * 4 + 1] = qir_uniform_f(c, 0.0);
1157 c->inputs[attr * 4 + 2] = qir_uniform_f(c, 0.0);
1158 c->inputs[attr * 4 + 3] = qir_uniform_f(c, 1.0);
1159 }
1160
1161 static void
1162 add_output(struct vc4_compile *c,
1163 uint32_t decl_offset,
1164 uint8_t semantic_name,
1165 uint8_t semantic_index,
1166 uint8_t semantic_swizzle)
1167 {
1168 uint32_t old_array_size = c->outputs_array_size;
1169 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
1170 decl_offset + 1);
1171
1172 if (old_array_size != c->outputs_array_size) {
1173 c->output_semantics = reralloc(c,
1174 c->output_semantics,
1175 struct vc4_varying_semantic,
1176 c->outputs_array_size);
1177 }
1178
1179 c->output_semantics[decl_offset].semantic = semantic_name;
1180 c->output_semantics[decl_offset].index = semantic_index;
1181 c->output_semantics[decl_offset].swizzle = semantic_swizzle;
1182 }
1183
1184 static void
1185 add_array_info(struct vc4_compile *c, uint32_t array_id,
1186 uint32_t start, uint32_t size)
1187 {
1188 if (array_id >= c->ubo_ranges_array_size) {
1189 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
1190 array_id + 1);
1191 c->ubo_ranges = reralloc(c, c->ubo_ranges,
1192 struct vc4_compiler_ubo_range,
1193 c->ubo_ranges_array_size);
1194 }
1195
1196 c->ubo_ranges[array_id].dst_offset = 0;
1197 c->ubo_ranges[array_id].src_offset = start;
1198 c->ubo_ranges[array_id].size = size;
1199 c->ubo_ranges[array_id].used = false;
1200 }
1201
1202 static void
1203 emit_tgsi_declaration(struct vc4_compile *c,
1204 struct tgsi_full_declaration *decl)
1205 {
1206 switch (decl->Declaration.File) {
1207 case TGSI_FILE_TEMPORARY: {
1208 uint32_t old_size = c->temps_array_size;
1209 resize_qreg_array(c, &c->temps, &c->temps_array_size,
1210 (decl->Range.Last + 1) * 4);
1211
1212 for (int i = old_size; i < c->temps_array_size; i++)
1213 c->temps[i] = qir_uniform_ui(c, 0);
1214 break;
1215 }
1216
1217 case TGSI_FILE_INPUT:
1218 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1219 (decl->Range.Last + 1) * 4);
1220
1221 for (int i = decl->Range.First;
1222 i <= decl->Range.Last;
1223 i++) {
1224 if (c->stage == QSTAGE_FRAG) {
1225 if (decl->Semantic.Name ==
1226 TGSI_SEMANTIC_POSITION) {
1227 emit_fragcoord_input(c, i);
1228 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
1229 emit_face_input(c, i);
1230 } else if (decl->Semantic.Name == TGSI_SEMANTIC_GENERIC &&
1231 (c->fs_key->point_sprite_mask &
1232 (1 << decl->Semantic.Index))) {
1233 emit_point_coord_input(c, i);
1234 } else {
1235 emit_fragment_input(c, i, decl);
1236 }
1237 } else {
1238 emit_vertex_input(c, i);
1239 }
1240 }
1241 break;
1242
1243 case TGSI_FILE_OUTPUT: {
1244 for (int i = 0; i < 4; i++) {
1245 add_output(c,
1246 decl->Range.First * 4 + i,
1247 decl->Semantic.Name,
1248 decl->Semantic.Index,
1249 i);
1250 }
1251
1252 switch (decl->Semantic.Name) {
1253 case TGSI_SEMANTIC_POSITION:
1254 c->output_position_index = decl->Range.First * 4;
1255 break;
1256 case TGSI_SEMANTIC_CLIPVERTEX:
1257 c->output_clipvertex_index = decl->Range.First * 4;
1258 break;
1259 case TGSI_SEMANTIC_COLOR:
1260 c->output_color_index = decl->Range.First * 4;
1261 break;
1262 case TGSI_SEMANTIC_PSIZE:
1263 c->output_point_size_index = decl->Range.First * 4;
1264 break;
1265 }
1266
1267 break;
1268
1269 case TGSI_FILE_CONSTANT:
1270 add_array_info(c,
1271 decl->Array.ArrayID,
1272 decl->Range.First * 16,
1273 (decl->Range.Last -
1274 decl->Range.First + 1) * 16);
1275 break;
1276 }
1277 }
1278 }
1279
1280 static void
1281 emit_tgsi_instruction(struct vc4_compile *c,
1282 struct tgsi_full_instruction *tgsi_inst)
1283 {
1284 static const struct {
1285 enum qop op;
1286 struct qreg (*func)(struct vc4_compile *c,
1287 struct tgsi_full_instruction *tgsi_inst,
1288 enum qop op,
1289 struct qreg *src, int i);
1290 } op_trans[] = {
1291 [TGSI_OPCODE_MOV] = { QOP_MOV, tgsi_to_qir_alu },
1292 [TGSI_OPCODE_ABS] = { 0, tgsi_to_qir_abs },
1293 [TGSI_OPCODE_MUL] = { QOP_FMUL, tgsi_to_qir_alu },
1294 [TGSI_OPCODE_ADD] = { QOP_FADD, tgsi_to_qir_alu },
1295 [TGSI_OPCODE_SUB] = { QOP_FSUB, tgsi_to_qir_alu },
1296 [TGSI_OPCODE_MIN] = { QOP_FMIN, tgsi_to_qir_alu },
1297 [TGSI_OPCODE_MAX] = { QOP_FMAX, tgsi_to_qir_alu },
1298 [TGSI_OPCODE_F2I] = { QOP_FTOI, tgsi_to_qir_alu },
1299 [TGSI_OPCODE_I2F] = { QOP_ITOF, tgsi_to_qir_alu },
1300 [TGSI_OPCODE_UADD] = { QOP_ADD, tgsi_to_qir_alu },
1301 [TGSI_OPCODE_USHR] = { QOP_SHR, tgsi_to_qir_alu },
1302 [TGSI_OPCODE_ISHR] = { QOP_ASR, tgsi_to_qir_alu },
1303 [TGSI_OPCODE_SHL] = { QOP_SHL, tgsi_to_qir_alu },
1304 [TGSI_OPCODE_IMIN] = { QOP_MIN, tgsi_to_qir_alu },
1305 [TGSI_OPCODE_IMAX] = { QOP_MAX, tgsi_to_qir_alu },
1306 [TGSI_OPCODE_AND] = { QOP_AND, tgsi_to_qir_alu },
1307 [TGSI_OPCODE_OR] = { QOP_OR, tgsi_to_qir_alu },
1308 [TGSI_OPCODE_XOR] = { QOP_XOR, tgsi_to_qir_alu },
1309 [TGSI_OPCODE_NOT] = { QOP_NOT, tgsi_to_qir_alu },
1310
1311 [TGSI_OPCODE_UMUL] = { 0, tgsi_to_qir_umul },
1312 [TGSI_OPCODE_UMAD] = { 0, tgsi_to_qir_umad },
1313 [TGSI_OPCODE_IDIV] = { 0, tgsi_to_qir_idiv },
1314 [TGSI_OPCODE_INEG] = { 0, tgsi_to_qir_ineg },
1315
1316 [TGSI_OPCODE_SEQ] = { 0, tgsi_to_qir_seq },
1317 [TGSI_OPCODE_SNE] = { 0, tgsi_to_qir_sne },
1318 [TGSI_OPCODE_SGE] = { 0, tgsi_to_qir_sge },
1319 [TGSI_OPCODE_SLT] = { 0, tgsi_to_qir_slt },
1320 [TGSI_OPCODE_FSEQ] = { 0, tgsi_to_qir_fseq },
1321 [TGSI_OPCODE_FSNE] = { 0, tgsi_to_qir_fsne },
1322 [TGSI_OPCODE_FSGE] = { 0, tgsi_to_qir_fsge },
1323 [TGSI_OPCODE_FSLT] = { 0, tgsi_to_qir_fslt },
1324 [TGSI_OPCODE_USEQ] = { 0, tgsi_to_qir_useq },
1325 [TGSI_OPCODE_USNE] = { 0, tgsi_to_qir_usne },
1326 [TGSI_OPCODE_ISGE] = { 0, tgsi_to_qir_isge },
1327 [TGSI_OPCODE_ISLT] = { 0, tgsi_to_qir_islt },
1328
1329 [TGSI_OPCODE_CMP] = { 0, tgsi_to_qir_cmp },
1330 [TGSI_OPCODE_UCMP] = { 0, tgsi_to_qir_ucmp },
1331 [TGSI_OPCODE_MAD] = { 0, tgsi_to_qir_mad },
1332 [TGSI_OPCODE_RCP] = { QOP_RCP, tgsi_to_qir_rcp },
1333 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_rsq },
1334 [TGSI_OPCODE_EX2] = { QOP_EXP2, tgsi_to_qir_scalar },
1335 [TGSI_OPCODE_LG2] = { QOP_LOG2, tgsi_to_qir_scalar },
1336 [TGSI_OPCODE_LRP] = { 0, tgsi_to_qir_lrp },
1337 [TGSI_OPCODE_TRUNC] = { 0, tgsi_to_qir_trunc },
1338 [TGSI_OPCODE_CEIL] = { 0, tgsi_to_qir_ceil },
1339 [TGSI_OPCODE_FRC] = { 0, tgsi_to_qir_frc },
1340 [TGSI_OPCODE_FLR] = { 0, tgsi_to_qir_flr },
1341 [TGSI_OPCODE_SIN] = { 0, tgsi_to_qir_sin },
1342 [TGSI_OPCODE_COS] = { 0, tgsi_to_qir_cos },
1343 [TGSI_OPCODE_CLAMP] = { 0, tgsi_to_qir_clamp },
1344 [TGSI_OPCODE_SSG] = { 0, tgsi_to_qir_ssg },
1345 [TGSI_OPCODE_ARL] = { 0, tgsi_to_qir_arl },
1346 [TGSI_OPCODE_UARL] = { 0, tgsi_to_qir_uarl },
1347 };
1348 static int asdf = 0;
1349 uint32_t tgsi_op = tgsi_inst->Instruction.Opcode;
1350
1351 if (tgsi_op == TGSI_OPCODE_END)
1352 return;
1353
1354 struct qreg src_regs[12];
1355 for (int s = 0; s < 3; s++) {
1356 for (int i = 0; i < 4; i++) {
1357 src_regs[4 * s + i] =
1358 get_src(c, tgsi_inst->Instruction.Opcode,
1359 &tgsi_inst->Src[s], i);
1360 }
1361 }
1362
1363 switch (tgsi_op) {
1364 case TGSI_OPCODE_TEX:
1365 case TGSI_OPCODE_TXP:
1366 case TGSI_OPCODE_TXB:
1367 case TGSI_OPCODE_TXL:
1368 tgsi_to_qir_tex(c, tgsi_inst,
1369 op_trans[tgsi_op].op, src_regs);
1370 return;
1371 case TGSI_OPCODE_KILL:
1372 c->discard = qir_uniform_f(c, 1.0);
1373 return;
1374 case TGSI_OPCODE_KILL_IF:
1375 for (int i = 0; i < 4; i++)
1376 tgsi_to_qir_kill_if(c, src_regs, i);
1377 return;
1378 default:
1379 break;
1380 }
1381
1382 if (tgsi_op > ARRAY_SIZE(op_trans) || !(op_trans[tgsi_op].func)) {
1383 fprintf(stderr, "unknown tgsi inst: ");
1384 tgsi_dump_instruction(tgsi_inst, asdf++);
1385 fprintf(stderr, "\n");
1386 abort();
1387 }
1388
1389 for (int i = 0; i < 4; i++) {
1390 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
1391 continue;
1392
1393 struct qreg result;
1394
1395 result = op_trans[tgsi_op].func(c, tgsi_inst,
1396 op_trans[tgsi_op].op,
1397 src_regs, i);
1398
1399 if (tgsi_inst->Instruction.Saturate) {
1400 float low = (tgsi_inst->Instruction.Saturate ==
1401 TGSI_SAT_MINUS_PLUS_ONE ? -1.0 : 0.0);
1402 result = qir_FMAX(c,
1403 qir_FMIN(c,
1404 result,
1405 qir_uniform_f(c, 1.0)),
1406 qir_uniform_f(c, low));
1407 }
1408
1409 update_dst(c, tgsi_inst, i, result);
1410 }
1411 }
1412
1413 static void
1414 parse_tgsi_immediate(struct vc4_compile *c, struct tgsi_full_immediate *imm)
1415 {
1416 for (int i = 0; i < 4; i++) {
1417 unsigned n = c->num_consts++;
1418 resize_qreg_array(c, &c->consts, &c->consts_array_size, n + 1);
1419 c->consts[n] = qir_uniform_ui(c, imm->u[i].Uint);
1420 }
1421 }
1422
1423 static struct qreg
1424 vc4_blend_channel(struct vc4_compile *c,
1425 struct qreg *dst,
1426 struct qreg *src,
1427 struct qreg val,
1428 unsigned factor,
1429 int channel)
1430 {
1431 switch(factor) {
1432 case PIPE_BLENDFACTOR_ONE:
1433 return val;
1434 case PIPE_BLENDFACTOR_SRC_COLOR:
1435 return qir_FMUL(c, val, src[channel]);
1436 case PIPE_BLENDFACTOR_SRC_ALPHA:
1437 return qir_FMUL(c, val, src[3]);
1438 case PIPE_BLENDFACTOR_DST_ALPHA:
1439 return qir_FMUL(c, val, dst[3]);
1440 case PIPE_BLENDFACTOR_DST_COLOR:
1441 return qir_FMUL(c, val, dst[channel]);
1442 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
1443 if (channel != 3) {
1444 return qir_FMUL(c,
1445 val,
1446 qir_FMIN(c,
1447 src[3],
1448 qir_FSUB(c,
1449 qir_uniform_f(c, 1.0),
1450 dst[3])));
1451 } else {
1452 return val;
1453 }
1454 case PIPE_BLENDFACTOR_CONST_COLOR:
1455 return qir_FMUL(c, val,
1456 get_temp_for_uniform(c,
1457 QUNIFORM_BLEND_CONST_COLOR,
1458 channel));
1459 case PIPE_BLENDFACTOR_CONST_ALPHA:
1460 return qir_FMUL(c, val,
1461 get_temp_for_uniform(c,
1462 QUNIFORM_BLEND_CONST_COLOR,
1463 3));
1464 case PIPE_BLENDFACTOR_ZERO:
1465 return qir_uniform_f(c, 0.0);
1466 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
1467 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1468 src[channel]));
1469 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
1470 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1471 src[3]));
1472 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
1473 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1474 dst[3]));
1475 case PIPE_BLENDFACTOR_INV_DST_COLOR:
1476 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1477 dst[channel]));
1478 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
1479 return qir_FMUL(c, val,
1480 qir_FSUB(c, qir_uniform_f(c, 1.0),
1481 get_temp_for_uniform(c,
1482 QUNIFORM_BLEND_CONST_COLOR,
1483 channel)));
1484 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
1485 return qir_FMUL(c, val,
1486 qir_FSUB(c, qir_uniform_f(c, 1.0),
1487 get_temp_for_uniform(c,
1488 QUNIFORM_BLEND_CONST_COLOR,
1489 3)));
1490
1491 default:
1492 case PIPE_BLENDFACTOR_SRC1_COLOR:
1493 case PIPE_BLENDFACTOR_SRC1_ALPHA:
1494 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
1495 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
1496 /* Unsupported. */
1497 fprintf(stderr, "Unknown blend factor %d\n", factor);
1498 return val;
1499 }
1500 }
1501
1502 static struct qreg
1503 vc4_blend_func(struct vc4_compile *c,
1504 struct qreg src, struct qreg dst,
1505 unsigned func)
1506 {
1507 switch (func) {
1508 case PIPE_BLEND_ADD:
1509 return qir_FADD(c, src, dst);
1510 case PIPE_BLEND_SUBTRACT:
1511 return qir_FSUB(c, src, dst);
1512 case PIPE_BLEND_REVERSE_SUBTRACT:
1513 return qir_FSUB(c, dst, src);
1514 case PIPE_BLEND_MIN:
1515 return qir_FMIN(c, src, dst);
1516 case PIPE_BLEND_MAX:
1517 return qir_FMAX(c, src, dst);
1518
1519 default:
1520 /* Unsupported. */
1521 fprintf(stderr, "Unknown blend func %d\n", func);
1522 return src;
1523
1524 }
1525 }
1526
1527 /**
1528 * Implements fixed function blending in shader code.
1529 *
1530 * VC4 doesn't have any hardware support for blending. Instead, you read the
1531 * current contents of the destination from the tile buffer after having
1532 * waited for the scoreboard (which is handled by vc4_qpu_emit.c), then do
1533 * math using your output color and that destination value, and update the
1534 * output color appropriately.
1535 */
1536 static void
1537 vc4_blend(struct vc4_compile *c, struct qreg *result,
1538 struct qreg *dst_color, struct qreg *src_color)
1539 {
1540 struct pipe_rt_blend_state *blend = &c->fs_key->blend;
1541
1542 if (!blend->blend_enable) {
1543 for (int i = 0; i < 4; i++)
1544 result[i] = src_color[i];
1545 return;
1546 }
1547
1548 struct qreg src_blend[4], dst_blend[4];
1549 for (int i = 0; i < 3; i++) {
1550 src_blend[i] = vc4_blend_channel(c,
1551 dst_color, src_color,
1552 src_color[i],
1553 blend->rgb_src_factor, i);
1554 dst_blend[i] = vc4_blend_channel(c,
1555 dst_color, src_color,
1556 dst_color[i],
1557 blend->rgb_dst_factor, i);
1558 }
1559 src_blend[3] = vc4_blend_channel(c,
1560 dst_color, src_color,
1561 src_color[3],
1562 blend->alpha_src_factor, 3);
1563 dst_blend[3] = vc4_blend_channel(c,
1564 dst_color, src_color,
1565 dst_color[3],
1566 blend->alpha_dst_factor, 3);
1567
1568 for (int i = 0; i < 3; i++) {
1569 result[i] = vc4_blend_func(c,
1570 src_blend[i], dst_blend[i],
1571 blend->rgb_func);
1572 }
1573 result[3] = vc4_blend_func(c,
1574 src_blend[3], dst_blend[3],
1575 blend->alpha_func);
1576 }
1577
1578 static void
1579 clip_distance_discard(struct vc4_compile *c)
1580 {
1581 for (int i = 0; i < PIPE_MAX_CLIP_PLANES; i++) {
1582 if (!(c->key->ucp_enables & (1 << i)))
1583 continue;
1584
1585 struct qreg dist = emit_fragment_varying(c,
1586 TGSI_SEMANTIC_CLIPDIST,
1587 i,
1588 TGSI_SWIZZLE_X);
1589
1590 qir_SF(c, dist);
1591
1592 if (c->discard.file == QFILE_NULL)
1593 c->discard = qir_uniform_f(c, 0.0);
1594
1595 c->discard = qir_SEL_X_Y_NS(c, qir_uniform_f(c, 1.0),
1596 c->discard);
1597 }
1598 }
1599
1600 static void
1601 alpha_test_discard(struct vc4_compile *c)
1602 {
1603 struct qreg src_alpha;
1604 struct qreg alpha_ref = get_temp_for_uniform(c, QUNIFORM_ALPHA_REF, 0);
1605
1606 if (!c->fs_key->alpha_test)
1607 return;
1608
1609 if (c->output_color_index != -1)
1610 src_alpha = c->outputs[c->output_color_index + 3];
1611 else
1612 src_alpha = qir_uniform_f(c, 1.0);
1613
1614 if (c->discard.file == QFILE_NULL)
1615 c->discard = qir_uniform_f(c, 0.0);
1616
1617 switch (c->fs_key->alpha_test_func) {
1618 case PIPE_FUNC_NEVER:
1619 c->discard = qir_uniform_f(c, 1.0);
1620 break;
1621 case PIPE_FUNC_ALWAYS:
1622 break;
1623 case PIPE_FUNC_EQUAL:
1624 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1625 c->discard = qir_SEL_X_Y_ZS(c, c->discard,
1626 qir_uniform_f(c, 1.0));
1627 break;
1628 case PIPE_FUNC_NOTEQUAL:
1629 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1630 c->discard = qir_SEL_X_Y_ZC(c, c->discard,
1631 qir_uniform_f(c, 1.0));
1632 break;
1633 case PIPE_FUNC_GREATER:
1634 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1635 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1636 qir_uniform_f(c, 1.0));
1637 break;
1638 case PIPE_FUNC_GEQUAL:
1639 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1640 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1641 qir_uniform_f(c, 1.0));
1642 break;
1643 case PIPE_FUNC_LESS:
1644 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1645 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1646 qir_uniform_f(c, 1.0));
1647 break;
1648 case PIPE_FUNC_LEQUAL:
1649 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1650 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1651 qir_uniform_f(c, 1.0));
1652 break;
1653 }
1654 }
1655
1656 static struct qreg
1657 vc4_logicop(struct vc4_compile *c, struct qreg src, struct qreg dst)
1658 {
1659 switch (c->fs_key->logicop_func) {
1660 case PIPE_LOGICOP_CLEAR:
1661 return qir_uniform_f(c, 0.0);
1662 case PIPE_LOGICOP_NOR:
1663 return qir_NOT(c, qir_OR(c, src, dst));
1664 case PIPE_LOGICOP_AND_INVERTED:
1665 return qir_AND(c, qir_NOT(c, src), dst);
1666 case PIPE_LOGICOP_COPY_INVERTED:
1667 return qir_NOT(c, src);
1668 case PIPE_LOGICOP_AND_REVERSE:
1669 return qir_AND(c, src, qir_NOT(c, dst));
1670 case PIPE_LOGICOP_INVERT:
1671 return qir_NOT(c, dst);
1672 case PIPE_LOGICOP_XOR:
1673 return qir_XOR(c, src, dst);
1674 case PIPE_LOGICOP_NAND:
1675 return qir_NOT(c, qir_AND(c, src, dst));
1676 case PIPE_LOGICOP_AND:
1677 return qir_AND(c, src, dst);
1678 case PIPE_LOGICOP_EQUIV:
1679 return qir_NOT(c, qir_XOR(c, src, dst));
1680 case PIPE_LOGICOP_NOOP:
1681 return dst;
1682 case PIPE_LOGICOP_OR_INVERTED:
1683 return qir_OR(c, qir_NOT(c, src), dst);
1684 case PIPE_LOGICOP_OR_REVERSE:
1685 return qir_OR(c, src, qir_NOT(c, dst));
1686 case PIPE_LOGICOP_OR:
1687 return qir_OR(c, src, dst);
1688 case PIPE_LOGICOP_SET:
1689 return qir_uniform_ui(c, ~0);
1690 case PIPE_LOGICOP_COPY:
1691 default:
1692 return src;
1693 }
1694 }
1695
1696 static void
1697 emit_frag_end(struct vc4_compile *c)
1698 {
1699 clip_distance_discard(c);
1700 alpha_test_discard(c);
1701
1702 enum pipe_format color_format = c->fs_key->color_format;
1703 const uint8_t *format_swiz = vc4_get_format_swizzle(color_format);
1704 struct qreg tlb_read_color[4] = { c->undef, c->undef, c->undef, c->undef };
1705 struct qreg dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1706 struct qreg linear_dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1707 struct qreg packed_dst_color = c->undef;
1708
1709 if (c->fs_key->blend.blend_enable ||
1710 c->fs_key->blend.colormask != 0xf ||
1711 c->fs_key->logicop_func != PIPE_LOGICOP_COPY) {
1712 struct qreg r4 = qir_TLB_COLOR_READ(c);
1713 for (int i = 0; i < 4; i++)
1714 tlb_read_color[i] = qir_R4_UNPACK(c, r4, i);
1715 for (int i = 0; i < 4; i++) {
1716 dst_color[i] = get_swizzled_channel(c,
1717 tlb_read_color,
1718 format_swiz[i]);
1719 if (util_format_is_srgb(color_format) && i != 3) {
1720 linear_dst_color[i] =
1721 qir_srgb_decode(c, dst_color[i]);
1722 } else {
1723 linear_dst_color[i] = dst_color[i];
1724 }
1725 }
1726
1727 /* Save the packed value for logic ops. Can't reuse r4
1728 * becuase other things might smash it (like sRGB)
1729 */
1730 packed_dst_color = qir_MOV(c, r4);
1731 }
1732
1733 struct qreg blend_color[4];
1734 struct qreg undef_array[4] = {
1735 c->undef, c->undef, c->undef, c->undef
1736 };
1737 vc4_blend(c, blend_color, linear_dst_color,
1738 (c->output_color_index != -1 ?
1739 c->outputs + c->output_color_index :
1740 undef_array));
1741
1742 if (util_format_is_srgb(color_format)) {
1743 for (int i = 0; i < 3; i++)
1744 blend_color[i] = qir_srgb_encode(c, blend_color[i]);
1745 }
1746
1747 /* If the bit isn't set in the color mask, then just return the
1748 * original dst color, instead.
1749 */
1750 for (int i = 0; i < 4; i++) {
1751 if (!(c->fs_key->blend.colormask & (1 << i))) {
1752 blend_color[i] = dst_color[i];
1753 }
1754 }
1755
1756 /* Debug: Sometimes you're getting a black output and just want to see
1757 * if the FS is getting executed at all. Spam magenta into the color
1758 * output.
1759 */
1760 if (0) {
1761 blend_color[0] = qir_uniform_f(c, 1.0);
1762 blend_color[1] = qir_uniform_f(c, 0.0);
1763 blend_color[2] = qir_uniform_f(c, 1.0);
1764 blend_color[3] = qir_uniform_f(c, 0.5);
1765 }
1766
1767 struct qreg swizzled_outputs[4];
1768 for (int i = 0; i < 4; i++) {
1769 swizzled_outputs[i] = get_swizzled_channel(c, blend_color,
1770 format_swiz[i]);
1771 }
1772
1773 if (c->discard.file != QFILE_NULL)
1774 qir_TLB_DISCARD_SETUP(c, c->discard);
1775
1776 if (c->fs_key->stencil_enabled) {
1777 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 0));
1778 if (c->fs_key->stencil_twoside) {
1779 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 1));
1780 }
1781 if (c->fs_key->stencil_full_writemasks) {
1782 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 2));
1783 }
1784 }
1785
1786 if (c->fs_key->depth_enabled) {
1787 struct qreg z;
1788 if (c->output_position_index != -1) {
1789 z = qir_FTOI(c, qir_FMUL(c, c->outputs[c->output_position_index + 2],
1790 qir_uniform_f(c, 0xffffff)));
1791 } else {
1792 z = qir_FRAG_Z(c);
1793 }
1794 qir_TLB_Z_WRITE(c, z);
1795 }
1796
1797 bool color_written = false;
1798 for (int i = 0; i < 4; i++) {
1799 if (swizzled_outputs[i].file != QFILE_NULL)
1800 color_written = true;
1801 }
1802
1803 struct qreg packed_color;
1804 if (color_written) {
1805 /* Fill in any undefined colors. The simulator will assertion
1806 * fail if we read something that wasn't written, and I don't
1807 * know what hardware does.
1808 */
1809 for (int i = 0; i < 4; i++) {
1810 if (swizzled_outputs[i].file == QFILE_NULL)
1811 swizzled_outputs[i] = qir_uniform_f(c, 0.0);
1812 }
1813 packed_color = qir_get_temp(c);
1814 qir_emit(c, qir_inst4(QOP_PACK_COLORS, packed_color,
1815 swizzled_outputs[0],
1816 swizzled_outputs[1],
1817 swizzled_outputs[2],
1818 swizzled_outputs[3]));
1819 } else {
1820 packed_color = qir_uniform_ui(c, 0);
1821 }
1822
1823
1824 if (c->fs_key->logicop_func != PIPE_LOGICOP_COPY) {
1825 packed_color = vc4_logicop(c, packed_color, packed_dst_color);
1826 }
1827
1828 qir_emit(c, qir_inst(QOP_TLB_COLOR_WRITE, c->undef,
1829 packed_color, c->undef));
1830 }
1831
1832 static void
1833 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1834 {
1835 struct qreg xyi[2];
1836
1837 for (int i = 0; i < 2; i++) {
1838 struct qreg scale =
1839 add_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1840
1841 xyi[i] = qir_FTOI(c, qir_FMUL(c,
1842 qir_FMUL(c,
1843 c->outputs[c->output_position_index + i],
1844 scale),
1845 rcp_w));
1846 }
1847
1848 qir_VPM_WRITE(c, qir_PACK_SCALED(c, xyi[0], xyi[1]));
1849 }
1850
1851 static void
1852 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1853 {
1854 struct qreg zscale = add_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1855 struct qreg zoffset = add_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1856
1857 qir_VPM_WRITE(c, qir_FMUL(c, qir_FADD(c, qir_FMUL(c,
1858 c->outputs[c->output_position_index + 2],
1859 zscale),
1860 zoffset),
1861 rcp_w));
1862 }
1863
1864 static void
1865 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1866 {
1867 qir_VPM_WRITE(c, rcp_w);
1868 }
1869
1870 static void
1871 emit_point_size_write(struct vc4_compile *c)
1872 {
1873 struct qreg point_size;
1874
1875 if (c->output_point_size_index)
1876 point_size = c->outputs[c->output_point_size_index + 3];
1877 else
1878 point_size = qir_uniform_f(c, 1.0);
1879
1880 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1881 * BCM21553).
1882 */
1883 point_size = qir_FMAX(c, point_size, qir_uniform_f(c, .125));
1884
1885 qir_VPM_WRITE(c, point_size);
1886 }
1887
1888 /**
1889 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1890 *
1891 * The simulator insists that there be at least one vertex attribute, so
1892 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also
1893 * insists that all vertex attributes loaded get read by the VS/CS, so we have
1894 * to consume it here.
1895 */
1896 static void
1897 emit_stub_vpm_read(struct vc4_compile *c)
1898 {
1899 if (c->num_inputs)
1900 return;
1901
1902 for (int i = 0; i < 4; i++) {
1903 qir_emit(c, qir_inst(QOP_VPM_READ,
1904 qir_get_temp(c),
1905 c->undef,
1906 c->undef));
1907 c->num_inputs++;
1908 }
1909 }
1910
1911 static void
1912 emit_ucp_clipdistance(struct vc4_compile *c)
1913 {
1914 unsigned cv;
1915 if (c->output_clipvertex_index != -1)
1916 cv = c->output_clipvertex_index;
1917 else if (c->output_position_index != -1)
1918 cv = c->output_position_index;
1919 else
1920 return;
1921
1922 for (int plane = 0; plane < PIPE_MAX_CLIP_PLANES; plane++) {
1923 if (!(c->key->ucp_enables & (1 << plane)))
1924 continue;
1925
1926 /* Pick the next outputs[] that hasn't been written to, since
1927 * there are no other program writes left to be processed at
1928 * this point. If something had been declared but not written
1929 * (like a w component), we'll just smash over the top of it.
1930 */
1931 uint32_t output_index = c->num_outputs++;
1932 add_output(c, output_index,
1933 TGSI_SEMANTIC_CLIPDIST,
1934 plane,
1935 TGSI_SWIZZLE_X);
1936
1937
1938 struct qreg dist = qir_uniform_f(c, 0.0);
1939 for (int i = 0; i < 4; i++) {
1940 struct qreg pos_chan = c->outputs[cv + i];
1941 struct qreg ucp =
1942 add_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1943 plane * 4 + i);
1944 dist = qir_FADD(c, dist, qir_FMUL(c, pos_chan, ucp));
1945 }
1946
1947 c->outputs[output_index] = dist;
1948 }
1949 }
1950
1951 static void
1952 emit_vert_end(struct vc4_compile *c,
1953 struct vc4_varying_semantic *fs_inputs,
1954 uint32_t num_fs_inputs)
1955 {
1956 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1957
1958 emit_stub_vpm_read(c);
1959 emit_ucp_clipdistance(c);
1960
1961 emit_scaled_viewport_write(c, rcp_w);
1962 emit_zs_write(c, rcp_w);
1963 emit_rcp_wc_write(c, rcp_w);
1964 if (c->vs_key->per_vertex_point_size)
1965 emit_point_size_write(c);
1966
1967 for (int i = 0; i < num_fs_inputs; i++) {
1968 struct vc4_varying_semantic *input = &fs_inputs[i];
1969 int j;
1970
1971 for (j = 0; j < c->num_outputs; j++) {
1972 struct vc4_varying_semantic *output =
1973 &c->output_semantics[j];
1974
1975 if (input->semantic == output->semantic &&
1976 input->index == output->index &&
1977 input->swizzle == output->swizzle) {
1978 qir_VPM_WRITE(c, c->outputs[j]);
1979 break;
1980 }
1981 }
1982 /* Emit padding if we didn't find a declared VS output for
1983 * this FS input.
1984 */
1985 if (j == c->num_outputs)
1986 qir_VPM_WRITE(c, qir_uniform_f(c, 0.0));
1987 }
1988 }
1989
1990 static void
1991 emit_coord_end(struct vc4_compile *c)
1992 {
1993 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1994
1995 emit_stub_vpm_read(c);
1996
1997 for (int i = 0; i < 4; i++)
1998 qir_VPM_WRITE(c, c->outputs[c->output_position_index + i]);
1999
2000 emit_scaled_viewport_write(c, rcp_w);
2001 emit_zs_write(c, rcp_w);
2002 emit_rcp_wc_write(c, rcp_w);
2003 if (c->vs_key->per_vertex_point_size)
2004 emit_point_size_write(c);
2005 }
2006
2007 static struct vc4_compile *
2008 vc4_shader_tgsi_to_qir(struct vc4_context *vc4, enum qstage stage,
2009 struct vc4_key *key)
2010 {
2011 struct vc4_compile *c = qir_compile_init();
2012 int ret;
2013
2014 c->stage = stage;
2015 for (int i = 0; i < 4; i++)
2016 c->addr[i] = qir_uniform_f(c, 0.0);
2017
2018 c->shader_state = &key->shader_state->base;
2019 c->program_id = key->shader_state->program_id;
2020 c->variant_id = key->shader_state->compiled_variant_count++;
2021
2022 c->key = key;
2023 switch (stage) {
2024 case QSTAGE_FRAG:
2025 c->fs_key = (struct vc4_fs_key *)key;
2026 if (c->fs_key->is_points) {
2027 c->point_x = emit_fragment_varying(c, ~0, ~0, 0);
2028 c->point_y = emit_fragment_varying(c, ~0, ~0, 0);
2029 } else if (c->fs_key->is_lines) {
2030 c->line_x = emit_fragment_varying(c, ~0, ~0, 0);
2031 }
2032 break;
2033 case QSTAGE_VERT:
2034 c->vs_key = (struct vc4_vs_key *)key;
2035 break;
2036 case QSTAGE_COORD:
2037 c->vs_key = (struct vc4_vs_key *)key;
2038 break;
2039 }
2040
2041 const struct tgsi_token *tokens = key->shader_state->base.tokens;
2042 if (c->fs_key && c->fs_key->light_twoside) {
2043 if (!key->shader_state->twoside_tokens) {
2044 const struct tgsi_lowering_config lowering_config = {
2045 .color_two_side = true,
2046 };
2047 struct tgsi_shader_info info;
2048 key->shader_state->twoside_tokens =
2049 tgsi_transform_lowering(&lowering_config,
2050 key->shader_state->base.tokens,
2051 &info);
2052
2053 /* If no transformation occurred, then NULL is
2054 * returned and we just use our original tokens.
2055 */
2056 if (!key->shader_state->twoside_tokens) {
2057 key->shader_state->twoside_tokens =
2058 key->shader_state->base.tokens;
2059 }
2060 }
2061 tokens = key->shader_state->twoside_tokens;
2062 }
2063
2064 ret = tgsi_parse_init(&c->parser, tokens);
2065 assert(ret == TGSI_PARSE_OK);
2066
2067 if (vc4_debug & VC4_DEBUG_TGSI) {
2068 fprintf(stderr, "%s prog %d/%d TGSI:\n",
2069 qir_get_stage_name(c->stage),
2070 c->program_id, c->variant_id);
2071 tgsi_dump(tokens, 0);
2072 }
2073
2074 while (!tgsi_parse_end_of_tokens(&c->parser)) {
2075 tgsi_parse_token(&c->parser);
2076
2077 switch (c->parser.FullToken.Token.Type) {
2078 case TGSI_TOKEN_TYPE_DECLARATION:
2079 emit_tgsi_declaration(c,
2080 &c->parser.FullToken.FullDeclaration);
2081 break;
2082
2083 case TGSI_TOKEN_TYPE_INSTRUCTION:
2084 emit_tgsi_instruction(c,
2085 &c->parser.FullToken.FullInstruction);
2086 break;
2087
2088 case TGSI_TOKEN_TYPE_IMMEDIATE:
2089 parse_tgsi_immediate(c,
2090 &c->parser.FullToken.FullImmediate);
2091 break;
2092 }
2093 }
2094
2095 switch (stage) {
2096 case QSTAGE_FRAG:
2097 emit_frag_end(c);
2098 break;
2099 case QSTAGE_VERT:
2100 emit_vert_end(c,
2101 vc4->prog.fs->input_semantics,
2102 vc4->prog.fs->num_inputs);
2103 break;
2104 case QSTAGE_COORD:
2105 emit_coord_end(c);
2106 break;
2107 }
2108
2109 tgsi_parse_free(&c->parser);
2110
2111 qir_optimize(c);
2112
2113 if (vc4_debug & VC4_DEBUG_QIR) {
2114 fprintf(stderr, "%s prog %d/%d QIR:\n",
2115 qir_get_stage_name(c->stage),
2116 c->program_id, c->variant_id);
2117 qir_dump(c);
2118 }
2119 qir_reorder_uniforms(c);
2120 vc4_generate_code(vc4, c);
2121
2122 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2123 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d instructions\n",
2124 qir_get_stage_name(c->stage),
2125 c->program_id, c->variant_id,
2126 c->qpu_inst_count);
2127 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d uniforms\n",
2128 qir_get_stage_name(c->stage),
2129 c->program_id, c->variant_id,
2130 c->num_uniforms);
2131 }
2132
2133 return c;
2134 }
2135
2136 static void *
2137 vc4_shader_state_create(struct pipe_context *pctx,
2138 const struct pipe_shader_state *cso)
2139 {
2140 struct vc4_context *vc4 = vc4_context(pctx);
2141 struct vc4_uncompiled_shader *so = CALLOC_STRUCT(vc4_uncompiled_shader);
2142 if (!so)
2143 return NULL;
2144
2145 const struct tgsi_lowering_config lowering_config = {
2146 .lower_DST = true,
2147 .lower_XPD = true,
2148 .lower_SCS = true,
2149 .lower_POW = true,
2150 .lower_LIT = true,
2151 .lower_EXP = true,
2152 .lower_LOG = true,
2153 .lower_DP4 = true,
2154 .lower_DP3 = true,
2155 .lower_DPH = true,
2156 .lower_DP2 = true,
2157 .lower_DP2A = true,
2158 };
2159
2160 struct tgsi_shader_info info;
2161 so->base.tokens = tgsi_transform_lowering(&lowering_config, cso->tokens, &info);
2162 if (!so->base.tokens)
2163 so->base.tokens = tgsi_dup_tokens(cso->tokens);
2164 so->program_id = vc4->next_uncompiled_program_id++;
2165
2166 return so;
2167 }
2168
2169 static void
2170 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
2171 struct vc4_compile *c)
2172 {
2173 int count = c->num_uniforms;
2174 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
2175
2176 uinfo->count = count;
2177 uinfo->data = ralloc_array(shader, uint32_t, count);
2178 memcpy(uinfo->data, c->uniform_data,
2179 count * sizeof(*uinfo->data));
2180 uinfo->contents = ralloc_array(shader, enum quniform_contents, count);
2181 memcpy(uinfo->contents, c->uniform_contents,
2182 count * sizeof(*uinfo->contents));
2183 uinfo->num_texture_samples = c->num_texture_samples;
2184 }
2185
2186 static struct vc4_compiled_shader *
2187 vc4_get_compiled_shader(struct vc4_context *vc4, enum qstage stage,
2188 struct vc4_key *key)
2189 {
2190 struct hash_table *ht;
2191 uint32_t key_size;
2192 if (stage == QSTAGE_FRAG) {
2193 ht = vc4->fs_cache;
2194 key_size = sizeof(struct vc4_fs_key);
2195 } else {
2196 ht = vc4->vs_cache;
2197 key_size = sizeof(struct vc4_vs_key);
2198 }
2199
2200 struct vc4_compiled_shader *shader;
2201 struct hash_entry *entry = _mesa_hash_table_search(ht, key);
2202 if (entry)
2203 return entry->data;
2204
2205 struct vc4_compile *c = vc4_shader_tgsi_to_qir(vc4, stage, key);
2206 shader = rzalloc(NULL, struct vc4_compiled_shader);
2207
2208 shader->program_id = vc4->next_compiled_program_id++;
2209 if (stage == QSTAGE_FRAG) {
2210 bool input_live[c->num_input_semantics];
2211 struct simple_node *node;
2212
2213 memset(input_live, 0, sizeof(input_live));
2214 foreach(node, &c->instructions) {
2215 struct qinst *inst = (struct qinst *)node;
2216 for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) {
2217 if (inst->src[i].file == QFILE_VARY)
2218 input_live[inst->src[i].index] = true;
2219 }
2220 }
2221
2222 shader->input_semantics = ralloc_array(shader,
2223 struct vc4_varying_semantic,
2224 c->num_input_semantics);
2225
2226 for (int i = 0; i < c->num_input_semantics; i++) {
2227 struct vc4_varying_semantic *sem = &c->input_semantics[i];
2228
2229 if (!input_live[i])
2230 continue;
2231
2232 /* Skip non-VS-output inputs. */
2233 if (sem->semantic == (uint8_t)~0)
2234 continue;
2235
2236 if (sem->semantic == TGSI_SEMANTIC_COLOR ||
2237 sem->semantic == TGSI_SEMANTIC_BCOLOR) {
2238 shader->color_inputs |= (1 << shader->num_inputs);
2239 }
2240
2241 shader->input_semantics[shader->num_inputs] = *sem;
2242 shader->num_inputs++;
2243 }
2244 } else {
2245 shader->num_inputs = c->num_inputs;
2246 }
2247
2248 copy_uniform_state_to_shader(shader, c);
2249 shader->bo = vc4_bo_alloc_mem(vc4->screen, c->qpu_insts,
2250 c->qpu_inst_count * sizeof(uint64_t),
2251 "code");
2252
2253 /* Copy the compiler UBO range state to the compiled shader, dropping
2254 * out arrays that were never referenced by an indirect load.
2255 *
2256 * (Note that QIR dead code elimination of an array access still
2257 * leaves that array alive, though)
2258 */
2259 if (c->num_ubo_ranges) {
2260 shader->num_ubo_ranges = c->num_ubo_ranges;
2261 shader->ubo_ranges = ralloc_array(shader, struct vc4_ubo_range,
2262 c->num_ubo_ranges);
2263 uint32_t j = 0;
2264 for (int i = 0; i < c->ubo_ranges_array_size; i++) {
2265 struct vc4_compiler_ubo_range *range =
2266 &c->ubo_ranges[i];
2267 if (!range->used)
2268 continue;
2269
2270 shader->ubo_ranges[j].dst_offset = range->dst_offset;
2271 shader->ubo_ranges[j].src_offset = range->src_offset;
2272 shader->ubo_ranges[j].size = range->size;
2273 shader->ubo_size += c->ubo_ranges[i].size;
2274 j++;
2275 }
2276 }
2277
2278 qir_compile_destroy(c);
2279
2280 struct vc4_key *dup_key;
2281 dup_key = ralloc_size(shader, key_size);
2282 memcpy(dup_key, key, key_size);
2283 _mesa_hash_table_insert(ht, dup_key, shader);
2284
2285 return shader;
2286 }
2287
2288 static void
2289 vc4_setup_shared_key(struct vc4_context *vc4, struct vc4_key *key,
2290 struct vc4_texture_stateobj *texstate)
2291 {
2292 for (int i = 0; i < texstate->num_textures; i++) {
2293 struct pipe_sampler_view *sampler = texstate->textures[i];
2294 struct pipe_sampler_state *sampler_state =
2295 texstate->samplers[i];
2296
2297 if (sampler) {
2298 key->tex[i].format = sampler->format;
2299 key->tex[i].swizzle[0] = sampler->swizzle_r;
2300 key->tex[i].swizzle[1] = sampler->swizzle_g;
2301 key->tex[i].swizzle[2] = sampler->swizzle_b;
2302 key->tex[i].swizzle[3] = sampler->swizzle_a;
2303 key->tex[i].compare_mode = sampler_state->compare_mode;
2304 key->tex[i].compare_func = sampler_state->compare_func;
2305 key->tex[i].wrap_s = sampler_state->wrap_s;
2306 key->tex[i].wrap_t = sampler_state->wrap_t;
2307 }
2308 }
2309
2310 key->ucp_enables = vc4->rasterizer->base.clip_plane_enable;
2311 }
2312
2313 static void
2314 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
2315 {
2316 struct vc4_fs_key local_key;
2317 struct vc4_fs_key *key = &local_key;
2318
2319 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2320 VC4_DIRTY_BLEND |
2321 VC4_DIRTY_FRAMEBUFFER |
2322 VC4_DIRTY_ZSA |
2323 VC4_DIRTY_RASTERIZER |
2324 VC4_DIRTY_FRAGTEX |
2325 VC4_DIRTY_TEXSTATE |
2326 VC4_DIRTY_PROG))) {
2327 return;
2328 }
2329
2330 memset(key, 0, sizeof(*key));
2331 vc4_setup_shared_key(vc4, &key->base, &vc4->fragtex);
2332 key->base.shader_state = vc4->prog.bind_fs;
2333 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
2334 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
2335 prim_mode <= PIPE_PRIM_LINE_STRIP);
2336 key->blend = vc4->blend->rt[0];
2337 if (vc4->blend->logicop_enable) {
2338 key->logicop_func = vc4->blend->logicop_func;
2339 } else {
2340 key->logicop_func = PIPE_LOGICOP_COPY;
2341 }
2342 if (vc4->framebuffer.cbufs[0])
2343 key->color_format = vc4->framebuffer.cbufs[0]->format;
2344
2345 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
2346 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
2347 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
2348 key->depth_enabled = (vc4->zsa->base.depth.enabled ||
2349 key->stencil_enabled);
2350 if (vc4->zsa->base.alpha.enabled) {
2351 key->alpha_test = true;
2352 key->alpha_test_func = vc4->zsa->base.alpha.func;
2353 }
2354
2355 if (key->is_points) {
2356 key->point_sprite_mask =
2357 vc4->rasterizer->base.sprite_coord_enable;
2358 key->point_coord_upper_left =
2359 (vc4->rasterizer->base.sprite_coord_mode ==
2360 PIPE_SPRITE_COORD_UPPER_LEFT);
2361 }
2362
2363 key->light_twoside = vc4->rasterizer->base.light_twoside;
2364
2365 struct vc4_compiled_shader *old_fs = vc4->prog.fs;
2366 vc4->prog.fs = vc4_get_compiled_shader(vc4, QSTAGE_FRAG, &key->base);
2367 if (vc4->prog.fs == old_fs)
2368 return;
2369
2370 if (vc4->rasterizer->base.flatshade &&
2371 old_fs && vc4->prog.fs->color_inputs != old_fs->color_inputs) {
2372 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
2373 }
2374 }
2375
2376 static void
2377 vc4_update_compiled_vs(struct vc4_context *vc4, uint8_t prim_mode)
2378 {
2379 struct vc4_vs_key local_key;
2380 struct vc4_vs_key *key = &local_key;
2381
2382 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2383 VC4_DIRTY_RASTERIZER |
2384 VC4_DIRTY_VERTTEX |
2385 VC4_DIRTY_TEXSTATE |
2386 VC4_DIRTY_VTXSTATE |
2387 VC4_DIRTY_PROG))) {
2388 return;
2389 }
2390
2391 memset(key, 0, sizeof(*key));
2392 vc4_setup_shared_key(vc4, &key->base, &vc4->verttex);
2393 key->base.shader_state = vc4->prog.bind_vs;
2394 key->compiled_fs_id = vc4->prog.fs->program_id;
2395
2396 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
2397 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
2398
2399 key->per_vertex_point_size =
2400 (prim_mode == PIPE_PRIM_POINTS &&
2401 vc4->rasterizer->base.point_size_per_vertex);
2402
2403 vc4->prog.vs = vc4_get_compiled_shader(vc4, QSTAGE_VERT, &key->base);
2404 key->is_coord = true;
2405 vc4->prog.cs = vc4_get_compiled_shader(vc4, QSTAGE_COORD, &key->base);
2406 }
2407
2408 void
2409 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
2410 {
2411 vc4_update_compiled_fs(vc4, prim_mode);
2412 vc4_update_compiled_vs(vc4, prim_mode);
2413 }
2414
2415 static uint32_t
2416 fs_cache_hash(const void *key)
2417 {
2418 return _mesa_hash_data(key, sizeof(struct vc4_fs_key));
2419 }
2420
2421 static uint32_t
2422 vs_cache_hash(const void *key)
2423 {
2424 return _mesa_hash_data(key, sizeof(struct vc4_vs_key));
2425 }
2426
2427 static bool
2428 fs_cache_compare(const void *key1, const void *key2)
2429 {
2430 return memcmp(key1, key2, sizeof(struct vc4_fs_key)) == 0;
2431 }
2432
2433 static bool
2434 vs_cache_compare(const void *key1, const void *key2)
2435 {
2436 return memcmp(key1, key2, sizeof(struct vc4_vs_key)) == 0;
2437 }
2438
2439 static void
2440 delete_from_cache_if_matches(struct hash_table *ht,
2441 struct hash_entry *entry,
2442 struct vc4_uncompiled_shader *so)
2443 {
2444 struct vc4_key *key = entry->data;
2445
2446 if (key->shader_state == so) {
2447 struct vc4_compiled_shader *shader = entry->data;
2448 _mesa_hash_table_remove(ht, entry);
2449 vc4_bo_unreference(&shader->bo);
2450 ralloc_free(shader);
2451 }
2452 }
2453
2454 static void
2455 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
2456 {
2457 struct vc4_context *vc4 = vc4_context(pctx);
2458 struct vc4_uncompiled_shader *so = hwcso;
2459
2460 struct hash_entry *entry;
2461 hash_table_foreach(vc4->fs_cache, entry)
2462 delete_from_cache_if_matches(vc4->fs_cache, entry, so);
2463 hash_table_foreach(vc4->vs_cache, entry)
2464 delete_from_cache_if_matches(vc4->vs_cache, entry, so);
2465
2466 if (so->twoside_tokens != so->base.tokens)
2467 free((void *)so->twoside_tokens);
2468 free((void *)so->base.tokens);
2469 free(so);
2470 }
2471
2472 static uint32_t translate_wrap(uint32_t p_wrap, bool using_nearest)
2473 {
2474 switch (p_wrap) {
2475 case PIPE_TEX_WRAP_REPEAT:
2476 return 0;
2477 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
2478 return 1;
2479 case PIPE_TEX_WRAP_MIRROR_REPEAT:
2480 return 2;
2481 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
2482 return 3;
2483 case PIPE_TEX_WRAP_CLAMP:
2484 return (using_nearest ? 1 : 3);
2485 default:
2486 fprintf(stderr, "Unknown wrap mode %d\n", p_wrap);
2487 assert(!"not reached");
2488 return 0;
2489 }
2490 }
2491
2492 static void
2493 write_texture_p0(struct vc4_context *vc4,
2494 struct vc4_texture_stateobj *texstate,
2495 uint32_t unit)
2496 {
2497 struct pipe_sampler_view *texture = texstate->textures[unit];
2498 struct vc4_resource *rsc = vc4_resource(texture->texture);
2499
2500 cl_reloc(vc4, &vc4->uniforms, rsc->bo,
2501 VC4_SET_FIELD(rsc->slices[0].offset >> 12, VC4_TEX_P0_OFFSET) |
2502 VC4_SET_FIELD(texture->u.tex.last_level -
2503 texture->u.tex.first_level, VC4_TEX_P0_MIPLVLS) |
2504 VC4_SET_FIELD(texture->target == PIPE_TEXTURE_CUBE,
2505 VC4_TEX_P0_CMMODE) |
2506 VC4_SET_FIELD(rsc->vc4_format & 7, VC4_TEX_P0_TYPE));
2507 }
2508
2509 static void
2510 write_texture_p1(struct vc4_context *vc4,
2511 struct vc4_texture_stateobj *texstate,
2512 uint32_t unit)
2513 {
2514 struct pipe_sampler_view *texture = texstate->textures[unit];
2515 struct vc4_resource *rsc = vc4_resource(texture->texture);
2516 struct pipe_sampler_state *sampler = texstate->samplers[unit];
2517 static const uint8_t minfilter_map[6] = {
2518 VC4_TEX_P1_MINFILT_NEAR_MIP_NEAR,
2519 VC4_TEX_P1_MINFILT_LIN_MIP_NEAR,
2520 VC4_TEX_P1_MINFILT_NEAR_MIP_LIN,
2521 VC4_TEX_P1_MINFILT_LIN_MIP_LIN,
2522 VC4_TEX_P1_MINFILT_NEAREST,
2523 VC4_TEX_P1_MINFILT_LINEAR,
2524 };
2525 static const uint32_t magfilter_map[] = {
2526 [PIPE_TEX_FILTER_NEAREST] = VC4_TEX_P1_MAGFILT_NEAREST,
2527 [PIPE_TEX_FILTER_LINEAR] = VC4_TEX_P1_MAGFILT_LINEAR,
2528 };
2529
2530 bool either_nearest =
2531 (sampler->mag_img_filter == PIPE_TEX_MIPFILTER_NEAREST ||
2532 sampler->min_img_filter == PIPE_TEX_MIPFILTER_NEAREST);
2533
2534 cl_u32(&vc4->uniforms,
2535 VC4_SET_FIELD(rsc->vc4_format >> 4, VC4_TEX_P1_TYPE4) |
2536 VC4_SET_FIELD(texture->texture->height0 & 2047,
2537 VC4_TEX_P1_HEIGHT) |
2538 VC4_SET_FIELD(texture->texture->width0 & 2047,
2539 VC4_TEX_P1_WIDTH) |
2540 VC4_SET_FIELD(magfilter_map[sampler->mag_img_filter],
2541 VC4_TEX_P1_MAGFILT) |
2542 VC4_SET_FIELD(minfilter_map[sampler->min_mip_filter * 2 +
2543 sampler->min_img_filter],
2544 VC4_TEX_P1_MINFILT) |
2545 VC4_SET_FIELD(translate_wrap(sampler->wrap_s, either_nearest),
2546 VC4_TEX_P1_WRAP_S) |
2547 VC4_SET_FIELD(translate_wrap(sampler->wrap_t, either_nearest),
2548 VC4_TEX_P1_WRAP_T));
2549 }
2550
2551 static void
2552 write_texture_p2(struct vc4_context *vc4,
2553 struct vc4_texture_stateobj *texstate,
2554 uint32_t data)
2555 {
2556 uint32_t unit = data & 0xffff;
2557 struct pipe_sampler_view *texture = texstate->textures[unit];
2558 struct vc4_resource *rsc = vc4_resource(texture->texture);
2559
2560 cl_u32(&vc4->uniforms,
2561 VC4_SET_FIELD(VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE,
2562 VC4_TEX_P2_PTYPE) |
2563 VC4_SET_FIELD(rsc->cube_map_stride >> 12, VC4_TEX_P2_CMST) |
2564 VC4_SET_FIELD((data >> 16) & 1, VC4_TEX_P2_BSLOD));
2565 }
2566
2567
2568 #define SWIZ(x,y,z,w) { \
2569 UTIL_FORMAT_SWIZZLE_##x, \
2570 UTIL_FORMAT_SWIZZLE_##y, \
2571 UTIL_FORMAT_SWIZZLE_##z, \
2572 UTIL_FORMAT_SWIZZLE_##w \
2573 }
2574
2575 static void
2576 write_texture_border_color(struct vc4_context *vc4,
2577 struct vc4_texture_stateobj *texstate,
2578 uint32_t unit)
2579 {
2580 struct pipe_sampler_state *sampler = texstate->samplers[unit];
2581 struct pipe_sampler_view *texture = texstate->textures[unit];
2582 struct vc4_resource *rsc = vc4_resource(texture->texture);
2583 union util_color uc;
2584
2585 const struct util_format_description *tex_format_desc =
2586 util_format_description(texture->format);
2587
2588 float border_color[4];
2589 for (int i = 0; i < 4; i++)
2590 border_color[i] = sampler->border_color.f[i];
2591 if (util_format_is_srgb(texture->format)) {
2592 for (int i = 0; i < 3; i++)
2593 border_color[i] =
2594 util_format_linear_to_srgb_float(border_color[i]);
2595 }
2596
2597 /* Turn the border color into the layout of channels that it would
2598 * have when stored as texture contents.
2599 */
2600 float storage_color[4];
2601 util_format_unswizzle_4f(storage_color,
2602 border_color,
2603 tex_format_desc->swizzle);
2604
2605 /* Now, pack so that when the vc4_format-sampled texture contents are
2606 * replaced with our border color, the vc4_get_format_swizzle()
2607 * swizzling will get the right channels.
2608 */
2609 if (util_format_is_depth_or_stencil(texture->format)) {
2610 uc.ui[0] = util_pack_z(PIPE_FORMAT_Z24X8_UNORM,
2611 sampler->border_color.f[0]) << 8;
2612 } else {
2613 switch (rsc->vc4_format) {
2614 default:
2615 case VC4_TEXTURE_TYPE_RGBA8888:
2616 util_pack_color(storage_color,
2617 PIPE_FORMAT_R8G8B8A8_UNORM, &uc);
2618 break;
2619 case VC4_TEXTURE_TYPE_RGBA4444:
2620 util_pack_color(storage_color,
2621 PIPE_FORMAT_A8B8G8R8_UNORM, &uc);
2622 break;
2623 case VC4_TEXTURE_TYPE_RGB565:
2624 util_pack_color(storage_color,
2625 PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
2626 break;
2627 case VC4_TEXTURE_TYPE_ALPHA:
2628 uc.ui[0] = float_to_ubyte(storage_color[0]) << 24;
2629 break;
2630 case VC4_TEXTURE_TYPE_LUMALPHA:
2631 uc.ui[0] = ((float_to_ubyte(storage_color[1]) << 24) |
2632 (float_to_ubyte(storage_color[0]) << 0));
2633 break;
2634 }
2635 }
2636
2637 cl_u32(&vc4->uniforms, uc.ui[0]);
2638 }
2639
2640 static uint32_t
2641 get_texrect_scale(struct vc4_texture_stateobj *texstate,
2642 enum quniform_contents contents,
2643 uint32_t data)
2644 {
2645 struct pipe_sampler_view *texture = texstate->textures[data];
2646 uint32_t dim;
2647
2648 if (contents == QUNIFORM_TEXRECT_SCALE_X)
2649 dim = texture->texture->width0;
2650 else
2651 dim = texture->texture->height0;
2652
2653 return fui(1.0f / dim);
2654 }
2655
2656 static struct vc4_bo *
2657 vc4_upload_ubo(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
2658 const uint32_t *gallium_uniforms)
2659 {
2660 if (!shader->ubo_size)
2661 return NULL;
2662
2663 struct vc4_bo *ubo = vc4_bo_alloc(vc4->screen, shader->ubo_size, "ubo");
2664 uint32_t *data = vc4_bo_map(ubo);
2665 for (uint32_t i = 0; i < shader->num_ubo_ranges; i++) {
2666 memcpy(data + shader->ubo_ranges[i].dst_offset,
2667 gallium_uniforms + shader->ubo_ranges[i].src_offset,
2668 shader->ubo_ranges[i].size);
2669 }
2670
2671 return ubo;
2672 }
2673
2674 void
2675 vc4_write_uniforms(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
2676 struct vc4_constbuf_stateobj *cb,
2677 struct vc4_texture_stateobj *texstate)
2678 {
2679 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
2680 const uint32_t *gallium_uniforms = cb->cb[0].user_buffer;
2681 struct vc4_bo *ubo = vc4_upload_ubo(vc4, shader, gallium_uniforms);
2682
2683 cl_start_shader_reloc(&vc4->uniforms, uinfo->num_texture_samples);
2684
2685 for (int i = 0; i < uinfo->count; i++) {
2686
2687 switch (uinfo->contents[i]) {
2688 case QUNIFORM_CONSTANT:
2689 cl_u32(&vc4->uniforms, uinfo->data[i]);
2690 break;
2691 case QUNIFORM_UNIFORM:
2692 cl_u32(&vc4->uniforms,
2693 gallium_uniforms[uinfo->data[i]]);
2694 break;
2695 case QUNIFORM_VIEWPORT_X_SCALE:
2696 cl_f(&vc4->uniforms, vc4->viewport.scale[0] * 16.0f);
2697 break;
2698 case QUNIFORM_VIEWPORT_Y_SCALE:
2699 cl_f(&vc4->uniforms, vc4->viewport.scale[1] * 16.0f);
2700 break;
2701
2702 case QUNIFORM_VIEWPORT_Z_OFFSET:
2703 cl_f(&vc4->uniforms, vc4->viewport.translate[2]);
2704 break;
2705 case QUNIFORM_VIEWPORT_Z_SCALE:
2706 cl_f(&vc4->uniforms, vc4->viewport.scale[2]);
2707 break;
2708
2709 case QUNIFORM_USER_CLIP_PLANE:
2710 cl_f(&vc4->uniforms,
2711 vc4->clip.ucp[uinfo->data[i] / 4][uinfo->data[i] % 4]);
2712 break;
2713
2714 case QUNIFORM_TEXTURE_CONFIG_P0:
2715 write_texture_p0(vc4, texstate, uinfo->data[i]);
2716 break;
2717
2718 case QUNIFORM_TEXTURE_CONFIG_P1:
2719 write_texture_p1(vc4, texstate, uinfo->data[i]);
2720 break;
2721
2722 case QUNIFORM_TEXTURE_CONFIG_P2:
2723 write_texture_p2(vc4, texstate, uinfo->data[i]);
2724 break;
2725
2726 case QUNIFORM_UBO_ADDR:
2727 cl_reloc(vc4, &vc4->uniforms, ubo, 0);
2728 break;
2729
2730 case QUNIFORM_TEXTURE_BORDER_COLOR:
2731 write_texture_border_color(vc4, texstate, uinfo->data[i]);
2732 break;
2733
2734 case QUNIFORM_TEXRECT_SCALE_X:
2735 case QUNIFORM_TEXRECT_SCALE_Y:
2736 cl_u32(&vc4->uniforms,
2737 get_texrect_scale(texstate,
2738 uinfo->contents[i],
2739 uinfo->data[i]));
2740 break;
2741
2742 case QUNIFORM_BLEND_CONST_COLOR:
2743 cl_f(&vc4->uniforms,
2744 vc4->blend_color.color[uinfo->data[i]]);
2745 break;
2746
2747 case QUNIFORM_STENCIL:
2748 cl_u32(&vc4->uniforms,
2749 vc4->zsa->stencil_uniforms[uinfo->data[i]] |
2750 (uinfo->data[i] <= 1 ?
2751 (vc4->stencil_ref.ref_value[uinfo->data[i]] << 8) :
2752 0));
2753 break;
2754
2755 case QUNIFORM_ALPHA_REF:
2756 cl_f(&vc4->uniforms, vc4->zsa->base.alpha.ref_value);
2757 break;
2758 }
2759 #if 0
2760 uint32_t written_val = *(uint32_t *)(vc4->uniforms.next - 4);
2761 fprintf(stderr, "%p: %d / 0x%08x (%f)\n",
2762 shader, i, written_val, uif(written_val));
2763 #endif
2764 }
2765 }
2766
2767 static void
2768 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
2769 {
2770 struct vc4_context *vc4 = vc4_context(pctx);
2771 vc4->prog.bind_fs = hwcso;
2772 vc4->prog.dirty |= VC4_SHADER_DIRTY_FP;
2773 vc4->dirty |= VC4_DIRTY_PROG;
2774 }
2775
2776 static void
2777 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
2778 {
2779 struct vc4_context *vc4 = vc4_context(pctx);
2780 vc4->prog.bind_vs = hwcso;
2781 vc4->prog.dirty |= VC4_SHADER_DIRTY_VP;
2782 vc4->dirty |= VC4_DIRTY_PROG;
2783 }
2784
2785 void
2786 vc4_program_init(struct pipe_context *pctx)
2787 {
2788 struct vc4_context *vc4 = vc4_context(pctx);
2789
2790 pctx->create_vs_state = vc4_shader_state_create;
2791 pctx->delete_vs_state = vc4_shader_state_delete;
2792
2793 pctx->create_fs_state = vc4_shader_state_create;
2794 pctx->delete_fs_state = vc4_shader_state_delete;
2795
2796 pctx->bind_fs_state = vc4_fp_state_bind;
2797 pctx->bind_vs_state = vc4_vp_state_bind;
2798
2799 vc4->fs_cache = _mesa_hash_table_create(pctx, fs_cache_hash,
2800 fs_cache_compare);
2801 vc4->vs_cache = _mesa_hash_table_create(pctx, vs_cache_hash,
2802 vs_cache_compare);
2803 }
2804
2805 void
2806 vc4_program_fini(struct pipe_context *pctx)
2807 {
2808 struct vc4_context *vc4 = vc4_context(pctx);
2809
2810 struct hash_entry *entry;
2811 hash_table_foreach(vc4->fs_cache, entry) {
2812 struct vc4_compiled_shader *shader = entry->data;
2813 vc4_bo_unreference(&shader->bo);
2814 ralloc_free(shader);
2815 _mesa_hash_table_remove(vc4->fs_cache, entry);
2816 }
2817
2818 hash_table_foreach(vc4->vs_cache, entry) {
2819 struct vc4_compiled_shader *shader = entry->data;
2820 vc4_bo_unreference(&shader->bo);
2821 ralloc_free(shader);
2822 _mesa_hash_table_remove(vc4->vs_cache, entry);
2823 }
2824 }