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vc4: Add support for computed depth writes.
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "pipe/p_state.h"
27 #include "util/u_format.h"
28 #include "util/u_hash_table.h"
29 #include "util/u_hash.h"
30 #include "util/u_memory.h"
31 #include "util/ralloc.h"
32 #include "tgsi/tgsi_dump.h"
33 #include "tgsi/tgsi_info.h"
34
35 #include "vc4_context.h"
36 #include "vc4_qpu.h"
37 #include "vc4_qir.h"
38 #ifdef USE_VC4_SIMULATOR
39 #include "simpenrose/simpenrose.h"
40 #endif
41
42 struct vc4_key {
43 struct pipe_shader_state *shader_state;
44 struct {
45 enum pipe_format format;
46 unsigned compare_mode:1;
47 unsigned compare_func:3;
48 uint8_t swizzle[4];
49 } tex[VC4_MAX_TEXTURE_SAMPLERS];
50 };
51
52 struct vc4_fs_key {
53 struct vc4_key base;
54 enum pipe_format color_format;
55 bool depth_enabled;
56 bool is_points;
57 bool is_lines;
58
59 struct pipe_rt_blend_state blend;
60 };
61
62 struct vc4_vs_key {
63 struct vc4_key base;
64 enum pipe_format attr_formats[8];
65 };
66
67 static void
68 resize_qreg_array(struct vc4_compile *c,
69 struct qreg **regs,
70 uint32_t *size,
71 uint32_t decl_size)
72 {
73 if (*size >= decl_size)
74 return;
75
76 *size = MAX2(*size * 2, decl_size);
77 *regs = reralloc(c, *regs, struct qreg, *size);
78 if (!*regs) {
79 fprintf(stderr, "Malloc failure\n");
80 abort();
81 }
82 }
83
84 static struct qreg
85 add_uniform(struct vc4_compile *c,
86 enum quniform_contents contents,
87 uint32_t data)
88 {
89 uint32_t uniform = c->num_uniforms++;
90 struct qreg u = { QFILE_UNIF, uniform };
91
92 c->uniform_contents[uniform] = contents;
93 c->uniform_data[uniform] = data;
94
95 return u;
96 }
97
98 static struct qreg
99 get_temp_for_uniform(struct vc4_compile *c, enum quniform_contents contents,
100 uint32_t data)
101 {
102 for (int i = 0; i < c->num_uniforms; i++) {
103 if (c->uniform_contents[i] == contents &&
104 c->uniform_data[i] == data)
105 return c->uniforms[i];
106 }
107
108 struct qreg u = add_uniform(c, contents, data);
109 struct qreg t = qir_MOV(c, u);
110
111 resize_qreg_array(c, &c->uniforms, &c->uniforms_array_size,
112 u.index + 1);
113
114 c->uniforms[u.index] = t;
115 return t;
116 }
117
118 static struct qreg
119 qir_uniform_ui(struct vc4_compile *c, uint32_t ui)
120 {
121 return get_temp_for_uniform(c, QUNIFORM_CONSTANT, ui);
122 }
123
124 static struct qreg
125 qir_uniform_f(struct vc4_compile *c, float f)
126 {
127 return qir_uniform_ui(c, fui(f));
128 }
129
130 static struct qreg
131 get_src(struct vc4_compile *c, unsigned tgsi_op,
132 struct tgsi_src_register *src, int i)
133 {
134 struct qreg r = c->undef;
135
136 uint32_t s = i;
137 switch (i) {
138 case TGSI_SWIZZLE_X:
139 s = src->SwizzleX;
140 break;
141 case TGSI_SWIZZLE_Y:
142 s = src->SwizzleY;
143 break;
144 case TGSI_SWIZZLE_Z:
145 s = src->SwizzleZ;
146 break;
147 case TGSI_SWIZZLE_W:
148 s = src->SwizzleW;
149 break;
150 default:
151 abort();
152 }
153
154 assert(!src->Indirect);
155
156 switch (src->File) {
157 case TGSI_FILE_NULL:
158 return r;
159 case TGSI_FILE_TEMPORARY:
160 r = c->temps[src->Index * 4 + s];
161 break;
162 case TGSI_FILE_IMMEDIATE:
163 r = c->consts[src->Index * 4 + s];
164 break;
165 case TGSI_FILE_CONSTANT:
166 r = get_temp_for_uniform(c, QUNIFORM_UNIFORM,
167 src->Index * 4 + s);
168 break;
169 case TGSI_FILE_INPUT:
170 r = c->inputs[src->Index * 4 + s];
171 break;
172 case TGSI_FILE_SAMPLER:
173 case TGSI_FILE_SAMPLER_VIEW:
174 r = c->undef;
175 break;
176 default:
177 fprintf(stderr, "unknown src file %d\n", src->File);
178 abort();
179 }
180
181 if (src->Absolute)
182 r = qir_FMAXABS(c, r, r);
183
184 if (src->Negate) {
185 switch (tgsi_opcode_infer_src_type(tgsi_op)) {
186 case TGSI_TYPE_SIGNED:
187 case TGSI_TYPE_UNSIGNED:
188 r = qir_SUB(c, qir_uniform_ui(c, 0), r);
189 break;
190 default:
191 r = qir_FSUB(c, qir_uniform_f(c, 0.0), r);
192 break;
193 }
194 }
195
196 return r;
197 };
198
199
200 static void
201 update_dst(struct vc4_compile *c, struct tgsi_full_instruction *tgsi_inst,
202 int i, struct qreg val)
203 {
204 struct tgsi_dst_register *tgsi_dst = &tgsi_inst->Dst[0].Register;
205
206 assert(!tgsi_dst->Indirect);
207
208 switch (tgsi_dst->File) {
209 case TGSI_FILE_TEMPORARY:
210 c->temps[tgsi_dst->Index * 4 + i] = val;
211 break;
212 case TGSI_FILE_OUTPUT:
213 c->outputs[tgsi_dst->Index * 4 + i] = val;
214 c->num_outputs = MAX2(c->num_outputs,
215 tgsi_dst->Index * 4 + i + 1);
216 break;
217 default:
218 fprintf(stderr, "unknown dst file %d\n", tgsi_dst->File);
219 abort();
220 }
221 };
222
223 static struct qreg
224 get_swizzled_channel(struct vc4_compile *c,
225 struct qreg *srcs, int swiz)
226 {
227 switch (swiz) {
228 default:
229 case UTIL_FORMAT_SWIZZLE_NONE:
230 fprintf(stderr, "warning: unknown swizzle\n");
231 /* FALLTHROUGH */
232 case UTIL_FORMAT_SWIZZLE_0:
233 return qir_uniform_f(c, 0.0);
234 case UTIL_FORMAT_SWIZZLE_1:
235 return qir_uniform_f(c, 1.0);
236 case UTIL_FORMAT_SWIZZLE_X:
237 case UTIL_FORMAT_SWIZZLE_Y:
238 case UTIL_FORMAT_SWIZZLE_Z:
239 case UTIL_FORMAT_SWIZZLE_W:
240 return srcs[swiz];
241 }
242 }
243
244 static struct qreg
245 tgsi_to_qir_alu(struct vc4_compile *c,
246 struct tgsi_full_instruction *tgsi_inst,
247 enum qop op, struct qreg *src, int i)
248 {
249 struct qreg dst = qir_get_temp(c);
250 qir_emit(c, qir_inst4(op, dst,
251 src[0 * 4 + i],
252 src[1 * 4 + i],
253 src[2 * 4 + i],
254 c->undef));
255 return dst;
256 }
257
258 static struct qreg
259 tgsi_to_qir_umul(struct vc4_compile *c,
260 struct tgsi_full_instruction *tgsi_inst,
261 enum qop op, struct qreg *src, int i)
262 {
263 struct qreg src0_hi = qir_SHR(c, src[0 * 4 + i],
264 qir_uniform_ui(c, 16));
265 struct qreg src0_lo = qir_AND(c, src[0 * 4 + i],
266 qir_uniform_ui(c, 0xffff));
267 struct qreg src1_hi = qir_SHR(c, src[1 * 4 + i],
268 qir_uniform_ui(c, 16));
269 struct qreg src1_lo = qir_AND(c, src[1 * 4 + i],
270 qir_uniform_ui(c, 0xffff));
271
272 struct qreg hilo = qir_MUL24(c, src0_hi, src1_lo);
273 struct qreg lohi = qir_MUL24(c, src0_lo, src1_hi);
274 struct qreg lolo = qir_MUL24(c, src0_lo, src1_lo);
275
276 return qir_ADD(c, lolo, qir_SHL(c,
277 qir_ADD(c, hilo, lohi),
278 qir_uniform_ui(c, 16)));
279 }
280
281 static struct qreg
282 tgsi_to_qir_idiv(struct vc4_compile *c,
283 struct tgsi_full_instruction *tgsi_inst,
284 enum qop op, struct qreg *src, int i)
285 {
286 return qir_FTOI(c, qir_FMUL(c,
287 qir_ITOF(c, src[0 * 4 + i]),
288 qir_RCP(c, qir_ITOF(c, src[1 * 4 + i]))));
289 }
290
291 static struct qreg
292 tgsi_to_qir_ineg(struct vc4_compile *c,
293 struct tgsi_full_instruction *tgsi_inst,
294 enum qop op, struct qreg *src, int i)
295 {
296 return qir_SUB(c, qir_uniform_ui(c, 0), src[0 * 4 + i]);
297 }
298
299 static struct qreg
300 tgsi_to_qir_seq(struct vc4_compile *c,
301 struct tgsi_full_instruction *tgsi_inst,
302 enum qop op, struct qreg *src, int i)
303 {
304 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
305 return qir_SEL_X_0_ZS(c, qir_uniform_f(c, 1.0));
306 }
307
308 static struct qreg
309 tgsi_to_qir_sne(struct vc4_compile *c,
310 struct tgsi_full_instruction *tgsi_inst,
311 enum qop op, struct qreg *src, int i)
312 {
313 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
314 return qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0));
315 }
316
317 static struct qreg
318 tgsi_to_qir_slt(struct vc4_compile *c,
319 struct tgsi_full_instruction *tgsi_inst,
320 enum qop op, struct qreg *src, int i)
321 {
322 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
323 return qir_SEL_X_0_NS(c, qir_uniform_f(c, 1.0));
324 }
325
326 static struct qreg
327 tgsi_to_qir_sge(struct vc4_compile *c,
328 struct tgsi_full_instruction *tgsi_inst,
329 enum qop op, struct qreg *src, int i)
330 {
331 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
332 return qir_SEL_X_0_NC(c, qir_uniform_f(c, 1.0));
333 }
334
335 static struct qreg
336 tgsi_to_qir_fseq(struct vc4_compile *c,
337 struct tgsi_full_instruction *tgsi_inst,
338 enum qop op, struct qreg *src, int i)
339 {
340 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
341 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
342 }
343
344 static struct qreg
345 tgsi_to_qir_fsne(struct vc4_compile *c,
346 struct tgsi_full_instruction *tgsi_inst,
347 enum qop op, struct qreg *src, int i)
348 {
349 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
350 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
351 }
352
353 static struct qreg
354 tgsi_to_qir_fslt(struct vc4_compile *c,
355 struct tgsi_full_instruction *tgsi_inst,
356 enum qop op, struct qreg *src, int i)
357 {
358 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
359 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
360 }
361
362 static struct qreg
363 tgsi_to_qir_fsge(struct vc4_compile *c,
364 struct tgsi_full_instruction *tgsi_inst,
365 enum qop op, struct qreg *src, int i)
366 {
367 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
368 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
369 }
370
371 static struct qreg
372 tgsi_to_qir_useq(struct vc4_compile *c,
373 struct tgsi_full_instruction *tgsi_inst,
374 enum qop op, struct qreg *src, int i)
375 {
376 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
377 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
378 }
379
380 static struct qreg
381 tgsi_to_qir_usne(struct vc4_compile *c,
382 struct tgsi_full_instruction *tgsi_inst,
383 enum qop op, struct qreg *src, int i)
384 {
385 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
386 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
387 }
388
389 static struct qreg
390 tgsi_to_qir_islt(struct vc4_compile *c,
391 struct tgsi_full_instruction *tgsi_inst,
392 enum qop op, struct qreg *src, int i)
393 {
394 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
395 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
396 }
397
398 static struct qreg
399 tgsi_to_qir_isge(struct vc4_compile *c,
400 struct tgsi_full_instruction *tgsi_inst,
401 enum qop op, struct qreg *src, int i)
402 {
403 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
404 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
405 }
406
407 static struct qreg
408 tgsi_to_qir_cmp(struct vc4_compile *c,
409 struct tgsi_full_instruction *tgsi_inst,
410 enum qop op, struct qreg *src, int i)
411 {
412 qir_SF(c, src[0 * 4 + i]);
413 return qir_SEL_X_Y_NS(c,
414 src[1 * 4 + i],
415 src[2 * 4 + i]);
416 }
417
418 static struct qreg
419 tgsi_to_qir_mad(struct vc4_compile *c,
420 struct tgsi_full_instruction *tgsi_inst,
421 enum qop op, struct qreg *src, int i)
422 {
423 return qir_FADD(c,
424 qir_FMUL(c,
425 src[0 * 4 + i],
426 src[1 * 4 + i]),
427 src[2 * 4 + i]);
428 }
429
430 static struct qreg
431 tgsi_to_qir_lit(struct vc4_compile *c,
432 struct tgsi_full_instruction *tgsi_inst,
433 enum qop op, struct qreg *src, int i)
434 {
435 struct qreg x = src[0 * 4 + 0];
436 struct qreg y = src[0 * 4 + 1];
437 struct qreg w = src[0 * 4 + 3];
438
439 switch (i) {
440 case 0:
441 case 3:
442 return qir_uniform_f(c, 1.0);
443 case 1:
444 return qir_FMAX(c, src[0 * 4 + 0], qir_uniform_f(c, 0.0));
445 case 2: {
446 struct qreg zero = qir_uniform_f(c, 0.0);
447
448 qir_SF(c, x);
449 /* XXX: Clamp w to -128..128 */
450 return qir_SEL_X_0_NC(c,
451 qir_EXP2(c, qir_FMUL(c,
452 w,
453 qir_LOG2(c,
454 qir_FMAX(c,
455 y,
456 zero)))));
457 }
458 default:
459 assert(!"not reached");
460 return c->undef;
461 }
462 }
463
464 static struct qreg
465 tgsi_to_qir_lrp(struct vc4_compile *c,
466 struct tgsi_full_instruction *tgsi_inst,
467 enum qop op, struct qreg *src, int i)
468 {
469 struct qreg src0 = src[0 * 4 + i];
470 struct qreg src1 = src[1 * 4 + i];
471 struct qreg src2 = src[2 * 4 + i];
472
473 /* LRP is:
474 * src0 * src1 + (1 - src0) * src2.
475 * -> src0 * src1 + src2 - src0 * src2
476 * -> src2 + src0 * (src1 - src2)
477 */
478 return qir_FADD(c, src2, qir_FMUL(c, src0, qir_FSUB(c, src1, src2)));
479
480 }
481
482 static void
483 tgsi_to_qir_tex(struct vc4_compile *c,
484 struct tgsi_full_instruction *tgsi_inst,
485 enum qop op, struct qreg *src)
486 {
487 assert(!tgsi_inst->Instruction.Saturate);
488
489 struct qreg s = src[0 * 4 + 0];
490 struct qreg t = src[0 * 4 + 1];
491 uint32_t unit = tgsi_inst->Src[1].Register.Index;
492
493 struct qreg proj = c->undef;
494 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
495 proj = qir_RCP(c, src[0 * 4 + 3]);
496 s = qir_FMUL(c, s, proj);
497 t = qir_FMUL(c, t, proj);
498 }
499
500 /* There is no native support for GL texture rectangle coordinates, so
501 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
502 * 1]).
503 */
504 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_RECT ||
505 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT) {
506 s = qir_FMUL(c, s,
507 get_temp_for_uniform(c,
508 QUNIFORM_TEXRECT_SCALE_X,
509 unit));
510 t = qir_FMUL(c, t,
511 get_temp_for_uniform(c,
512 QUNIFORM_TEXRECT_SCALE_Y,
513 unit));
514 }
515
516 qir_TEX_T(c, t, add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit));
517
518 struct qreg sampler_p1 = add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1,
519 unit);
520 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB) {
521 qir_TEX_B(c, src[0 * 4 + 3], sampler_p1);
522 qir_TEX_S(c, s, add_uniform(c, QUNIFORM_CONSTANT, 0));
523 } else {
524 qir_TEX_S(c, s, sampler_p1);
525 }
526
527 c->num_texture_samples++;
528 struct qreg r4 = qir_TEX_RESULT(c);
529
530 enum pipe_format format = c->key->tex[unit].format;
531
532 struct qreg unpacked[4];
533 if (util_format_is_depth_or_stencil(format)) {
534 struct qreg depthf = qir_ITOF(c, qir_SHR(c, r4,
535 qir_uniform_ui(c, 8)));
536 struct qreg normalized = qir_FMUL(c, depthf,
537 qir_uniform_f(c, 1.0f/0xffffff));
538
539 struct qreg depth_output;
540
541 struct qreg compare = src[0 * 4 + 2];
542
543 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP)
544 compare = qir_FMUL(c, compare, proj);
545
546 struct qreg one = qir_uniform_f(c, 1.0f);
547 if (c->key->tex[unit].compare_mode) {
548 switch (c->key->tex[unit].compare_func) {
549 case PIPE_FUNC_NEVER:
550 depth_output = qir_uniform_f(c, 0.0f);
551 break;
552 case PIPE_FUNC_ALWAYS:
553 depth_output = one;
554 break;
555 case PIPE_FUNC_EQUAL:
556 qir_SF(c, qir_FSUB(c, compare, normalized));
557 depth_output = qir_SEL_X_0_ZS(c, one);
558 break;
559 case PIPE_FUNC_NOTEQUAL:
560 qir_SF(c, qir_FSUB(c, compare, normalized));
561 depth_output = qir_SEL_X_0_ZC(c, one);
562 break;
563 case PIPE_FUNC_GREATER:
564 qir_SF(c, qir_FSUB(c, compare, normalized));
565 depth_output = qir_SEL_X_0_NC(c, one);
566 break;
567 case PIPE_FUNC_GEQUAL:
568 qir_SF(c, qir_FSUB(c, normalized, compare));
569 depth_output = qir_SEL_X_0_NS(c, one);
570 break;
571 case PIPE_FUNC_LESS:
572 qir_SF(c, qir_FSUB(c, compare, normalized));
573 depth_output = qir_SEL_X_0_NS(c, one);
574 break;
575 case PIPE_FUNC_LEQUAL:
576 qir_SF(c, qir_FSUB(c, normalized, compare));
577 depth_output = qir_SEL_X_0_NC(c, one);
578 break;
579 }
580 } else {
581 depth_output = normalized;
582 }
583
584 for (int i = 0; i < 4; i++)
585 unpacked[i] = depth_output;
586 } else {
587 for (int i = 0; i < 4; i++)
588 unpacked[i] = qir_R4_UNPACK(c, r4, i);
589 }
590
591 const uint8_t *format_swiz = vc4_get_format_swizzle(format);
592 uint8_t swiz[4];
593 util_format_compose_swizzles(format_swiz, c->key->tex[unit].swizzle, swiz);
594 for (int i = 0; i < 4; i++) {
595 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
596 continue;
597
598 update_dst(c, tgsi_inst, i,
599 get_swizzled_channel(c, unpacked, swiz[i]));
600 }
601 }
602
603 static struct qreg
604 tgsi_to_qir_pow(struct vc4_compile *c,
605 struct tgsi_full_instruction *tgsi_inst,
606 enum qop op, struct qreg *src, int i)
607 {
608 /* Note that this instruction replicates its result from the x channel
609 */
610 return qir_EXP2(c, qir_FMUL(c,
611 src[1 * 4 + 0],
612 qir_LOG2(c, src[0 * 4 + 0])));
613 }
614
615 static struct qreg
616 tgsi_to_qir_trunc(struct vc4_compile *c,
617 struct tgsi_full_instruction *tgsi_inst,
618 enum qop op, struct qreg *src, int i)
619 {
620 return qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
621 }
622
623 /**
624 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
625 * to zero).
626 */
627 static struct qreg
628 tgsi_to_qir_frc(struct vc4_compile *c,
629 struct tgsi_full_instruction *tgsi_inst,
630 enum qop op, struct qreg *src, int i)
631 {
632 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
633 struct qreg diff = qir_FSUB(c, src[0 * 4 + i], trunc);
634 qir_SF(c, diff);
635 return qir_SEL_X_Y_NS(c,
636 qir_FADD(c, diff, qir_uniform_f(c, 1.0)),
637 diff);
638 }
639
640 /**
641 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
642 * zero).
643 */
644 static struct qreg
645 tgsi_to_qir_flr(struct vc4_compile *c,
646 struct tgsi_full_instruction *tgsi_inst,
647 enum qop op, struct qreg *src, int i)
648 {
649 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
650
651 /* This will be < 0 if we truncated and the truncation was of a value
652 * that was < 0 in the first place.
653 */
654 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], trunc));
655
656 return qir_SEL_X_Y_NS(c,
657 qir_FSUB(c, trunc, qir_uniform_f(c, 1.0)),
658 trunc);
659 }
660
661 static struct qreg
662 tgsi_to_qir_dp(struct vc4_compile *c,
663 struct tgsi_full_instruction *tgsi_inst,
664 int num, struct qreg *src, int i)
665 {
666 struct qreg sum = qir_FMUL(c, src[0 * 4 + 0], src[1 * 4 + 0]);
667 for (int j = 1; j < num; j++) {
668 sum = qir_FADD(c, sum, qir_FMUL(c,
669 src[0 * 4 + j],
670 src[1 * 4 + j]));
671 }
672 return sum;
673 }
674
675 static struct qreg
676 tgsi_to_qir_dp2(struct vc4_compile *c,
677 struct tgsi_full_instruction *tgsi_inst,
678 enum qop op, struct qreg *src, int i)
679 {
680 return tgsi_to_qir_dp(c, tgsi_inst, 2, src, i);
681 }
682
683 static struct qreg
684 tgsi_to_qir_dp3(struct vc4_compile *c,
685 struct tgsi_full_instruction *tgsi_inst,
686 enum qop op, struct qreg *src, int i)
687 {
688 return tgsi_to_qir_dp(c, tgsi_inst, 3, src, i);
689 }
690
691 static struct qreg
692 tgsi_to_qir_dp4(struct vc4_compile *c,
693 struct tgsi_full_instruction *tgsi_inst,
694 enum qop op, struct qreg *src, int i)
695 {
696 return tgsi_to_qir_dp(c, tgsi_inst, 4, src, i);
697 }
698
699 static struct qreg
700 tgsi_to_qir_abs(struct vc4_compile *c,
701 struct tgsi_full_instruction *tgsi_inst,
702 enum qop op, struct qreg *src, int i)
703 {
704 struct qreg arg = src[0 * 4 + i];
705 return qir_FMAXABS(c, arg, arg);
706 }
707
708 /* Note that this instruction replicates its result from the x channel */
709 static struct qreg
710 tgsi_to_qir_sin(struct vc4_compile *c,
711 struct tgsi_full_instruction *tgsi_inst,
712 enum qop op, struct qreg *src, int i)
713 {
714 float coeff[] = {
715 2.0 * M_PI,
716 -pow(2.0 * M_PI, 3) / (3 * 2 * 1),
717 pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
718 -pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
719 };
720
721 struct qreg scaled_x =
722 qir_FMUL(c,
723 src[0 * 4 + 0],
724 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
725
726
727 struct qreg x = tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0);
728 struct qreg x2 = qir_FMUL(c, x, x);
729 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
730 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
731 x = qir_FMUL(c, x, x2);
732 sum = qir_FADD(c,
733 sum,
734 qir_FMUL(c,
735 x,
736 qir_uniform_f(c, coeff[i])));
737 }
738 return sum;
739 }
740
741 /* Note that this instruction replicates its result from the x channel */
742 static struct qreg
743 tgsi_to_qir_cos(struct vc4_compile *c,
744 struct tgsi_full_instruction *tgsi_inst,
745 enum qop op, struct qreg *src, int i)
746 {
747 float coeff[] = {
748 1.0f,
749 -pow(2.0 * M_PI, 2) / (2 * 1),
750 pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
751 -pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
752 };
753
754 struct qreg scaled_x =
755 qir_FMUL(c, src[0 * 4 + 0],
756 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
757 struct qreg x_frac = tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0);
758
759 struct qreg sum = qir_uniform_f(c, coeff[0]);
760 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
761 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
762 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
763 if (i != 1)
764 x = qir_FMUL(c, x, x2);
765
766 struct qreg mul = qir_FMUL(c,
767 x,
768 qir_uniform_f(c, coeff[i]));
769 if (i == 0)
770 sum = mul;
771 else
772 sum = qir_FADD(c, sum, mul);
773 }
774 return sum;
775 }
776
777 static void
778 emit_vertex_input(struct vc4_compile *c, int attr)
779 {
780 enum pipe_format format = c->vs_key->attr_formats[attr];
781 struct qreg vpm_reads[4];
782
783 /* Right now, we're setting the VPM offsets to be 16 bytes wide every
784 * time, so we always read 4 32-bit VPM entries.
785 */
786 for (int i = 0; i < 4; i++) {
787 vpm_reads[i] = qir_get_temp(c);
788 qir_emit(c, qir_inst(QOP_VPM_READ,
789 vpm_reads[i],
790 c->undef,
791 c->undef));
792 c->num_inputs++;
793 }
794
795 bool format_warned = false;
796 const struct util_format_description *desc =
797 util_format_description(format);
798
799 for (int i = 0; i < 4; i++) {
800 uint8_t swiz = desc->swizzle[i];
801
802 if (swiz <= UTIL_FORMAT_SWIZZLE_W &&
803 !format_warned &&
804 (desc->channel[swiz].type != UTIL_FORMAT_TYPE_FLOAT ||
805 desc->channel[swiz].size != 32)) {
806 fprintf(stderr,
807 "vtx element %d unsupported type: %s\n",
808 attr, util_format_name(format));
809 format_warned = true;
810 }
811
812 c->inputs[attr * 4 + i] =
813 get_swizzled_channel(c, vpm_reads, swiz);
814 }
815 }
816
817 static void
818 tgsi_to_qir_kill_if(struct vc4_compile *c, struct qreg *src, int i)
819 {
820 if (c->discard.file == QFILE_NULL)
821 c->discard = qir_uniform_f(c, 0.0);
822 qir_SF(c, src[0 * 4 + i]);
823 c->discard = qir_SEL_X_Y_NS(c, qir_uniform_f(c, 1.0),
824 c->discard);
825 }
826
827 static void
828 emit_fragcoord_input(struct vc4_compile *c, int attr)
829 {
830 c->inputs[attr * 4 + 0] = qir_FRAG_X(c);
831 c->inputs[attr * 4 + 1] = qir_FRAG_Y(c);
832 c->inputs[attr * 4 + 2] =
833 qir_FMUL(c,
834 qir_ITOF(c, qir_FRAG_Z(c)),
835 qir_uniform_f(c, 1.0 / 0xffffff));
836 c->inputs[attr * 4 + 3] = qir_FRAG_RCP_W(c);
837 }
838
839 static struct qreg
840 emit_fragment_varying(struct vc4_compile *c, int index)
841 {
842 struct qreg vary = {
843 QFILE_VARY,
844 index
845 };
846
847 /* XXX: multiply by W */
848 return qir_VARY_ADD_C(c, qir_MOV(c, vary));
849 }
850
851 static void
852 emit_fragment_input(struct vc4_compile *c, int attr)
853 {
854 for (int i = 0; i < 4; i++) {
855 c->inputs[attr * 4 + i] =
856 emit_fragment_varying(c, attr * 4 + i);
857 c->num_inputs++;
858 }
859 }
860
861 static void
862 emit_tgsi_declaration(struct vc4_compile *c,
863 struct tgsi_full_declaration *decl)
864 {
865 switch (decl->Declaration.File) {
866 case TGSI_FILE_TEMPORARY:
867 resize_qreg_array(c, &c->temps, &c->temps_array_size,
868 (decl->Range.Last + 1) * 4);
869 break;
870
871 case TGSI_FILE_INPUT:
872 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
873 (decl->Range.Last + 1) * 4);
874
875 for (int i = decl->Range.First;
876 i <= decl->Range.Last;
877 i++) {
878 if (c->stage == QSTAGE_FRAG) {
879 if (decl->Semantic.Name ==
880 TGSI_SEMANTIC_POSITION) {
881 emit_fragcoord_input(c, i);
882 } else {
883 emit_fragment_input(c, i);
884 }
885 } else {
886 emit_vertex_input(c, i);
887 }
888 }
889 break;
890
891 case TGSI_FILE_OUTPUT:
892 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
893 (decl->Range.Last + 1) * 4);
894
895 switch (decl->Semantic.Name) {
896 case TGSI_SEMANTIC_POSITION:
897 c->output_position_index = decl->Range.First * 4;
898 break;
899 case TGSI_SEMANTIC_COLOR:
900 c->output_color_index = decl->Range.First * 4;
901 break;
902 }
903
904 break;
905 }
906 }
907
908 static void
909 emit_tgsi_instruction(struct vc4_compile *c,
910 struct tgsi_full_instruction *tgsi_inst)
911 {
912 struct {
913 enum qop op;
914 struct qreg (*func)(struct vc4_compile *c,
915 struct tgsi_full_instruction *tgsi_inst,
916 enum qop op,
917 struct qreg *src, int i);
918 } op_trans[] = {
919 [TGSI_OPCODE_MOV] = { QOP_MOV, tgsi_to_qir_alu },
920 [TGSI_OPCODE_ABS] = { 0, tgsi_to_qir_abs },
921 [TGSI_OPCODE_MUL] = { QOP_FMUL, tgsi_to_qir_alu },
922 [TGSI_OPCODE_ADD] = { QOP_FADD, tgsi_to_qir_alu },
923 [TGSI_OPCODE_SUB] = { QOP_FSUB, tgsi_to_qir_alu },
924 [TGSI_OPCODE_MIN] = { QOP_FMIN, tgsi_to_qir_alu },
925 [TGSI_OPCODE_MAX] = { QOP_FMAX, tgsi_to_qir_alu },
926 [TGSI_OPCODE_F2I] = { QOP_FTOI, tgsi_to_qir_alu },
927 [TGSI_OPCODE_I2F] = { QOP_ITOF, tgsi_to_qir_alu },
928 [TGSI_OPCODE_UADD] = { QOP_ADD, tgsi_to_qir_alu },
929 [TGSI_OPCODE_USHR] = { QOP_SHR, tgsi_to_qir_alu },
930 [TGSI_OPCODE_ISHR] = { QOP_ASR, tgsi_to_qir_alu },
931 [TGSI_OPCODE_SHL] = { QOP_SHL, tgsi_to_qir_alu },
932 [TGSI_OPCODE_IMIN] = { QOP_MIN, tgsi_to_qir_alu },
933 [TGSI_OPCODE_IMAX] = { QOP_MAX, tgsi_to_qir_alu },
934 [TGSI_OPCODE_AND] = { QOP_AND, tgsi_to_qir_alu },
935 [TGSI_OPCODE_OR] = { QOP_OR, tgsi_to_qir_alu },
936 [TGSI_OPCODE_XOR] = { QOP_XOR, tgsi_to_qir_alu },
937 [TGSI_OPCODE_NOT] = { QOP_NOT, tgsi_to_qir_alu },
938
939 [TGSI_OPCODE_UMUL] = { 0, tgsi_to_qir_umul },
940 [TGSI_OPCODE_IDIV] = { 0, tgsi_to_qir_idiv },
941 [TGSI_OPCODE_INEG] = { 0, tgsi_to_qir_ineg },
942
943 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_alu },
944 [TGSI_OPCODE_SEQ] = { 0, tgsi_to_qir_seq },
945 [TGSI_OPCODE_SNE] = { 0, tgsi_to_qir_sne },
946 [TGSI_OPCODE_SGE] = { 0, tgsi_to_qir_sge },
947 [TGSI_OPCODE_SLT] = { 0, tgsi_to_qir_slt },
948 [TGSI_OPCODE_FSEQ] = { 0, tgsi_to_qir_fseq },
949 [TGSI_OPCODE_FSNE] = { 0, tgsi_to_qir_fsne },
950 [TGSI_OPCODE_FSGE] = { 0, tgsi_to_qir_fsge },
951 [TGSI_OPCODE_FSLT] = { 0, tgsi_to_qir_fslt },
952 [TGSI_OPCODE_USEQ] = { 0, tgsi_to_qir_useq },
953 [TGSI_OPCODE_USNE] = { 0, tgsi_to_qir_usne },
954 [TGSI_OPCODE_ISGE] = { 0, tgsi_to_qir_isge },
955 [TGSI_OPCODE_ISLT] = { 0, tgsi_to_qir_islt },
956
957 [TGSI_OPCODE_CMP] = { 0, tgsi_to_qir_cmp },
958 [TGSI_OPCODE_MAD] = { 0, tgsi_to_qir_mad },
959 [TGSI_OPCODE_DP2] = { 0, tgsi_to_qir_dp2 },
960 [TGSI_OPCODE_DP3] = { 0, tgsi_to_qir_dp3 },
961 [TGSI_OPCODE_DP4] = { 0, tgsi_to_qir_dp4 },
962 [TGSI_OPCODE_RCP] = { QOP_RCP, tgsi_to_qir_alu },
963 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_alu },
964 [TGSI_OPCODE_EX2] = { QOP_EXP2, tgsi_to_qir_alu },
965 [TGSI_OPCODE_LG2] = { QOP_LOG2, tgsi_to_qir_alu },
966 [TGSI_OPCODE_LIT] = { 0, tgsi_to_qir_lit },
967 [TGSI_OPCODE_LRP] = { 0, tgsi_to_qir_lrp },
968 [TGSI_OPCODE_POW] = { 0, tgsi_to_qir_pow },
969 [TGSI_OPCODE_TRUNC] = { 0, tgsi_to_qir_trunc },
970 [TGSI_OPCODE_FRC] = { 0, tgsi_to_qir_frc },
971 [TGSI_OPCODE_FLR] = { 0, tgsi_to_qir_flr },
972 [TGSI_OPCODE_SIN] = { 0, tgsi_to_qir_sin },
973 [TGSI_OPCODE_COS] = { 0, tgsi_to_qir_cos },
974 };
975 static int asdf = 0;
976 uint32_t tgsi_op = tgsi_inst->Instruction.Opcode;
977
978 if (tgsi_op == TGSI_OPCODE_END)
979 return;
980
981 struct qreg src_regs[12];
982 for (int s = 0; s < 3; s++) {
983 for (int i = 0; i < 4; i++) {
984 src_regs[4 * s + i] =
985 get_src(c, tgsi_inst->Instruction.Opcode,
986 &tgsi_inst->Src[s].Register, i);
987 }
988 }
989
990 switch (tgsi_op) {
991 case TGSI_OPCODE_TEX:
992 case TGSI_OPCODE_TXP:
993 case TGSI_OPCODE_TXB:
994 tgsi_to_qir_tex(c, tgsi_inst,
995 op_trans[tgsi_op].op, src_regs);
996 return;
997 case TGSI_OPCODE_KILL:
998 c->discard = qir_uniform_f(c, 1.0);
999 return;
1000 case TGSI_OPCODE_KILL_IF:
1001 for (int i = 0; i < 4; i++)
1002 tgsi_to_qir_kill_if(c, src_regs, i);
1003 return;
1004 default:
1005 break;
1006 }
1007
1008 if (tgsi_op > ARRAY_SIZE(op_trans) || !(op_trans[tgsi_op].func)) {
1009 fprintf(stderr, "unknown tgsi inst: ");
1010 tgsi_dump_instruction(tgsi_inst, asdf++);
1011 fprintf(stderr, "\n");
1012 abort();
1013 }
1014
1015 for (int i = 0; i < 4; i++) {
1016 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
1017 continue;
1018
1019 struct qreg result;
1020
1021 result = op_trans[tgsi_op].func(c, tgsi_inst,
1022 op_trans[tgsi_op].op,
1023 src_regs, i);
1024
1025 if (tgsi_inst->Instruction.Saturate) {
1026 float low = (tgsi_inst->Instruction.Saturate ==
1027 TGSI_SAT_MINUS_PLUS_ONE ? -1.0 : 0.0);
1028 result = qir_FMAX(c,
1029 qir_FMIN(c,
1030 result,
1031 qir_uniform_f(c, 1.0)),
1032 qir_uniform_f(c, low));
1033 }
1034
1035 update_dst(c, tgsi_inst, i, result);
1036 }
1037 }
1038
1039 static void
1040 parse_tgsi_immediate(struct vc4_compile *c, struct tgsi_full_immediate *imm)
1041 {
1042 for (int i = 0; i < 4; i++) {
1043 unsigned n = c->num_consts++;
1044 resize_qreg_array(c, &c->consts, &c->consts_array_size, n + 1);
1045 c->consts[n] = qir_uniform_ui(c, imm->u[i].Uint);
1046 }
1047 }
1048
1049 static struct qreg
1050 vc4_blend_channel(struct vc4_compile *c,
1051 struct qreg *dst,
1052 struct qreg *src,
1053 struct qreg val,
1054 unsigned factor,
1055 int channel)
1056 {
1057 switch(factor) {
1058 case PIPE_BLENDFACTOR_ONE:
1059 return val;
1060 case PIPE_BLENDFACTOR_SRC_COLOR:
1061 return qir_FMUL(c, val, src[channel]);
1062 case PIPE_BLENDFACTOR_SRC_ALPHA:
1063 return qir_FMUL(c, val, src[3]);
1064 case PIPE_BLENDFACTOR_DST_ALPHA:
1065 return qir_FMUL(c, val, dst[3]);
1066 case PIPE_BLENDFACTOR_DST_COLOR:
1067 return qir_FMUL(c, val, dst[channel]);
1068 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
1069 return qir_FMIN(c, src[3], qir_FSUB(c,
1070 qir_uniform_f(c, 1.0),
1071 dst[3]));
1072 case PIPE_BLENDFACTOR_CONST_COLOR:
1073 return qir_FMUL(c, val,
1074 get_temp_for_uniform(c,
1075 QUNIFORM_BLEND_CONST_COLOR,
1076 channel));
1077 case PIPE_BLENDFACTOR_CONST_ALPHA:
1078 return qir_FMUL(c, val,
1079 get_temp_for_uniform(c,
1080 QUNIFORM_BLEND_CONST_COLOR,
1081 3));
1082 case PIPE_BLENDFACTOR_ZERO:
1083 return qir_uniform_f(c, 0.0);
1084 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
1085 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1086 src[channel]));
1087 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
1088 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1089 src[3]));
1090 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
1091 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1092 dst[3]));
1093 case PIPE_BLENDFACTOR_INV_DST_COLOR:
1094 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1095 dst[channel]));
1096 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
1097 return qir_FMUL(c, val,
1098 qir_FSUB(c, qir_uniform_f(c, 1.0),
1099 get_temp_for_uniform(c,
1100 QUNIFORM_BLEND_CONST_COLOR,
1101 channel)));
1102 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
1103 return qir_FMUL(c, val,
1104 qir_FSUB(c, qir_uniform_f(c, 1.0),
1105 get_temp_for_uniform(c,
1106 QUNIFORM_BLEND_CONST_COLOR,
1107 3)));
1108
1109 default:
1110 case PIPE_BLENDFACTOR_SRC1_COLOR:
1111 case PIPE_BLENDFACTOR_SRC1_ALPHA:
1112 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
1113 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
1114 /* Unsupported. */
1115 fprintf(stderr, "Unknown blend factor %d\n", factor);
1116 return val;
1117 }
1118 }
1119
1120 static struct qreg
1121 vc4_blend_func(struct vc4_compile *c,
1122 struct qreg src, struct qreg dst,
1123 unsigned func)
1124 {
1125 switch (func) {
1126 case PIPE_BLEND_ADD:
1127 return qir_FADD(c, src, dst);
1128 case PIPE_BLEND_SUBTRACT:
1129 return qir_FSUB(c, src, dst);
1130 case PIPE_BLEND_REVERSE_SUBTRACT:
1131 return qir_FSUB(c, dst, src);
1132 case PIPE_BLEND_MIN:
1133 return qir_FMIN(c, src, dst);
1134 case PIPE_BLEND_MAX:
1135 return qir_FMAX(c, src, dst);
1136
1137 default:
1138 /* Unsupported. */
1139 fprintf(stderr, "Unknown blend func %d\n", func);
1140 return src;
1141
1142 }
1143 }
1144
1145 /**
1146 * Implements fixed function blending in shader code.
1147 *
1148 * VC4 doesn't have any hardware support for blending. Instead, you read the
1149 * current contents of the destination from the tile buffer after having
1150 * waited for the scoreboard (which is handled by vc4_qpu_emit.c), then do
1151 * math using your output color and that destination value, and update the
1152 * output color appropriately.
1153 */
1154 static void
1155 vc4_blend(struct vc4_compile *c, struct qreg *result,
1156 struct qreg *dst_color, struct qreg *src_color)
1157 {
1158 struct pipe_rt_blend_state *blend = &c->fs_key->blend;
1159
1160 if (!blend->blend_enable) {
1161 for (int i = 0; i < 4; i++)
1162 result[i] = src_color[i];
1163 return;
1164 }
1165
1166 struct qreg src_blend[4], dst_blend[4];
1167 for (int i = 0; i < 3; i++) {
1168 src_blend[i] = vc4_blend_channel(c,
1169 dst_color, src_color,
1170 src_color[i],
1171 blend->rgb_src_factor, i);
1172 dst_blend[i] = vc4_blend_channel(c,
1173 dst_color, src_color,
1174 dst_color[i],
1175 blend->rgb_dst_factor, i);
1176 }
1177 src_blend[3] = vc4_blend_channel(c,
1178 dst_color, src_color,
1179 src_color[3],
1180 blend->alpha_src_factor, 3);
1181 dst_blend[3] = vc4_blend_channel(c,
1182 dst_color, src_color,
1183 dst_color[3],
1184 blend->alpha_dst_factor, 3);
1185
1186 for (int i = 0; i < 3; i++) {
1187 result[i] = vc4_blend_func(c,
1188 src_blend[i], dst_blend[i],
1189 blend->rgb_func);
1190 }
1191 result[3] = vc4_blend_func(c,
1192 src_blend[3], dst_blend[3],
1193 blend->alpha_func);
1194 }
1195
1196 static void
1197 emit_frag_end(struct vc4_compile *c)
1198 {
1199 enum pipe_format color_format = c->fs_key->color_format;
1200 const uint8_t *format_swiz = vc4_get_format_swizzle(color_format);
1201 struct qreg tlb_read_color[4] = { c->undef, c->undef, c->undef, c->undef };
1202 struct qreg dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1203 if (c->fs_key->blend.blend_enable ||
1204 c->fs_key->blend.colormask != 0xf) {
1205 struct qreg r4 = qir_TLB_COLOR_READ(c);
1206 for (int i = 0; i < 4; i++)
1207 tlb_read_color[i] = qir_R4_UNPACK(c, r4, i);
1208 for (int i = 0; i < 4; i++)
1209 dst_color[i] = get_swizzled_channel(c,
1210 tlb_read_color,
1211 format_swiz[i]);
1212 }
1213
1214 struct qreg blend_color[4];
1215 struct qreg undef_array[4] = {
1216 c->undef, c->undef, c->undef, c->undef
1217 };
1218 vc4_blend(c, blend_color, dst_color,
1219 (c->output_color_index != -1 ?
1220 c->outputs + c->output_color_index :
1221 undef_array));
1222
1223 /* If the bit isn't set in the color mask, then just return the
1224 * original dst color, instead.
1225 */
1226 for (int i = 0; i < 4; i++) {
1227 if (!(c->fs_key->blend.colormask & (1 << i))) {
1228 blend_color[i] = dst_color[i];
1229 }
1230 }
1231
1232 /* Debug: Sometimes you're getting a black output and just want to see
1233 * if the FS is getting executed at all. Spam magenta into the color
1234 * output.
1235 */
1236 if (0) {
1237 blend_color[0] = qir_uniform_f(c, 1.0);
1238 blend_color[1] = qir_uniform_f(c, 0.0);
1239 blend_color[2] = qir_uniform_f(c, 1.0);
1240 blend_color[3] = qir_uniform_f(c, 0.5);
1241 }
1242
1243 struct qreg swizzled_outputs[4];
1244 for (int i = 0; i < 4; i++) {
1245 swizzled_outputs[i] = get_swizzled_channel(c, blend_color,
1246 format_swiz[i]);
1247 }
1248
1249 if (c->discard.file != QFILE_NULL)
1250 qir_TLB_DISCARD_SETUP(c, c->discard);
1251
1252 if (c->fs_key->depth_enabled) {
1253 struct qreg z;
1254 if (c->output_position_index != -1) {
1255 z = qir_FTOI(c, qir_FMUL(c, c->outputs[c->output_position_index + 2],
1256 qir_uniform_f(c, 0xffffff)));
1257 } else {
1258 z = qir_FRAG_Z(c);
1259 }
1260 qir_TLB_Z_WRITE(c, z);
1261 }
1262
1263 bool color_written = false;
1264 for (int i = 0; i < 4; i++) {
1265 if (swizzled_outputs[i].file != QFILE_NULL)
1266 color_written = true;
1267 }
1268
1269 struct qreg packed_color;
1270 if (color_written) {
1271 /* Fill in any undefined colors. The simulator will assertion
1272 * fail if we read something that wasn't written, and I don't
1273 * know what hardware does.
1274 */
1275 for (int i = 0; i < 4; i++) {
1276 if (swizzled_outputs[i].file == QFILE_NULL)
1277 swizzled_outputs[i] = qir_uniform_f(c, 0.0);
1278 }
1279 packed_color = qir_get_temp(c);
1280 qir_emit(c, qir_inst4(QOP_PACK_COLORS, packed_color,
1281 swizzled_outputs[0],
1282 swizzled_outputs[1],
1283 swizzled_outputs[2],
1284 swizzled_outputs[3]));
1285 } else {
1286 packed_color = qir_uniform_ui(c, 0);
1287 }
1288
1289 qir_emit(c, qir_inst(QOP_TLB_COLOR_WRITE, c->undef,
1290 packed_color, c->undef));
1291 }
1292
1293 static void
1294 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1295 {
1296 struct qreg xyi[2];
1297
1298 for (int i = 0; i < 2; i++) {
1299 struct qreg scale =
1300 add_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1301
1302 xyi[i] = qir_FTOI(c, qir_FMUL(c,
1303 qir_FMUL(c,
1304 c->outputs[i],
1305 scale),
1306 rcp_w));
1307 }
1308
1309 qir_VPM_WRITE(c, qir_PACK_SCALED(c, xyi[0], xyi[1]));
1310 }
1311
1312 static void
1313 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1314 {
1315 struct qreg zscale = add_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1316 struct qreg zoffset = add_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1317
1318 qir_VPM_WRITE(c, qir_FMUL(c, qir_FADD(c, qir_FMUL(c,
1319 c->outputs[2],
1320 zscale),
1321 zoffset),
1322 rcp_w));
1323 }
1324
1325 static void
1326 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1327 {
1328 qir_VPM_WRITE(c, rcp_w);
1329 }
1330
1331 static void
1332 emit_vert_end(struct vc4_compile *c)
1333 {
1334 struct qreg rcp_w = qir_RCP(c, c->outputs[3]);
1335
1336 emit_scaled_viewport_write(c, rcp_w);
1337 emit_zs_write(c, rcp_w);
1338 emit_rcp_wc_write(c, rcp_w);
1339
1340 for (int i = 4; i < c->num_outputs; i++) {
1341 qir_VPM_WRITE(c, c->outputs[i]);
1342 }
1343 }
1344
1345 static void
1346 emit_coord_end(struct vc4_compile *c)
1347 {
1348 struct qreg rcp_w = qir_RCP(c, c->outputs[3]);
1349
1350 for (int i = 0; i < 4; i++)
1351 qir_VPM_WRITE(c, c->outputs[i]);
1352
1353 emit_scaled_viewport_write(c, rcp_w);
1354 emit_zs_write(c, rcp_w);
1355 emit_rcp_wc_write(c, rcp_w);
1356 }
1357
1358 static struct vc4_compile *
1359 vc4_shader_tgsi_to_qir(struct vc4_compiled_shader *shader, enum qstage stage,
1360 struct vc4_key *key)
1361 {
1362 struct vc4_compile *c = qir_compile_init();
1363 int ret;
1364
1365 c->stage = stage;
1366
1367 c->uniform_data = ralloc_array(c, uint32_t, 1024);
1368 c->uniform_contents = ralloc_array(c, enum quniform_contents, 1024);
1369
1370 c->shader_state = key->shader_state;
1371 ret = tgsi_parse_init(&c->parser, c->shader_state->tokens);
1372 assert(ret == TGSI_PARSE_OK);
1373
1374 if (vc4_debug & VC4_DEBUG_TGSI) {
1375 fprintf(stderr, "TGSI:\n");
1376 tgsi_dump(c->shader_state->tokens, 0);
1377 }
1378
1379 c->key = key;
1380 switch (stage) {
1381 case QSTAGE_FRAG:
1382 c->fs_key = (struct vc4_fs_key *)key;
1383 if (c->fs_key->is_points) {
1384 c->point_x = emit_fragment_varying(c, 0);
1385 c->point_y = emit_fragment_varying(c, 0);
1386 } else if (c->fs_key->is_lines) {
1387 c->line_x = emit_fragment_varying(c, 0);
1388 }
1389 break;
1390 case QSTAGE_VERT:
1391 c->vs_key = (struct vc4_vs_key *)key;
1392 break;
1393 case QSTAGE_COORD:
1394 c->vs_key = (struct vc4_vs_key *)key;
1395 break;
1396 }
1397
1398 while (!tgsi_parse_end_of_tokens(&c->parser)) {
1399 tgsi_parse_token(&c->parser);
1400
1401 switch (c->parser.FullToken.Token.Type) {
1402 case TGSI_TOKEN_TYPE_DECLARATION:
1403 emit_tgsi_declaration(c,
1404 &c->parser.FullToken.FullDeclaration);
1405 break;
1406
1407 case TGSI_TOKEN_TYPE_INSTRUCTION:
1408 emit_tgsi_instruction(c,
1409 &c->parser.FullToken.FullInstruction);
1410 break;
1411
1412 case TGSI_TOKEN_TYPE_IMMEDIATE:
1413 parse_tgsi_immediate(c,
1414 &c->parser.FullToken.FullImmediate);
1415 break;
1416 }
1417 }
1418
1419 switch (stage) {
1420 case QSTAGE_FRAG:
1421 emit_frag_end(c);
1422 break;
1423 case QSTAGE_VERT:
1424 emit_vert_end(c);
1425 break;
1426 case QSTAGE_COORD:
1427 emit_coord_end(c);
1428 break;
1429 }
1430
1431 tgsi_parse_free(&c->parser);
1432
1433 qir_optimize(c);
1434
1435 if (vc4_debug & VC4_DEBUG_QIR) {
1436 fprintf(stderr, "QIR:\n");
1437 qir_dump(c);
1438 }
1439 vc4_generate_code(c);
1440
1441 if (vc4_debug & VC4_DEBUG_SHADERDB) {
1442 fprintf(stderr, "SHADER-DB: %s: %d instructions\n",
1443 qir_get_stage_name(c->stage), c->qpu_inst_count);
1444 fprintf(stderr, "SHADER-DB: %s: %d uniforms\n",
1445 qir_get_stage_name(c->stage), c->num_uniforms);
1446 }
1447
1448 return c;
1449 }
1450
1451 static void *
1452 vc4_shader_state_create(struct pipe_context *pctx,
1453 const struct pipe_shader_state *cso)
1454 {
1455 struct pipe_shader_state *so = CALLOC_STRUCT(pipe_shader_state);
1456 if (!so)
1457 return NULL;
1458
1459 so->tokens = tgsi_dup_tokens(cso->tokens);
1460
1461 return so;
1462 }
1463
1464 static void
1465 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
1466 int shader_index,
1467 struct vc4_compile *c)
1468 {
1469 int count = c->num_uniforms;
1470 struct vc4_shader_uniform_info *uinfo = &shader->uniforms[shader_index];
1471
1472 uinfo->count = count;
1473 uinfo->data = malloc(count * sizeof(*uinfo->data));
1474 memcpy(uinfo->data, c->uniform_data,
1475 count * sizeof(*uinfo->data));
1476 uinfo->contents = malloc(count * sizeof(*uinfo->contents));
1477 memcpy(uinfo->contents, c->uniform_contents,
1478 count * sizeof(*uinfo->contents));
1479 uinfo->num_texture_samples = c->num_texture_samples;
1480 }
1481
1482 static void
1483 vc4_fs_compile(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1484 struct vc4_fs_key *key)
1485 {
1486 struct vc4_compile *c = vc4_shader_tgsi_to_qir(shader, QSTAGE_FRAG,
1487 &key->base);
1488 shader->num_inputs = c->num_inputs;
1489 copy_uniform_state_to_shader(shader, 0, c);
1490 shader->bo = vc4_bo_alloc_mem(vc4->screen, c->qpu_insts,
1491 c->qpu_inst_count * sizeof(uint64_t),
1492 "fs_code");
1493
1494 qir_compile_destroy(c);
1495 }
1496
1497 static void
1498 vc4_vs_compile(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1499 struct vc4_vs_key *key)
1500 {
1501 struct vc4_compile *vs_c = vc4_shader_tgsi_to_qir(shader,
1502 QSTAGE_VERT,
1503 &key->base);
1504 copy_uniform_state_to_shader(shader, 0, vs_c);
1505
1506 struct vc4_compile *cs_c = vc4_shader_tgsi_to_qir(shader,
1507 QSTAGE_COORD,
1508 &key->base);
1509 copy_uniform_state_to_shader(shader, 1, cs_c);
1510
1511 uint32_t vs_size = vs_c->qpu_inst_count * sizeof(uint64_t);
1512 uint32_t cs_size = cs_c->qpu_inst_count * sizeof(uint64_t);
1513 shader->coord_shader_offset = vs_size; /* XXX: alignment? */
1514 shader->bo = vc4_bo_alloc(vc4->screen,
1515 shader->coord_shader_offset + cs_size,
1516 "vs_code");
1517
1518 void *map = vc4_bo_map(shader->bo);
1519 memcpy(map, vs_c->qpu_insts, vs_size);
1520 memcpy(map + shader->coord_shader_offset,
1521 cs_c->qpu_insts, cs_size);
1522
1523 qir_compile_destroy(vs_c);
1524 qir_compile_destroy(cs_c);
1525 }
1526
1527 static void
1528 vc4_setup_shared_key(struct vc4_key *key, struct vc4_texture_stateobj *texstate)
1529 {
1530 for (int i = 0; i < texstate->num_textures; i++) {
1531 struct pipe_sampler_view *sampler = texstate->textures[i];
1532 struct pipe_sampler_state *sampler_state =
1533 texstate->samplers[i];
1534
1535 if (sampler) {
1536 struct pipe_resource *prsc = sampler->texture;
1537 key->tex[i].format = prsc->format;
1538 key->tex[i].swizzle[0] = sampler->swizzle_r;
1539 key->tex[i].swizzle[1] = sampler->swizzle_g;
1540 key->tex[i].swizzle[2] = sampler->swizzle_b;
1541 key->tex[i].swizzle[3] = sampler->swizzle_a;
1542 key->tex[i].compare_mode = sampler_state->compare_mode;
1543 key->tex[i].compare_func = sampler_state->compare_func;
1544 }
1545 }
1546 }
1547
1548 static void
1549 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
1550 {
1551 struct vc4_fs_key local_key;
1552 struct vc4_fs_key *key = &local_key;
1553
1554 memset(key, 0, sizeof(*key));
1555 vc4_setup_shared_key(&key->base, &vc4->fragtex);
1556 key->base.shader_state = vc4->prog.bind_fs;
1557 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
1558 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
1559 prim_mode <= PIPE_PRIM_LINE_STRIP);
1560 key->blend = vc4->blend->rt[0];
1561
1562 if (vc4->framebuffer.cbufs[0])
1563 key->color_format = vc4->framebuffer.cbufs[0]->format;
1564
1565 key->depth_enabled = vc4->zsa->base.depth.enabled;
1566
1567 vc4->prog.fs = util_hash_table_get(vc4->fs_cache, key);
1568 if (vc4->prog.fs)
1569 return;
1570
1571 key = malloc(sizeof(*key));
1572 memcpy(key, &local_key, sizeof(*key));
1573
1574 struct vc4_compiled_shader *shader = CALLOC_STRUCT(vc4_compiled_shader);
1575 vc4_fs_compile(vc4, shader, key);
1576 util_hash_table_set(vc4->fs_cache, key, shader);
1577
1578 vc4->prog.fs = shader;
1579 }
1580
1581 static void
1582 vc4_update_compiled_vs(struct vc4_context *vc4)
1583 {
1584 struct vc4_vs_key local_key;
1585 struct vc4_vs_key *key = &local_key;
1586
1587 memset(key, 0, sizeof(*key));
1588 vc4_setup_shared_key(&key->base, &vc4->verttex);
1589 key->base.shader_state = vc4->prog.bind_vs;
1590
1591 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
1592 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
1593
1594 vc4->prog.vs = util_hash_table_get(vc4->vs_cache, key);
1595 if (vc4->prog.vs)
1596 return;
1597
1598 key = malloc(sizeof(*key));
1599 memcpy(key, &local_key, sizeof(*key));
1600
1601 struct vc4_compiled_shader *shader = CALLOC_STRUCT(vc4_compiled_shader);
1602 vc4_vs_compile(vc4, shader, key);
1603 util_hash_table_set(vc4->vs_cache, key, shader);
1604
1605 vc4->prog.vs = shader;
1606 }
1607
1608 void
1609 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
1610 {
1611 vc4_update_compiled_fs(vc4, prim_mode);
1612 vc4_update_compiled_vs(vc4);
1613 }
1614
1615 static unsigned
1616 fs_cache_hash(void *key)
1617 {
1618 return util_hash_crc32(key, sizeof(struct vc4_fs_key));
1619 }
1620
1621 static unsigned
1622 vs_cache_hash(void *key)
1623 {
1624 return util_hash_crc32(key, sizeof(struct vc4_vs_key));
1625 }
1626
1627 static int
1628 fs_cache_compare(void *key1, void *key2)
1629 {
1630 return memcmp(key1, key2, sizeof(struct vc4_fs_key));
1631 }
1632
1633 static int
1634 vs_cache_compare(void *key1, void *key2)
1635 {
1636 return memcmp(key1, key2, sizeof(struct vc4_vs_key));
1637 }
1638
1639 struct delete_state {
1640 struct vc4_context *vc4;
1641 struct pipe_shader_state *shader_state;
1642 };
1643
1644 static enum pipe_error
1645 fs_delete_from_cache(void *in_key, void *in_value, void *data)
1646 {
1647 struct delete_state *del = data;
1648 struct vc4_fs_key *key = in_key;
1649 struct vc4_compiled_shader *shader = in_value;
1650
1651 if (key->base.shader_state == data) {
1652 util_hash_table_remove(del->vc4->fs_cache, key);
1653 vc4_bo_unreference(&shader->bo);
1654 free(shader);
1655 }
1656
1657 return 0;
1658 }
1659
1660 static enum pipe_error
1661 vs_delete_from_cache(void *in_key, void *in_value, void *data)
1662 {
1663 struct delete_state *del = data;
1664 struct vc4_vs_key *key = in_key;
1665 struct vc4_compiled_shader *shader = in_value;
1666
1667 if (key->base.shader_state == data) {
1668 util_hash_table_remove(del->vc4->vs_cache, key);
1669 vc4_bo_unreference(&shader->bo);
1670 free(shader);
1671 }
1672
1673 return 0;
1674 }
1675
1676 static void
1677 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
1678 {
1679 struct vc4_context *vc4 = vc4_context(pctx);
1680 struct pipe_shader_state *so = hwcso;
1681 struct delete_state del;
1682
1683 del.vc4 = vc4;
1684 del.shader_state = so;
1685 util_hash_table_foreach(vc4->fs_cache, fs_delete_from_cache, &del);
1686 util_hash_table_foreach(vc4->vs_cache, vs_delete_from_cache, &del);
1687
1688 free((void *)so->tokens);
1689 free(so);
1690 }
1691
1692 static uint32_t translate_wrap(uint32_t p_wrap)
1693 {
1694 switch (p_wrap) {
1695 case PIPE_TEX_WRAP_REPEAT:
1696 return 0;
1697 case PIPE_TEX_WRAP_CLAMP:
1698 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1699 return 1;
1700 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1701 return 2;
1702 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1703 return 3;
1704 default:
1705 fprintf(stderr, "Unknown wrap mode %d\n", p_wrap);
1706 assert(!"not reached");
1707 return 0;
1708 }
1709 }
1710
1711 static void
1712 write_texture_p0(struct vc4_context *vc4,
1713 struct vc4_texture_stateobj *texstate,
1714 uint32_t unit)
1715 {
1716 struct pipe_sampler_view *texture = texstate->textures[unit];
1717 struct vc4_resource *rsc = vc4_resource(texture->texture);
1718
1719 cl_reloc(vc4, &vc4->uniforms, rsc->bo,
1720 rsc->slices[0].offset | texture->u.tex.last_level |
1721 ((rsc->vc4_format & 7) << 4));
1722 }
1723
1724 static void
1725 write_texture_p1(struct vc4_context *vc4,
1726 struct vc4_texture_stateobj *texstate,
1727 uint32_t unit)
1728 {
1729 struct pipe_sampler_view *texture = texstate->textures[unit];
1730 struct vc4_resource *rsc = vc4_resource(texture->texture);
1731 struct pipe_sampler_state *sampler = texstate->samplers[unit];
1732 static const uint32_t mipfilter_map[] = {
1733 [PIPE_TEX_MIPFILTER_NEAREST] = 2,
1734 [PIPE_TEX_MIPFILTER_LINEAR] = 4,
1735 [PIPE_TEX_MIPFILTER_NONE] = 0
1736 };
1737 static const uint32_t imgfilter_map[] = {
1738 [PIPE_TEX_FILTER_NEAREST] = 1,
1739 [PIPE_TEX_FILTER_LINEAR] = 0,
1740 };
1741
1742 cl_u32(&vc4->uniforms,
1743 ((rsc->vc4_format >> 4) << 31) |
1744 (texture->texture->height0 << 20) |
1745 (texture->texture->width0 << 8) |
1746 (imgfilter_map[sampler->mag_img_filter] << 7) |
1747 ((imgfilter_map[sampler->min_img_filter] +
1748 mipfilter_map[sampler->min_mip_filter]) << 4) |
1749 (translate_wrap(sampler->wrap_t) << 2) |
1750 (translate_wrap(sampler->wrap_s) << 0));
1751 }
1752
1753 static uint32_t
1754 get_texrect_scale(struct vc4_texture_stateobj *texstate,
1755 enum quniform_contents contents,
1756 uint32_t data)
1757 {
1758 struct pipe_sampler_view *texture = texstate->textures[data];
1759 uint32_t dim;
1760
1761 if (contents == QUNIFORM_TEXRECT_SCALE_X)
1762 dim = texture->texture->width0;
1763 else
1764 dim = texture->texture->height0;
1765
1766 return fui(1.0f / dim);
1767 }
1768
1769 void
1770 vc4_write_uniforms(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1771 struct vc4_constbuf_stateobj *cb,
1772 struct vc4_texture_stateobj *texstate,
1773 int shader_index)
1774 {
1775 struct vc4_shader_uniform_info *uinfo = &shader->uniforms[shader_index];
1776 const uint32_t *gallium_uniforms = cb->cb[0].user_buffer;
1777
1778 cl_start_shader_reloc(&vc4->uniforms, uinfo->num_texture_samples);
1779
1780 for (int i = 0; i < uinfo->count; i++) {
1781
1782 switch (uinfo->contents[i]) {
1783 case QUNIFORM_CONSTANT:
1784 cl_u32(&vc4->uniforms, uinfo->data[i]);
1785 break;
1786 case QUNIFORM_UNIFORM:
1787 cl_u32(&vc4->uniforms,
1788 gallium_uniforms[uinfo->data[i]]);
1789 break;
1790 case QUNIFORM_VIEWPORT_X_SCALE:
1791 cl_f(&vc4->uniforms, vc4->viewport.scale[0] * 16.0f);
1792 break;
1793 case QUNIFORM_VIEWPORT_Y_SCALE:
1794 cl_f(&vc4->uniforms, vc4->viewport.scale[1] * 16.0f);
1795 break;
1796
1797 case QUNIFORM_VIEWPORT_Z_OFFSET:
1798 cl_f(&vc4->uniforms, vc4->viewport.translate[2]);
1799 break;
1800 case QUNIFORM_VIEWPORT_Z_SCALE:
1801 cl_f(&vc4->uniforms, vc4->viewport.scale[2]);
1802 break;
1803
1804 case QUNIFORM_TEXTURE_CONFIG_P0:
1805 write_texture_p0(vc4, texstate, uinfo->data[i]);
1806 break;
1807
1808 case QUNIFORM_TEXTURE_CONFIG_P1:
1809 write_texture_p1(vc4, texstate, uinfo->data[i]);
1810 break;
1811
1812 case QUNIFORM_TEXRECT_SCALE_X:
1813 case QUNIFORM_TEXRECT_SCALE_Y:
1814 cl_u32(&vc4->uniforms,
1815 get_texrect_scale(texstate,
1816 uinfo->contents[i],
1817 uinfo->data[i]));
1818 break;
1819
1820 case QUNIFORM_BLEND_CONST_COLOR:
1821 cl_f(&vc4->uniforms,
1822 vc4->blend_color.color[uinfo->data[i]]);
1823 break;
1824 }
1825 #if 0
1826 uint32_t written_val = *(uint32_t *)(vc4->uniforms.next - 4);
1827 fprintf(stderr, "%p/%d: %d: 0x%08x (%f)\n",
1828 shader, shader_index, i, written_val, uif(written_val));
1829 #endif
1830 }
1831 }
1832
1833 static void
1834 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
1835 {
1836 struct vc4_context *vc4 = vc4_context(pctx);
1837 vc4->prog.bind_fs = hwcso;
1838 vc4->prog.dirty |= VC4_SHADER_DIRTY_FP;
1839 vc4->dirty |= VC4_DIRTY_PROG;
1840 }
1841
1842 static void
1843 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
1844 {
1845 struct vc4_context *vc4 = vc4_context(pctx);
1846 vc4->prog.bind_vs = hwcso;
1847 vc4->prog.dirty |= VC4_SHADER_DIRTY_VP;
1848 vc4->dirty |= VC4_DIRTY_PROG;
1849 }
1850
1851 void
1852 vc4_program_init(struct pipe_context *pctx)
1853 {
1854 struct vc4_context *vc4 = vc4_context(pctx);
1855
1856 pctx->create_vs_state = vc4_shader_state_create;
1857 pctx->delete_vs_state = vc4_shader_state_delete;
1858
1859 pctx->create_fs_state = vc4_shader_state_create;
1860 pctx->delete_fs_state = vc4_shader_state_delete;
1861
1862 pctx->bind_fs_state = vc4_fp_state_bind;
1863 pctx->bind_vs_state = vc4_vp_state_bind;
1864
1865 vc4->fs_cache = util_hash_table_create(fs_cache_hash, fs_cache_compare);
1866 vc4->vs_cache = util_hash_table_create(vs_cache_hash, vs_cache_compare);
1867 }