2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "util/u_format.h"
27 #include "util/u_hash.h"
28 #include "util/u_math.h"
29 #include "util/u_memory.h"
30 #include "util/ralloc.h"
31 #include "util/hash_table.h"
32 #include "tgsi/tgsi_dump.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "compiler/nir/nir.h"
35 #include "compiler/nir/nir_builder.h"
36 #include "nir/tgsi_to_nir.h"
37 #include "vc4_context.h"
40 #ifdef USE_VC4_SIMULATOR
41 #include "simpenrose/simpenrose.h"
45 ntq_get_src(struct vc4_compile
*c
, nir_src src
, int i
);
47 ntq_emit_cf_list(struct vc4_compile
*c
, struct exec_list
*list
);
50 resize_qreg_array(struct vc4_compile
*c
,
55 if (*size
>= decl_size
)
58 uint32_t old_size
= *size
;
59 *size
= MAX2(*size
* 2, decl_size
);
60 *regs
= reralloc(c
, *regs
, struct qreg
, *size
);
62 fprintf(stderr
, "Malloc failure\n");
66 for (uint32_t i
= old_size
; i
< *size
; i
++)
67 (*regs
)[i
] = c
->undef
;
71 indirect_uniform_load(struct vc4_compile
*c
, nir_intrinsic_instr
*intr
)
73 struct qreg indirect_offset
= ntq_get_src(c
, intr
->src
[0], 0);
74 uint32_t offset
= intr
->const_index
[0];
75 struct vc4_compiler_ubo_range
*range
= NULL
;
77 for (i
= 0; i
< c
->num_uniform_ranges
; i
++) {
78 range
= &c
->ubo_ranges
[i
];
79 if (offset
>= range
->src_offset
&&
80 offset
< range
->src_offset
+ range
->size
) {
84 /* The driver-location-based offset always has to be within a declared
90 range
->dst_offset
= c
->next_ubo_dst_offset
;
91 c
->next_ubo_dst_offset
+= range
->size
;
95 offset
-= range
->src_offset
;
97 /* Adjust for where we stored the TGSI register base. */
98 indirect_offset
= qir_ADD(c
, indirect_offset
,
99 qir_uniform_ui(c
, (range
->dst_offset
+
102 /* Clamp to [0, array size). Note that MIN/MAX are signed. */
103 indirect_offset
= qir_MAX(c
, indirect_offset
, qir_uniform_ui(c
, 0));
104 indirect_offset
= qir_MIN(c
, indirect_offset
,
105 qir_uniform_ui(c
, (range
->dst_offset
+
108 qir_TEX_DIRECT(c
, indirect_offset
, qir_uniform(c
, QUNIFORM_UBO_ADDR
, 0));
109 c
->num_texture_samples
++;
110 return qir_TEX_RESULT(c
);
113 nir_ssa_def
*vc4_nir_get_state_uniform(struct nir_builder
*b
,
114 enum quniform_contents contents
)
116 nir_intrinsic_instr
*intr
=
117 nir_intrinsic_instr_create(b
->shader
,
118 nir_intrinsic_load_uniform
);
119 intr
->const_index
[0] = (VC4_NIR_STATE_UNIFORM_OFFSET
+ contents
) * 4;
120 intr
->num_components
= 1;
121 intr
->src
[0] = nir_src_for_ssa(nir_imm_int(b
, 0));
122 nir_ssa_dest_init(&intr
->instr
, &intr
->dest
, 1, 32, NULL
);
123 nir_builder_instr_insert(b
, &intr
->instr
);
124 return &intr
->dest
.ssa
;
128 vc4_nir_get_swizzled_channel(nir_builder
*b
, nir_ssa_def
**srcs
, int swiz
)
132 case PIPE_SWIZZLE_NONE
:
133 fprintf(stderr
, "warning: unknown swizzle\n");
136 return nir_imm_float(b
, 0.0);
138 return nir_imm_float(b
, 1.0);
148 ntq_init_ssa_def(struct vc4_compile
*c
, nir_ssa_def
*def
)
150 struct qreg
*qregs
= ralloc_array(c
->def_ht
, struct qreg
,
151 def
->num_components
);
152 _mesa_hash_table_insert(c
->def_ht
, def
, qregs
);
157 ntq_store_dest(struct vc4_compile
*c
, nir_dest
*dest
, int chan
,
161 assert(chan
< dest
->ssa
.num_components
);
164 struct hash_entry
*entry
=
165 _mesa_hash_table_search(c
->def_ht
, &dest
->ssa
);
170 qregs
= ntq_init_ssa_def(c
, &dest
->ssa
);
172 qregs
[chan
] = result
;
174 nir_register
*reg
= dest
->reg
.reg
;
175 assert(dest
->reg
.base_offset
== 0);
176 assert(reg
->num_array_elems
== 0);
177 struct hash_entry
*entry
=
178 _mesa_hash_table_search(c
->def_ht
, reg
);
179 struct qreg
*qregs
= entry
->data
;
181 /* Conditionally move the result to the destination if the
184 if (c
->execute
.file
!= QFILE_NULL
) {
185 qir_SF(c
, c
->execute
);
186 qir_MOV_cond(c
, QPU_COND_ZS
, qregs
[chan
], result
);
188 qir_MOV_dest(c
, qregs
[chan
], result
);
194 ntq_get_dest(struct vc4_compile
*c
, nir_dest
*dest
)
197 struct qreg
*qregs
= ntq_init_ssa_def(c
, &dest
->ssa
);
198 for (int i
= 0; i
< dest
->ssa
.num_components
; i
++)
202 nir_register
*reg
= dest
->reg
.reg
;
203 assert(dest
->reg
.base_offset
== 0);
204 assert(reg
->num_array_elems
== 0);
205 struct hash_entry
*entry
=
206 _mesa_hash_table_search(c
->def_ht
, reg
);
212 ntq_get_src(struct vc4_compile
*c
, nir_src src
, int i
)
214 struct hash_entry
*entry
;
216 entry
= _mesa_hash_table_search(c
->def_ht
, src
.ssa
);
217 assert(i
< src
.ssa
->num_components
);
219 nir_register
*reg
= src
.reg
.reg
;
220 entry
= _mesa_hash_table_search(c
->def_ht
, reg
);
221 assert(reg
->num_array_elems
== 0);
222 assert(src
.reg
.base_offset
== 0);
223 assert(i
< reg
->num_components
);
226 struct qreg
*qregs
= entry
->data
;
231 ntq_get_alu_src(struct vc4_compile
*c
, nir_alu_instr
*instr
,
234 assert(util_is_power_of_two(instr
->dest
.write_mask
));
235 unsigned chan
= ffs(instr
->dest
.write_mask
) - 1;
236 struct qreg r
= ntq_get_src(c
, instr
->src
[src
].src
,
237 instr
->src
[src
].swizzle
[chan
]);
239 assert(!instr
->src
[src
].abs
);
240 assert(!instr
->src
[src
].negate
);
245 static inline struct qreg
246 qir_SAT(struct vc4_compile
*c
, struct qreg val
)
249 qir_FMIN(c
, val
, qir_uniform_f(c
, 1.0)),
250 qir_uniform_f(c
, 0.0));
254 ntq_rcp(struct vc4_compile
*c
, struct qreg x
)
256 struct qreg r
= qir_RCP(c
, x
);
258 /* Apply a Newton-Raphson step to improve the accuracy. */
259 r
= qir_FMUL(c
, r
, qir_FSUB(c
,
260 qir_uniform_f(c
, 2.0),
267 ntq_rsq(struct vc4_compile
*c
, struct qreg x
)
269 struct qreg r
= qir_RSQ(c
, x
);
271 /* Apply a Newton-Raphson step to improve the accuracy. */
272 r
= qir_FMUL(c
, r
, qir_FSUB(c
,
273 qir_uniform_f(c
, 1.5),
275 qir_uniform_f(c
, 0.5),
277 qir_FMUL(c
, r
, r
)))));
283 ntq_umul(struct vc4_compile
*c
, struct qreg src0
, struct qreg src1
)
285 struct qreg src0_hi
= qir_SHR(c
, src0
,
286 qir_uniform_ui(c
, 24));
287 struct qreg src1_hi
= qir_SHR(c
, src1
,
288 qir_uniform_ui(c
, 24));
290 struct qreg hilo
= qir_MUL24(c
, src0_hi
, src1
);
291 struct qreg lohi
= qir_MUL24(c
, src0
, src1_hi
);
292 struct qreg lolo
= qir_MUL24(c
, src0
, src1
);
294 return qir_ADD(c
, lolo
, qir_SHL(c
,
295 qir_ADD(c
, hilo
, lohi
),
296 qir_uniform_ui(c
, 24)));
300 ntq_scale_depth_texture(struct vc4_compile
*c
, struct qreg src
)
302 struct qreg depthf
= qir_ITOF(c
, qir_SHR(c
, src
,
303 qir_uniform_ui(c
, 8)));
304 return qir_FMUL(c
, depthf
, qir_uniform_f(c
, 1.0f
/0xffffff));
308 * Emits a lowered TXF_MS from an MSAA texture.
310 * The addressing math has been lowered in NIR, and now we just need to read
314 ntq_emit_txf(struct vc4_compile
*c
, nir_tex_instr
*instr
)
316 uint32_t tile_width
= 32;
317 uint32_t tile_height
= 32;
318 uint32_t tile_size
= (tile_height
* tile_width
*
319 VC4_MAX_SAMPLES
* sizeof(uint32_t));
321 unsigned unit
= instr
->texture_index
;
322 uint32_t w
= align(c
->key
->tex
[unit
].msaa_width
, tile_width
);
323 uint32_t w_tiles
= w
/ tile_width
;
324 uint32_t h
= align(c
->key
->tex
[unit
].msaa_height
, tile_height
);
325 uint32_t h_tiles
= h
/ tile_height
;
326 uint32_t size
= w_tiles
* h_tiles
* tile_size
;
329 assert(instr
->num_srcs
== 1);
330 assert(instr
->src
[0].src_type
== nir_tex_src_coord
);
331 addr
= ntq_get_src(c
, instr
->src
[0].src
, 0);
333 /* Perform the clamping required by kernel validation. */
334 addr
= qir_MAX(c
, addr
, qir_uniform_ui(c
, 0));
335 addr
= qir_MIN(c
, addr
, qir_uniform_ui(c
, size
- 4));
337 qir_TEX_DIRECT(c
, addr
, qir_uniform(c
, QUNIFORM_TEXTURE_MSAA_ADDR
, unit
));
339 struct qreg tex
= qir_TEX_RESULT(c
);
340 c
->num_texture_samples
++;
343 enum pipe_format format
= c
->key
->tex
[unit
].format
;
344 if (util_format_is_depth_or_stencil(format
)) {
345 struct qreg scaled
= ntq_scale_depth_texture(c
, tex
);
346 for (int i
= 0; i
< 4; i
++)
349 for (int i
= 0; i
< 4; i
++)
350 dest
[i
] = qir_UNPACK_8_F(c
, tex
, i
);
353 for (int i
= 0; i
< 4; i
++)
354 ntq_store_dest(c
, &instr
->dest
, i
, dest
[i
]);
358 ntq_emit_tex(struct vc4_compile
*c
, nir_tex_instr
*instr
)
360 struct qreg s
, t
, r
, lod
, compare
;
361 bool is_txb
= false, is_txl
= false;
362 unsigned unit
= instr
->texture_index
;
364 if (instr
->op
== nir_texop_txf
) {
365 ntq_emit_txf(c
, instr
);
369 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
370 switch (instr
->src
[i
].src_type
) {
371 case nir_tex_src_coord
:
372 s
= ntq_get_src(c
, instr
->src
[i
].src
, 0);
373 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
)
374 t
= qir_uniform_f(c
, 0.5);
376 t
= ntq_get_src(c
, instr
->src
[i
].src
, 1);
377 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
378 r
= ntq_get_src(c
, instr
->src
[i
].src
, 2);
380 case nir_tex_src_bias
:
381 lod
= ntq_get_src(c
, instr
->src
[i
].src
, 0);
384 case nir_tex_src_lod
:
385 lod
= ntq_get_src(c
, instr
->src
[i
].src
, 0);
388 case nir_tex_src_comparitor
:
389 compare
= ntq_get_src(c
, instr
->src
[i
].src
, 0);
392 unreachable("unknown texture source");
396 if (c
->key
->tex
[unit
].force_first_level
) {
397 lod
= qir_uniform(c
, QUNIFORM_TEXTURE_FIRST_LEVEL
, unit
);
402 struct qreg texture_u
[] = {
403 qir_uniform(c
, QUNIFORM_TEXTURE_CONFIG_P0
, unit
),
404 qir_uniform(c
, QUNIFORM_TEXTURE_CONFIG_P1
, unit
),
405 qir_uniform(c
, QUNIFORM_CONSTANT
, 0),
406 qir_uniform(c
, QUNIFORM_CONSTANT
, 0),
408 uint32_t next_texture_u
= 0;
410 /* There is no native support for GL texture rectangle coordinates, so
411 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
414 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_RECT
) {
416 qir_uniform(c
, QUNIFORM_TEXRECT_SCALE_X
, unit
));
418 qir_uniform(c
, QUNIFORM_TEXRECT_SCALE_Y
, unit
));
421 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
|| is_txl
) {
422 texture_u
[2] = qir_uniform(c
, QUNIFORM_TEXTURE_CONFIG_P2
,
423 unit
| (is_txl
<< 16));
426 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
427 qir_TEX_R(c
, r
, texture_u
[next_texture_u
++]);
428 } else if (c
->key
->tex
[unit
].wrap_s
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
429 c
->key
->tex
[unit
].wrap_s
== PIPE_TEX_WRAP_CLAMP
||
430 c
->key
->tex
[unit
].wrap_t
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
431 c
->key
->tex
[unit
].wrap_t
== PIPE_TEX_WRAP_CLAMP
) {
432 qir_TEX_R(c
, qir_uniform(c
, QUNIFORM_TEXTURE_BORDER_COLOR
, unit
),
433 texture_u
[next_texture_u
++]);
436 if (c
->key
->tex
[unit
].wrap_s
== PIPE_TEX_WRAP_CLAMP
) {
440 if (c
->key
->tex
[unit
].wrap_t
== PIPE_TEX_WRAP_CLAMP
) {
444 qir_TEX_T(c
, t
, texture_u
[next_texture_u
++]);
446 if (is_txl
|| is_txb
)
447 qir_TEX_B(c
, lod
, texture_u
[next_texture_u
++]);
449 qir_TEX_S(c
, s
, texture_u
[next_texture_u
++]);
451 c
->num_texture_samples
++;
452 struct qreg tex
= qir_TEX_RESULT(c
);
454 enum pipe_format format
= c
->key
->tex
[unit
].format
;
456 struct qreg
*dest
= ntq_get_dest(c
, &instr
->dest
);
457 if (util_format_is_depth_or_stencil(format
)) {
458 struct qreg normalized
= ntq_scale_depth_texture(c
, tex
);
459 struct qreg depth_output
;
461 struct qreg u0
= qir_uniform_f(c
, 0.0f
);
462 struct qreg u1
= qir_uniform_f(c
, 1.0f
);
463 if (c
->key
->tex
[unit
].compare_mode
) {
464 switch (c
->key
->tex
[unit
].compare_func
) {
465 case PIPE_FUNC_NEVER
:
466 depth_output
= qir_uniform_f(c
, 0.0f
);
468 case PIPE_FUNC_ALWAYS
:
471 case PIPE_FUNC_EQUAL
:
472 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
473 depth_output
= qir_SEL(c
, QPU_COND_ZS
, u1
, u0
);
475 case PIPE_FUNC_NOTEQUAL
:
476 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
477 depth_output
= qir_SEL(c
, QPU_COND_ZC
, u1
, u0
);
479 case PIPE_FUNC_GREATER
:
480 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
481 depth_output
= qir_SEL(c
, QPU_COND_NC
, u1
, u0
);
483 case PIPE_FUNC_GEQUAL
:
484 qir_SF(c
, qir_FSUB(c
, normalized
, compare
));
485 depth_output
= qir_SEL(c
, QPU_COND_NS
, u1
, u0
);
488 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
489 depth_output
= qir_SEL(c
, QPU_COND_NS
, u1
, u0
);
491 case PIPE_FUNC_LEQUAL
:
492 qir_SF(c
, qir_FSUB(c
, normalized
, compare
));
493 depth_output
= qir_SEL(c
, QPU_COND_NC
, u1
, u0
);
497 depth_output
= normalized
;
500 for (int i
= 0; i
< 4; i
++)
501 dest
[i
] = depth_output
;
503 for (int i
= 0; i
< 4; i
++)
504 dest
[i
] = qir_UNPACK_8_F(c
, tex
, i
);
509 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
513 ntq_ffract(struct vc4_compile
*c
, struct qreg src
)
515 struct qreg trunc
= qir_ITOF(c
, qir_FTOI(c
, src
));
516 struct qreg diff
= qir_FSUB(c
, src
, trunc
);
518 return qir_SEL(c
, QPU_COND_NS
,
519 qir_FADD(c
, diff
, qir_uniform_f(c
, 1.0)), diff
);
523 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
527 ntq_ffloor(struct vc4_compile
*c
, struct qreg src
)
529 struct qreg trunc
= qir_ITOF(c
, qir_FTOI(c
, src
));
531 /* This will be < 0 if we truncated and the truncation was of a value
532 * that was < 0 in the first place.
534 qir_SF(c
, qir_FSUB(c
, src
, trunc
));
536 return qir_SEL(c
, QPU_COND_NS
,
537 qir_FSUB(c
, trunc
, qir_uniform_f(c
, 1.0)), trunc
);
541 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
545 ntq_fceil(struct vc4_compile
*c
, struct qreg src
)
547 struct qreg trunc
= qir_ITOF(c
, qir_FTOI(c
, src
));
549 /* This will be < 0 if we truncated and the truncation was of a value
550 * that was > 0 in the first place.
552 qir_SF(c
, qir_FSUB(c
, trunc
, src
));
554 return qir_SEL(c
, QPU_COND_NS
,
555 qir_FADD(c
, trunc
, qir_uniform_f(c
, 1.0)), trunc
);
559 ntq_fsin(struct vc4_compile
*c
, struct qreg src
)
563 pow(2.0 * M_PI
, 3) / (3 * 2 * 1),
564 -pow(2.0 * M_PI
, 5) / (5 * 4 * 3 * 2 * 1),
565 pow(2.0 * M_PI
, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
566 -pow(2.0 * M_PI
, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
569 struct qreg scaled_x
=
572 qir_uniform_f(c
, 1.0 / (M_PI
* 2.0)));
574 struct qreg x
= qir_FADD(c
,
575 ntq_ffract(c
, scaled_x
),
576 qir_uniform_f(c
, -0.5));
577 struct qreg x2
= qir_FMUL(c
, x
, x
);
578 struct qreg sum
= qir_FMUL(c
, x
, qir_uniform_f(c
, coeff
[0]));
579 for (int i
= 1; i
< ARRAY_SIZE(coeff
); i
++) {
580 x
= qir_FMUL(c
, x
, x2
);
585 qir_uniform_f(c
, coeff
[i
])));
591 ntq_fcos(struct vc4_compile
*c
, struct qreg src
)
595 pow(2.0 * M_PI
, 2) / (2 * 1),
596 -pow(2.0 * M_PI
, 4) / (4 * 3 * 2 * 1),
597 pow(2.0 * M_PI
, 6) / (6 * 5 * 4 * 3 * 2 * 1),
598 -pow(2.0 * M_PI
, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
599 pow(2.0 * M_PI
, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
602 struct qreg scaled_x
=
604 qir_uniform_f(c
, 1.0f
/ (M_PI
* 2.0f
)));
605 struct qreg x_frac
= qir_FADD(c
,
606 ntq_ffract(c
, scaled_x
),
607 qir_uniform_f(c
, -0.5));
609 struct qreg sum
= qir_uniform_f(c
, coeff
[0]);
610 struct qreg x2
= qir_FMUL(c
, x_frac
, x_frac
);
611 struct qreg x
= x2
; /* Current x^2, x^4, or x^6 */
612 for (int i
= 1; i
< ARRAY_SIZE(coeff
); i
++) {
614 x
= qir_FMUL(c
, x
, x2
);
616 struct qreg mul
= qir_FMUL(c
,
618 qir_uniform_f(c
, coeff
[i
]));
622 sum
= qir_FADD(c
, sum
, mul
);
628 ntq_fsign(struct vc4_compile
*c
, struct qreg src
)
630 struct qreg t
= qir_get_temp(c
);
633 qir_MOV_dest(c
, t
, qir_uniform_f(c
, 0.0));
634 qir_MOV_dest(c
, t
, qir_uniform_f(c
, 1.0))->cond
= QPU_COND_ZC
;
635 qir_MOV_dest(c
, t
, qir_uniform_f(c
, -1.0))->cond
= QPU_COND_NS
;
640 emit_vertex_input(struct vc4_compile
*c
, int attr
)
642 enum pipe_format format
= c
->vs_key
->attr_formats
[attr
];
643 uint32_t attr_size
= util_format_get_blocksize(format
);
645 c
->vattr_sizes
[attr
] = align(attr_size
, 4);
646 for (int i
= 0; i
< align(attr_size
, 4) / 4; i
++) {
647 c
->inputs
[attr
* 4 + i
] =
648 qir_MOV(c
, qir_reg(QFILE_VPM
, attr
* 4 + i
));
654 emit_fragcoord_input(struct vc4_compile
*c
, int attr
)
656 c
->inputs
[attr
* 4 + 0] = qir_ITOF(c
, qir_reg(QFILE_FRAG_X
, 0));
657 c
->inputs
[attr
* 4 + 1] = qir_ITOF(c
, qir_reg(QFILE_FRAG_Y
, 0));
658 c
->inputs
[attr
* 4 + 2] =
660 qir_ITOF(c
, qir_FRAG_Z(c
)),
661 qir_uniform_f(c
, 1.0 / 0xffffff));
662 c
->inputs
[attr
* 4 + 3] = qir_RCP(c
, qir_FRAG_W(c
));
666 emit_fragment_varying(struct vc4_compile
*c
, gl_varying_slot slot
,
669 uint32_t i
= c
->num_input_slots
++;
675 if (c
->num_input_slots
>= c
->input_slots_array_size
) {
676 c
->input_slots_array_size
=
677 MAX2(4, c
->input_slots_array_size
* 2);
679 c
->input_slots
= reralloc(c
, c
->input_slots
,
680 struct vc4_varying_slot
,
681 c
->input_slots_array_size
);
684 c
->input_slots
[i
].slot
= slot
;
685 c
->input_slots
[i
].swizzle
= swizzle
;
687 return qir_VARY_ADD_C(c
, qir_FMUL(c
, vary
, qir_FRAG_W(c
)));
691 emit_fragment_input(struct vc4_compile
*c
, int attr
, gl_varying_slot slot
)
693 for (int i
= 0; i
< 4; i
++) {
694 c
->inputs
[attr
* 4 + i
] =
695 emit_fragment_varying(c
, slot
, i
);
701 add_output(struct vc4_compile
*c
,
702 uint32_t decl_offset
,
706 uint32_t old_array_size
= c
->outputs_array_size
;
707 resize_qreg_array(c
, &c
->outputs
, &c
->outputs_array_size
,
710 if (old_array_size
!= c
->outputs_array_size
) {
711 c
->output_slots
= reralloc(c
,
713 struct vc4_varying_slot
,
714 c
->outputs_array_size
);
717 c
->output_slots
[decl_offset
].slot
= slot
;
718 c
->output_slots
[decl_offset
].swizzle
= swizzle
;
722 declare_uniform_range(struct vc4_compile
*c
, uint32_t start
, uint32_t size
)
724 unsigned array_id
= c
->num_uniform_ranges
++;
725 if (array_id
>= c
->ubo_ranges_array_size
) {
726 c
->ubo_ranges_array_size
= MAX2(c
->ubo_ranges_array_size
* 2,
728 c
->ubo_ranges
= reralloc(c
, c
->ubo_ranges
,
729 struct vc4_compiler_ubo_range
,
730 c
->ubo_ranges_array_size
);
733 c
->ubo_ranges
[array_id
].dst_offset
= 0;
734 c
->ubo_ranges
[array_id
].src_offset
= start
;
735 c
->ubo_ranges
[array_id
].size
= size
;
736 c
->ubo_ranges
[array_id
].used
= false;
740 ntq_src_is_only_ssa_def_user(nir_src
*src
)
745 if (!list_empty(&src
->ssa
->if_uses
))
748 return (src
->ssa
->uses
.next
== &src
->use_link
&&
749 src
->ssa
->uses
.next
->next
== &src
->ssa
->uses
);
753 * In general, emits a nir_pack_unorm_4x8 as a series of MOVs with the pack
756 * However, as an optimization, it tries to find the instructions generating
757 * the sources to be packed and just emit the pack flag there, if possible.
760 ntq_emit_pack_unorm_4x8(struct vc4_compile
*c
, nir_alu_instr
*instr
)
762 struct qreg result
= qir_get_temp(c
);
763 struct nir_alu_instr
*vec4
= NULL
;
765 /* If packing from a vec4 op (as expected), identify it so that we can
766 * peek back at what generated its sources.
768 if (instr
->src
[0].src
.is_ssa
&&
769 instr
->src
[0].src
.ssa
->parent_instr
->type
== nir_instr_type_alu
&&
770 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
)->op
==
772 vec4
= nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
775 /* If the pack is replicating the same channel 4 times, use the 8888
776 * pack flag. This is common for blending using the alpha
779 if (instr
->src
[0].swizzle
[0] == instr
->src
[0].swizzle
[1] &&
780 instr
->src
[0].swizzle
[0] == instr
->src
[0].swizzle
[2] &&
781 instr
->src
[0].swizzle
[0] == instr
->src
[0].swizzle
[3]) {
782 struct qreg rep
= ntq_get_src(c
,
784 instr
->src
[0].swizzle
[0]);
785 ntq_store_dest(c
, &instr
->dest
.dest
, 0, qir_PACK_8888_F(c
, rep
));
789 for (int i
= 0; i
< 4; i
++) {
790 int swiz
= instr
->src
[0].swizzle
[i
];
793 src
= ntq_get_src(c
, vec4
->src
[swiz
].src
,
794 vec4
->src
[swiz
].swizzle
[0]);
796 src
= ntq_get_src(c
, instr
->src
[0].src
, swiz
);
800 ntq_src_is_only_ssa_def_user(&vec4
->src
[swiz
].src
) &&
801 src
.file
== QFILE_TEMP
&&
802 c
->defs
[src
.index
] &&
803 qir_is_mul(c
->defs
[src
.index
]) &&
804 !c
->defs
[src
.index
]->dst
.pack
) {
805 struct qinst
*rewrite
= c
->defs
[src
.index
];
806 c
->defs
[src
.index
] = NULL
;
807 rewrite
->dst
= result
;
808 rewrite
->dst
.pack
= QPU_PACK_MUL_8A
+ i
;
812 qir_PACK_8_F(c
, result
, src
, i
);
815 ntq_store_dest(c
, &instr
->dest
.dest
, 0, result
);
818 /** Handles sign-extended bitfield extracts for 16 bits. */
820 ntq_emit_ibfe(struct vc4_compile
*c
, struct qreg base
, struct qreg offset
,
823 assert(bits
.file
== QFILE_UNIF
&&
824 c
->uniform_contents
[bits
.index
] == QUNIFORM_CONSTANT
&&
825 c
->uniform_data
[bits
.index
] == 16);
827 assert(offset
.file
== QFILE_UNIF
&&
828 c
->uniform_contents
[offset
.index
] == QUNIFORM_CONSTANT
);
829 int offset_bit
= c
->uniform_data
[offset
.index
];
830 assert(offset_bit
% 16 == 0);
832 return qir_UNPACK_16_I(c
, base
, offset_bit
/ 16);
835 /** Handles unsigned bitfield extracts for 8 bits. */
837 ntq_emit_ubfe(struct vc4_compile
*c
, struct qreg base
, struct qreg offset
,
840 assert(bits
.file
== QFILE_UNIF
&&
841 c
->uniform_contents
[bits
.index
] == QUNIFORM_CONSTANT
&&
842 c
->uniform_data
[bits
.index
] == 8);
844 assert(offset
.file
== QFILE_UNIF
&&
845 c
->uniform_contents
[offset
.index
] == QUNIFORM_CONSTANT
);
846 int offset_bit
= c
->uniform_data
[offset
.index
];
847 assert(offset_bit
% 8 == 0);
849 return qir_UNPACK_8_I(c
, base
, offset_bit
/ 8);
853 * If compare_instr is a valid comparison instruction, emits the
854 * compare_instr's comparison and returns the sel_instr's return value based
855 * on the compare_instr's result.
858 ntq_emit_comparison(struct vc4_compile
*c
, struct qreg
*dest
,
859 nir_alu_instr
*compare_instr
,
860 nir_alu_instr
*sel_instr
)
864 switch (compare_instr
->op
) {
890 struct qreg src0
= ntq_get_alu_src(c
, compare_instr
, 0);
891 struct qreg src1
= ntq_get_alu_src(c
, compare_instr
, 1);
893 unsigned unsized_type
=
894 nir_alu_type_get_base_type(nir_op_infos
[compare_instr
->op
].input_types
[0]);
895 if (unsized_type
== nir_type_float
)
896 qir_SF(c
, qir_FSUB(c
, src0
, src1
));
898 qir_SF(c
, qir_SUB(c
, src0
, src1
));
900 switch (sel_instr
->op
) {
905 *dest
= qir_SEL(c
, cond
,
906 qir_uniform_f(c
, 1.0), qir_uniform_f(c
, 0.0));
910 *dest
= qir_SEL(c
, cond
,
911 ntq_get_alu_src(c
, sel_instr
, 1),
912 ntq_get_alu_src(c
, sel_instr
, 2));
916 *dest
= qir_SEL(c
, cond
,
917 qir_uniform_ui(c
, ~0), qir_uniform_ui(c
, 0));
925 * Attempts to fold a comparison generating a boolean result into the
926 * condition code for selecting between two values, instead of comparing the
927 * boolean result against 0 to generate the condition code.
929 static struct qreg
ntq_emit_bcsel(struct vc4_compile
*c
, nir_alu_instr
*instr
,
932 if (!instr
->src
[0].src
.is_ssa
)
934 nir_alu_instr
*compare
=
935 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
940 if (ntq_emit_comparison(c
, &dest
, compare
, instr
))
945 return qir_SEL(c
, QPU_COND_NS
, src
[1], src
[2]);
949 ntq_emit_alu(struct vc4_compile
*c
, nir_alu_instr
*instr
)
951 /* This should always be lowered to ALU operations for VC4. */
952 assert(!instr
->dest
.saturate
);
954 /* Vectors are special in that they have non-scalarized writemasks,
955 * and just take the first swizzle channel for each argument in order
956 * into each writemask channel.
958 if (instr
->op
== nir_op_vec2
||
959 instr
->op
== nir_op_vec3
||
960 instr
->op
== nir_op_vec4
) {
962 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
963 srcs
[i
] = ntq_get_src(c
, instr
->src
[i
].src
,
964 instr
->src
[i
].swizzle
[0]);
965 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
966 ntq_store_dest(c
, &instr
->dest
.dest
, i
, srcs
[i
]);
970 if (instr
->op
== nir_op_pack_unorm_4x8
) {
971 ntq_emit_pack_unorm_4x8(c
, instr
);
975 if (instr
->op
== nir_op_unpack_unorm_4x8
) {
976 struct qreg src
= ntq_get_src(c
, instr
->src
[0].src
,
977 instr
->src
[0].swizzle
[0]);
978 for (int i
= 0; i
< 4; i
++) {
979 if (instr
->dest
.write_mask
& (1 << i
))
980 ntq_store_dest(c
, &instr
->dest
.dest
, i
,
981 qir_UNPACK_8_F(c
, src
, i
));
986 /* General case: We can just grab the one used channel per src. */
987 struct qreg src
[nir_op_infos
[instr
->op
].num_inputs
];
988 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
989 src
[i
] = ntq_get_alu_src(c
, instr
, i
);
997 result
= qir_MOV(c
, src
[0]);
1000 result
= qir_FMUL(c
, src
[0], src
[1]);
1003 result
= qir_FADD(c
, src
[0], src
[1]);
1006 result
= qir_FSUB(c
, src
[0], src
[1]);
1009 result
= qir_FMIN(c
, src
[0], src
[1]);
1012 result
= qir_FMAX(c
, src
[0], src
[1]);
1017 result
= qir_FTOI(c
, src
[0]);
1021 result
= qir_ITOF(c
, src
[0]);
1024 result
= qir_AND(c
, src
[0], qir_uniform_f(c
, 1.0));
1027 result
= qir_AND(c
, src
[0], qir_uniform_ui(c
, 1));
1032 result
= qir_SEL(c
, QPU_COND_ZC
,
1033 qir_uniform_ui(c
, ~0),
1034 qir_uniform_ui(c
, 0));
1038 result
= qir_ADD(c
, src
[0], src
[1]);
1041 result
= qir_SHR(c
, src
[0], src
[1]);
1044 result
= qir_SUB(c
, src
[0], src
[1]);
1047 result
= qir_ASR(c
, src
[0], src
[1]);
1050 result
= qir_SHL(c
, src
[0], src
[1]);
1053 result
= qir_MIN(c
, src
[0], src
[1]);
1056 result
= qir_MAX(c
, src
[0], src
[1]);
1059 result
= qir_AND(c
, src
[0], src
[1]);
1062 result
= qir_OR(c
, src
[0], src
[1]);
1065 result
= qir_XOR(c
, src
[0], src
[1]);
1068 result
= qir_NOT(c
, src
[0]);
1072 result
= ntq_umul(c
, src
[0], src
[1]);
1088 if (!ntq_emit_comparison(c
, &result
, instr
, instr
)) {
1089 fprintf(stderr
, "Bad comparison instruction\n");
1094 result
= ntq_emit_bcsel(c
, instr
, src
);
1098 result
= qir_SEL(c
, QPU_COND_ZC
, src
[1], src
[2]);
1102 result
= ntq_rcp(c
, src
[0]);
1105 result
= ntq_rsq(c
, src
[0]);
1108 result
= qir_EXP2(c
, src
[0]);
1111 result
= qir_LOG2(c
, src
[0]);
1115 result
= qir_ITOF(c
, qir_FTOI(c
, src
[0]));
1118 result
= ntq_fceil(c
, src
[0]);
1121 result
= ntq_ffract(c
, src
[0]);
1124 result
= ntq_ffloor(c
, src
[0]);
1128 result
= ntq_fsin(c
, src
[0]);
1131 result
= ntq_fcos(c
, src
[0]);
1135 result
= ntq_fsign(c
, src
[0]);
1139 result
= qir_FMAXABS(c
, src
[0], src
[0]);
1142 result
= qir_MAX(c
, src
[0],
1143 qir_SUB(c
, qir_uniform_ui(c
, 0), src
[0]));
1146 case nir_op_ibitfield_extract
:
1147 result
= ntq_emit_ibfe(c
, src
[0], src
[1], src
[2]);
1150 case nir_op_ubitfield_extract
:
1151 result
= ntq_emit_ubfe(c
, src
[0], src
[1], src
[2]);
1154 case nir_op_usadd_4x8
:
1155 result
= qir_V8ADDS(c
, src
[0], src
[1]);
1158 case nir_op_ussub_4x8
:
1159 result
= qir_V8SUBS(c
, src
[0], src
[1]);
1162 case nir_op_umin_4x8
:
1163 result
= qir_V8MIN(c
, src
[0], src
[1]);
1166 case nir_op_umax_4x8
:
1167 result
= qir_V8MAX(c
, src
[0], src
[1]);
1170 case nir_op_umul_unorm_4x8
:
1171 result
= qir_V8MULD(c
, src
[0], src
[1]);
1175 fprintf(stderr
, "unknown NIR ALU inst: ");
1176 nir_print_instr(&instr
->instr
, stderr
);
1177 fprintf(stderr
, "\n");
1181 /* We have a scalar result, so the instruction should only have a
1182 * single channel written to.
1184 assert(util_is_power_of_two(instr
->dest
.write_mask
));
1185 ntq_store_dest(c
, &instr
->dest
.dest
,
1186 ffs(instr
->dest
.write_mask
) - 1, result
);
1190 emit_frag_end(struct vc4_compile
*c
)
1193 if (c
->output_color_index
!= -1) {
1194 color
= c
->outputs
[c
->output_color_index
];
1196 color
= qir_uniform_ui(c
, 0);
1199 uint32_t discard_cond
= QPU_COND_ALWAYS
;
1200 if (c
->discard
.file
!= QFILE_NULL
) {
1201 qir_SF(c
, c
->discard
);
1202 discard_cond
= QPU_COND_ZS
;
1205 if (c
->fs_key
->stencil_enabled
) {
1206 qir_MOV_dest(c
, qir_reg(QFILE_TLB_STENCIL_SETUP
, 0),
1207 qir_uniform(c
, QUNIFORM_STENCIL
, 0));
1208 if (c
->fs_key
->stencil_twoside
) {
1209 qir_MOV_dest(c
, qir_reg(QFILE_TLB_STENCIL_SETUP
, 0),
1210 qir_uniform(c
, QUNIFORM_STENCIL
, 1));
1212 if (c
->fs_key
->stencil_full_writemasks
) {
1213 qir_MOV_dest(c
, qir_reg(QFILE_TLB_STENCIL_SETUP
, 0),
1214 qir_uniform(c
, QUNIFORM_STENCIL
, 2));
1218 if (c
->output_sample_mask_index
!= -1) {
1219 qir_MS_MASK(c
, c
->outputs
[c
->output_sample_mask_index
]);
1222 if (c
->fs_key
->depth_enabled
) {
1223 if (c
->output_position_index
!= -1) {
1224 qir_FTOI_dest(c
, qir_reg(QFILE_TLB_Z_WRITE
, 0),
1226 c
->outputs
[c
->output_position_index
+ 2],
1227 qir_uniform_f(c
, 0xffffff)))->cond
= discard_cond
;
1229 qir_MOV_dest(c
, qir_reg(QFILE_TLB_Z_WRITE
, 0),
1230 qir_FRAG_Z(c
))->cond
= discard_cond
;
1234 if (!c
->msaa_per_sample_output
) {
1235 qir_MOV_dest(c
, qir_reg(QFILE_TLB_COLOR_WRITE
, 0),
1236 color
)->cond
= discard_cond
;
1238 for (int i
= 0; i
< VC4_MAX_SAMPLES
; i
++) {
1239 qir_MOV_dest(c
, qir_reg(QFILE_TLB_COLOR_WRITE_MS
, 0),
1240 c
->sample_colors
[i
])->cond
= discard_cond
;
1246 emit_scaled_viewport_write(struct vc4_compile
*c
, struct qreg rcp_w
)
1248 struct qreg packed
= qir_get_temp(c
);
1250 for (int i
= 0; i
< 2; i
++) {
1252 qir_uniform(c
, QUNIFORM_VIEWPORT_X_SCALE
+ i
, 0);
1254 struct qreg packed_chan
= packed
;
1255 packed_chan
.pack
= QPU_PACK_A_16A
+ i
;
1257 qir_FTOI_dest(c
, packed_chan
,
1260 c
->outputs
[c
->output_position_index
+ i
],
1265 qir_VPM_WRITE(c
, packed
);
1269 emit_zs_write(struct vc4_compile
*c
, struct qreg rcp_w
)
1271 struct qreg zscale
= qir_uniform(c
, QUNIFORM_VIEWPORT_Z_SCALE
, 0);
1272 struct qreg zoffset
= qir_uniform(c
, QUNIFORM_VIEWPORT_Z_OFFSET
, 0);
1274 qir_VPM_WRITE(c
, qir_FADD(c
, qir_FMUL(c
, qir_FMUL(c
,
1275 c
->outputs
[c
->output_position_index
+ 2],
1282 emit_rcp_wc_write(struct vc4_compile
*c
, struct qreg rcp_w
)
1284 qir_VPM_WRITE(c
, rcp_w
);
1288 emit_point_size_write(struct vc4_compile
*c
)
1290 struct qreg point_size
;
1292 if (c
->output_point_size_index
!= -1)
1293 point_size
= c
->outputs
[c
->output_point_size_index
];
1295 point_size
= qir_uniform_f(c
, 1.0);
1297 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1300 point_size
= qir_FMAX(c
, point_size
, qir_uniform_f(c
, .125));
1302 qir_VPM_WRITE(c
, point_size
);
1306 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1308 * The simulator insists that there be at least one vertex attribute, so
1309 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also
1310 * insists that all vertex attributes loaded get read by the VS/CS, so we have
1311 * to consume it here.
1314 emit_stub_vpm_read(struct vc4_compile
*c
)
1319 c
->vattr_sizes
[0] = 4;
1320 (void)qir_MOV(c
, qir_reg(QFILE_VPM
, 0));
1325 emit_vert_end(struct vc4_compile
*c
,
1326 struct vc4_varying_slot
*fs_inputs
,
1327 uint32_t num_fs_inputs
)
1329 struct qreg rcp_w
= qir_RCP(c
, c
->outputs
[c
->output_position_index
+ 3]);
1331 emit_stub_vpm_read(c
);
1333 emit_scaled_viewport_write(c
, rcp_w
);
1334 emit_zs_write(c
, rcp_w
);
1335 emit_rcp_wc_write(c
, rcp_w
);
1336 if (c
->vs_key
->per_vertex_point_size
)
1337 emit_point_size_write(c
);
1339 for (int i
= 0; i
< num_fs_inputs
; i
++) {
1340 struct vc4_varying_slot
*input
= &fs_inputs
[i
];
1343 for (j
= 0; j
< c
->num_outputs
; j
++) {
1344 struct vc4_varying_slot
*output
=
1345 &c
->output_slots
[j
];
1347 if (input
->slot
== output
->slot
&&
1348 input
->swizzle
== output
->swizzle
) {
1349 qir_VPM_WRITE(c
, c
->outputs
[j
]);
1353 /* Emit padding if we didn't find a declared VS output for
1356 if (j
== c
->num_outputs
)
1357 qir_VPM_WRITE(c
, qir_uniform_f(c
, 0.0));
1362 emit_coord_end(struct vc4_compile
*c
)
1364 struct qreg rcp_w
= qir_RCP(c
, c
->outputs
[c
->output_position_index
+ 3]);
1366 emit_stub_vpm_read(c
);
1368 for (int i
= 0; i
< 4; i
++)
1369 qir_VPM_WRITE(c
, c
->outputs
[c
->output_position_index
+ i
]);
1371 emit_scaled_viewport_write(c
, rcp_w
);
1372 emit_zs_write(c
, rcp_w
);
1373 emit_rcp_wc_write(c
, rcp_w
);
1374 if (c
->vs_key
->per_vertex_point_size
)
1375 emit_point_size_write(c
);
1379 vc4_optimize_nir(struct nir_shader
*s
)
1386 NIR_PASS_V(s
, nir_lower_vars_to_ssa
);
1387 NIR_PASS_V(s
, nir_lower_alu_to_scalar
);
1388 NIR_PASS_V(s
, nir_lower_phis_to_scalar
);
1390 NIR_PASS(progress
, s
, nir_copy_prop
);
1391 NIR_PASS(progress
, s
, nir_opt_remove_phis
);
1392 NIR_PASS(progress
, s
, nir_opt_dce
);
1393 NIR_PASS(progress
, s
, nir_opt_dead_cf
);
1394 NIR_PASS(progress
, s
, nir_opt_cse
);
1395 NIR_PASS(progress
, s
, nir_opt_peephole_select
);
1396 NIR_PASS(progress
, s
, nir_opt_algebraic
);
1397 NIR_PASS(progress
, s
, nir_opt_constant_folding
);
1398 NIR_PASS(progress
, s
, nir_opt_undef
);
1403 driver_location_compare(const void *in_a
, const void *in_b
)
1405 const nir_variable
*const *a
= in_a
;
1406 const nir_variable
*const *b
= in_b
;
1408 return (*a
)->data
.driver_location
- (*b
)->data
.driver_location
;
1412 ntq_setup_inputs(struct vc4_compile
*c
)
1414 unsigned num_entries
= 0;
1415 nir_foreach_variable(var
, &c
->s
->inputs
)
1418 nir_variable
*vars
[num_entries
];
1421 nir_foreach_variable(var
, &c
->s
->inputs
)
1424 /* Sort the variables so that we emit the input setup in
1425 * driver_location order. This is required for VPM reads, whose data
1426 * is fetched into the VPM in driver_location (TGSI register index)
1429 qsort(&vars
, num_entries
, sizeof(*vars
), driver_location_compare
);
1431 for (unsigned i
= 0; i
< num_entries
; i
++) {
1432 nir_variable
*var
= vars
[i
];
1433 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1434 unsigned loc
= var
->data
.driver_location
;
1436 assert(array_len
== 1);
1438 resize_qreg_array(c
, &c
->inputs
, &c
->inputs_array_size
,
1441 if (c
->stage
== QSTAGE_FRAG
) {
1442 if (var
->data
.location
== VARYING_SLOT_POS
) {
1443 emit_fragcoord_input(c
, loc
);
1444 } else if (var
->data
.location
>= VARYING_SLOT_VAR0
&&
1445 (c
->fs_key
->point_sprite_mask
&
1446 (1 << (var
->data
.location
-
1447 VARYING_SLOT_VAR0
)))) {
1448 c
->inputs
[loc
* 4 + 0] = c
->point_x
;
1449 c
->inputs
[loc
* 4 + 1] = c
->point_y
;
1451 emit_fragment_input(c
, loc
, var
->data
.location
);
1454 emit_vertex_input(c
, loc
);
1460 ntq_setup_outputs(struct vc4_compile
*c
)
1462 nir_foreach_variable(var
, &c
->s
->outputs
) {
1463 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1464 unsigned loc
= var
->data
.driver_location
* 4;
1466 assert(array_len
== 1);
1469 for (int i
= 0; i
< 4; i
++)
1470 add_output(c
, loc
+ i
, var
->data
.location
, i
);
1472 if (c
->stage
== QSTAGE_FRAG
) {
1473 switch (var
->data
.location
) {
1474 case FRAG_RESULT_COLOR
:
1475 case FRAG_RESULT_DATA0
:
1476 c
->output_color_index
= loc
;
1478 case FRAG_RESULT_DEPTH
:
1479 c
->output_position_index
= loc
;
1481 case FRAG_RESULT_SAMPLE_MASK
:
1482 c
->output_sample_mask_index
= loc
;
1486 switch (var
->data
.location
) {
1487 case VARYING_SLOT_POS
:
1488 c
->output_position_index
= loc
;
1490 case VARYING_SLOT_PSIZ
:
1491 c
->output_point_size_index
= loc
;
1499 ntq_setup_uniforms(struct vc4_compile
*c
)
1501 nir_foreach_variable(var
, &c
->s
->uniforms
) {
1502 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1503 unsigned array_elem_size
= 4 * sizeof(float);
1505 declare_uniform_range(c
, var
->data
.driver_location
* array_elem_size
,
1506 array_len
* array_elem_size
);
1512 * Sets up the mapping from nir_register to struct qreg *.
1514 * Each nir_register gets a struct qreg per 32-bit component being stored.
1517 ntq_setup_registers(struct vc4_compile
*c
, struct exec_list
*list
)
1519 foreach_list_typed(nir_register
, nir_reg
, node
, list
) {
1520 unsigned array_len
= MAX2(nir_reg
->num_array_elems
, 1);
1521 struct qreg
*qregs
= ralloc_array(c
->def_ht
, struct qreg
,
1523 nir_reg
->num_components
);
1525 _mesa_hash_table_insert(c
->def_ht
, nir_reg
, qregs
);
1527 for (int i
= 0; i
< array_len
* nir_reg
->num_components
; i
++)
1528 qregs
[i
] = qir_get_temp(c
);
1533 ntq_emit_load_const(struct vc4_compile
*c
, nir_load_const_instr
*instr
)
1535 struct qreg
*qregs
= ntq_init_ssa_def(c
, &instr
->def
);
1536 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1537 qregs
[i
] = qir_uniform_ui(c
, instr
->value
.u32
[i
]);
1539 _mesa_hash_table_insert(c
->def_ht
, &instr
->def
, qregs
);
1543 ntq_emit_ssa_undef(struct vc4_compile
*c
, nir_ssa_undef_instr
*instr
)
1545 struct qreg
*qregs
= ntq_init_ssa_def(c
, &instr
->def
);
1547 /* QIR needs there to be *some* value, so pick 0 (same as for
1548 * ntq_setup_registers().
1550 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1551 qregs
[i
] = qir_uniform_ui(c
, 0);
1555 ntq_emit_intrinsic(struct vc4_compile
*c
, nir_intrinsic_instr
*instr
)
1557 nir_const_value
*const_offset
;
1560 switch (instr
->intrinsic
) {
1561 case nir_intrinsic_load_uniform
:
1562 assert(instr
->num_components
== 1);
1563 const_offset
= nir_src_as_const_value(instr
->src
[0]);
1565 offset
= instr
->const_index
[0] + const_offset
->u32
[0];
1566 assert(offset
% 4 == 0);
1567 /* We need dwords */
1568 offset
= offset
/ 4;
1569 if (offset
< VC4_NIR_STATE_UNIFORM_OFFSET
) {
1570 ntq_store_dest(c
, &instr
->dest
, 0,
1571 qir_uniform(c
, QUNIFORM_UNIFORM
,
1574 ntq_store_dest(c
, &instr
->dest
, 0,
1575 qir_uniform(c
, offset
-
1576 VC4_NIR_STATE_UNIFORM_OFFSET
,
1580 ntq_store_dest(c
, &instr
->dest
, 0,
1581 indirect_uniform_load(c
, instr
));
1585 case nir_intrinsic_load_user_clip_plane
:
1586 for (int i
= 0; i
< instr
->num_components
; i
++) {
1587 ntq_store_dest(c
, &instr
->dest
, i
,
1588 qir_uniform(c
, QUNIFORM_USER_CLIP_PLANE
,
1589 instr
->const_index
[0] * 4 +
1594 case nir_intrinsic_load_sample_mask_in
:
1595 ntq_store_dest(c
, &instr
->dest
, 0,
1596 qir_uniform(c
, QUNIFORM_SAMPLE_MASK
, 0));
1599 case nir_intrinsic_load_front_face
:
1600 /* The register contains 0 (front) or 1 (back), and we need to
1601 * turn it into a NIR bool where true means front.
1603 ntq_store_dest(c
, &instr
->dest
, 0,
1605 qir_uniform_ui(c
, -1),
1606 qir_reg(QFILE_FRAG_REV_FLAG
, 0)));
1609 case nir_intrinsic_load_input
:
1610 assert(instr
->num_components
== 1);
1611 const_offset
= nir_src_as_const_value(instr
->src
[0]);
1612 assert(const_offset
&& "vc4 doesn't support indirect inputs");
1613 if (instr
->const_index
[0] >= VC4_NIR_TLB_COLOR_READ_INPUT
) {
1614 assert(const_offset
->u32
[0] == 0);
1615 /* Reads of the per-sample color need to be done in
1618 int sample_index
= (instr
->const_index
[0] -
1619 VC4_NIR_TLB_COLOR_READ_INPUT
);
1620 for (int i
= 0; i
<= sample_index
; i
++) {
1621 if (c
->color_reads
[i
].file
== QFILE_NULL
) {
1623 qir_TLB_COLOR_READ(c
);
1626 ntq_store_dest(c
, &instr
->dest
, 0,
1627 c
->color_reads
[sample_index
]);
1629 offset
= instr
->const_index
[0] + const_offset
->u32
[0];
1630 ntq_store_dest(c
, &instr
->dest
, 0,
1635 case nir_intrinsic_store_output
:
1636 const_offset
= nir_src_as_const_value(instr
->src
[1]);
1637 assert(const_offset
&& "vc4 doesn't support indirect outputs");
1638 offset
= instr
->const_index
[0] + const_offset
->u32
[0];
1640 /* MSAA color outputs are the only case where we have an
1641 * output that's not lowered to being a store of a single 32
1644 if (c
->stage
== QSTAGE_FRAG
&& instr
->num_components
== 4) {
1645 assert(offset
== c
->output_color_index
);
1646 for (int i
= 0; i
< 4; i
++) {
1647 c
->sample_colors
[i
] =
1648 qir_MOV(c
, ntq_get_src(c
, instr
->src
[0],
1652 assert(instr
->num_components
== 1);
1653 c
->outputs
[offset
] =
1654 qir_MOV(c
, ntq_get_src(c
, instr
->src
[0], 0));
1655 c
->num_outputs
= MAX2(c
->num_outputs
, offset
+ 1);
1659 case nir_intrinsic_discard
:
1660 c
->discard
= qir_uniform_ui(c
, ~0);
1663 case nir_intrinsic_discard_if
:
1664 if (c
->discard
.file
== QFILE_NULL
)
1665 c
->discard
= qir_uniform_ui(c
, 0);
1666 c
->discard
= qir_OR(c
, c
->discard
,
1667 ntq_get_src(c
, instr
->src
[0], 0));
1671 fprintf(stderr
, "Unknown intrinsic: ");
1672 nir_print_instr(&instr
->instr
, stderr
);
1673 fprintf(stderr
, "\n");
1678 /* Clears (activates) the execute flags for any channels whose jump target
1679 * matches this block.
1682 ntq_activate_execute_for_block(struct vc4_compile
*c
)
1684 qir_SF(c
, qir_SUB(c
,
1686 qir_uniform_ui(c
, c
->cur_block
->index
)));
1687 qir_MOV_cond(c
, QPU_COND_ZS
, c
->execute
, qir_uniform_ui(c
, 0));
1691 ntq_emit_if(struct vc4_compile
*c
, nir_if
*if_stmt
)
1693 if (!c
->vc4
->screen
->has_control_flow
) {
1695 "IF statement support requires updated kernel.\n");
1699 nir_cf_node
*nir_first_else_node
= nir_if_first_else_node(if_stmt
);
1700 nir_cf_node
*nir_last_else_node
= nir_if_last_else_node(if_stmt
);
1701 nir_block
*nir_else_block
= nir_cf_node_as_block(nir_first_else_node
);
1702 bool empty_else_block
=
1703 (nir_first_else_node
== nir_last_else_node
&&
1704 exec_list_is_empty(&nir_else_block
->instr_list
));
1706 struct qblock
*then_block
= qir_new_block(c
);
1707 struct qblock
*after_block
= qir_new_block(c
);
1708 struct qblock
*else_block
;
1709 if (empty_else_block
)
1710 else_block
= after_block
;
1712 else_block
= qir_new_block(c
);
1714 bool was_top_level
= false;
1715 if (c
->execute
.file
== QFILE_NULL
) {
1716 c
->execute
= qir_MOV(c
, qir_uniform_ui(c
, 0));
1717 was_top_level
= true;
1720 /* Set ZS for executing (execute == 0) and jumping (if->condition ==
1721 * 0) channels, and then update execute flags for those to point to
1726 ntq_get_src(c
, if_stmt
->condition
, 0)));
1727 qir_MOV_cond(c
, QPU_COND_ZS
, c
->execute
,
1728 qir_uniform_ui(c
, else_block
->index
));
1730 /* Jump to ELSE if nothing is active for THEN, otherwise fall
1733 qir_SF(c
, c
->execute
);
1734 qir_BRANCH(c
, QPU_COND_BRANCH_ALL_ZC
);
1735 qir_link_blocks(c
->cur_block
, else_block
);
1736 qir_link_blocks(c
->cur_block
, then_block
);
1738 /* Process the THEN block. */
1739 qir_set_emit_block(c
, then_block
);
1740 ntq_emit_cf_list(c
, &if_stmt
->then_list
);
1742 if (!empty_else_block
) {
1743 /* Handle the end of the THEN block. First, all currently
1744 * active channels update their execute flags to point to
1747 qir_SF(c
, c
->execute
);
1748 qir_MOV_cond(c
, QPU_COND_ZS
, c
->execute
,
1749 qir_uniform_ui(c
, after_block
->index
));
1751 /* If everything points at ENDIF, then jump there immediately. */
1752 qir_SF(c
, qir_SUB(c
, c
->execute
, qir_uniform_ui(c
, after_block
->index
)));
1753 qir_BRANCH(c
, QPU_COND_BRANCH_ALL_ZS
);
1754 qir_link_blocks(c
->cur_block
, after_block
);
1755 qir_link_blocks(c
->cur_block
, else_block
);
1757 qir_set_emit_block(c
, else_block
);
1758 ntq_activate_execute_for_block(c
);
1759 ntq_emit_cf_list(c
, &if_stmt
->else_list
);
1762 qir_link_blocks(c
->cur_block
, after_block
);
1764 qir_set_emit_block(c
, after_block
);
1766 c
->execute
= c
->undef
;
1768 ntq_activate_execute_for_block(c
);
1773 ntq_emit_jump(struct vc4_compile
*c
, nir_jump_instr
*jump
)
1775 switch (jump
->type
) {
1776 case nir_jump_break
:
1777 qir_SF(c
, c
->execute
);
1778 qir_MOV_cond(c
, QPU_COND_ZS
, c
->execute
,
1779 qir_uniform_ui(c
, c
->loop_break_block
->index
));
1782 case nir_jump_continue
:
1783 qir_SF(c
, c
->execute
);
1784 qir_MOV_cond(c
, QPU_COND_ZS
, c
->execute
,
1785 qir_uniform_ui(c
, c
->loop_cont_block
->index
));
1788 case nir_jump_return
:
1789 unreachable("All returns shouold be lowered\n");
1794 ntq_emit_instr(struct vc4_compile
*c
, nir_instr
*instr
)
1796 switch (instr
->type
) {
1797 case nir_instr_type_alu
:
1798 ntq_emit_alu(c
, nir_instr_as_alu(instr
));
1801 case nir_instr_type_intrinsic
:
1802 ntq_emit_intrinsic(c
, nir_instr_as_intrinsic(instr
));
1805 case nir_instr_type_load_const
:
1806 ntq_emit_load_const(c
, nir_instr_as_load_const(instr
));
1809 case nir_instr_type_ssa_undef
:
1810 ntq_emit_ssa_undef(c
, nir_instr_as_ssa_undef(instr
));
1813 case nir_instr_type_tex
:
1814 ntq_emit_tex(c
, nir_instr_as_tex(instr
));
1817 case nir_instr_type_jump
:
1818 ntq_emit_jump(c
, nir_instr_as_jump(instr
));
1822 fprintf(stderr
, "Unknown NIR instr type: ");
1823 nir_print_instr(instr
, stderr
);
1824 fprintf(stderr
, "\n");
1830 ntq_emit_block(struct vc4_compile
*c
, nir_block
*block
)
1832 nir_foreach_instr(instr
, block
) {
1833 ntq_emit_instr(c
, instr
);
1837 static void ntq_emit_cf_list(struct vc4_compile
*c
, struct exec_list
*list
);
1840 ntq_emit_loop(struct vc4_compile
*c
, nir_loop
*loop
)
1842 if (!c
->vc4
->screen
->has_control_flow
) {
1844 "loop support requires updated kernel.\n");
1845 ntq_emit_cf_list(c
, &loop
->body
);
1849 bool was_top_level
= false;
1850 if (c
->execute
.file
== QFILE_NULL
) {
1851 c
->execute
= qir_MOV(c
, qir_uniform_ui(c
, 0));
1852 was_top_level
= true;
1855 struct qblock
*save_loop_cont_block
= c
->loop_cont_block
;
1856 struct qblock
*save_loop_break_block
= c
->loop_break_block
;
1858 c
->loop_cont_block
= qir_new_block(c
);
1859 c
->loop_break_block
= qir_new_block(c
);
1861 qir_link_blocks(c
->cur_block
, c
->loop_cont_block
);
1862 qir_set_emit_block(c
, c
->loop_cont_block
);
1863 ntq_activate_execute_for_block(c
);
1865 ntq_emit_cf_list(c
, &loop
->body
);
1867 /* If anything had explicitly continued, or is here at the end of the
1868 * loop, then we need to loop again. SF updates are masked by the
1869 * instruction's condition, so we can do the OR of the two conditions
1872 qir_SF(c
, c
->execute
);
1873 struct qinst
*cont_check
=
1877 qir_uniform_ui(c
, c
->loop_cont_block
->index
));
1878 cont_check
->cond
= QPU_COND_ZC
;
1879 cont_check
->sf
= true;
1881 qir_BRANCH(c
, QPU_COND_BRANCH_ANY_ZS
);
1882 qir_link_blocks(c
->cur_block
, c
->loop_cont_block
);
1883 qir_link_blocks(c
->cur_block
, c
->loop_break_block
);
1885 qir_set_emit_block(c
, c
->loop_break_block
);
1887 c
->execute
= c
->undef
;
1889 ntq_activate_execute_for_block(c
);
1891 c
->loop_break_block
= save_loop_break_block
;
1892 c
->loop_cont_block
= save_loop_cont_block
;
1896 ntq_emit_function(struct vc4_compile
*c
, nir_function_impl
*func
)
1898 fprintf(stderr
, "FUNCTIONS not handled.\n");
1903 ntq_emit_cf_list(struct vc4_compile
*c
, struct exec_list
*list
)
1905 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
1906 switch (node
->type
) {
1907 case nir_cf_node_block
:
1908 ntq_emit_block(c
, nir_cf_node_as_block(node
));
1911 case nir_cf_node_if
:
1912 ntq_emit_if(c
, nir_cf_node_as_if(node
));
1915 case nir_cf_node_loop
:
1916 ntq_emit_loop(c
, nir_cf_node_as_loop(node
));
1919 case nir_cf_node_function
:
1920 ntq_emit_function(c
, nir_cf_node_as_function(node
));
1924 fprintf(stderr
, "Unknown NIR node type\n");
1931 ntq_emit_impl(struct vc4_compile
*c
, nir_function_impl
*impl
)
1933 ntq_setup_registers(c
, &impl
->registers
);
1934 ntq_emit_cf_list(c
, &impl
->body
);
1938 nir_to_qir(struct vc4_compile
*c
)
1940 ntq_setup_inputs(c
);
1941 ntq_setup_outputs(c
);
1942 ntq_setup_uniforms(c
);
1943 ntq_setup_registers(c
, &c
->s
->registers
);
1945 /* Find the main function and emit the body. */
1946 nir_foreach_function(function
, c
->s
) {
1947 assert(strcmp(function
->name
, "main") == 0);
1948 assert(function
->impl
);
1949 ntq_emit_impl(c
, function
->impl
);
1953 static const nir_shader_compiler_options nir_options
= {
1954 .lower_extract_byte
= true,
1955 .lower_extract_word
= true,
1957 .lower_flrp32
= true,
1960 .lower_fsqrt
= true,
1961 .lower_negate
= true,
1965 count_nir_instrs(nir_shader
*nir
)
1968 nir_foreach_function(function
, nir
) {
1969 if (!function
->impl
)
1971 nir_foreach_block(block
, function
->impl
) {
1972 nir_foreach_instr(instr
, block
)
1979 static struct vc4_compile
*
1980 vc4_shader_ntq(struct vc4_context
*vc4
, enum qstage stage
,
1981 struct vc4_key
*key
)
1983 struct vc4_compile
*c
= qir_compile_init();
1987 c
->shader_state
= &key
->shader_state
->base
;
1988 c
->program_id
= key
->shader_state
->program_id
;
1990 p_atomic_inc_return(&key
->shader_state
->compiled_variant_count
);
1995 c
->fs_key
= (struct vc4_fs_key
*)key
;
1996 if (c
->fs_key
->is_points
) {
1997 c
->point_x
= emit_fragment_varying(c
, ~0, 0);
1998 c
->point_y
= emit_fragment_varying(c
, ~0, 0);
1999 } else if (c
->fs_key
->is_lines
) {
2000 c
->line_x
= emit_fragment_varying(c
, ~0, 0);
2004 c
->vs_key
= (struct vc4_vs_key
*)key
;
2007 c
->vs_key
= (struct vc4_vs_key
*)key
;
2011 c
->s
= nir_shader_clone(c
, key
->shader_state
->base
.ir
.nir
);
2012 NIR_PASS_V(c
->s
, nir_opt_global_to_local
);
2013 NIR_PASS_V(c
->s
, nir_convert_to_ssa
);
2015 if (stage
== QSTAGE_FRAG
)
2016 NIR_PASS_V(c
->s
, vc4_nir_lower_blend
, c
);
2018 struct nir_lower_tex_options tex_options
= {
2019 /* We would need to implement txs, but we don't want the
2020 * int/float conversions
2022 .lower_rect
= false,
2026 /* Apply swizzles to all samplers. */
2027 .swizzle_result
= ~0,
2030 /* Lower the format swizzle and ARB_texture_swizzle-style swizzle.
2031 * The format swizzling applies before sRGB decode, and
2032 * ARB_texture_swizzle is the last thing before returning the sample.
2034 for (int i
= 0; i
< ARRAY_SIZE(key
->tex
); i
++) {
2035 enum pipe_format format
= c
->key
->tex
[i
].format
;
2040 const uint8_t *format_swizzle
= vc4_get_format_swizzle(format
);
2042 for (int j
= 0; j
< 4; j
++) {
2043 uint8_t arb_swiz
= c
->key
->tex
[i
].swizzle
[j
];
2045 if (arb_swiz
<= 3) {
2046 tex_options
.swizzles
[i
][j
] =
2047 format_swizzle
[arb_swiz
];
2049 tex_options
.swizzles
[i
][j
] = arb_swiz
;
2053 if (util_format_is_srgb(format
))
2054 tex_options
.lower_srgb
|= (1 << i
);
2057 NIR_PASS_V(c
->s
, nir_normalize_cubemap_coords
);
2058 NIR_PASS_V(c
->s
, nir_lower_tex
, &tex_options
);
2060 if (c
->fs_key
&& c
->fs_key
->light_twoside
)
2061 NIR_PASS_V(c
->s
, nir_lower_two_sided_color
);
2063 if (c
->vs_key
&& c
->vs_key
->clamp_color
)
2064 NIR_PASS_V(c
->s
, nir_lower_clamp_color_outputs
);
2066 if (stage
== QSTAGE_FRAG
)
2067 NIR_PASS_V(c
->s
, nir_lower_clip_fs
, c
->key
->ucp_enables
);
2069 NIR_PASS_V(c
->s
, nir_lower_clip_vs
, c
->key
->ucp_enables
);
2071 NIR_PASS_V(c
->s
, vc4_nir_lower_io
, c
);
2072 NIR_PASS_V(c
->s
, vc4_nir_lower_txf_ms
, c
);
2073 NIR_PASS_V(c
->s
, nir_lower_idiv
);
2074 NIR_PASS_V(c
->s
, nir_lower_load_const_to_scalar
);
2076 vc4_optimize_nir(c
->s
);
2078 NIR_PASS_V(c
->s
, nir_remove_dead_variables
, nir_var_local
);
2079 NIR_PASS_V(c
->s
, nir_convert_from_ssa
, true);
2081 if (vc4_debug
& VC4_DEBUG_SHADERDB
) {
2082 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %d NIR instructions\n",
2083 qir_get_stage_name(c
->stage
),
2084 c
->program_id
, c
->variant_id
,
2085 count_nir_instrs(c
->s
));
2088 if (vc4_debug
& VC4_DEBUG_NIR
) {
2089 fprintf(stderr
, "%s prog %d/%d NIR:\n",
2090 qir_get_stage_name(c
->stage
),
2091 c
->program_id
, c
->variant_id
);
2092 nir_print_shader(c
->s
, stderr
);
2103 c
->vs_key
->fs_inputs
->input_slots
,
2104 c
->vs_key
->fs_inputs
->num_inputs
);
2111 if (vc4_debug
& VC4_DEBUG_QIR
) {
2112 fprintf(stderr
, "%s prog %d/%d pre-opt QIR:\n",
2113 qir_get_stage_name(c
->stage
),
2114 c
->program_id
, c
->variant_id
);
2116 fprintf(stderr
, "\n");
2120 qir_lower_uniforms(c
);
2122 qir_schedule_instructions(c
);
2123 qir_emit_uniform_stream_resets(c
);
2125 if (vc4_debug
& VC4_DEBUG_QIR
) {
2126 fprintf(stderr
, "%s prog %d/%d QIR:\n",
2127 qir_get_stage_name(c
->stage
),
2128 c
->program_id
, c
->variant_id
);
2130 fprintf(stderr
, "\n");
2133 qir_reorder_uniforms(c
);
2134 vc4_generate_code(vc4
, c
);
2136 if (vc4_debug
& VC4_DEBUG_SHADERDB
) {
2137 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %d instructions\n",
2138 qir_get_stage_name(c
->stage
),
2139 c
->program_id
, c
->variant_id
,
2141 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %d uniforms\n",
2142 qir_get_stage_name(c
->stage
),
2143 c
->program_id
, c
->variant_id
,
2153 vc4_shader_state_create(struct pipe_context
*pctx
,
2154 const struct pipe_shader_state
*cso
)
2156 struct vc4_context
*vc4
= vc4_context(pctx
);
2157 struct vc4_uncompiled_shader
*so
= CALLOC_STRUCT(vc4_uncompiled_shader
);
2161 so
->program_id
= vc4
->next_uncompiled_program_id
++;
2163 nir_shader
*s
= tgsi_to_nir(cso
->tokens
, &nir_options
);
2165 if (vc4_debug
& VC4_DEBUG_TGSI
) {
2166 fprintf(stderr
, "%s prog %d TGSI:\n",
2167 gl_shader_stage_name(s
->stage
),
2169 tgsi_dump(cso
->tokens
, 0);
2170 fprintf(stderr
, "\n");
2173 so
->base
.type
= PIPE_SHADER_IR_NIR
;
2174 so
->base
.ir
.nir
= s
;
2176 if (vc4_debug
& VC4_DEBUG_NIR
) {
2177 fprintf(stderr
, "%s prog %d NIR:\n",
2178 gl_shader_stage_name(s
->stage
),
2180 nir_print_shader(s
, stderr
);
2181 fprintf(stderr
, "\n");
2188 copy_uniform_state_to_shader(struct vc4_compiled_shader
*shader
,
2189 struct vc4_compile
*c
)
2191 int count
= c
->num_uniforms
;
2192 struct vc4_shader_uniform_info
*uinfo
= &shader
->uniforms
;
2194 uinfo
->count
= count
;
2195 uinfo
->data
= ralloc_array(shader
, uint32_t, count
);
2196 memcpy(uinfo
->data
, c
->uniform_data
,
2197 count
* sizeof(*uinfo
->data
));
2198 uinfo
->contents
= ralloc_array(shader
, enum quniform_contents
, count
);
2199 memcpy(uinfo
->contents
, c
->uniform_contents
,
2200 count
* sizeof(*uinfo
->contents
));
2201 uinfo
->num_texture_samples
= c
->num_texture_samples
;
2203 vc4_set_shader_uniform_dirty_flags(shader
);
2207 vc4_setup_compiled_fs_inputs(struct vc4_context
*vc4
, struct vc4_compile
*c
,
2208 struct vc4_compiled_shader
*shader
)
2210 struct vc4_fs_inputs inputs
;
2212 memset(&inputs
, 0, sizeof(inputs
));
2213 inputs
.input_slots
= ralloc_array(shader
,
2214 struct vc4_varying_slot
,
2215 c
->num_input_slots
);
2217 bool input_live
[c
->num_input_slots
];
2219 memset(input_live
, 0, sizeof(input_live
));
2220 qir_for_each_inst_inorder(inst
, c
) {
2221 for (int i
= 0; i
< qir_get_op_nsrc(inst
->op
); i
++) {
2222 if (inst
->src
[i
].file
== QFILE_VARY
)
2223 input_live
[inst
->src
[i
].index
] = true;
2227 for (int i
= 0; i
< c
->num_input_slots
; i
++) {
2228 struct vc4_varying_slot
*slot
= &c
->input_slots
[i
];
2233 /* Skip non-VS-output inputs. */
2234 if (slot
->slot
== (uint8_t)~0)
2237 if (slot
->slot
== VARYING_SLOT_COL0
||
2238 slot
->slot
== VARYING_SLOT_COL1
||
2239 slot
->slot
== VARYING_SLOT_BFC0
||
2240 slot
->slot
== VARYING_SLOT_BFC1
) {
2241 shader
->color_inputs
|= (1 << inputs
.num_inputs
);
2244 inputs
.input_slots
[inputs
.num_inputs
] = *slot
;
2245 inputs
.num_inputs
++;
2247 shader
->num_inputs
= inputs
.num_inputs
;
2249 /* Add our set of inputs to the set of all inputs seen. This way, we
2250 * can have a single pointer that identifies an FS inputs set,
2251 * allowing VS to avoid recompiling when the FS is recompiled (or a
2252 * new one is bound using separate shader objects) but the inputs
2255 struct set_entry
*entry
= _mesa_set_search(vc4
->fs_inputs_set
, &inputs
);
2257 shader
->fs_inputs
= entry
->key
;
2258 ralloc_free(inputs
.input_slots
);
2260 struct vc4_fs_inputs
*alloc_inputs
;
2262 alloc_inputs
= rzalloc(vc4
->fs_inputs_set
, struct vc4_fs_inputs
);
2263 memcpy(alloc_inputs
, &inputs
, sizeof(inputs
));
2264 ralloc_steal(alloc_inputs
, inputs
.input_slots
);
2265 _mesa_set_add(vc4
->fs_inputs_set
, alloc_inputs
);
2267 shader
->fs_inputs
= alloc_inputs
;
2271 static struct vc4_compiled_shader
*
2272 vc4_get_compiled_shader(struct vc4_context
*vc4
, enum qstage stage
,
2273 struct vc4_key
*key
)
2275 struct hash_table
*ht
;
2277 if (stage
== QSTAGE_FRAG
) {
2279 key_size
= sizeof(struct vc4_fs_key
);
2282 key_size
= sizeof(struct vc4_vs_key
);
2285 struct vc4_compiled_shader
*shader
;
2286 struct hash_entry
*entry
= _mesa_hash_table_search(ht
, key
);
2290 struct vc4_compile
*c
= vc4_shader_ntq(vc4
, stage
, key
);
2291 shader
= rzalloc(NULL
, struct vc4_compiled_shader
);
2293 shader
->program_id
= vc4
->next_compiled_program_id
++;
2294 if (stage
== QSTAGE_FRAG
) {
2295 vc4_setup_compiled_fs_inputs(vc4
, c
, shader
);
2297 /* Note: the temporary clone in c->s has been freed. */
2298 nir_shader
*orig_shader
= key
->shader_state
->base
.ir
.nir
;
2299 if (orig_shader
->info
.outputs_written
& (1 << FRAG_RESULT_DEPTH
))
2300 shader
->disable_early_z
= true;
2302 shader
->num_inputs
= c
->num_inputs
;
2304 shader
->vattr_offsets
[0] = 0;
2305 for (int i
= 0; i
< 8; i
++) {
2306 shader
->vattr_offsets
[i
+ 1] =
2307 shader
->vattr_offsets
[i
] + c
->vattr_sizes
[i
];
2309 if (c
->vattr_sizes
[i
])
2310 shader
->vattrs_live
|= (1 << i
);
2314 copy_uniform_state_to_shader(shader
, c
);
2315 shader
->bo
= vc4_bo_alloc_shader(vc4
->screen
, c
->qpu_insts
,
2316 c
->qpu_inst_count
* sizeof(uint64_t));
2318 /* Copy the compiler UBO range state to the compiled shader, dropping
2319 * out arrays that were never referenced by an indirect load.
2321 * (Note that QIR dead code elimination of an array access still
2322 * leaves that array alive, though)
2324 if (c
->num_ubo_ranges
) {
2325 shader
->num_ubo_ranges
= c
->num_ubo_ranges
;
2326 shader
->ubo_ranges
= ralloc_array(shader
, struct vc4_ubo_range
,
2329 for (int i
= 0; i
< c
->num_uniform_ranges
; i
++) {
2330 struct vc4_compiler_ubo_range
*range
=
2335 shader
->ubo_ranges
[j
].dst_offset
= range
->dst_offset
;
2336 shader
->ubo_ranges
[j
].src_offset
= range
->src_offset
;
2337 shader
->ubo_ranges
[j
].size
= range
->size
;
2338 shader
->ubo_size
+= c
->ubo_ranges
[i
].size
;
2342 if (shader
->ubo_size
) {
2343 if (vc4_debug
& VC4_DEBUG_SHADERDB
) {
2344 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %d UBO uniforms\n",
2345 qir_get_stage_name(c
->stage
),
2346 c
->program_id
, c
->variant_id
,
2347 shader
->ubo_size
/ 4);
2351 qir_compile_destroy(c
);
2353 struct vc4_key
*dup_key
;
2354 dup_key
= ralloc_size(shader
, key_size
);
2355 memcpy(dup_key
, key
, key_size
);
2356 _mesa_hash_table_insert(ht
, dup_key
, shader
);
2362 vc4_setup_shared_key(struct vc4_context
*vc4
, struct vc4_key
*key
,
2363 struct vc4_texture_stateobj
*texstate
)
2365 for (int i
= 0; i
< texstate
->num_textures
; i
++) {
2366 struct pipe_sampler_view
*sampler
= texstate
->textures
[i
];
2367 struct vc4_sampler_view
*vc4_sampler
= vc4_sampler_view(sampler
);
2368 struct pipe_sampler_state
*sampler_state
=
2369 texstate
->samplers
[i
];
2374 key
->tex
[i
].format
= sampler
->format
;
2375 key
->tex
[i
].swizzle
[0] = sampler
->swizzle_r
;
2376 key
->tex
[i
].swizzle
[1] = sampler
->swizzle_g
;
2377 key
->tex
[i
].swizzle
[2] = sampler
->swizzle_b
;
2378 key
->tex
[i
].swizzle
[3] = sampler
->swizzle_a
;
2380 if (sampler
->texture
->nr_samples
> 1) {
2381 key
->tex
[i
].msaa_width
= sampler
->texture
->width0
;
2382 key
->tex
[i
].msaa_height
= sampler
->texture
->height0
;
2383 } else if (sampler
){
2384 key
->tex
[i
].compare_mode
= sampler_state
->compare_mode
;
2385 key
->tex
[i
].compare_func
= sampler_state
->compare_func
;
2386 key
->tex
[i
].wrap_s
= sampler_state
->wrap_s
;
2387 key
->tex
[i
].wrap_t
= sampler_state
->wrap_t
;
2388 key
->tex
[i
].force_first_level
=
2389 vc4_sampler
->force_first_level
;
2393 key
->ucp_enables
= vc4
->rasterizer
->base
.clip_plane_enable
;
2397 vc4_update_compiled_fs(struct vc4_context
*vc4
, uint8_t prim_mode
)
2399 struct vc4_fs_key local_key
;
2400 struct vc4_fs_key
*key
= &local_key
;
2402 if (!(vc4
->dirty
& (VC4_DIRTY_PRIM_MODE
|
2404 VC4_DIRTY_FRAMEBUFFER
|
2406 VC4_DIRTY_RASTERIZER
|
2407 VC4_DIRTY_SAMPLE_MASK
|
2409 VC4_DIRTY_UNCOMPILED_FS
))) {
2413 memset(key
, 0, sizeof(*key
));
2414 vc4_setup_shared_key(vc4
, &key
->base
, &vc4
->fragtex
);
2415 key
->base
.shader_state
= vc4
->prog
.bind_fs
;
2416 key
->is_points
= (prim_mode
== PIPE_PRIM_POINTS
);
2417 key
->is_lines
= (prim_mode
>= PIPE_PRIM_LINES
&&
2418 prim_mode
<= PIPE_PRIM_LINE_STRIP
);
2419 key
->blend
= vc4
->blend
->rt
[0];
2420 if (vc4
->blend
->logicop_enable
) {
2421 key
->logicop_func
= vc4
->blend
->logicop_func
;
2423 key
->logicop_func
= PIPE_LOGICOP_COPY
;
2426 key
->msaa
= vc4
->rasterizer
->base
.multisample
;
2427 key
->sample_coverage
= (vc4
->rasterizer
->base
.multisample
&&
2428 vc4
->sample_mask
!= (1 << VC4_MAX_SAMPLES
) - 1);
2429 key
->sample_alpha_to_coverage
= vc4
->blend
->alpha_to_coverage
;
2430 key
->sample_alpha_to_one
= vc4
->blend
->alpha_to_one
;
2433 if (vc4
->framebuffer
.cbufs
[0])
2434 key
->color_format
= vc4
->framebuffer
.cbufs
[0]->format
;
2436 key
->stencil_enabled
= vc4
->zsa
->stencil_uniforms
[0] != 0;
2437 key
->stencil_twoside
= vc4
->zsa
->stencil_uniforms
[1] != 0;
2438 key
->stencil_full_writemasks
= vc4
->zsa
->stencil_uniforms
[2] != 0;
2439 key
->depth_enabled
= (vc4
->zsa
->base
.depth
.enabled
||
2440 key
->stencil_enabled
);
2441 if (vc4
->zsa
->base
.alpha
.enabled
) {
2442 key
->alpha_test
= true;
2443 key
->alpha_test_func
= vc4
->zsa
->base
.alpha
.func
;
2446 if (key
->is_points
) {
2447 key
->point_sprite_mask
=
2448 vc4
->rasterizer
->base
.sprite_coord_enable
;
2449 key
->point_coord_upper_left
=
2450 (vc4
->rasterizer
->base
.sprite_coord_mode
==
2451 PIPE_SPRITE_COORD_UPPER_LEFT
);
2454 key
->light_twoside
= vc4
->rasterizer
->base
.light_twoside
;
2456 struct vc4_compiled_shader
*old_fs
= vc4
->prog
.fs
;
2457 vc4
->prog
.fs
= vc4_get_compiled_shader(vc4
, QSTAGE_FRAG
, &key
->base
);
2458 if (vc4
->prog
.fs
== old_fs
)
2461 vc4
->dirty
|= VC4_DIRTY_COMPILED_FS
;
2463 if (vc4
->rasterizer
->base
.flatshade
&&
2464 old_fs
&& vc4
->prog
.fs
->color_inputs
!= old_fs
->color_inputs
) {
2465 vc4
->dirty
|= VC4_DIRTY_FLAT_SHADE_FLAGS
;
2468 if (old_fs
&& vc4
->prog
.fs
->fs_inputs
!= old_fs
->fs_inputs
)
2469 vc4
->dirty
|= VC4_DIRTY_FS_INPUTS
;
2473 vc4_update_compiled_vs(struct vc4_context
*vc4
, uint8_t prim_mode
)
2475 struct vc4_vs_key local_key
;
2476 struct vc4_vs_key
*key
= &local_key
;
2478 if (!(vc4
->dirty
& (VC4_DIRTY_PRIM_MODE
|
2479 VC4_DIRTY_RASTERIZER
|
2481 VC4_DIRTY_VTXSTATE
|
2482 VC4_DIRTY_UNCOMPILED_VS
|
2483 VC4_DIRTY_FS_INPUTS
))) {
2487 memset(key
, 0, sizeof(*key
));
2488 vc4_setup_shared_key(vc4
, &key
->base
, &vc4
->verttex
);
2489 key
->base
.shader_state
= vc4
->prog
.bind_vs
;
2490 key
->fs_inputs
= vc4
->prog
.fs
->fs_inputs
;
2491 key
->clamp_color
= vc4
->rasterizer
->base
.clamp_vertex_color
;
2493 for (int i
= 0; i
< ARRAY_SIZE(key
->attr_formats
); i
++)
2494 key
->attr_formats
[i
] = vc4
->vtx
->pipe
[i
].src_format
;
2496 key
->per_vertex_point_size
=
2497 (prim_mode
== PIPE_PRIM_POINTS
&&
2498 vc4
->rasterizer
->base
.point_size_per_vertex
);
2500 struct vc4_compiled_shader
*vs
=
2501 vc4_get_compiled_shader(vc4
, QSTAGE_VERT
, &key
->base
);
2502 if (vs
!= vc4
->prog
.vs
) {
2504 vc4
->dirty
|= VC4_DIRTY_COMPILED_VS
;
2507 key
->is_coord
= true;
2508 /* Coord shaders don't care what the FS inputs are. */
2509 key
->fs_inputs
= NULL
;
2510 struct vc4_compiled_shader
*cs
=
2511 vc4_get_compiled_shader(vc4
, QSTAGE_COORD
, &key
->base
);
2512 if (cs
!= vc4
->prog
.cs
) {
2514 vc4
->dirty
|= VC4_DIRTY_COMPILED_CS
;
2519 vc4_update_compiled_shaders(struct vc4_context
*vc4
, uint8_t prim_mode
)
2521 vc4_update_compiled_fs(vc4
, prim_mode
);
2522 vc4_update_compiled_vs(vc4
, prim_mode
);
2526 fs_cache_hash(const void *key
)
2528 return _mesa_hash_data(key
, sizeof(struct vc4_fs_key
));
2532 vs_cache_hash(const void *key
)
2534 return _mesa_hash_data(key
, sizeof(struct vc4_vs_key
));
2538 fs_cache_compare(const void *key1
, const void *key2
)
2540 return memcmp(key1
, key2
, sizeof(struct vc4_fs_key
)) == 0;
2544 vs_cache_compare(const void *key1
, const void *key2
)
2546 return memcmp(key1
, key2
, sizeof(struct vc4_vs_key
)) == 0;
2550 fs_inputs_hash(const void *key
)
2552 const struct vc4_fs_inputs
*inputs
= key
;
2554 return _mesa_hash_data(inputs
->input_slots
,
2555 sizeof(*inputs
->input_slots
) *
2556 inputs
->num_inputs
);
2560 fs_inputs_compare(const void *key1
, const void *key2
)
2562 const struct vc4_fs_inputs
*inputs1
= key1
;
2563 const struct vc4_fs_inputs
*inputs2
= key2
;
2565 return (inputs1
->num_inputs
== inputs2
->num_inputs
&&
2566 memcmp(inputs1
->input_slots
,
2567 inputs2
->input_slots
,
2568 sizeof(*inputs1
->input_slots
) *
2569 inputs1
->num_inputs
) == 0);
2573 delete_from_cache_if_matches(struct hash_table
*ht
,
2574 struct hash_entry
*entry
,
2575 struct vc4_uncompiled_shader
*so
)
2577 const struct vc4_key
*key
= entry
->key
;
2579 if (key
->shader_state
== so
) {
2580 struct vc4_compiled_shader
*shader
= entry
->data
;
2581 _mesa_hash_table_remove(ht
, entry
);
2582 vc4_bo_unreference(&shader
->bo
);
2583 ralloc_free(shader
);
2588 vc4_shader_state_delete(struct pipe_context
*pctx
, void *hwcso
)
2590 struct vc4_context
*vc4
= vc4_context(pctx
);
2591 struct vc4_uncompiled_shader
*so
= hwcso
;
2593 struct hash_entry
*entry
;
2594 hash_table_foreach(vc4
->fs_cache
, entry
)
2595 delete_from_cache_if_matches(vc4
->fs_cache
, entry
, so
);
2596 hash_table_foreach(vc4
->vs_cache
, entry
)
2597 delete_from_cache_if_matches(vc4
->vs_cache
, entry
, so
);
2599 ralloc_free(so
->base
.ir
.nir
);
2604 vc4_fp_state_bind(struct pipe_context
*pctx
, void *hwcso
)
2606 struct vc4_context
*vc4
= vc4_context(pctx
);
2607 vc4
->prog
.bind_fs
= hwcso
;
2608 vc4
->dirty
|= VC4_DIRTY_UNCOMPILED_FS
;
2612 vc4_vp_state_bind(struct pipe_context
*pctx
, void *hwcso
)
2614 struct vc4_context
*vc4
= vc4_context(pctx
);
2615 vc4
->prog
.bind_vs
= hwcso
;
2616 vc4
->dirty
|= VC4_DIRTY_UNCOMPILED_VS
;
2620 vc4_program_init(struct pipe_context
*pctx
)
2622 struct vc4_context
*vc4
= vc4_context(pctx
);
2624 pctx
->create_vs_state
= vc4_shader_state_create
;
2625 pctx
->delete_vs_state
= vc4_shader_state_delete
;
2627 pctx
->create_fs_state
= vc4_shader_state_create
;
2628 pctx
->delete_fs_state
= vc4_shader_state_delete
;
2630 pctx
->bind_fs_state
= vc4_fp_state_bind
;
2631 pctx
->bind_vs_state
= vc4_vp_state_bind
;
2633 vc4
->fs_cache
= _mesa_hash_table_create(pctx
, fs_cache_hash
,
2635 vc4
->vs_cache
= _mesa_hash_table_create(pctx
, vs_cache_hash
,
2637 vc4
->fs_inputs_set
= _mesa_set_create(pctx
, fs_inputs_hash
,
2642 vc4_program_fini(struct pipe_context
*pctx
)
2644 struct vc4_context
*vc4
= vc4_context(pctx
);
2646 struct hash_entry
*entry
;
2647 hash_table_foreach(vc4
->fs_cache
, entry
) {
2648 struct vc4_compiled_shader
*shader
= entry
->data
;
2649 vc4_bo_unreference(&shader
->bo
);
2650 ralloc_free(shader
);
2651 _mesa_hash_table_remove(vc4
->fs_cache
, entry
);
2654 hash_table_foreach(vc4
->vs_cache
, entry
) {
2655 struct vc4_compiled_shader
*shader
= entry
->data
;
2656 vc4_bo_unreference(&shader
->bo
);
2657 ralloc_free(shader
);
2658 _mesa_hash_table_remove(vc4
->vs_cache
, entry
);