2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "util/u_format.h"
27 #include "util/u_hash.h"
28 #include "util/u_math.h"
29 #include "util/u_memory.h"
30 #include "util/ralloc.h"
31 #include "util/hash_table.h"
32 #include "tgsi/tgsi_dump.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "compiler/nir/nir.h"
35 #include "compiler/nir/nir_builder.h"
36 #include "nir/tgsi_to_nir.h"
37 #include "vc4_context.h"
40 #include "mesa/state_tracker/st_glsl_types.h"
41 #ifdef USE_VC4_SIMULATOR
42 #include "simpenrose/simpenrose.h"
46 ntq_get_src(struct vc4_compile
*c
, nir_src src
, int i
);
48 ntq_emit_cf_list(struct vc4_compile
*c
, struct exec_list
*list
);
51 resize_qreg_array(struct vc4_compile
*c
,
56 if (*size
>= decl_size
)
59 uint32_t old_size
= *size
;
60 *size
= MAX2(*size
* 2, decl_size
);
61 *regs
= reralloc(c
, *regs
, struct qreg
, *size
);
63 fprintf(stderr
, "Malloc failure\n");
67 for (uint32_t i
= old_size
; i
< *size
; i
++)
68 (*regs
)[i
] = c
->undef
;
72 indirect_uniform_load(struct vc4_compile
*c
, nir_intrinsic_instr
*intr
)
74 struct qreg indirect_offset
= ntq_get_src(c
, intr
->src
[0], 0);
75 uint32_t offset
= nir_intrinsic_base(intr
);
76 struct vc4_compiler_ubo_range
*range
= NULL
;
78 for (i
= 0; i
< c
->num_uniform_ranges
; i
++) {
79 range
= &c
->ubo_ranges
[i
];
80 if (offset
>= range
->src_offset
&&
81 offset
< range
->src_offset
+ range
->size
) {
85 /* The driver-location-based offset always has to be within a declared
91 range
->dst_offset
= c
->next_ubo_dst_offset
;
92 c
->next_ubo_dst_offset
+= range
->size
;
96 offset
-= range
->src_offset
;
98 /* Adjust for where we stored the TGSI register base. */
99 indirect_offset
= qir_ADD(c
, indirect_offset
,
100 qir_uniform_ui(c
, (range
->dst_offset
+
103 /* Clamp to [0, array size). Note that MIN/MAX are signed. */
104 indirect_offset
= qir_MAX(c
, indirect_offset
, qir_uniform_ui(c
, 0));
105 indirect_offset
= qir_MIN(c
, indirect_offset
,
106 qir_uniform_ui(c
, (range
->dst_offset
+
109 qir_TEX_DIRECT(c
, indirect_offset
, qir_uniform(c
, QUNIFORM_UBO_ADDR
, 0));
110 c
->num_texture_samples
++;
111 return qir_TEX_RESULT(c
);
115 vc4_nir_get_swizzled_channel(nir_builder
*b
, nir_ssa_def
**srcs
, int swiz
)
119 case PIPE_SWIZZLE_NONE
:
120 fprintf(stderr
, "warning: unknown swizzle\n");
123 return nir_imm_float(b
, 0.0);
125 return nir_imm_float(b
, 1.0);
135 ntq_init_ssa_def(struct vc4_compile
*c
, nir_ssa_def
*def
)
137 struct qreg
*qregs
= ralloc_array(c
->def_ht
, struct qreg
,
138 def
->num_components
);
139 _mesa_hash_table_insert(c
->def_ht
, def
, qregs
);
144 ntq_store_dest(struct vc4_compile
*c
, nir_dest
*dest
, int chan
,
148 assert(chan
< dest
->ssa
.num_components
);
151 struct hash_entry
*entry
=
152 _mesa_hash_table_search(c
->def_ht
, &dest
->ssa
);
157 qregs
= ntq_init_ssa_def(c
, &dest
->ssa
);
159 qregs
[chan
] = result
;
161 nir_register
*reg
= dest
->reg
.reg
;
162 assert(dest
->reg
.base_offset
== 0);
163 assert(reg
->num_array_elems
== 0);
164 struct hash_entry
*entry
=
165 _mesa_hash_table_search(c
->def_ht
, reg
);
166 struct qreg
*qregs
= entry
->data
;
168 /* Conditionally move the result to the destination if the
171 if (c
->execute
.file
!= QFILE_NULL
) {
172 qir_SF(c
, c
->execute
);
173 qir_MOV_cond(c
, QPU_COND_ZS
, qregs
[chan
], result
);
175 qir_MOV_dest(c
, qregs
[chan
], result
);
181 ntq_get_dest(struct vc4_compile
*c
, nir_dest
*dest
)
184 struct qreg
*qregs
= ntq_init_ssa_def(c
, &dest
->ssa
);
185 for (int i
= 0; i
< dest
->ssa
.num_components
; i
++)
189 nir_register
*reg
= dest
->reg
.reg
;
190 assert(dest
->reg
.base_offset
== 0);
191 assert(reg
->num_array_elems
== 0);
192 struct hash_entry
*entry
=
193 _mesa_hash_table_search(c
->def_ht
, reg
);
199 ntq_get_src(struct vc4_compile
*c
, nir_src src
, int i
)
201 struct hash_entry
*entry
;
203 entry
= _mesa_hash_table_search(c
->def_ht
, src
.ssa
);
204 assert(i
< src
.ssa
->num_components
);
206 nir_register
*reg
= src
.reg
.reg
;
207 entry
= _mesa_hash_table_search(c
->def_ht
, reg
);
208 assert(reg
->num_array_elems
== 0);
209 assert(src
.reg
.base_offset
== 0);
210 assert(i
< reg
->num_components
);
213 struct qreg
*qregs
= entry
->data
;
218 ntq_get_alu_src(struct vc4_compile
*c
, nir_alu_instr
*instr
,
221 assert(util_is_power_of_two(instr
->dest
.write_mask
));
222 unsigned chan
= ffs(instr
->dest
.write_mask
) - 1;
223 struct qreg r
= ntq_get_src(c
, instr
->src
[src
].src
,
224 instr
->src
[src
].swizzle
[chan
]);
226 assert(!instr
->src
[src
].abs
);
227 assert(!instr
->src
[src
].negate
);
232 static inline struct qreg
233 qir_SAT(struct vc4_compile
*c
, struct qreg val
)
236 qir_FMIN(c
, val
, qir_uniform_f(c
, 1.0)),
237 qir_uniform_f(c
, 0.0));
241 ntq_rcp(struct vc4_compile
*c
, struct qreg x
)
243 struct qreg r
= qir_RCP(c
, x
);
245 /* Apply a Newton-Raphson step to improve the accuracy. */
246 r
= qir_FMUL(c
, r
, qir_FSUB(c
,
247 qir_uniform_f(c
, 2.0),
254 ntq_rsq(struct vc4_compile
*c
, struct qreg x
)
256 struct qreg r
= qir_RSQ(c
, x
);
258 /* Apply a Newton-Raphson step to improve the accuracy. */
259 r
= qir_FMUL(c
, r
, qir_FSUB(c
,
260 qir_uniform_f(c
, 1.5),
262 qir_uniform_f(c
, 0.5),
264 qir_FMUL(c
, r
, r
)))));
270 ntq_umul(struct vc4_compile
*c
, struct qreg src0
, struct qreg src1
)
272 struct qreg src0_hi
= qir_SHR(c
, src0
,
273 qir_uniform_ui(c
, 24));
274 struct qreg src1_hi
= qir_SHR(c
, src1
,
275 qir_uniform_ui(c
, 24));
277 struct qreg hilo
= qir_MUL24(c
, src0_hi
, src1
);
278 struct qreg lohi
= qir_MUL24(c
, src0
, src1_hi
);
279 struct qreg lolo
= qir_MUL24(c
, src0
, src1
);
281 return qir_ADD(c
, lolo
, qir_SHL(c
,
282 qir_ADD(c
, hilo
, lohi
),
283 qir_uniform_ui(c
, 24)));
287 ntq_scale_depth_texture(struct vc4_compile
*c
, struct qreg src
)
289 struct qreg depthf
= qir_ITOF(c
, qir_SHR(c
, src
,
290 qir_uniform_ui(c
, 8)));
291 return qir_FMUL(c
, depthf
, qir_uniform_f(c
, 1.0f
/0xffffff));
295 * Emits a lowered TXF_MS from an MSAA texture.
297 * The addressing math has been lowered in NIR, and now we just need to read
301 ntq_emit_txf(struct vc4_compile
*c
, nir_tex_instr
*instr
)
303 uint32_t tile_width
= 32;
304 uint32_t tile_height
= 32;
305 uint32_t tile_size
= (tile_height
* tile_width
*
306 VC4_MAX_SAMPLES
* sizeof(uint32_t));
308 unsigned unit
= instr
->texture_index
;
309 uint32_t w
= align(c
->key
->tex
[unit
].msaa_width
, tile_width
);
310 uint32_t w_tiles
= w
/ tile_width
;
311 uint32_t h
= align(c
->key
->tex
[unit
].msaa_height
, tile_height
);
312 uint32_t h_tiles
= h
/ tile_height
;
313 uint32_t size
= w_tiles
* h_tiles
* tile_size
;
316 assert(instr
->num_srcs
== 1);
317 assert(instr
->src
[0].src_type
== nir_tex_src_coord
);
318 addr
= ntq_get_src(c
, instr
->src
[0].src
, 0);
320 /* Perform the clamping required by kernel validation. */
321 addr
= qir_MAX(c
, addr
, qir_uniform_ui(c
, 0));
322 addr
= qir_MIN(c
, addr
, qir_uniform_ui(c
, size
- 4));
324 qir_TEX_DIRECT(c
, addr
, qir_uniform(c
, QUNIFORM_TEXTURE_MSAA_ADDR
, unit
));
326 struct qreg tex
= qir_TEX_RESULT(c
);
327 c
->num_texture_samples
++;
330 enum pipe_format format
= c
->key
->tex
[unit
].format
;
331 if (util_format_is_depth_or_stencil(format
)) {
332 struct qreg scaled
= ntq_scale_depth_texture(c
, tex
);
333 for (int i
= 0; i
< 4; i
++)
336 for (int i
= 0; i
< 4; i
++)
337 dest
[i
] = qir_UNPACK_8_F(c
, tex
, i
);
340 for (int i
= 0; i
< 4; i
++)
341 ntq_store_dest(c
, &instr
->dest
, i
, dest
[i
]);
345 ntq_emit_tex(struct vc4_compile
*c
, nir_tex_instr
*instr
)
347 struct qreg s
, t
, r
, lod
, compare
;
348 bool is_txb
= false, is_txl
= false;
349 unsigned unit
= instr
->texture_index
;
351 if (instr
->op
== nir_texop_txf
) {
352 ntq_emit_txf(c
, instr
);
356 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
357 switch (instr
->src
[i
].src_type
) {
358 case nir_tex_src_coord
:
359 s
= ntq_get_src(c
, instr
->src
[i
].src
, 0);
360 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
)
361 t
= qir_uniform_f(c
, 0.5);
363 t
= ntq_get_src(c
, instr
->src
[i
].src
, 1);
364 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
365 r
= ntq_get_src(c
, instr
->src
[i
].src
, 2);
367 case nir_tex_src_bias
:
368 lod
= ntq_get_src(c
, instr
->src
[i
].src
, 0);
371 case nir_tex_src_lod
:
372 lod
= ntq_get_src(c
, instr
->src
[i
].src
, 0);
375 case nir_tex_src_comparitor
:
376 compare
= ntq_get_src(c
, instr
->src
[i
].src
, 0);
379 unreachable("unknown texture source");
383 if (c
->key
->tex
[unit
].force_first_level
) {
384 lod
= qir_uniform(c
, QUNIFORM_TEXTURE_FIRST_LEVEL
, unit
);
389 struct qreg texture_u
[] = {
390 qir_uniform(c
, QUNIFORM_TEXTURE_CONFIG_P0
, unit
),
391 qir_uniform(c
, QUNIFORM_TEXTURE_CONFIG_P1
, unit
),
392 qir_uniform(c
, QUNIFORM_CONSTANT
, 0),
393 qir_uniform(c
, QUNIFORM_CONSTANT
, 0),
395 uint32_t next_texture_u
= 0;
397 /* There is no native support for GL texture rectangle coordinates, so
398 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
401 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_RECT
) {
403 qir_uniform(c
, QUNIFORM_TEXRECT_SCALE_X
, unit
));
405 qir_uniform(c
, QUNIFORM_TEXRECT_SCALE_Y
, unit
));
408 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
|| is_txl
) {
409 texture_u
[2] = qir_uniform(c
, QUNIFORM_TEXTURE_CONFIG_P2
,
410 unit
| (is_txl
<< 16));
413 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
414 qir_TEX_R(c
, r
, texture_u
[next_texture_u
++]);
415 } else if (c
->key
->tex
[unit
].wrap_s
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
416 c
->key
->tex
[unit
].wrap_s
== PIPE_TEX_WRAP_CLAMP
||
417 c
->key
->tex
[unit
].wrap_t
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
418 c
->key
->tex
[unit
].wrap_t
== PIPE_TEX_WRAP_CLAMP
) {
419 qir_TEX_R(c
, qir_uniform(c
, QUNIFORM_TEXTURE_BORDER_COLOR
, unit
),
420 texture_u
[next_texture_u
++]);
423 if (c
->key
->tex
[unit
].wrap_s
== PIPE_TEX_WRAP_CLAMP
) {
427 if (c
->key
->tex
[unit
].wrap_t
== PIPE_TEX_WRAP_CLAMP
) {
431 qir_TEX_T(c
, t
, texture_u
[next_texture_u
++]);
433 if (is_txl
|| is_txb
)
434 qir_TEX_B(c
, lod
, texture_u
[next_texture_u
++]);
436 qir_TEX_S(c
, s
, texture_u
[next_texture_u
++]);
438 c
->num_texture_samples
++;
439 struct qreg tex
= qir_TEX_RESULT(c
);
441 enum pipe_format format
= c
->key
->tex
[unit
].format
;
443 struct qreg
*dest
= ntq_get_dest(c
, &instr
->dest
);
444 if (util_format_is_depth_or_stencil(format
)) {
445 struct qreg normalized
= ntq_scale_depth_texture(c
, tex
);
446 struct qreg depth_output
;
448 struct qreg u0
= qir_uniform_f(c
, 0.0f
);
449 struct qreg u1
= qir_uniform_f(c
, 1.0f
);
450 if (c
->key
->tex
[unit
].compare_mode
) {
451 switch (c
->key
->tex
[unit
].compare_func
) {
452 case PIPE_FUNC_NEVER
:
453 depth_output
= qir_uniform_f(c
, 0.0f
);
455 case PIPE_FUNC_ALWAYS
:
458 case PIPE_FUNC_EQUAL
:
459 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
460 depth_output
= qir_SEL(c
, QPU_COND_ZS
, u1
, u0
);
462 case PIPE_FUNC_NOTEQUAL
:
463 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
464 depth_output
= qir_SEL(c
, QPU_COND_ZC
, u1
, u0
);
466 case PIPE_FUNC_GREATER
:
467 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
468 depth_output
= qir_SEL(c
, QPU_COND_NC
, u1
, u0
);
470 case PIPE_FUNC_GEQUAL
:
471 qir_SF(c
, qir_FSUB(c
, normalized
, compare
));
472 depth_output
= qir_SEL(c
, QPU_COND_NS
, u1
, u0
);
475 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
476 depth_output
= qir_SEL(c
, QPU_COND_NS
, u1
, u0
);
478 case PIPE_FUNC_LEQUAL
:
479 qir_SF(c
, qir_FSUB(c
, normalized
, compare
));
480 depth_output
= qir_SEL(c
, QPU_COND_NC
, u1
, u0
);
484 depth_output
= normalized
;
487 for (int i
= 0; i
< 4; i
++)
488 dest
[i
] = depth_output
;
490 for (int i
= 0; i
< 4; i
++)
491 dest
[i
] = qir_UNPACK_8_F(c
, tex
, i
);
496 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
500 ntq_ffract(struct vc4_compile
*c
, struct qreg src
)
502 struct qreg trunc
= qir_ITOF(c
, qir_FTOI(c
, src
));
503 struct qreg diff
= qir_FSUB(c
, src
, trunc
);
505 return qir_SEL(c
, QPU_COND_NS
,
506 qir_FADD(c
, diff
, qir_uniform_f(c
, 1.0)), diff
);
510 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
514 ntq_ffloor(struct vc4_compile
*c
, struct qreg src
)
516 struct qreg trunc
= qir_ITOF(c
, qir_FTOI(c
, src
));
518 /* This will be < 0 if we truncated and the truncation was of a value
519 * that was < 0 in the first place.
521 qir_SF(c
, qir_FSUB(c
, src
, trunc
));
523 return qir_SEL(c
, QPU_COND_NS
,
524 qir_FSUB(c
, trunc
, qir_uniform_f(c
, 1.0)), trunc
);
528 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
532 ntq_fceil(struct vc4_compile
*c
, struct qreg src
)
534 struct qreg trunc
= qir_ITOF(c
, qir_FTOI(c
, src
));
536 /* This will be < 0 if we truncated and the truncation was of a value
537 * that was > 0 in the first place.
539 qir_SF(c
, qir_FSUB(c
, trunc
, src
));
541 return qir_SEL(c
, QPU_COND_NS
,
542 qir_FADD(c
, trunc
, qir_uniform_f(c
, 1.0)), trunc
);
546 ntq_fsin(struct vc4_compile
*c
, struct qreg src
)
550 pow(2.0 * M_PI
, 3) / (3 * 2 * 1),
551 -pow(2.0 * M_PI
, 5) / (5 * 4 * 3 * 2 * 1),
552 pow(2.0 * M_PI
, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
553 -pow(2.0 * M_PI
, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
556 struct qreg scaled_x
=
559 qir_uniform_f(c
, 1.0 / (M_PI
* 2.0)));
561 struct qreg x
= qir_FADD(c
,
562 ntq_ffract(c
, scaled_x
),
563 qir_uniform_f(c
, -0.5));
564 struct qreg x2
= qir_FMUL(c
, x
, x
);
565 struct qreg sum
= qir_FMUL(c
, x
, qir_uniform_f(c
, coeff
[0]));
566 for (int i
= 1; i
< ARRAY_SIZE(coeff
); i
++) {
567 x
= qir_FMUL(c
, x
, x2
);
572 qir_uniform_f(c
, coeff
[i
])));
578 ntq_fcos(struct vc4_compile
*c
, struct qreg src
)
582 pow(2.0 * M_PI
, 2) / (2 * 1),
583 -pow(2.0 * M_PI
, 4) / (4 * 3 * 2 * 1),
584 pow(2.0 * M_PI
, 6) / (6 * 5 * 4 * 3 * 2 * 1),
585 -pow(2.0 * M_PI
, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
586 pow(2.0 * M_PI
, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
589 struct qreg scaled_x
=
591 qir_uniform_f(c
, 1.0f
/ (M_PI
* 2.0f
)));
592 struct qreg x_frac
= qir_FADD(c
,
593 ntq_ffract(c
, scaled_x
),
594 qir_uniform_f(c
, -0.5));
596 struct qreg sum
= qir_uniform_f(c
, coeff
[0]);
597 struct qreg x2
= qir_FMUL(c
, x_frac
, x_frac
);
598 struct qreg x
= x2
; /* Current x^2, x^4, or x^6 */
599 for (int i
= 1; i
< ARRAY_SIZE(coeff
); i
++) {
601 x
= qir_FMUL(c
, x
, x2
);
603 struct qreg mul
= qir_FMUL(c
,
605 qir_uniform_f(c
, coeff
[i
]));
609 sum
= qir_FADD(c
, sum
, mul
);
615 ntq_fsign(struct vc4_compile
*c
, struct qreg src
)
617 struct qreg t
= qir_get_temp(c
);
620 qir_MOV_dest(c
, t
, qir_uniform_f(c
, 0.0));
621 qir_MOV_dest(c
, t
, qir_uniform_f(c
, 1.0))->cond
= QPU_COND_ZC
;
622 qir_MOV_dest(c
, t
, qir_uniform_f(c
, -1.0))->cond
= QPU_COND_NS
;
627 emit_vertex_input(struct vc4_compile
*c
, int attr
)
629 enum pipe_format format
= c
->vs_key
->attr_formats
[attr
];
630 uint32_t attr_size
= util_format_get_blocksize(format
);
632 c
->vattr_sizes
[attr
] = align(attr_size
, 4);
633 for (int i
= 0; i
< align(attr_size
, 4) / 4; i
++) {
634 c
->inputs
[attr
* 4 + i
] =
635 qir_MOV(c
, qir_reg(QFILE_VPM
, attr
* 4 + i
));
641 emit_fragcoord_input(struct vc4_compile
*c
, int attr
)
643 c
->inputs
[attr
* 4 + 0] = qir_ITOF(c
, qir_reg(QFILE_FRAG_X
, 0));
644 c
->inputs
[attr
* 4 + 1] = qir_ITOF(c
, qir_reg(QFILE_FRAG_Y
, 0));
645 c
->inputs
[attr
* 4 + 2] =
647 qir_ITOF(c
, qir_FRAG_Z(c
)),
648 qir_uniform_f(c
, 1.0 / 0xffffff));
649 c
->inputs
[attr
* 4 + 3] = qir_RCP(c
, qir_FRAG_W(c
));
653 emit_fragment_varying(struct vc4_compile
*c
, gl_varying_slot slot
,
656 uint32_t i
= c
->num_input_slots
++;
662 if (c
->num_input_slots
>= c
->input_slots_array_size
) {
663 c
->input_slots_array_size
=
664 MAX2(4, c
->input_slots_array_size
* 2);
666 c
->input_slots
= reralloc(c
, c
->input_slots
,
667 struct vc4_varying_slot
,
668 c
->input_slots_array_size
);
671 c
->input_slots
[i
].slot
= slot
;
672 c
->input_slots
[i
].swizzle
= swizzle
;
674 return qir_VARY_ADD_C(c
, qir_FMUL(c
, vary
, qir_FRAG_W(c
)));
678 emit_fragment_input(struct vc4_compile
*c
, int attr
, gl_varying_slot slot
)
680 for (int i
= 0; i
< 4; i
++) {
681 c
->inputs
[attr
* 4 + i
] =
682 emit_fragment_varying(c
, slot
, i
);
688 add_output(struct vc4_compile
*c
,
689 uint32_t decl_offset
,
693 uint32_t old_array_size
= c
->outputs_array_size
;
694 resize_qreg_array(c
, &c
->outputs
, &c
->outputs_array_size
,
697 if (old_array_size
!= c
->outputs_array_size
) {
698 c
->output_slots
= reralloc(c
,
700 struct vc4_varying_slot
,
701 c
->outputs_array_size
);
704 c
->output_slots
[decl_offset
].slot
= slot
;
705 c
->output_slots
[decl_offset
].swizzle
= swizzle
;
709 declare_uniform_range(struct vc4_compile
*c
, uint32_t start
, uint32_t size
)
711 unsigned array_id
= c
->num_uniform_ranges
++;
712 if (array_id
>= c
->ubo_ranges_array_size
) {
713 c
->ubo_ranges_array_size
= MAX2(c
->ubo_ranges_array_size
* 2,
715 c
->ubo_ranges
= reralloc(c
, c
->ubo_ranges
,
716 struct vc4_compiler_ubo_range
,
717 c
->ubo_ranges_array_size
);
720 c
->ubo_ranges
[array_id
].dst_offset
= 0;
721 c
->ubo_ranges
[array_id
].src_offset
= start
;
722 c
->ubo_ranges
[array_id
].size
= size
;
723 c
->ubo_ranges
[array_id
].used
= false;
727 ntq_src_is_only_ssa_def_user(nir_src
*src
)
732 if (!list_empty(&src
->ssa
->if_uses
))
735 return (src
->ssa
->uses
.next
== &src
->use_link
&&
736 src
->ssa
->uses
.next
->next
== &src
->ssa
->uses
);
740 * In general, emits a nir_pack_unorm_4x8 as a series of MOVs with the pack
743 * However, as an optimization, it tries to find the instructions generating
744 * the sources to be packed and just emit the pack flag there, if possible.
747 ntq_emit_pack_unorm_4x8(struct vc4_compile
*c
, nir_alu_instr
*instr
)
749 struct qreg result
= qir_get_temp(c
);
750 struct nir_alu_instr
*vec4
= NULL
;
752 /* If packing from a vec4 op (as expected), identify it so that we can
753 * peek back at what generated its sources.
755 if (instr
->src
[0].src
.is_ssa
&&
756 instr
->src
[0].src
.ssa
->parent_instr
->type
== nir_instr_type_alu
&&
757 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
)->op
==
759 vec4
= nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
762 /* If the pack is replicating the same channel 4 times, use the 8888
763 * pack flag. This is common for blending using the alpha
766 if (instr
->src
[0].swizzle
[0] == instr
->src
[0].swizzle
[1] &&
767 instr
->src
[0].swizzle
[0] == instr
->src
[0].swizzle
[2] &&
768 instr
->src
[0].swizzle
[0] == instr
->src
[0].swizzle
[3]) {
769 struct qreg rep
= ntq_get_src(c
,
771 instr
->src
[0].swizzle
[0]);
772 ntq_store_dest(c
, &instr
->dest
.dest
, 0, qir_PACK_8888_F(c
, rep
));
776 for (int i
= 0; i
< 4; i
++) {
777 int swiz
= instr
->src
[0].swizzle
[i
];
780 src
= ntq_get_src(c
, vec4
->src
[swiz
].src
,
781 vec4
->src
[swiz
].swizzle
[0]);
783 src
= ntq_get_src(c
, instr
->src
[0].src
, swiz
);
787 ntq_src_is_only_ssa_def_user(&vec4
->src
[swiz
].src
) &&
788 src
.file
== QFILE_TEMP
&&
789 c
->defs
[src
.index
] &&
790 qir_is_mul(c
->defs
[src
.index
]) &&
791 !c
->defs
[src
.index
]->dst
.pack
) {
792 struct qinst
*rewrite
= c
->defs
[src
.index
];
793 c
->defs
[src
.index
] = NULL
;
794 rewrite
->dst
= result
;
795 rewrite
->dst
.pack
= QPU_PACK_MUL_8A
+ i
;
799 qir_PACK_8_F(c
, result
, src
, i
);
802 ntq_store_dest(c
, &instr
->dest
.dest
, 0, result
);
805 /** Handles sign-extended bitfield extracts for 16 bits. */
807 ntq_emit_ibfe(struct vc4_compile
*c
, struct qreg base
, struct qreg offset
,
810 assert(bits
.file
== QFILE_UNIF
&&
811 c
->uniform_contents
[bits
.index
] == QUNIFORM_CONSTANT
&&
812 c
->uniform_data
[bits
.index
] == 16);
814 assert(offset
.file
== QFILE_UNIF
&&
815 c
->uniform_contents
[offset
.index
] == QUNIFORM_CONSTANT
);
816 int offset_bit
= c
->uniform_data
[offset
.index
];
817 assert(offset_bit
% 16 == 0);
819 return qir_UNPACK_16_I(c
, base
, offset_bit
/ 16);
822 /** Handles unsigned bitfield extracts for 8 bits. */
824 ntq_emit_ubfe(struct vc4_compile
*c
, struct qreg base
, struct qreg offset
,
827 assert(bits
.file
== QFILE_UNIF
&&
828 c
->uniform_contents
[bits
.index
] == QUNIFORM_CONSTANT
&&
829 c
->uniform_data
[bits
.index
] == 8);
831 assert(offset
.file
== QFILE_UNIF
&&
832 c
->uniform_contents
[offset
.index
] == QUNIFORM_CONSTANT
);
833 int offset_bit
= c
->uniform_data
[offset
.index
];
834 assert(offset_bit
% 8 == 0);
836 return qir_UNPACK_8_I(c
, base
, offset_bit
/ 8);
840 * If compare_instr is a valid comparison instruction, emits the
841 * compare_instr's comparison and returns the sel_instr's return value based
842 * on the compare_instr's result.
845 ntq_emit_comparison(struct vc4_compile
*c
, struct qreg
*dest
,
846 nir_alu_instr
*compare_instr
,
847 nir_alu_instr
*sel_instr
)
851 switch (compare_instr
->op
) {
877 struct qreg src0
= ntq_get_alu_src(c
, compare_instr
, 0);
878 struct qreg src1
= ntq_get_alu_src(c
, compare_instr
, 1);
880 unsigned unsized_type
=
881 nir_alu_type_get_base_type(nir_op_infos
[compare_instr
->op
].input_types
[0]);
882 if (unsized_type
== nir_type_float
)
883 qir_SF(c
, qir_FSUB(c
, src0
, src1
));
885 qir_SF(c
, qir_SUB(c
, src0
, src1
));
887 switch (sel_instr
->op
) {
892 *dest
= qir_SEL(c
, cond
,
893 qir_uniform_f(c
, 1.0), qir_uniform_f(c
, 0.0));
897 *dest
= qir_SEL(c
, cond
,
898 ntq_get_alu_src(c
, sel_instr
, 1),
899 ntq_get_alu_src(c
, sel_instr
, 2));
903 *dest
= qir_SEL(c
, cond
,
904 qir_uniform_ui(c
, ~0), qir_uniform_ui(c
, 0));
912 * Attempts to fold a comparison generating a boolean result into the
913 * condition code for selecting between two values, instead of comparing the
914 * boolean result against 0 to generate the condition code.
916 static struct qreg
ntq_emit_bcsel(struct vc4_compile
*c
, nir_alu_instr
*instr
,
919 if (!instr
->src
[0].src
.is_ssa
)
921 nir_alu_instr
*compare
=
922 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
927 if (ntq_emit_comparison(c
, &dest
, compare
, instr
))
932 return qir_SEL(c
, QPU_COND_NS
, src
[1], src
[2]);
936 ntq_emit_alu(struct vc4_compile
*c
, nir_alu_instr
*instr
)
938 /* This should always be lowered to ALU operations for VC4. */
939 assert(!instr
->dest
.saturate
);
941 /* Vectors are special in that they have non-scalarized writemasks,
942 * and just take the first swizzle channel for each argument in order
943 * into each writemask channel.
945 if (instr
->op
== nir_op_vec2
||
946 instr
->op
== nir_op_vec3
||
947 instr
->op
== nir_op_vec4
) {
949 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
950 srcs
[i
] = ntq_get_src(c
, instr
->src
[i
].src
,
951 instr
->src
[i
].swizzle
[0]);
952 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
953 ntq_store_dest(c
, &instr
->dest
.dest
, i
, srcs
[i
]);
957 if (instr
->op
== nir_op_pack_unorm_4x8
) {
958 ntq_emit_pack_unorm_4x8(c
, instr
);
962 if (instr
->op
== nir_op_unpack_unorm_4x8
) {
963 struct qreg src
= ntq_get_src(c
, instr
->src
[0].src
,
964 instr
->src
[0].swizzle
[0]);
965 for (int i
= 0; i
< 4; i
++) {
966 if (instr
->dest
.write_mask
& (1 << i
))
967 ntq_store_dest(c
, &instr
->dest
.dest
, i
,
968 qir_UNPACK_8_F(c
, src
, i
));
973 /* General case: We can just grab the one used channel per src. */
974 struct qreg src
[nir_op_infos
[instr
->op
].num_inputs
];
975 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
976 src
[i
] = ntq_get_alu_src(c
, instr
, i
);
984 result
= qir_MOV(c
, src
[0]);
987 result
= qir_FMUL(c
, src
[0], src
[1]);
990 result
= qir_FADD(c
, src
[0], src
[1]);
993 result
= qir_FSUB(c
, src
[0], src
[1]);
996 result
= qir_FMIN(c
, src
[0], src
[1]);
999 result
= qir_FMAX(c
, src
[0], src
[1]);
1004 result
= qir_FTOI(c
, src
[0]);
1008 result
= qir_ITOF(c
, src
[0]);
1011 result
= qir_AND(c
, src
[0], qir_uniform_f(c
, 1.0));
1014 result
= qir_AND(c
, src
[0], qir_uniform_ui(c
, 1));
1019 result
= qir_SEL(c
, QPU_COND_ZC
,
1020 qir_uniform_ui(c
, ~0),
1021 qir_uniform_ui(c
, 0));
1025 result
= qir_ADD(c
, src
[0], src
[1]);
1028 result
= qir_SHR(c
, src
[0], src
[1]);
1031 result
= qir_SUB(c
, src
[0], src
[1]);
1034 result
= qir_ASR(c
, src
[0], src
[1]);
1037 result
= qir_SHL(c
, src
[0], src
[1]);
1040 result
= qir_MIN(c
, src
[0], src
[1]);
1043 result
= qir_MAX(c
, src
[0], src
[1]);
1046 result
= qir_AND(c
, src
[0], src
[1]);
1049 result
= qir_OR(c
, src
[0], src
[1]);
1052 result
= qir_XOR(c
, src
[0], src
[1]);
1055 result
= qir_NOT(c
, src
[0]);
1059 result
= ntq_umul(c
, src
[0], src
[1]);
1075 if (!ntq_emit_comparison(c
, &result
, instr
, instr
)) {
1076 fprintf(stderr
, "Bad comparison instruction\n");
1081 result
= ntq_emit_bcsel(c
, instr
, src
);
1085 result
= qir_SEL(c
, QPU_COND_ZC
, src
[1], src
[2]);
1089 result
= ntq_rcp(c
, src
[0]);
1092 result
= ntq_rsq(c
, src
[0]);
1095 result
= qir_EXP2(c
, src
[0]);
1098 result
= qir_LOG2(c
, src
[0]);
1102 result
= qir_ITOF(c
, qir_FTOI(c
, src
[0]));
1105 result
= ntq_fceil(c
, src
[0]);
1108 result
= ntq_ffract(c
, src
[0]);
1111 result
= ntq_ffloor(c
, src
[0]);
1115 result
= ntq_fsin(c
, src
[0]);
1118 result
= ntq_fcos(c
, src
[0]);
1122 result
= ntq_fsign(c
, src
[0]);
1126 result
= qir_FMAXABS(c
, src
[0], src
[0]);
1129 result
= qir_MAX(c
, src
[0],
1130 qir_SUB(c
, qir_uniform_ui(c
, 0), src
[0]));
1133 case nir_op_ibitfield_extract
:
1134 result
= ntq_emit_ibfe(c
, src
[0], src
[1], src
[2]);
1137 case nir_op_ubitfield_extract
:
1138 result
= ntq_emit_ubfe(c
, src
[0], src
[1], src
[2]);
1141 case nir_op_usadd_4x8
:
1142 result
= qir_V8ADDS(c
, src
[0], src
[1]);
1145 case nir_op_ussub_4x8
:
1146 result
= qir_V8SUBS(c
, src
[0], src
[1]);
1149 case nir_op_umin_4x8
:
1150 result
= qir_V8MIN(c
, src
[0], src
[1]);
1153 case nir_op_umax_4x8
:
1154 result
= qir_V8MAX(c
, src
[0], src
[1]);
1157 case nir_op_umul_unorm_4x8
:
1158 result
= qir_V8MULD(c
, src
[0], src
[1]);
1162 fprintf(stderr
, "unknown NIR ALU inst: ");
1163 nir_print_instr(&instr
->instr
, stderr
);
1164 fprintf(stderr
, "\n");
1168 /* We have a scalar result, so the instruction should only have a
1169 * single channel written to.
1171 assert(util_is_power_of_two(instr
->dest
.write_mask
));
1172 ntq_store_dest(c
, &instr
->dest
.dest
,
1173 ffs(instr
->dest
.write_mask
) - 1, result
);
1177 emit_frag_end(struct vc4_compile
*c
)
1180 if (c
->output_color_index
!= -1) {
1181 color
= c
->outputs
[c
->output_color_index
];
1183 color
= qir_uniform_ui(c
, 0);
1186 uint32_t discard_cond
= QPU_COND_ALWAYS
;
1187 if (c
->discard
.file
!= QFILE_NULL
) {
1188 qir_SF(c
, c
->discard
);
1189 discard_cond
= QPU_COND_ZS
;
1192 if (c
->fs_key
->stencil_enabled
) {
1193 qir_MOV_dest(c
, qir_reg(QFILE_TLB_STENCIL_SETUP
, 0),
1194 qir_uniform(c
, QUNIFORM_STENCIL
, 0));
1195 if (c
->fs_key
->stencil_twoside
) {
1196 qir_MOV_dest(c
, qir_reg(QFILE_TLB_STENCIL_SETUP
, 0),
1197 qir_uniform(c
, QUNIFORM_STENCIL
, 1));
1199 if (c
->fs_key
->stencil_full_writemasks
) {
1200 qir_MOV_dest(c
, qir_reg(QFILE_TLB_STENCIL_SETUP
, 0),
1201 qir_uniform(c
, QUNIFORM_STENCIL
, 2));
1205 if (c
->output_sample_mask_index
!= -1) {
1206 qir_MS_MASK(c
, c
->outputs
[c
->output_sample_mask_index
]);
1209 if (c
->fs_key
->depth_enabled
) {
1210 if (c
->output_position_index
!= -1) {
1211 qir_FTOI_dest(c
, qir_reg(QFILE_TLB_Z_WRITE
, 0),
1213 c
->outputs
[c
->output_position_index
],
1214 qir_uniform_f(c
, 0xffffff)))->cond
= discard_cond
;
1216 qir_MOV_dest(c
, qir_reg(QFILE_TLB_Z_WRITE
, 0),
1217 qir_FRAG_Z(c
))->cond
= discard_cond
;
1221 if (!c
->msaa_per_sample_output
) {
1222 qir_MOV_dest(c
, qir_reg(QFILE_TLB_COLOR_WRITE
, 0),
1223 color
)->cond
= discard_cond
;
1225 for (int i
= 0; i
< VC4_MAX_SAMPLES
; i
++) {
1226 qir_MOV_dest(c
, qir_reg(QFILE_TLB_COLOR_WRITE_MS
, 0),
1227 c
->sample_colors
[i
])->cond
= discard_cond
;
1233 emit_scaled_viewport_write(struct vc4_compile
*c
, struct qreg rcp_w
)
1235 struct qreg packed
= qir_get_temp(c
);
1237 for (int i
= 0; i
< 2; i
++) {
1239 qir_uniform(c
, QUNIFORM_VIEWPORT_X_SCALE
+ i
, 0);
1241 struct qreg packed_chan
= packed
;
1242 packed_chan
.pack
= QPU_PACK_A_16A
+ i
;
1244 qir_FTOI_dest(c
, packed_chan
,
1247 c
->outputs
[c
->output_position_index
+ i
],
1252 qir_VPM_WRITE(c
, packed
);
1256 emit_zs_write(struct vc4_compile
*c
, struct qreg rcp_w
)
1258 struct qreg zscale
= qir_uniform(c
, QUNIFORM_VIEWPORT_Z_SCALE
, 0);
1259 struct qreg zoffset
= qir_uniform(c
, QUNIFORM_VIEWPORT_Z_OFFSET
, 0);
1261 qir_VPM_WRITE(c
, qir_FADD(c
, qir_FMUL(c
, qir_FMUL(c
,
1262 c
->outputs
[c
->output_position_index
+ 2],
1269 emit_rcp_wc_write(struct vc4_compile
*c
, struct qreg rcp_w
)
1271 qir_VPM_WRITE(c
, rcp_w
);
1275 emit_point_size_write(struct vc4_compile
*c
)
1277 struct qreg point_size
;
1279 if (c
->output_point_size_index
!= -1)
1280 point_size
= c
->outputs
[c
->output_point_size_index
];
1282 point_size
= qir_uniform_f(c
, 1.0);
1284 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1287 point_size
= qir_FMAX(c
, point_size
, qir_uniform_f(c
, .125));
1289 qir_VPM_WRITE(c
, point_size
);
1293 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1295 * The simulator insists that there be at least one vertex attribute, so
1296 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also
1297 * insists that all vertex attributes loaded get read by the VS/CS, so we have
1298 * to consume it here.
1301 emit_stub_vpm_read(struct vc4_compile
*c
)
1306 c
->vattr_sizes
[0] = 4;
1307 (void)qir_MOV(c
, qir_reg(QFILE_VPM
, 0));
1312 emit_vert_end(struct vc4_compile
*c
,
1313 struct vc4_varying_slot
*fs_inputs
,
1314 uint32_t num_fs_inputs
)
1316 struct qreg rcp_w
= qir_RCP(c
, c
->outputs
[c
->output_position_index
+ 3]);
1318 emit_stub_vpm_read(c
);
1320 emit_scaled_viewport_write(c
, rcp_w
);
1321 emit_zs_write(c
, rcp_w
);
1322 emit_rcp_wc_write(c
, rcp_w
);
1323 if (c
->vs_key
->per_vertex_point_size
)
1324 emit_point_size_write(c
);
1326 for (int i
= 0; i
< num_fs_inputs
; i
++) {
1327 struct vc4_varying_slot
*input
= &fs_inputs
[i
];
1330 for (j
= 0; j
< c
->num_outputs
; j
++) {
1331 struct vc4_varying_slot
*output
=
1332 &c
->output_slots
[j
];
1334 if (input
->slot
== output
->slot
&&
1335 input
->swizzle
== output
->swizzle
) {
1336 qir_VPM_WRITE(c
, c
->outputs
[j
]);
1340 /* Emit padding if we didn't find a declared VS output for
1343 if (j
== c
->num_outputs
)
1344 qir_VPM_WRITE(c
, qir_uniform_f(c
, 0.0));
1349 emit_coord_end(struct vc4_compile
*c
)
1351 struct qreg rcp_w
= qir_RCP(c
, c
->outputs
[c
->output_position_index
+ 3]);
1353 emit_stub_vpm_read(c
);
1355 for (int i
= 0; i
< 4; i
++)
1356 qir_VPM_WRITE(c
, c
->outputs
[c
->output_position_index
+ i
]);
1358 emit_scaled_viewport_write(c
, rcp_w
);
1359 emit_zs_write(c
, rcp_w
);
1360 emit_rcp_wc_write(c
, rcp_w
);
1361 if (c
->vs_key
->per_vertex_point_size
)
1362 emit_point_size_write(c
);
1366 vc4_optimize_nir(struct nir_shader
*s
)
1373 NIR_PASS_V(s
, nir_lower_vars_to_ssa
);
1374 NIR_PASS_V(s
, nir_lower_alu_to_scalar
);
1375 NIR_PASS_V(s
, nir_lower_phis_to_scalar
);
1377 NIR_PASS(progress
, s
, nir_copy_prop
);
1378 NIR_PASS(progress
, s
, nir_opt_remove_phis
);
1379 NIR_PASS(progress
, s
, nir_opt_dce
);
1380 NIR_PASS(progress
, s
, nir_opt_dead_cf
);
1381 NIR_PASS(progress
, s
, nir_opt_cse
);
1382 NIR_PASS(progress
, s
, nir_opt_peephole_select
);
1383 NIR_PASS(progress
, s
, nir_opt_algebraic
);
1384 NIR_PASS(progress
, s
, nir_opt_constant_folding
);
1385 NIR_PASS(progress
, s
, nir_opt_undef
);
1390 driver_location_compare(const void *in_a
, const void *in_b
)
1392 const nir_variable
*const *a
= in_a
;
1393 const nir_variable
*const *b
= in_b
;
1395 return (*a
)->data
.driver_location
- (*b
)->data
.driver_location
;
1399 ntq_setup_inputs(struct vc4_compile
*c
)
1401 unsigned num_entries
= 0;
1402 nir_foreach_variable(var
, &c
->s
->inputs
)
1405 nir_variable
*vars
[num_entries
];
1408 nir_foreach_variable(var
, &c
->s
->inputs
)
1411 /* Sort the variables so that we emit the input setup in
1412 * driver_location order. This is required for VPM reads, whose data
1413 * is fetched into the VPM in driver_location (TGSI register index)
1416 qsort(&vars
, num_entries
, sizeof(*vars
), driver_location_compare
);
1418 for (unsigned i
= 0; i
< num_entries
; i
++) {
1419 nir_variable
*var
= vars
[i
];
1420 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1421 unsigned loc
= var
->data
.driver_location
;
1423 assert(array_len
== 1);
1425 resize_qreg_array(c
, &c
->inputs
, &c
->inputs_array_size
,
1428 if (c
->stage
== QSTAGE_FRAG
) {
1429 if (var
->data
.location
== VARYING_SLOT_POS
) {
1430 emit_fragcoord_input(c
, loc
);
1431 } else if (var
->data
.location
== VARYING_SLOT_PNTC
||
1432 (var
->data
.location
>= VARYING_SLOT_VAR0
&&
1433 (c
->fs_key
->point_sprite_mask
&
1434 (1 << (var
->data
.location
-
1435 VARYING_SLOT_VAR0
))))) {
1436 c
->inputs
[loc
* 4 + 0] = c
->point_x
;
1437 c
->inputs
[loc
* 4 + 1] = c
->point_y
;
1439 emit_fragment_input(c
, loc
, var
->data
.location
);
1442 emit_vertex_input(c
, loc
);
1448 ntq_setup_outputs(struct vc4_compile
*c
)
1450 nir_foreach_variable(var
, &c
->s
->outputs
) {
1451 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1452 unsigned loc
= var
->data
.driver_location
* 4;
1454 assert(array_len
== 1);
1457 for (int i
= 0; i
< 4; i
++)
1458 add_output(c
, loc
+ i
, var
->data
.location
, i
);
1460 if (c
->stage
== QSTAGE_FRAG
) {
1461 switch (var
->data
.location
) {
1462 case FRAG_RESULT_COLOR
:
1463 case FRAG_RESULT_DATA0
:
1464 c
->output_color_index
= loc
;
1466 case FRAG_RESULT_DEPTH
:
1467 c
->output_position_index
= loc
;
1469 case FRAG_RESULT_SAMPLE_MASK
:
1470 c
->output_sample_mask_index
= loc
;
1474 switch (var
->data
.location
) {
1475 case VARYING_SLOT_POS
:
1476 c
->output_position_index
= loc
;
1478 case VARYING_SLOT_PSIZ
:
1479 c
->output_point_size_index
= loc
;
1487 ntq_setup_uniforms(struct vc4_compile
*c
)
1489 nir_foreach_variable(var
, &c
->s
->uniforms
) {
1490 uint32_t vec4_count
= st_glsl_type_size(var
->type
);
1491 unsigned vec4_size
= 4 * sizeof(float);
1493 declare_uniform_range(c
, var
->data
.driver_location
* vec4_size
,
1494 vec4_count
* vec4_size
);
1500 * Sets up the mapping from nir_register to struct qreg *.
1502 * Each nir_register gets a struct qreg per 32-bit component being stored.
1505 ntq_setup_registers(struct vc4_compile
*c
, struct exec_list
*list
)
1507 foreach_list_typed(nir_register
, nir_reg
, node
, list
) {
1508 unsigned array_len
= MAX2(nir_reg
->num_array_elems
, 1);
1509 struct qreg
*qregs
= ralloc_array(c
->def_ht
, struct qreg
,
1511 nir_reg
->num_components
);
1513 _mesa_hash_table_insert(c
->def_ht
, nir_reg
, qregs
);
1515 for (int i
= 0; i
< array_len
* nir_reg
->num_components
; i
++)
1516 qregs
[i
] = qir_get_temp(c
);
1521 ntq_emit_load_const(struct vc4_compile
*c
, nir_load_const_instr
*instr
)
1523 struct qreg
*qregs
= ntq_init_ssa_def(c
, &instr
->def
);
1524 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1525 qregs
[i
] = qir_uniform_ui(c
, instr
->value
.u32
[i
]);
1527 _mesa_hash_table_insert(c
->def_ht
, &instr
->def
, qregs
);
1531 ntq_emit_ssa_undef(struct vc4_compile
*c
, nir_ssa_undef_instr
*instr
)
1533 struct qreg
*qregs
= ntq_init_ssa_def(c
, &instr
->def
);
1535 /* QIR needs there to be *some* value, so pick 0 (same as for
1536 * ntq_setup_registers().
1538 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1539 qregs
[i
] = qir_uniform_ui(c
, 0);
1543 ntq_emit_intrinsic(struct vc4_compile
*c
, nir_intrinsic_instr
*instr
)
1545 nir_const_value
*const_offset
;
1548 switch (instr
->intrinsic
) {
1549 case nir_intrinsic_load_uniform
:
1550 assert(instr
->num_components
== 1);
1551 const_offset
= nir_src_as_const_value(instr
->src
[0]);
1553 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1554 assert(offset
% 4 == 0);
1555 /* We need dwords */
1556 offset
= offset
/ 4;
1557 ntq_store_dest(c
, &instr
->dest
, 0,
1558 qir_uniform(c
, QUNIFORM_UNIFORM
,
1561 ntq_store_dest(c
, &instr
->dest
, 0,
1562 indirect_uniform_load(c
, instr
));
1566 case nir_intrinsic_load_user_clip_plane
:
1567 for (int i
= 0; i
< instr
->num_components
; i
++) {
1568 ntq_store_dest(c
, &instr
->dest
, i
,
1569 qir_uniform(c
, QUNIFORM_USER_CLIP_PLANE
,
1570 nir_intrinsic_ucp_id(instr
) *
1575 case nir_intrinsic_load_blend_const_color_r_float
:
1576 case nir_intrinsic_load_blend_const_color_g_float
:
1577 case nir_intrinsic_load_blend_const_color_b_float
:
1578 case nir_intrinsic_load_blend_const_color_a_float
:
1579 ntq_store_dest(c
, &instr
->dest
, 0,
1580 qir_uniform(c
, QUNIFORM_BLEND_CONST_COLOR_X
+
1582 nir_intrinsic_load_blend_const_color_r_float
),
1586 case nir_intrinsic_load_blend_const_color_rgba8888_unorm
:
1587 ntq_store_dest(c
, &instr
->dest
, 0,
1588 qir_uniform(c
, QUNIFORM_BLEND_CONST_COLOR_RGBA
,
1592 case nir_intrinsic_load_blend_const_color_aaaa8888_unorm
:
1593 ntq_store_dest(c
, &instr
->dest
, 0,
1594 qir_uniform(c
, QUNIFORM_BLEND_CONST_COLOR_AAAA
,
1598 case nir_intrinsic_load_alpha_ref_float
:
1599 ntq_store_dest(c
, &instr
->dest
, 0,
1600 qir_uniform(c
, QUNIFORM_ALPHA_REF
, 0));
1603 case nir_intrinsic_load_sample_mask_in
:
1604 ntq_store_dest(c
, &instr
->dest
, 0,
1605 qir_uniform(c
, QUNIFORM_SAMPLE_MASK
, 0));
1608 case nir_intrinsic_load_front_face
:
1609 /* The register contains 0 (front) or 1 (back), and we need to
1610 * turn it into a NIR bool where true means front.
1612 ntq_store_dest(c
, &instr
->dest
, 0,
1614 qir_uniform_ui(c
, -1),
1615 qir_reg(QFILE_FRAG_REV_FLAG
, 0)));
1618 case nir_intrinsic_load_input
:
1619 assert(instr
->num_components
== 1);
1620 const_offset
= nir_src_as_const_value(instr
->src
[0]);
1621 assert(const_offset
&& "vc4 doesn't support indirect inputs");
1622 if (c
->stage
== QSTAGE_FRAG
&&
1623 nir_intrinsic_base(instr
) >= VC4_NIR_TLB_COLOR_READ_INPUT
) {
1624 assert(const_offset
->u32
[0] == 0);
1625 /* Reads of the per-sample color need to be done in
1628 int sample_index
= (nir_intrinsic_base(instr
) -
1629 VC4_NIR_TLB_COLOR_READ_INPUT
);
1630 for (int i
= 0; i
<= sample_index
; i
++) {
1631 if (c
->color_reads
[i
].file
== QFILE_NULL
) {
1633 qir_TLB_COLOR_READ(c
);
1636 ntq_store_dest(c
, &instr
->dest
, 0,
1637 c
->color_reads
[sample_index
]);
1639 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1640 int comp
= nir_intrinsic_component(instr
);
1641 ntq_store_dest(c
, &instr
->dest
, 0,
1642 c
->inputs
[offset
* 4 + comp
]);
1646 case nir_intrinsic_store_output
:
1647 const_offset
= nir_src_as_const_value(instr
->src
[1]);
1648 assert(const_offset
&& "vc4 doesn't support indirect outputs");
1649 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1651 /* MSAA color outputs are the only case where we have an
1652 * output that's not lowered to being a store of a single 32
1655 if (c
->stage
== QSTAGE_FRAG
&& instr
->num_components
== 4) {
1656 assert(offset
== c
->output_color_index
);
1657 for (int i
= 0; i
< 4; i
++) {
1658 c
->sample_colors
[i
] =
1659 qir_MOV(c
, ntq_get_src(c
, instr
->src
[0],
1663 offset
= offset
* 4 + nir_intrinsic_component(instr
);
1664 assert(instr
->num_components
== 1);
1665 c
->outputs
[offset
] =
1666 qir_MOV(c
, ntq_get_src(c
, instr
->src
[0], 0));
1667 c
->num_outputs
= MAX2(c
->num_outputs
, offset
+ 1);
1671 case nir_intrinsic_discard
:
1672 c
->discard
= qir_uniform_ui(c
, ~0);
1675 case nir_intrinsic_discard_if
:
1676 if (c
->discard
.file
== QFILE_NULL
)
1677 c
->discard
= qir_uniform_ui(c
, 0);
1678 c
->discard
= qir_OR(c
, c
->discard
,
1679 ntq_get_src(c
, instr
->src
[0], 0));
1683 fprintf(stderr
, "Unknown intrinsic: ");
1684 nir_print_instr(&instr
->instr
, stderr
);
1685 fprintf(stderr
, "\n");
1690 /* Clears (activates) the execute flags for any channels whose jump target
1691 * matches this block.
1694 ntq_activate_execute_for_block(struct vc4_compile
*c
)
1696 qir_SF(c
, qir_SUB(c
,
1698 qir_uniform_ui(c
, c
->cur_block
->index
)));
1699 qir_MOV_cond(c
, QPU_COND_ZS
, c
->execute
, qir_uniform_ui(c
, 0));
1703 ntq_emit_if(struct vc4_compile
*c
, nir_if
*if_stmt
)
1705 if (!c
->vc4
->screen
->has_control_flow
) {
1707 "IF statement support requires updated kernel.\n");
1711 nir_cf_node
*nir_first_else_node
= nir_if_first_else_node(if_stmt
);
1712 nir_cf_node
*nir_last_else_node
= nir_if_last_else_node(if_stmt
);
1713 nir_block
*nir_else_block
= nir_cf_node_as_block(nir_first_else_node
);
1714 bool empty_else_block
=
1715 (nir_first_else_node
== nir_last_else_node
&&
1716 exec_list_is_empty(&nir_else_block
->instr_list
));
1718 struct qblock
*then_block
= qir_new_block(c
);
1719 struct qblock
*after_block
= qir_new_block(c
);
1720 struct qblock
*else_block
;
1721 if (empty_else_block
)
1722 else_block
= after_block
;
1724 else_block
= qir_new_block(c
);
1726 bool was_top_level
= false;
1727 if (c
->execute
.file
== QFILE_NULL
) {
1728 c
->execute
= qir_MOV(c
, qir_uniform_ui(c
, 0));
1729 was_top_level
= true;
1732 /* Set ZS for executing (execute == 0) and jumping (if->condition ==
1733 * 0) channels, and then update execute flags for those to point to
1738 ntq_get_src(c
, if_stmt
->condition
, 0)));
1739 qir_MOV_cond(c
, QPU_COND_ZS
, c
->execute
,
1740 qir_uniform_ui(c
, else_block
->index
));
1742 /* Jump to ELSE if nothing is active for THEN, otherwise fall
1745 qir_SF(c
, c
->execute
);
1746 qir_BRANCH(c
, QPU_COND_BRANCH_ALL_ZC
);
1747 qir_link_blocks(c
->cur_block
, else_block
);
1748 qir_link_blocks(c
->cur_block
, then_block
);
1750 /* Process the THEN block. */
1751 qir_set_emit_block(c
, then_block
);
1752 ntq_emit_cf_list(c
, &if_stmt
->then_list
);
1754 if (!empty_else_block
) {
1755 /* Handle the end of the THEN block. First, all currently
1756 * active channels update their execute flags to point to
1759 qir_SF(c
, c
->execute
);
1760 qir_MOV_cond(c
, QPU_COND_ZS
, c
->execute
,
1761 qir_uniform_ui(c
, after_block
->index
));
1763 /* If everything points at ENDIF, then jump there immediately. */
1764 qir_SF(c
, qir_SUB(c
, c
->execute
, qir_uniform_ui(c
, after_block
->index
)));
1765 qir_BRANCH(c
, QPU_COND_BRANCH_ALL_ZS
);
1766 qir_link_blocks(c
->cur_block
, after_block
);
1767 qir_link_blocks(c
->cur_block
, else_block
);
1769 qir_set_emit_block(c
, else_block
);
1770 ntq_activate_execute_for_block(c
);
1771 ntq_emit_cf_list(c
, &if_stmt
->else_list
);
1774 qir_link_blocks(c
->cur_block
, after_block
);
1776 qir_set_emit_block(c
, after_block
);
1778 c
->execute
= c
->undef
;
1780 ntq_activate_execute_for_block(c
);
1785 ntq_emit_jump(struct vc4_compile
*c
, nir_jump_instr
*jump
)
1787 switch (jump
->type
) {
1788 case nir_jump_break
:
1789 qir_SF(c
, c
->execute
);
1790 qir_MOV_cond(c
, QPU_COND_ZS
, c
->execute
,
1791 qir_uniform_ui(c
, c
->loop_break_block
->index
));
1794 case nir_jump_continue
:
1795 qir_SF(c
, c
->execute
);
1796 qir_MOV_cond(c
, QPU_COND_ZS
, c
->execute
,
1797 qir_uniform_ui(c
, c
->loop_cont_block
->index
));
1800 case nir_jump_return
:
1801 unreachable("All returns shouold be lowered\n");
1806 ntq_emit_instr(struct vc4_compile
*c
, nir_instr
*instr
)
1808 switch (instr
->type
) {
1809 case nir_instr_type_alu
:
1810 ntq_emit_alu(c
, nir_instr_as_alu(instr
));
1813 case nir_instr_type_intrinsic
:
1814 ntq_emit_intrinsic(c
, nir_instr_as_intrinsic(instr
));
1817 case nir_instr_type_load_const
:
1818 ntq_emit_load_const(c
, nir_instr_as_load_const(instr
));
1821 case nir_instr_type_ssa_undef
:
1822 ntq_emit_ssa_undef(c
, nir_instr_as_ssa_undef(instr
));
1825 case nir_instr_type_tex
:
1826 ntq_emit_tex(c
, nir_instr_as_tex(instr
));
1829 case nir_instr_type_jump
:
1830 ntq_emit_jump(c
, nir_instr_as_jump(instr
));
1834 fprintf(stderr
, "Unknown NIR instr type: ");
1835 nir_print_instr(instr
, stderr
);
1836 fprintf(stderr
, "\n");
1842 ntq_emit_block(struct vc4_compile
*c
, nir_block
*block
)
1844 nir_foreach_instr(instr
, block
) {
1845 ntq_emit_instr(c
, instr
);
1849 static void ntq_emit_cf_list(struct vc4_compile
*c
, struct exec_list
*list
);
1852 ntq_emit_loop(struct vc4_compile
*c
, nir_loop
*loop
)
1854 if (!c
->vc4
->screen
->has_control_flow
) {
1856 "loop support requires updated kernel.\n");
1857 ntq_emit_cf_list(c
, &loop
->body
);
1861 bool was_top_level
= false;
1862 if (c
->execute
.file
== QFILE_NULL
) {
1863 c
->execute
= qir_MOV(c
, qir_uniform_ui(c
, 0));
1864 was_top_level
= true;
1867 struct qblock
*save_loop_cont_block
= c
->loop_cont_block
;
1868 struct qblock
*save_loop_break_block
= c
->loop_break_block
;
1870 c
->loop_cont_block
= qir_new_block(c
);
1871 c
->loop_break_block
= qir_new_block(c
);
1873 qir_link_blocks(c
->cur_block
, c
->loop_cont_block
);
1874 qir_set_emit_block(c
, c
->loop_cont_block
);
1875 ntq_activate_execute_for_block(c
);
1877 ntq_emit_cf_list(c
, &loop
->body
);
1879 /* If anything had explicitly continued, or is here at the end of the
1880 * loop, then we need to loop again. SF updates are masked by the
1881 * instruction's condition, so we can do the OR of the two conditions
1884 qir_SF(c
, c
->execute
);
1885 struct qinst
*cont_check
=
1889 qir_uniform_ui(c
, c
->loop_cont_block
->index
));
1890 cont_check
->cond
= QPU_COND_ZC
;
1891 cont_check
->sf
= true;
1893 qir_BRANCH(c
, QPU_COND_BRANCH_ANY_ZS
);
1894 qir_link_blocks(c
->cur_block
, c
->loop_cont_block
);
1895 qir_link_blocks(c
->cur_block
, c
->loop_break_block
);
1897 qir_set_emit_block(c
, c
->loop_break_block
);
1899 c
->execute
= c
->undef
;
1901 ntq_activate_execute_for_block(c
);
1903 c
->loop_break_block
= save_loop_break_block
;
1904 c
->loop_cont_block
= save_loop_cont_block
;
1908 ntq_emit_function(struct vc4_compile
*c
, nir_function_impl
*func
)
1910 fprintf(stderr
, "FUNCTIONS not handled.\n");
1915 ntq_emit_cf_list(struct vc4_compile
*c
, struct exec_list
*list
)
1917 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
1918 switch (node
->type
) {
1919 case nir_cf_node_block
:
1920 ntq_emit_block(c
, nir_cf_node_as_block(node
));
1923 case nir_cf_node_if
:
1924 ntq_emit_if(c
, nir_cf_node_as_if(node
));
1927 case nir_cf_node_loop
:
1928 ntq_emit_loop(c
, nir_cf_node_as_loop(node
));
1931 case nir_cf_node_function
:
1932 ntq_emit_function(c
, nir_cf_node_as_function(node
));
1936 fprintf(stderr
, "Unknown NIR node type\n");
1943 ntq_emit_impl(struct vc4_compile
*c
, nir_function_impl
*impl
)
1945 ntq_setup_registers(c
, &impl
->registers
);
1946 ntq_emit_cf_list(c
, &impl
->body
);
1950 nir_to_qir(struct vc4_compile
*c
)
1952 ntq_setup_inputs(c
);
1953 ntq_setup_outputs(c
);
1954 ntq_setup_uniforms(c
);
1955 ntq_setup_registers(c
, &c
->s
->registers
);
1957 /* Find the main function and emit the body. */
1958 nir_foreach_function(function
, c
->s
) {
1959 assert(strcmp(function
->name
, "main") == 0);
1960 assert(function
->impl
);
1961 ntq_emit_impl(c
, function
->impl
);
1965 static const nir_shader_compiler_options nir_options
= {
1966 .lower_extract_byte
= true,
1967 .lower_extract_word
= true,
1969 .lower_flrp32
= true,
1972 .lower_fsqrt
= true,
1973 .lower_negate
= true,
1974 .native_integers
= true,
1978 vc4_screen_get_compiler_options(struct pipe_screen
*pscreen
,
1979 enum pipe_shader_ir ir
, unsigned shader
)
1981 return &nir_options
;
1985 count_nir_instrs(nir_shader
*nir
)
1988 nir_foreach_function(function
, nir
) {
1989 if (!function
->impl
)
1991 nir_foreach_block(block
, function
->impl
) {
1992 nir_foreach_instr(instr
, block
)
1999 static struct vc4_compile
*
2000 vc4_shader_ntq(struct vc4_context
*vc4
, enum qstage stage
,
2001 struct vc4_key
*key
)
2003 struct vc4_compile
*c
= qir_compile_init();
2007 c
->shader_state
= &key
->shader_state
->base
;
2008 c
->program_id
= key
->shader_state
->program_id
;
2010 p_atomic_inc_return(&key
->shader_state
->compiled_variant_count
);
2015 c
->fs_key
= (struct vc4_fs_key
*)key
;
2016 if (c
->fs_key
->is_points
) {
2017 c
->point_x
= emit_fragment_varying(c
, ~0, 0);
2018 c
->point_y
= emit_fragment_varying(c
, ~0, 0);
2019 } else if (c
->fs_key
->is_lines
) {
2020 c
->line_x
= emit_fragment_varying(c
, ~0, 0);
2024 c
->vs_key
= (struct vc4_vs_key
*)key
;
2027 c
->vs_key
= (struct vc4_vs_key
*)key
;
2031 c
->s
= nir_shader_clone(c
, key
->shader_state
->base
.ir
.nir
);
2033 if (stage
== QSTAGE_FRAG
)
2034 NIR_PASS_V(c
->s
, vc4_nir_lower_blend
, c
);
2036 struct nir_lower_tex_options tex_options
= {
2037 /* We would need to implement txs, but we don't want the
2038 * int/float conversions
2040 .lower_rect
= false,
2044 /* Apply swizzles to all samplers. */
2045 .swizzle_result
= ~0,
2048 /* Lower the format swizzle and ARB_texture_swizzle-style swizzle.
2049 * The format swizzling applies before sRGB decode, and
2050 * ARB_texture_swizzle is the last thing before returning the sample.
2052 for (int i
= 0; i
< ARRAY_SIZE(key
->tex
); i
++) {
2053 enum pipe_format format
= c
->key
->tex
[i
].format
;
2058 const uint8_t *format_swizzle
= vc4_get_format_swizzle(format
);
2060 for (int j
= 0; j
< 4; j
++) {
2061 uint8_t arb_swiz
= c
->key
->tex
[i
].swizzle
[j
];
2063 if (arb_swiz
<= 3) {
2064 tex_options
.swizzles
[i
][j
] =
2065 format_swizzle
[arb_swiz
];
2067 tex_options
.swizzles
[i
][j
] = arb_swiz
;
2071 if (util_format_is_srgb(format
))
2072 tex_options
.lower_srgb
|= (1 << i
);
2075 NIR_PASS_V(c
->s
, nir_lower_tex
, &tex_options
);
2077 if (c
->fs_key
&& c
->fs_key
->light_twoside
)
2078 NIR_PASS_V(c
->s
, nir_lower_two_sided_color
);
2080 if (c
->vs_key
&& c
->vs_key
->clamp_color
)
2081 NIR_PASS_V(c
->s
, nir_lower_clamp_color_outputs
);
2083 if (c
->key
->ucp_enables
) {
2084 if (stage
== QSTAGE_FRAG
) {
2085 NIR_PASS_V(c
->s
, nir_lower_clip_fs
, c
->key
->ucp_enables
);
2087 NIR_PASS_V(c
->s
, nir_lower_clip_vs
, c
->key
->ucp_enables
);
2088 NIR_PASS_V(c
->s
, nir_lower_io_to_scalar
,
2089 nir_var_shader_out
);
2093 /* FS input scalarizing must happen after nir_lower_two_sided_color,
2094 * which only handles a vec4 at a time. Similarly, VS output
2095 * scalarizing must happen after nir_lower_clip_vs.
2097 if (c
->stage
== QSTAGE_FRAG
)
2098 NIR_PASS_V(c
->s
, nir_lower_io_to_scalar
, nir_var_shader_in
);
2100 NIR_PASS_V(c
->s
, nir_lower_io_to_scalar
, nir_var_shader_out
);
2102 NIR_PASS_V(c
->s
, vc4_nir_lower_io
, c
);
2103 NIR_PASS_V(c
->s
, vc4_nir_lower_txf_ms
, c
);
2104 NIR_PASS_V(c
->s
, nir_lower_idiv
);
2106 vc4_optimize_nir(c
->s
);
2108 NIR_PASS_V(c
->s
, nir_convert_from_ssa
, true);
2110 if (vc4_debug
& VC4_DEBUG_SHADERDB
) {
2111 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %d NIR instructions\n",
2112 qir_get_stage_name(c
->stage
),
2113 c
->program_id
, c
->variant_id
,
2114 count_nir_instrs(c
->s
));
2117 if (vc4_debug
& VC4_DEBUG_NIR
) {
2118 fprintf(stderr
, "%s prog %d/%d NIR:\n",
2119 qir_get_stage_name(c
->stage
),
2120 c
->program_id
, c
->variant_id
);
2121 nir_print_shader(c
->s
, stderr
);
2132 c
->vs_key
->fs_inputs
->input_slots
,
2133 c
->vs_key
->fs_inputs
->num_inputs
);
2140 if (vc4_debug
& VC4_DEBUG_QIR
) {
2141 fprintf(stderr
, "%s prog %d/%d pre-opt QIR:\n",
2142 qir_get_stage_name(c
->stage
),
2143 c
->program_id
, c
->variant_id
);
2145 fprintf(stderr
, "\n");
2149 qir_lower_uniforms(c
);
2151 qir_schedule_instructions(c
);
2152 qir_emit_uniform_stream_resets(c
);
2154 if (vc4_debug
& VC4_DEBUG_QIR
) {
2155 fprintf(stderr
, "%s prog %d/%d QIR:\n",
2156 qir_get_stage_name(c
->stage
),
2157 c
->program_id
, c
->variant_id
);
2159 fprintf(stderr
, "\n");
2162 qir_reorder_uniforms(c
);
2163 vc4_generate_code(vc4
, c
);
2165 if (vc4_debug
& VC4_DEBUG_SHADERDB
) {
2166 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %d instructions\n",
2167 qir_get_stage_name(c
->stage
),
2168 c
->program_id
, c
->variant_id
,
2170 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %d uniforms\n",
2171 qir_get_stage_name(c
->stage
),
2172 c
->program_id
, c
->variant_id
,
2182 vc4_shader_state_create(struct pipe_context
*pctx
,
2183 const struct pipe_shader_state
*cso
)
2185 struct vc4_context
*vc4
= vc4_context(pctx
);
2186 struct vc4_uncompiled_shader
*so
= CALLOC_STRUCT(vc4_uncompiled_shader
);
2190 so
->program_id
= vc4
->next_uncompiled_program_id
++;
2194 if (cso
->type
== PIPE_SHADER_IR_NIR
) {
2195 /* The backend takes ownership of the NIR shader on state
2200 assert(cso
->type
== PIPE_SHADER_IR_TGSI
);
2202 if (vc4_debug
& VC4_DEBUG_TGSI
) {
2203 fprintf(stderr
, "prog %d TGSI:\n",
2205 tgsi_dump(cso
->tokens
, 0);
2206 fprintf(stderr
, "\n");
2208 s
= tgsi_to_nir(cso
->tokens
, &nir_options
);
2211 NIR_PASS_V(s
, nir_opt_global_to_local
);
2212 NIR_PASS_V(s
, nir_convert_to_ssa
);
2213 NIR_PASS_V(s
, nir_normalize_cubemap_coords
);
2215 NIR_PASS_V(s
, nir_lower_load_const_to_scalar
);
2217 vc4_optimize_nir(s
);
2219 NIR_PASS_V(s
, nir_remove_dead_variables
, nir_var_local
);
2221 /* Garbage collect dead instructions */
2224 so
->base
.type
= PIPE_SHADER_IR_NIR
;
2225 so
->base
.ir
.nir
= s
;
2227 if (vc4_debug
& VC4_DEBUG_NIR
) {
2228 fprintf(stderr
, "%s prog %d NIR:\n",
2229 gl_shader_stage_name(s
->stage
),
2231 nir_print_shader(s
, stderr
);
2232 fprintf(stderr
, "\n");
2239 copy_uniform_state_to_shader(struct vc4_compiled_shader
*shader
,
2240 struct vc4_compile
*c
)
2242 int count
= c
->num_uniforms
;
2243 struct vc4_shader_uniform_info
*uinfo
= &shader
->uniforms
;
2245 uinfo
->count
= count
;
2246 uinfo
->data
= ralloc_array(shader
, uint32_t, count
);
2247 memcpy(uinfo
->data
, c
->uniform_data
,
2248 count
* sizeof(*uinfo
->data
));
2249 uinfo
->contents
= ralloc_array(shader
, enum quniform_contents
, count
);
2250 memcpy(uinfo
->contents
, c
->uniform_contents
,
2251 count
* sizeof(*uinfo
->contents
));
2252 uinfo
->num_texture_samples
= c
->num_texture_samples
;
2254 vc4_set_shader_uniform_dirty_flags(shader
);
2258 vc4_setup_compiled_fs_inputs(struct vc4_context
*vc4
, struct vc4_compile
*c
,
2259 struct vc4_compiled_shader
*shader
)
2261 struct vc4_fs_inputs inputs
;
2263 memset(&inputs
, 0, sizeof(inputs
));
2264 inputs
.input_slots
= ralloc_array(shader
,
2265 struct vc4_varying_slot
,
2266 c
->num_input_slots
);
2268 bool input_live
[c
->num_input_slots
];
2270 memset(input_live
, 0, sizeof(input_live
));
2271 qir_for_each_inst_inorder(inst
, c
) {
2272 for (int i
= 0; i
< qir_get_op_nsrc(inst
->op
); i
++) {
2273 if (inst
->src
[i
].file
== QFILE_VARY
)
2274 input_live
[inst
->src
[i
].index
] = true;
2278 for (int i
= 0; i
< c
->num_input_slots
; i
++) {
2279 struct vc4_varying_slot
*slot
= &c
->input_slots
[i
];
2284 /* Skip non-VS-output inputs. */
2285 if (slot
->slot
== (uint8_t)~0)
2288 if (slot
->slot
== VARYING_SLOT_COL0
||
2289 slot
->slot
== VARYING_SLOT_COL1
||
2290 slot
->slot
== VARYING_SLOT_BFC0
||
2291 slot
->slot
== VARYING_SLOT_BFC1
) {
2292 shader
->color_inputs
|= (1 << inputs
.num_inputs
);
2295 inputs
.input_slots
[inputs
.num_inputs
] = *slot
;
2296 inputs
.num_inputs
++;
2298 shader
->num_inputs
= inputs
.num_inputs
;
2300 /* Add our set of inputs to the set of all inputs seen. This way, we
2301 * can have a single pointer that identifies an FS inputs set,
2302 * allowing VS to avoid recompiling when the FS is recompiled (or a
2303 * new one is bound using separate shader objects) but the inputs
2306 struct set_entry
*entry
= _mesa_set_search(vc4
->fs_inputs_set
, &inputs
);
2308 shader
->fs_inputs
= entry
->key
;
2309 ralloc_free(inputs
.input_slots
);
2311 struct vc4_fs_inputs
*alloc_inputs
;
2313 alloc_inputs
= rzalloc(vc4
->fs_inputs_set
, struct vc4_fs_inputs
);
2314 memcpy(alloc_inputs
, &inputs
, sizeof(inputs
));
2315 ralloc_steal(alloc_inputs
, inputs
.input_slots
);
2316 _mesa_set_add(vc4
->fs_inputs_set
, alloc_inputs
);
2318 shader
->fs_inputs
= alloc_inputs
;
2322 static struct vc4_compiled_shader
*
2323 vc4_get_compiled_shader(struct vc4_context
*vc4
, enum qstage stage
,
2324 struct vc4_key
*key
)
2326 struct hash_table
*ht
;
2328 if (stage
== QSTAGE_FRAG
) {
2330 key_size
= sizeof(struct vc4_fs_key
);
2333 key_size
= sizeof(struct vc4_vs_key
);
2336 struct vc4_compiled_shader
*shader
;
2337 struct hash_entry
*entry
= _mesa_hash_table_search(ht
, key
);
2341 struct vc4_compile
*c
= vc4_shader_ntq(vc4
, stage
, key
);
2342 shader
= rzalloc(NULL
, struct vc4_compiled_shader
);
2344 shader
->program_id
= vc4
->next_compiled_program_id
++;
2345 if (stage
== QSTAGE_FRAG
) {
2346 vc4_setup_compiled_fs_inputs(vc4
, c
, shader
);
2348 /* Note: the temporary clone in c->s has been freed. */
2349 nir_shader
*orig_shader
= key
->shader_state
->base
.ir
.nir
;
2350 if (orig_shader
->info
.outputs_written
& (1 << FRAG_RESULT_DEPTH
))
2351 shader
->disable_early_z
= true;
2353 shader
->num_inputs
= c
->num_inputs
;
2355 shader
->vattr_offsets
[0] = 0;
2356 for (int i
= 0; i
< 8; i
++) {
2357 shader
->vattr_offsets
[i
+ 1] =
2358 shader
->vattr_offsets
[i
] + c
->vattr_sizes
[i
];
2360 if (c
->vattr_sizes
[i
])
2361 shader
->vattrs_live
|= (1 << i
);
2365 copy_uniform_state_to_shader(shader
, c
);
2366 shader
->bo
= vc4_bo_alloc_shader(vc4
->screen
, c
->qpu_insts
,
2367 c
->qpu_inst_count
* sizeof(uint64_t));
2369 /* Copy the compiler UBO range state to the compiled shader, dropping
2370 * out arrays that were never referenced by an indirect load.
2372 * (Note that QIR dead code elimination of an array access still
2373 * leaves that array alive, though)
2375 if (c
->num_ubo_ranges
) {
2376 shader
->num_ubo_ranges
= c
->num_ubo_ranges
;
2377 shader
->ubo_ranges
= ralloc_array(shader
, struct vc4_ubo_range
,
2380 for (int i
= 0; i
< c
->num_uniform_ranges
; i
++) {
2381 struct vc4_compiler_ubo_range
*range
=
2386 shader
->ubo_ranges
[j
].dst_offset
= range
->dst_offset
;
2387 shader
->ubo_ranges
[j
].src_offset
= range
->src_offset
;
2388 shader
->ubo_ranges
[j
].size
= range
->size
;
2389 shader
->ubo_size
+= c
->ubo_ranges
[i
].size
;
2393 if (shader
->ubo_size
) {
2394 if (vc4_debug
& VC4_DEBUG_SHADERDB
) {
2395 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %d UBO uniforms\n",
2396 qir_get_stage_name(c
->stage
),
2397 c
->program_id
, c
->variant_id
,
2398 shader
->ubo_size
/ 4);
2402 qir_compile_destroy(c
);
2404 struct vc4_key
*dup_key
;
2405 dup_key
= ralloc_size(shader
, key_size
);
2406 memcpy(dup_key
, key
, key_size
);
2407 _mesa_hash_table_insert(ht
, dup_key
, shader
);
2413 vc4_setup_shared_key(struct vc4_context
*vc4
, struct vc4_key
*key
,
2414 struct vc4_texture_stateobj
*texstate
)
2416 for (int i
= 0; i
< texstate
->num_textures
; i
++) {
2417 struct pipe_sampler_view
*sampler
= texstate
->textures
[i
];
2418 struct vc4_sampler_view
*vc4_sampler
= vc4_sampler_view(sampler
);
2419 struct pipe_sampler_state
*sampler_state
=
2420 texstate
->samplers
[i
];
2425 key
->tex
[i
].format
= sampler
->format
;
2426 key
->tex
[i
].swizzle
[0] = sampler
->swizzle_r
;
2427 key
->tex
[i
].swizzle
[1] = sampler
->swizzle_g
;
2428 key
->tex
[i
].swizzle
[2] = sampler
->swizzle_b
;
2429 key
->tex
[i
].swizzle
[3] = sampler
->swizzle_a
;
2431 if (sampler
->texture
->nr_samples
> 1) {
2432 key
->tex
[i
].msaa_width
= sampler
->texture
->width0
;
2433 key
->tex
[i
].msaa_height
= sampler
->texture
->height0
;
2434 } else if (sampler
){
2435 key
->tex
[i
].compare_mode
= sampler_state
->compare_mode
;
2436 key
->tex
[i
].compare_func
= sampler_state
->compare_func
;
2437 key
->tex
[i
].wrap_s
= sampler_state
->wrap_s
;
2438 key
->tex
[i
].wrap_t
= sampler_state
->wrap_t
;
2439 key
->tex
[i
].force_first_level
=
2440 vc4_sampler
->force_first_level
;
2444 key
->ucp_enables
= vc4
->rasterizer
->base
.clip_plane_enable
;
2448 vc4_update_compiled_fs(struct vc4_context
*vc4
, uint8_t prim_mode
)
2450 struct vc4_fs_key local_key
;
2451 struct vc4_fs_key
*key
= &local_key
;
2453 if (!(vc4
->dirty
& (VC4_DIRTY_PRIM_MODE
|
2455 VC4_DIRTY_FRAMEBUFFER
|
2457 VC4_DIRTY_RASTERIZER
|
2458 VC4_DIRTY_SAMPLE_MASK
|
2460 VC4_DIRTY_UNCOMPILED_FS
))) {
2464 memset(key
, 0, sizeof(*key
));
2465 vc4_setup_shared_key(vc4
, &key
->base
, &vc4
->fragtex
);
2466 key
->base
.shader_state
= vc4
->prog
.bind_fs
;
2467 key
->is_points
= (prim_mode
== PIPE_PRIM_POINTS
);
2468 key
->is_lines
= (prim_mode
>= PIPE_PRIM_LINES
&&
2469 prim_mode
<= PIPE_PRIM_LINE_STRIP
);
2470 key
->blend
= vc4
->blend
->rt
[0];
2471 if (vc4
->blend
->logicop_enable
) {
2472 key
->logicop_func
= vc4
->blend
->logicop_func
;
2474 key
->logicop_func
= PIPE_LOGICOP_COPY
;
2477 key
->msaa
= vc4
->rasterizer
->base
.multisample
;
2478 key
->sample_coverage
= (vc4
->rasterizer
->base
.multisample
&&
2479 vc4
->sample_mask
!= (1 << VC4_MAX_SAMPLES
) - 1);
2480 key
->sample_alpha_to_coverage
= vc4
->blend
->alpha_to_coverage
;
2481 key
->sample_alpha_to_one
= vc4
->blend
->alpha_to_one
;
2484 if (vc4
->framebuffer
.cbufs
[0])
2485 key
->color_format
= vc4
->framebuffer
.cbufs
[0]->format
;
2487 key
->stencil_enabled
= vc4
->zsa
->stencil_uniforms
[0] != 0;
2488 key
->stencil_twoside
= vc4
->zsa
->stencil_uniforms
[1] != 0;
2489 key
->stencil_full_writemasks
= vc4
->zsa
->stencil_uniforms
[2] != 0;
2490 key
->depth_enabled
= (vc4
->zsa
->base
.depth
.enabled
||
2491 key
->stencil_enabled
);
2492 if (vc4
->zsa
->base
.alpha
.enabled
) {
2493 key
->alpha_test
= true;
2494 key
->alpha_test_func
= vc4
->zsa
->base
.alpha
.func
;
2497 if (key
->is_points
) {
2498 key
->point_sprite_mask
=
2499 vc4
->rasterizer
->base
.sprite_coord_enable
;
2500 key
->point_coord_upper_left
=
2501 (vc4
->rasterizer
->base
.sprite_coord_mode
==
2502 PIPE_SPRITE_COORD_UPPER_LEFT
);
2505 key
->light_twoside
= vc4
->rasterizer
->base
.light_twoside
;
2507 struct vc4_compiled_shader
*old_fs
= vc4
->prog
.fs
;
2508 vc4
->prog
.fs
= vc4_get_compiled_shader(vc4
, QSTAGE_FRAG
, &key
->base
);
2509 if (vc4
->prog
.fs
== old_fs
)
2512 vc4
->dirty
|= VC4_DIRTY_COMPILED_FS
;
2514 if (vc4
->rasterizer
->base
.flatshade
&&
2515 old_fs
&& vc4
->prog
.fs
->color_inputs
!= old_fs
->color_inputs
) {
2516 vc4
->dirty
|= VC4_DIRTY_FLAT_SHADE_FLAGS
;
2519 if (old_fs
&& vc4
->prog
.fs
->fs_inputs
!= old_fs
->fs_inputs
)
2520 vc4
->dirty
|= VC4_DIRTY_FS_INPUTS
;
2524 vc4_update_compiled_vs(struct vc4_context
*vc4
, uint8_t prim_mode
)
2526 struct vc4_vs_key local_key
;
2527 struct vc4_vs_key
*key
= &local_key
;
2529 if (!(vc4
->dirty
& (VC4_DIRTY_PRIM_MODE
|
2530 VC4_DIRTY_RASTERIZER
|
2532 VC4_DIRTY_VTXSTATE
|
2533 VC4_DIRTY_UNCOMPILED_VS
|
2534 VC4_DIRTY_FS_INPUTS
))) {
2538 memset(key
, 0, sizeof(*key
));
2539 vc4_setup_shared_key(vc4
, &key
->base
, &vc4
->verttex
);
2540 key
->base
.shader_state
= vc4
->prog
.bind_vs
;
2541 key
->fs_inputs
= vc4
->prog
.fs
->fs_inputs
;
2542 key
->clamp_color
= vc4
->rasterizer
->base
.clamp_vertex_color
;
2544 for (int i
= 0; i
< ARRAY_SIZE(key
->attr_formats
); i
++)
2545 key
->attr_formats
[i
] = vc4
->vtx
->pipe
[i
].src_format
;
2547 key
->per_vertex_point_size
=
2548 (prim_mode
== PIPE_PRIM_POINTS
&&
2549 vc4
->rasterizer
->base
.point_size_per_vertex
);
2551 struct vc4_compiled_shader
*vs
=
2552 vc4_get_compiled_shader(vc4
, QSTAGE_VERT
, &key
->base
);
2553 if (vs
!= vc4
->prog
.vs
) {
2555 vc4
->dirty
|= VC4_DIRTY_COMPILED_VS
;
2558 key
->is_coord
= true;
2559 /* Coord shaders don't care what the FS inputs are. */
2560 key
->fs_inputs
= NULL
;
2561 struct vc4_compiled_shader
*cs
=
2562 vc4_get_compiled_shader(vc4
, QSTAGE_COORD
, &key
->base
);
2563 if (cs
!= vc4
->prog
.cs
) {
2565 vc4
->dirty
|= VC4_DIRTY_COMPILED_CS
;
2570 vc4_update_compiled_shaders(struct vc4_context
*vc4
, uint8_t prim_mode
)
2572 vc4_update_compiled_fs(vc4
, prim_mode
);
2573 vc4_update_compiled_vs(vc4
, prim_mode
);
2577 fs_cache_hash(const void *key
)
2579 return _mesa_hash_data(key
, sizeof(struct vc4_fs_key
));
2583 vs_cache_hash(const void *key
)
2585 return _mesa_hash_data(key
, sizeof(struct vc4_vs_key
));
2589 fs_cache_compare(const void *key1
, const void *key2
)
2591 return memcmp(key1
, key2
, sizeof(struct vc4_fs_key
)) == 0;
2595 vs_cache_compare(const void *key1
, const void *key2
)
2597 return memcmp(key1
, key2
, sizeof(struct vc4_vs_key
)) == 0;
2601 fs_inputs_hash(const void *key
)
2603 const struct vc4_fs_inputs
*inputs
= key
;
2605 return _mesa_hash_data(inputs
->input_slots
,
2606 sizeof(*inputs
->input_slots
) *
2607 inputs
->num_inputs
);
2611 fs_inputs_compare(const void *key1
, const void *key2
)
2613 const struct vc4_fs_inputs
*inputs1
= key1
;
2614 const struct vc4_fs_inputs
*inputs2
= key2
;
2616 return (inputs1
->num_inputs
== inputs2
->num_inputs
&&
2617 memcmp(inputs1
->input_slots
,
2618 inputs2
->input_slots
,
2619 sizeof(*inputs1
->input_slots
) *
2620 inputs1
->num_inputs
) == 0);
2624 delete_from_cache_if_matches(struct hash_table
*ht
,
2625 struct hash_entry
*entry
,
2626 struct vc4_uncompiled_shader
*so
)
2628 const struct vc4_key
*key
= entry
->key
;
2630 if (key
->shader_state
== so
) {
2631 struct vc4_compiled_shader
*shader
= entry
->data
;
2632 _mesa_hash_table_remove(ht
, entry
);
2633 vc4_bo_unreference(&shader
->bo
);
2634 ralloc_free(shader
);
2639 vc4_shader_state_delete(struct pipe_context
*pctx
, void *hwcso
)
2641 struct vc4_context
*vc4
= vc4_context(pctx
);
2642 struct vc4_uncompiled_shader
*so
= hwcso
;
2644 struct hash_entry
*entry
;
2645 hash_table_foreach(vc4
->fs_cache
, entry
)
2646 delete_from_cache_if_matches(vc4
->fs_cache
, entry
, so
);
2647 hash_table_foreach(vc4
->vs_cache
, entry
)
2648 delete_from_cache_if_matches(vc4
->vs_cache
, entry
, so
);
2650 ralloc_free(so
->base
.ir
.nir
);
2655 vc4_fp_state_bind(struct pipe_context
*pctx
, void *hwcso
)
2657 struct vc4_context
*vc4
= vc4_context(pctx
);
2658 vc4
->prog
.bind_fs
= hwcso
;
2659 vc4
->dirty
|= VC4_DIRTY_UNCOMPILED_FS
;
2663 vc4_vp_state_bind(struct pipe_context
*pctx
, void *hwcso
)
2665 struct vc4_context
*vc4
= vc4_context(pctx
);
2666 vc4
->prog
.bind_vs
= hwcso
;
2667 vc4
->dirty
|= VC4_DIRTY_UNCOMPILED_VS
;
2671 vc4_program_init(struct pipe_context
*pctx
)
2673 struct vc4_context
*vc4
= vc4_context(pctx
);
2675 pctx
->create_vs_state
= vc4_shader_state_create
;
2676 pctx
->delete_vs_state
= vc4_shader_state_delete
;
2678 pctx
->create_fs_state
= vc4_shader_state_create
;
2679 pctx
->delete_fs_state
= vc4_shader_state_delete
;
2681 pctx
->bind_fs_state
= vc4_fp_state_bind
;
2682 pctx
->bind_vs_state
= vc4_vp_state_bind
;
2684 vc4
->fs_cache
= _mesa_hash_table_create(pctx
, fs_cache_hash
,
2686 vc4
->vs_cache
= _mesa_hash_table_create(pctx
, vs_cache_hash
,
2688 vc4
->fs_inputs_set
= _mesa_set_create(pctx
, fs_inputs_hash
,
2693 vc4_program_fini(struct pipe_context
*pctx
)
2695 struct vc4_context
*vc4
= vc4_context(pctx
);
2697 struct hash_entry
*entry
;
2698 hash_table_foreach(vc4
->fs_cache
, entry
) {
2699 struct vc4_compiled_shader
*shader
= entry
->data
;
2700 vc4_bo_unreference(&shader
->bo
);
2701 ralloc_free(shader
);
2702 _mesa_hash_table_remove(vc4
->fs_cache
, entry
);
2705 hash_table_foreach(vc4
->vs_cache
, entry
) {
2706 struct vc4_compiled_shader
*shader
= entry
->data
;
2707 vc4_bo_unreference(&shader
->bo
);
2708 ralloc_free(shader
);
2709 _mesa_hash_table_remove(vc4
->vs_cache
, entry
);