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vc4: Add support for 16-bit signed/unsigned norm/scaled vertex attrs.
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "pipe/p_state.h"
27 #include "util/u_format.h"
28 #include "util/u_hash.h"
29 #include "util/u_memory.h"
30 #include "util/u_pack_color.h"
31 #include "util/format_srgb.h"
32 #include "util/ralloc.h"
33 #include "util/hash_table.h"
34 #include "tgsi/tgsi_dump.h"
35 #include "tgsi/tgsi_info.h"
36 #include "tgsi/tgsi_lowering.h"
37
38 #include "vc4_context.h"
39 #include "vc4_qpu.h"
40 #include "vc4_qir.h"
41 #ifdef USE_VC4_SIMULATOR
42 #include "simpenrose/simpenrose.h"
43 #endif
44
45 struct vc4_key {
46 struct vc4_uncompiled_shader *shader_state;
47 struct {
48 enum pipe_format format;
49 unsigned compare_mode:1;
50 unsigned compare_func:3;
51 unsigned wrap_s:3;
52 unsigned wrap_t:3;
53 uint8_t swizzle[4];
54 } tex[VC4_MAX_TEXTURE_SAMPLERS];
55 uint8_t ucp_enables;
56 };
57
58 struct vc4_fs_key {
59 struct vc4_key base;
60 enum pipe_format color_format;
61 bool depth_enabled;
62 bool stencil_enabled;
63 bool stencil_twoside;
64 bool stencil_full_writemasks;
65 bool is_points;
66 bool is_lines;
67 bool alpha_test;
68 bool point_coord_upper_left;
69 bool light_twoside;
70 uint8_t alpha_test_func;
71 uint8_t logicop_func;
72 uint32_t point_sprite_mask;
73
74 struct pipe_rt_blend_state blend;
75 };
76
77 struct vc4_vs_key {
78 struct vc4_key base;
79
80 /**
81 * This is a proxy for the array of FS input semantics, which is
82 * larger than we would want to put in the key.
83 */
84 uint64_t compiled_fs_id;
85
86 enum pipe_format attr_formats[8];
87 bool is_coord;
88 bool per_vertex_point_size;
89 };
90
91 static void
92 resize_qreg_array(struct vc4_compile *c,
93 struct qreg **regs,
94 uint32_t *size,
95 uint32_t decl_size)
96 {
97 if (*size >= decl_size)
98 return;
99
100 uint32_t old_size = *size;
101 *size = MAX2(*size * 2, decl_size);
102 *regs = reralloc(c, *regs, struct qreg, *size);
103 if (!*regs) {
104 fprintf(stderr, "Malloc failure\n");
105 abort();
106 }
107
108 for (uint32_t i = old_size; i < *size; i++)
109 (*regs)[i] = c->undef;
110 }
111
112 static struct qreg
113 add_uniform(struct vc4_compile *c,
114 enum quniform_contents contents,
115 uint32_t data)
116 {
117 for (int i = 0; i < c->num_uniforms; i++) {
118 if (c->uniform_contents[i] == contents &&
119 c->uniform_data[i] == data) {
120 return (struct qreg) { QFILE_UNIF, i };
121 }
122 }
123
124 uint32_t uniform = c->num_uniforms++;
125 struct qreg u = { QFILE_UNIF, uniform };
126
127 if (uniform >= c->uniform_array_size) {
128 c->uniform_array_size = MAX2(MAX2(16, uniform + 1),
129 c->uniform_array_size * 2);
130
131 c->uniform_data = reralloc(c, c->uniform_data,
132 uint32_t,
133 c->uniform_array_size);
134 c->uniform_contents = reralloc(c, c->uniform_contents,
135 enum quniform_contents,
136 c->uniform_array_size);
137 }
138
139 c->uniform_contents[uniform] = contents;
140 c->uniform_data[uniform] = data;
141
142 return u;
143 }
144
145 static struct qreg
146 get_temp_for_uniform(struct vc4_compile *c, enum quniform_contents contents,
147 uint32_t data)
148 {
149 struct qreg u = add_uniform(c, contents, data);
150 struct qreg t = qir_MOV(c, u);
151 return t;
152 }
153
154 static struct qreg
155 qir_uniform_ui(struct vc4_compile *c, uint32_t ui)
156 {
157 return get_temp_for_uniform(c, QUNIFORM_CONSTANT, ui);
158 }
159
160 static struct qreg
161 qir_uniform_f(struct vc4_compile *c, float f)
162 {
163 return qir_uniform_ui(c, fui(f));
164 }
165
166 static struct qreg
167 indirect_uniform_load(struct vc4_compile *c,
168 struct tgsi_full_src_register *src, int swiz)
169 {
170 struct tgsi_ind_register *indirect = &src->Indirect;
171 struct vc4_compiler_ubo_range *range = &c->ubo_ranges[indirect->ArrayID];
172 if (!range->used) {
173 range->used = true;
174 range->dst_offset = c->next_ubo_dst_offset;
175 c->next_ubo_dst_offset += range->size;
176 c->num_ubo_ranges++;
177 };
178
179 assert(src->Register.Indirect);
180 assert(indirect->File == TGSI_FILE_ADDRESS);
181
182 struct qreg addr_val = c->addr[indirect->Swizzle];
183 struct qreg indirect_offset =
184 qir_ADD(c, addr_val, qir_uniform_ui(c,
185 range->dst_offset +
186 (src->Register.Index * 16)+
187 swiz * 4));
188 indirect_offset = qir_MIN(c, indirect_offset, qir_uniform_ui(c, (range->dst_offset +
189 range->size - 4)));
190
191 qir_TEX_DIRECT(c, indirect_offset, add_uniform(c, QUNIFORM_UBO_ADDR, 0));
192 struct qreg r4 = qir_TEX_RESULT(c);
193 c->num_texture_samples++;
194 return qir_MOV(c, r4);
195 }
196
197 static struct qreg
198 get_src(struct vc4_compile *c, unsigned tgsi_op,
199 struct tgsi_full_src_register *full_src, int i)
200 {
201 struct tgsi_src_register *src = &full_src->Register;
202 struct qreg r = c->undef;
203
204 uint32_t s = i;
205 switch (i) {
206 case TGSI_SWIZZLE_X:
207 s = src->SwizzleX;
208 break;
209 case TGSI_SWIZZLE_Y:
210 s = src->SwizzleY;
211 break;
212 case TGSI_SWIZZLE_Z:
213 s = src->SwizzleZ;
214 break;
215 case TGSI_SWIZZLE_W:
216 s = src->SwizzleW;
217 break;
218 default:
219 abort();
220 }
221
222 switch (src->File) {
223 case TGSI_FILE_NULL:
224 return r;
225 case TGSI_FILE_TEMPORARY:
226 r = c->temps[src->Index * 4 + s];
227 break;
228 case TGSI_FILE_IMMEDIATE:
229 r = c->consts[src->Index * 4 + s];
230 break;
231 case TGSI_FILE_CONSTANT:
232 if (src->Indirect) {
233 r = indirect_uniform_load(c, full_src, s);
234 } else {
235 r = get_temp_for_uniform(c, QUNIFORM_UNIFORM,
236 src->Index * 4 + s);
237 }
238 break;
239 case TGSI_FILE_INPUT:
240 r = c->inputs[src->Index * 4 + s];
241 break;
242 case TGSI_FILE_SAMPLER:
243 case TGSI_FILE_SAMPLER_VIEW:
244 r = c->undef;
245 break;
246 default:
247 fprintf(stderr, "unknown src file %d\n", src->File);
248 abort();
249 }
250
251 if (src->Absolute)
252 r = qir_FMAXABS(c, r, r);
253
254 if (src->Negate) {
255 switch (tgsi_opcode_infer_src_type(tgsi_op)) {
256 case TGSI_TYPE_SIGNED:
257 case TGSI_TYPE_UNSIGNED:
258 r = qir_SUB(c, qir_uniform_ui(c, 0), r);
259 break;
260 default:
261 r = qir_FSUB(c, qir_uniform_f(c, 0.0), r);
262 break;
263 }
264 }
265
266 return r;
267 };
268
269
270 static void
271 update_dst(struct vc4_compile *c, struct tgsi_full_instruction *tgsi_inst,
272 int i, struct qreg val)
273 {
274 struct tgsi_dst_register *tgsi_dst = &tgsi_inst->Dst[0].Register;
275
276 assert(!tgsi_dst->Indirect);
277
278 switch (tgsi_dst->File) {
279 case TGSI_FILE_TEMPORARY:
280 c->temps[tgsi_dst->Index * 4 + i] = val;
281 break;
282 case TGSI_FILE_OUTPUT:
283 c->outputs[tgsi_dst->Index * 4 + i] = val;
284 c->num_outputs = MAX2(c->num_outputs,
285 tgsi_dst->Index * 4 + i + 1);
286 break;
287 case TGSI_FILE_ADDRESS:
288 assert(tgsi_dst->Index == 0);
289 c->addr[i] = val;
290 break;
291 default:
292 fprintf(stderr, "unknown dst file %d\n", tgsi_dst->File);
293 abort();
294 }
295 };
296
297 static struct qreg
298 get_swizzled_channel(struct vc4_compile *c,
299 struct qreg *srcs, int swiz)
300 {
301 switch (swiz) {
302 default:
303 case UTIL_FORMAT_SWIZZLE_NONE:
304 fprintf(stderr, "warning: unknown swizzle\n");
305 /* FALLTHROUGH */
306 case UTIL_FORMAT_SWIZZLE_0:
307 return qir_uniform_f(c, 0.0);
308 case UTIL_FORMAT_SWIZZLE_1:
309 return qir_uniform_f(c, 1.0);
310 case UTIL_FORMAT_SWIZZLE_X:
311 case UTIL_FORMAT_SWIZZLE_Y:
312 case UTIL_FORMAT_SWIZZLE_Z:
313 case UTIL_FORMAT_SWIZZLE_W:
314 return srcs[swiz];
315 }
316 }
317
318 static struct qreg
319 tgsi_to_qir_alu(struct vc4_compile *c,
320 struct tgsi_full_instruction *tgsi_inst,
321 enum qop op, struct qreg *src, int i)
322 {
323 struct qreg dst = qir_get_temp(c);
324 qir_emit(c, qir_inst4(op, dst,
325 src[0 * 4 + i],
326 src[1 * 4 + i],
327 src[2 * 4 + i],
328 c->undef));
329 return dst;
330 }
331
332 static struct qreg
333 tgsi_to_qir_scalar(struct vc4_compile *c,
334 struct tgsi_full_instruction *tgsi_inst,
335 enum qop op, struct qreg *src, int i)
336 {
337 struct qreg dst = qir_get_temp(c);
338 qir_emit(c, qir_inst(op, dst,
339 src[0 * 4 + 0],
340 c->undef));
341 return dst;
342 }
343
344 static struct qreg
345 tgsi_to_qir_rcp(struct vc4_compile *c,
346 struct tgsi_full_instruction *tgsi_inst,
347 enum qop op, struct qreg *src, int i)
348 {
349 struct qreg x = src[0 * 4 + 0];
350 struct qreg r = qir_RCP(c, x);
351
352 /* Apply a Newton-Raphson step to improve the accuracy. */
353 r = qir_FMUL(c, r, qir_FSUB(c,
354 qir_uniform_f(c, 2.0),
355 qir_FMUL(c, x, r)));
356
357 return r;
358 }
359
360 static struct qreg
361 tgsi_to_qir_rsq(struct vc4_compile *c,
362 struct tgsi_full_instruction *tgsi_inst,
363 enum qop op, struct qreg *src, int i)
364 {
365 struct qreg x = src[0 * 4 + 0];
366 struct qreg r = qir_RSQ(c, x);
367
368 /* Apply a Newton-Raphson step to improve the accuracy. */
369 r = qir_FMUL(c, r, qir_FSUB(c,
370 qir_uniform_f(c, 1.5),
371 qir_FMUL(c,
372 qir_uniform_f(c, 0.5),
373 qir_FMUL(c, x,
374 qir_FMUL(c, r, r)))));
375
376 return r;
377 }
378
379 static struct qreg
380 qir_srgb_decode(struct vc4_compile *c, struct qreg srgb)
381 {
382 struct qreg low = qir_FMUL(c, srgb, qir_uniform_f(c, 1.0 / 12.92));
383 struct qreg high = qir_POW(c,
384 qir_FMUL(c,
385 qir_FADD(c,
386 srgb,
387 qir_uniform_f(c, 0.055)),
388 qir_uniform_f(c, 1.0 / 1.055)),
389 qir_uniform_f(c, 2.4));
390
391 qir_SF(c, qir_FSUB(c, srgb, qir_uniform_f(c, 0.04045)));
392 return qir_SEL_X_Y_NS(c, low, high);
393 }
394
395 static struct qreg
396 qir_srgb_encode(struct vc4_compile *c, struct qreg linear)
397 {
398 struct qreg low = qir_FMUL(c, linear, qir_uniform_f(c, 12.92));
399 struct qreg high = qir_FSUB(c,
400 qir_FMUL(c,
401 qir_uniform_f(c, 1.055),
402 qir_POW(c,
403 linear,
404 qir_uniform_f(c, 0.41666))),
405 qir_uniform_f(c, 0.055));
406
407 qir_SF(c, qir_FSUB(c, linear, qir_uniform_f(c, 0.0031308)));
408 return qir_SEL_X_Y_NS(c, low, high);
409 }
410
411 static struct qreg
412 tgsi_to_qir_umul(struct vc4_compile *c,
413 struct tgsi_full_instruction *tgsi_inst,
414 enum qop op, struct qreg *src, int i)
415 {
416 struct qreg src0_hi = qir_SHR(c, src[0 * 4 + i],
417 qir_uniform_ui(c, 16));
418 struct qreg src0_lo = qir_AND(c, src[0 * 4 + i],
419 qir_uniform_ui(c, 0xffff));
420 struct qreg src1_hi = qir_SHR(c, src[1 * 4 + i],
421 qir_uniform_ui(c, 16));
422 struct qreg src1_lo = qir_AND(c, src[1 * 4 + i],
423 qir_uniform_ui(c, 0xffff));
424
425 struct qreg hilo = qir_MUL24(c, src0_hi, src1_lo);
426 struct qreg lohi = qir_MUL24(c, src0_lo, src1_hi);
427 struct qreg lolo = qir_MUL24(c, src0_lo, src1_lo);
428
429 return qir_ADD(c, lolo, qir_SHL(c,
430 qir_ADD(c, hilo, lohi),
431 qir_uniform_ui(c, 16)));
432 }
433
434 static struct qreg
435 tgsi_to_qir_umad(struct vc4_compile *c,
436 struct tgsi_full_instruction *tgsi_inst,
437 enum qop op, struct qreg *src, int i)
438 {
439 return qir_ADD(c, tgsi_to_qir_umul(c, NULL, 0, src, i), src[2 * 4 + i]);
440 }
441
442 static struct qreg
443 tgsi_to_qir_idiv(struct vc4_compile *c,
444 struct tgsi_full_instruction *tgsi_inst,
445 enum qop op, struct qreg *src, int i)
446 {
447 return qir_FTOI(c, qir_FMUL(c,
448 qir_ITOF(c, src[0 * 4 + i]),
449 qir_RCP(c, qir_ITOF(c, src[1 * 4 + i]))));
450 }
451
452 static struct qreg
453 tgsi_to_qir_ineg(struct vc4_compile *c,
454 struct tgsi_full_instruction *tgsi_inst,
455 enum qop op, struct qreg *src, int i)
456 {
457 return qir_SUB(c, qir_uniform_ui(c, 0), src[0 * 4 + i]);
458 }
459
460 static struct qreg
461 tgsi_to_qir_seq(struct vc4_compile *c,
462 struct tgsi_full_instruction *tgsi_inst,
463 enum qop op, struct qreg *src, int i)
464 {
465 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
466 return qir_SEL_X_0_ZS(c, qir_uniform_f(c, 1.0));
467 }
468
469 static struct qreg
470 tgsi_to_qir_sne(struct vc4_compile *c,
471 struct tgsi_full_instruction *tgsi_inst,
472 enum qop op, struct qreg *src, int i)
473 {
474 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
475 return qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0));
476 }
477
478 static struct qreg
479 tgsi_to_qir_slt(struct vc4_compile *c,
480 struct tgsi_full_instruction *tgsi_inst,
481 enum qop op, struct qreg *src, int i)
482 {
483 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
484 return qir_SEL_X_0_NS(c, qir_uniform_f(c, 1.0));
485 }
486
487 static struct qreg
488 tgsi_to_qir_sge(struct vc4_compile *c,
489 struct tgsi_full_instruction *tgsi_inst,
490 enum qop op, struct qreg *src, int i)
491 {
492 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
493 return qir_SEL_X_0_NC(c, qir_uniform_f(c, 1.0));
494 }
495
496 static struct qreg
497 tgsi_to_qir_fseq(struct vc4_compile *c,
498 struct tgsi_full_instruction *tgsi_inst,
499 enum qop op, struct qreg *src, int i)
500 {
501 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
502 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
503 }
504
505 static struct qreg
506 tgsi_to_qir_fsne(struct vc4_compile *c,
507 struct tgsi_full_instruction *tgsi_inst,
508 enum qop op, struct qreg *src, int i)
509 {
510 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
511 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
512 }
513
514 static struct qreg
515 tgsi_to_qir_fslt(struct vc4_compile *c,
516 struct tgsi_full_instruction *tgsi_inst,
517 enum qop op, struct qreg *src, int i)
518 {
519 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
520 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
521 }
522
523 static struct qreg
524 tgsi_to_qir_fsge(struct vc4_compile *c,
525 struct tgsi_full_instruction *tgsi_inst,
526 enum qop op, struct qreg *src, int i)
527 {
528 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
529 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
530 }
531
532 static struct qreg
533 tgsi_to_qir_useq(struct vc4_compile *c,
534 struct tgsi_full_instruction *tgsi_inst,
535 enum qop op, struct qreg *src, int i)
536 {
537 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
538 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
539 }
540
541 static struct qreg
542 tgsi_to_qir_usne(struct vc4_compile *c,
543 struct tgsi_full_instruction *tgsi_inst,
544 enum qop op, struct qreg *src, int i)
545 {
546 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
547 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
548 }
549
550 static struct qreg
551 tgsi_to_qir_islt(struct vc4_compile *c,
552 struct tgsi_full_instruction *tgsi_inst,
553 enum qop op, struct qreg *src, int i)
554 {
555 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
556 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
557 }
558
559 static struct qreg
560 tgsi_to_qir_isge(struct vc4_compile *c,
561 struct tgsi_full_instruction *tgsi_inst,
562 enum qop op, struct qreg *src, int i)
563 {
564 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
565 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
566 }
567
568 static struct qreg
569 tgsi_to_qir_cmp(struct vc4_compile *c,
570 struct tgsi_full_instruction *tgsi_inst,
571 enum qop op, struct qreg *src, int i)
572 {
573 qir_SF(c, src[0 * 4 + i]);
574 return qir_SEL_X_Y_NS(c,
575 src[1 * 4 + i],
576 src[2 * 4 + i]);
577 }
578
579 static struct qreg
580 tgsi_to_qir_ucmp(struct vc4_compile *c,
581 struct tgsi_full_instruction *tgsi_inst,
582 enum qop op, struct qreg *src, int i)
583 {
584 qir_SF(c, src[0 * 4 + i]);
585 return qir_SEL_X_Y_ZC(c,
586 src[1 * 4 + i],
587 src[2 * 4 + i]);
588 }
589
590 static struct qreg
591 tgsi_to_qir_mad(struct vc4_compile *c,
592 struct tgsi_full_instruction *tgsi_inst,
593 enum qop op, struct qreg *src, int i)
594 {
595 return qir_FADD(c,
596 qir_FMUL(c,
597 src[0 * 4 + i],
598 src[1 * 4 + i]),
599 src[2 * 4 + i]);
600 }
601
602 static struct qreg
603 tgsi_to_qir_lrp(struct vc4_compile *c,
604 struct tgsi_full_instruction *tgsi_inst,
605 enum qop op, struct qreg *src, int i)
606 {
607 struct qreg src0 = src[0 * 4 + i];
608 struct qreg src1 = src[1 * 4 + i];
609 struct qreg src2 = src[2 * 4 + i];
610
611 /* LRP is:
612 * src0 * src1 + (1 - src0) * src2.
613 * -> src0 * src1 + src2 - src0 * src2
614 * -> src2 + src0 * (src1 - src2)
615 */
616 return qir_FADD(c, src2, qir_FMUL(c, src0, qir_FSUB(c, src1, src2)));
617
618 }
619
620 static void
621 tgsi_to_qir_tex(struct vc4_compile *c,
622 struct tgsi_full_instruction *tgsi_inst,
623 enum qop op, struct qreg *src)
624 {
625 assert(!tgsi_inst->Instruction.Saturate);
626
627 struct qreg s = src[0 * 4 + 0];
628 struct qreg t = src[0 * 4 + 1];
629 struct qreg r = src[0 * 4 + 2];
630 uint32_t unit = tgsi_inst->Src[1].Register.Index;
631 bool is_txl = tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL;
632
633 struct qreg proj = c->undef;
634 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
635 proj = qir_RCP(c, src[0 * 4 + 3]);
636 s = qir_FMUL(c, s, proj);
637 t = qir_FMUL(c, t, proj);
638 }
639
640 struct qreg texture_u[] = {
641 add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit),
642 add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
643 add_uniform(c, QUNIFORM_CONSTANT, 0),
644 add_uniform(c, QUNIFORM_CONSTANT, 0),
645 };
646 uint32_t next_texture_u = 0;
647
648 /* There is no native support for GL texture rectangle coordinates, so
649 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
650 * 1]).
651 */
652 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_RECT ||
653 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT) {
654 s = qir_FMUL(c, s,
655 get_temp_for_uniform(c,
656 QUNIFORM_TEXRECT_SCALE_X,
657 unit));
658 t = qir_FMUL(c, t,
659 get_temp_for_uniform(c,
660 QUNIFORM_TEXRECT_SCALE_Y,
661 unit));
662 }
663
664 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
665 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
666 is_txl) {
667 texture_u[2] = add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P2,
668 unit | (is_txl << 16));
669 }
670
671 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
672 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE) {
673 struct qreg ma = qir_FMAXABS(c, qir_FMAXABS(c, s, t), r);
674 struct qreg rcp_ma = qir_RCP(c, ma);
675 s = qir_FMUL(c, s, rcp_ma);
676 t = qir_FMUL(c, t, rcp_ma);
677 r = qir_FMUL(c, r, rcp_ma);
678
679 qir_TEX_R(c, r, texture_u[next_texture_u++]);
680 } else if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
681 c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP ||
682 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
683 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
684 qir_TEX_R(c, get_temp_for_uniform(c, QUNIFORM_TEXTURE_BORDER_COLOR, unit),
685 texture_u[next_texture_u++]);
686 }
687
688 if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP) {
689 s = qir_FMIN(c, qir_FMAX(c, s, qir_uniform_f(c, 0.0)),
690 qir_uniform_f(c, 1.0));
691 }
692
693 if (c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
694 t = qir_FMIN(c, qir_FMAX(c, t, qir_uniform_f(c, 0.0)),
695 qir_uniform_f(c, 1.0));
696 }
697
698 qir_TEX_T(c, t, texture_u[next_texture_u++]);
699
700 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
701 tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL)
702 qir_TEX_B(c, src[0 * 4 + 3], texture_u[next_texture_u++]);
703
704 qir_TEX_S(c, s, texture_u[next_texture_u++]);
705
706 c->num_texture_samples++;
707 struct qreg r4 = qir_TEX_RESULT(c);
708
709 enum pipe_format format = c->key->tex[unit].format;
710
711 struct qreg unpacked[4];
712 if (util_format_is_depth_or_stencil(format)) {
713 struct qreg depthf = qir_ITOF(c, qir_SHR(c, r4,
714 qir_uniform_ui(c, 8)));
715 struct qreg normalized = qir_FMUL(c, depthf,
716 qir_uniform_f(c, 1.0f/0xffffff));
717
718 struct qreg depth_output;
719
720 struct qreg one = qir_uniform_f(c, 1.0f);
721 if (c->key->tex[unit].compare_mode) {
722 struct qreg compare = src[0 * 4 + 2];
723
724 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP)
725 compare = qir_FMUL(c, compare, proj);
726
727 switch (c->key->tex[unit].compare_func) {
728 case PIPE_FUNC_NEVER:
729 depth_output = qir_uniform_f(c, 0.0f);
730 break;
731 case PIPE_FUNC_ALWAYS:
732 depth_output = one;
733 break;
734 case PIPE_FUNC_EQUAL:
735 qir_SF(c, qir_FSUB(c, compare, normalized));
736 depth_output = qir_SEL_X_0_ZS(c, one);
737 break;
738 case PIPE_FUNC_NOTEQUAL:
739 qir_SF(c, qir_FSUB(c, compare, normalized));
740 depth_output = qir_SEL_X_0_ZC(c, one);
741 break;
742 case PIPE_FUNC_GREATER:
743 qir_SF(c, qir_FSUB(c, compare, normalized));
744 depth_output = qir_SEL_X_0_NC(c, one);
745 break;
746 case PIPE_FUNC_GEQUAL:
747 qir_SF(c, qir_FSUB(c, normalized, compare));
748 depth_output = qir_SEL_X_0_NS(c, one);
749 break;
750 case PIPE_FUNC_LESS:
751 qir_SF(c, qir_FSUB(c, compare, normalized));
752 depth_output = qir_SEL_X_0_NS(c, one);
753 break;
754 case PIPE_FUNC_LEQUAL:
755 qir_SF(c, qir_FSUB(c, normalized, compare));
756 depth_output = qir_SEL_X_0_NC(c, one);
757 break;
758 }
759 } else {
760 depth_output = normalized;
761 }
762
763 for (int i = 0; i < 4; i++)
764 unpacked[i] = depth_output;
765 } else {
766 for (int i = 0; i < 4; i++)
767 unpacked[i] = qir_R4_UNPACK(c, r4, i);
768 }
769
770 const uint8_t *format_swiz = vc4_get_format_swizzle(format);
771 struct qreg texture_output[4];
772 for (int i = 0; i < 4; i++) {
773 texture_output[i] = get_swizzled_channel(c, unpacked,
774 format_swiz[i]);
775 }
776
777 if (util_format_is_srgb(format)) {
778 for (int i = 0; i < 3; i++)
779 texture_output[i] = qir_srgb_decode(c,
780 texture_output[i]);
781 }
782
783 for (int i = 0; i < 4; i++) {
784 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
785 continue;
786
787 update_dst(c, tgsi_inst, i,
788 get_swizzled_channel(c, texture_output,
789 c->key->tex[unit].swizzle[i]));
790 }
791 }
792
793 static struct qreg
794 tgsi_to_qir_trunc(struct vc4_compile *c,
795 struct tgsi_full_instruction *tgsi_inst,
796 enum qop op, struct qreg *src, int i)
797 {
798 return qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
799 }
800
801 /**
802 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
803 * to zero).
804 */
805 static struct qreg
806 tgsi_to_qir_frc(struct vc4_compile *c,
807 struct tgsi_full_instruction *tgsi_inst,
808 enum qop op, struct qreg *src, int i)
809 {
810 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
811 struct qreg diff = qir_FSUB(c, src[0 * 4 + i], trunc);
812 qir_SF(c, diff);
813 return qir_SEL_X_Y_NS(c,
814 qir_FADD(c, diff, qir_uniform_f(c, 1.0)),
815 diff);
816 }
817
818 /**
819 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
820 * zero).
821 */
822 static struct qreg
823 tgsi_to_qir_flr(struct vc4_compile *c,
824 struct tgsi_full_instruction *tgsi_inst,
825 enum qop op, struct qreg *src, int i)
826 {
827 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
828
829 /* This will be < 0 if we truncated and the truncation was of a value
830 * that was < 0 in the first place.
831 */
832 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], trunc));
833
834 return qir_SEL_X_Y_NS(c,
835 qir_FSUB(c, trunc, qir_uniform_f(c, 1.0)),
836 trunc);
837 }
838
839 /**
840 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
841 * zero).
842 */
843 static struct qreg
844 tgsi_to_qir_ceil(struct vc4_compile *c,
845 struct tgsi_full_instruction *tgsi_inst,
846 enum qop op, struct qreg *src, int i)
847 {
848 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
849
850 /* This will be < 0 if we truncated and the truncation was of a value
851 * that was > 0 in the first place.
852 */
853 qir_SF(c, qir_FSUB(c, trunc, src[0 * 4 + i]));
854
855 return qir_SEL_X_Y_NS(c,
856 qir_FADD(c, trunc, qir_uniform_f(c, 1.0)),
857 trunc);
858 }
859
860 static struct qreg
861 tgsi_to_qir_abs(struct vc4_compile *c,
862 struct tgsi_full_instruction *tgsi_inst,
863 enum qop op, struct qreg *src, int i)
864 {
865 struct qreg arg = src[0 * 4 + i];
866 return qir_FMAXABS(c, arg, arg);
867 }
868
869 /* Note that this instruction replicates its result from the x channel */
870 static struct qreg
871 tgsi_to_qir_sin(struct vc4_compile *c,
872 struct tgsi_full_instruction *tgsi_inst,
873 enum qop op, struct qreg *src, int i)
874 {
875 float coeff[] = {
876 -2.0 * M_PI,
877 pow(2.0 * M_PI, 3) / (3 * 2 * 1),
878 -pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
879 pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
880 -pow(2.0 * M_PI, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
881 };
882
883 struct qreg scaled_x =
884 qir_FMUL(c,
885 src[0 * 4 + 0],
886 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
887
888 struct qreg x = qir_FADD(c,
889 tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0),
890 qir_uniform_f(c, -0.5));
891 struct qreg x2 = qir_FMUL(c, x, x);
892 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
893 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
894 x = qir_FMUL(c, x, x2);
895 sum = qir_FADD(c,
896 sum,
897 qir_FMUL(c,
898 x,
899 qir_uniform_f(c, coeff[i])));
900 }
901 return sum;
902 }
903
904 /* Note that this instruction replicates its result from the x channel */
905 static struct qreg
906 tgsi_to_qir_cos(struct vc4_compile *c,
907 struct tgsi_full_instruction *tgsi_inst,
908 enum qop op, struct qreg *src, int i)
909 {
910 float coeff[] = {
911 -1.0f,
912 pow(2.0 * M_PI, 2) / (2 * 1),
913 -pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
914 pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
915 -pow(2.0 * M_PI, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
916 pow(2.0 * M_PI, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
917 };
918
919 struct qreg scaled_x =
920 qir_FMUL(c, src[0 * 4 + 0],
921 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
922 struct qreg x_frac = qir_FADD(c,
923 tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0),
924 qir_uniform_f(c, -0.5));
925
926 struct qreg sum = qir_uniform_f(c, coeff[0]);
927 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
928 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
929 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
930 if (i != 1)
931 x = qir_FMUL(c, x, x2);
932
933 struct qreg mul = qir_FMUL(c,
934 x,
935 qir_uniform_f(c, coeff[i]));
936 if (i == 0)
937 sum = mul;
938 else
939 sum = qir_FADD(c, sum, mul);
940 }
941 return sum;
942 }
943
944 static struct qreg
945 tgsi_to_qir_clamp(struct vc4_compile *c,
946 struct tgsi_full_instruction *tgsi_inst,
947 enum qop op, struct qreg *src, int i)
948 {
949 return qir_FMAX(c, qir_FMIN(c,
950 src[0 * 4 + i],
951 src[2 * 4 + i]),
952 src[1 * 4 + i]);
953 }
954
955 static struct qreg
956 tgsi_to_qir_ssg(struct vc4_compile *c,
957 struct tgsi_full_instruction *tgsi_inst,
958 enum qop op, struct qreg *src, int i)
959 {
960 qir_SF(c, src[0 * 4 + i]);
961 return qir_SEL_X_Y_NC(c,
962 qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0)),
963 qir_uniform_f(c, -1.0));
964 }
965
966 /* Compare to tgsi_to_qir_flr() for the floor logic. */
967 static struct qreg
968 tgsi_to_qir_arl(struct vc4_compile *c,
969 struct tgsi_full_instruction *tgsi_inst,
970 enum qop op, struct qreg *src, int i)
971 {
972 struct qreg trunc = qir_FTOI(c, src[0 * 4 + i]);
973 struct qreg scaled = qir_SHL(c, trunc, qir_uniform_ui(c, 4));
974
975 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], qir_ITOF(c, trunc)));
976
977 return qir_SEL_X_Y_NS(c, qir_SUB(c, scaled, qir_uniform_ui(c, 4)),
978 scaled);
979 }
980
981 static struct qreg
982 tgsi_to_qir_uarl(struct vc4_compile *c,
983 struct tgsi_full_instruction *tgsi_inst,
984 enum qop op, struct qreg *src, int i)
985 {
986 return qir_SHL(c, src[0 * 4 + i], qir_uniform_ui(c, 4));
987 }
988
989 static struct qreg
990 get_channel_from_vpm(struct vc4_compile *c,
991 struct qreg *vpm_reads,
992 uint8_t swiz,
993 const struct util_format_description *desc)
994 {
995 const struct util_format_channel_description *chan =
996 &desc->channel[swiz];
997 struct qreg temp;
998
999 if (swiz > UTIL_FORMAT_SWIZZLE_W)
1000 return get_swizzled_channel(c, vpm_reads, swiz);
1001 else if (chan->size == 32 &&
1002 chan->type == UTIL_FORMAT_TYPE_FLOAT) {
1003 return get_swizzled_channel(c, vpm_reads, swiz);
1004 } else if (chan->size == 8 &&
1005 (chan->type == UTIL_FORMAT_TYPE_UNSIGNED ||
1006 chan->type == UTIL_FORMAT_TYPE_SIGNED)) {
1007 struct qreg vpm = vpm_reads[0];
1008 if (chan->type == UTIL_FORMAT_TYPE_SIGNED) {
1009 temp = qir_XOR(c, vpm, qir_uniform_ui(c, 0x80808080));
1010 if (chan->normalized) {
1011 return qir_FSUB(c, qir_FMUL(c,
1012 qir_UNPACK_8_F(c, temp, swiz),
1013 qir_uniform_f(c, 2.0)),
1014 qir_uniform_f(c, 1.0));
1015 } else {
1016 return qir_FADD(c,
1017 qir_ITOF(c,
1018 qir_UNPACK_8_I(c, temp,
1019 swiz)),
1020 qir_uniform_f(c, -128.0));
1021 }
1022 } else {
1023 if (chan->normalized) {
1024 return qir_UNPACK_8_F(c, vpm, swiz);
1025 } else {
1026 return qir_ITOF(c, qir_UNPACK_8_I(c, vpm, swiz));
1027 }
1028 }
1029 } else if (chan->size == 16 &&
1030 (chan->type == UTIL_FORMAT_TYPE_UNSIGNED ||
1031 chan->type == UTIL_FORMAT_TYPE_SIGNED)) {
1032 struct qreg vpm = vpm_reads[swiz / 2];
1033
1034 /* Note that UNPACK_16F eats a half float, not ints, so we use
1035 * UNPACK_16_I for all of these.
1036 */
1037 if (chan->type == UTIL_FORMAT_TYPE_SIGNED) {
1038 temp = qir_ITOF(c, qir_UNPACK_16_I(c, vpm, swiz % 2));
1039 if (chan->normalized) {
1040 return qir_FMUL(c, temp,
1041 qir_uniform_f(c, 1/32768.0f));
1042 } else {
1043 return temp;
1044 }
1045 } else {
1046 /* UNPACK_16I sign-extends, so we have to emit ANDs. */
1047 temp = vpm;
1048 if (swiz == 1 || swiz == 3)
1049 temp = qir_UNPACK_16_I(c, temp, 1);
1050 temp = qir_AND(c, temp, qir_uniform_ui(c, 0xffff));
1051 temp = qir_ITOF(c, temp);
1052
1053 if (chan->normalized) {
1054 return qir_FMUL(c, temp,
1055 qir_uniform_f(c, 1 / 65535.0));
1056 } else {
1057 return temp;
1058 }
1059 }
1060 } else {
1061 return c->undef;
1062 }
1063 }
1064
1065 static void
1066 emit_vertex_input(struct vc4_compile *c, int attr)
1067 {
1068 enum pipe_format format = c->vs_key->attr_formats[attr];
1069 struct qreg vpm_reads[4];
1070
1071 /* Right now, we're setting the VPM offsets to be 16 bytes wide every
1072 * time, so we always read 4 32-bit VPM entries.
1073 */
1074 for (int i = 0; i < 4; i++) {
1075 vpm_reads[i] = qir_get_temp(c);
1076 qir_emit(c, qir_inst(QOP_VPM_READ,
1077 vpm_reads[i],
1078 c->undef,
1079 c->undef));
1080 c->num_inputs++;
1081 }
1082
1083 bool format_warned = false;
1084 const struct util_format_description *desc =
1085 util_format_description(format);
1086
1087 for (int i = 0; i < 4; i++) {
1088 uint8_t swiz = desc->swizzle[i];
1089 struct qreg result = get_channel_from_vpm(c, vpm_reads,
1090 swiz, desc);
1091
1092 if (result.file == QFILE_NULL) {
1093 if (!format_warned) {
1094 fprintf(stderr,
1095 "vtx element %d unsupported type: %s\n",
1096 attr, util_format_name(format));
1097 format_warned = true;
1098 }
1099 result = qir_uniform_f(c, 0.0);
1100 }
1101 c->inputs[attr * 4 + i] = result;
1102 }
1103 }
1104
1105 static void
1106 tgsi_to_qir_kill_if(struct vc4_compile *c, struct qreg *src, int i)
1107 {
1108 if (c->discard.file == QFILE_NULL)
1109 c->discard = qir_uniform_f(c, 0.0);
1110 qir_SF(c, src[0 * 4 + i]);
1111 c->discard = qir_SEL_X_Y_NS(c, qir_uniform_f(c, 1.0),
1112 c->discard);
1113 }
1114
1115 static void
1116 emit_fragcoord_input(struct vc4_compile *c, int attr)
1117 {
1118 c->inputs[attr * 4 + 0] = qir_FRAG_X(c);
1119 c->inputs[attr * 4 + 1] = qir_FRAG_Y(c);
1120 c->inputs[attr * 4 + 2] =
1121 qir_FMUL(c,
1122 qir_ITOF(c, qir_FRAG_Z(c)),
1123 qir_uniform_f(c, 1.0 / 0xffffff));
1124 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
1125 }
1126
1127 static void
1128 emit_point_coord_input(struct vc4_compile *c, int attr)
1129 {
1130 if (c->point_x.file == QFILE_NULL) {
1131 c->point_x = qir_uniform_f(c, 0.0);
1132 c->point_y = qir_uniform_f(c, 0.0);
1133 }
1134
1135 c->inputs[attr * 4 + 0] = c->point_x;
1136 if (c->fs_key->point_coord_upper_left) {
1137 c->inputs[attr * 4 + 1] = qir_FSUB(c,
1138 qir_uniform_f(c, 1.0),
1139 c->point_y);
1140 } else {
1141 c->inputs[attr * 4 + 1] = c->point_y;
1142 }
1143 c->inputs[attr * 4 + 2] = qir_uniform_f(c, 0.0);
1144 c->inputs[attr * 4 + 3] = qir_uniform_f(c, 1.0);
1145 }
1146
1147 static struct qreg
1148 emit_fragment_varying(struct vc4_compile *c, uint8_t semantic,
1149 uint8_t index, uint8_t swizzle)
1150 {
1151 uint32_t i = c->num_input_semantics++;
1152 struct qreg vary = {
1153 QFILE_VARY,
1154 i
1155 };
1156
1157 if (c->num_input_semantics >= c->input_semantics_array_size) {
1158 c->input_semantics_array_size =
1159 MAX2(4, c->input_semantics_array_size * 2);
1160
1161 c->input_semantics = reralloc(c, c->input_semantics,
1162 struct vc4_varying_semantic,
1163 c->input_semantics_array_size);
1164 }
1165
1166 c->input_semantics[i].semantic = semantic;
1167 c->input_semantics[i].index = index;
1168 c->input_semantics[i].swizzle = swizzle;
1169
1170 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
1171 }
1172
1173 static void
1174 emit_fragment_input(struct vc4_compile *c, int attr,
1175 struct tgsi_full_declaration *decl)
1176 {
1177 for (int i = 0; i < 4; i++) {
1178 c->inputs[attr * 4 + i] =
1179 emit_fragment_varying(c,
1180 decl->Semantic.Name,
1181 decl->Semantic.Index,
1182 i);
1183 c->num_inputs++;
1184 }
1185 }
1186
1187 static void
1188 emit_face_input(struct vc4_compile *c, int attr)
1189 {
1190 c->inputs[attr * 4 + 0] = qir_FSUB(c,
1191 qir_uniform_f(c, 1.0),
1192 qir_FMUL(c,
1193 qir_ITOF(c, qir_FRAG_REV_FLAG(c)),
1194 qir_uniform_f(c, 2.0)));
1195 c->inputs[attr * 4 + 1] = qir_uniform_f(c, 0.0);
1196 c->inputs[attr * 4 + 2] = qir_uniform_f(c, 0.0);
1197 c->inputs[attr * 4 + 3] = qir_uniform_f(c, 1.0);
1198 }
1199
1200 static void
1201 add_output(struct vc4_compile *c,
1202 uint32_t decl_offset,
1203 uint8_t semantic_name,
1204 uint8_t semantic_index,
1205 uint8_t semantic_swizzle)
1206 {
1207 uint32_t old_array_size = c->outputs_array_size;
1208 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
1209 decl_offset + 1);
1210
1211 if (old_array_size != c->outputs_array_size) {
1212 c->output_semantics = reralloc(c,
1213 c->output_semantics,
1214 struct vc4_varying_semantic,
1215 c->outputs_array_size);
1216 }
1217
1218 c->output_semantics[decl_offset].semantic = semantic_name;
1219 c->output_semantics[decl_offset].index = semantic_index;
1220 c->output_semantics[decl_offset].swizzle = semantic_swizzle;
1221 }
1222
1223 static void
1224 add_array_info(struct vc4_compile *c, uint32_t array_id,
1225 uint32_t start, uint32_t size)
1226 {
1227 if (array_id >= c->ubo_ranges_array_size) {
1228 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
1229 array_id + 1);
1230 c->ubo_ranges = reralloc(c, c->ubo_ranges,
1231 struct vc4_compiler_ubo_range,
1232 c->ubo_ranges_array_size);
1233 }
1234
1235 c->ubo_ranges[array_id].dst_offset = 0;
1236 c->ubo_ranges[array_id].src_offset = start;
1237 c->ubo_ranges[array_id].size = size;
1238 c->ubo_ranges[array_id].used = false;
1239 }
1240
1241 static void
1242 emit_tgsi_declaration(struct vc4_compile *c,
1243 struct tgsi_full_declaration *decl)
1244 {
1245 switch (decl->Declaration.File) {
1246 case TGSI_FILE_TEMPORARY: {
1247 uint32_t old_size = c->temps_array_size;
1248 resize_qreg_array(c, &c->temps, &c->temps_array_size,
1249 (decl->Range.Last + 1) * 4);
1250
1251 for (int i = old_size; i < c->temps_array_size; i++)
1252 c->temps[i] = qir_uniform_ui(c, 0);
1253 break;
1254 }
1255
1256 case TGSI_FILE_INPUT:
1257 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1258 (decl->Range.Last + 1) * 4);
1259
1260 for (int i = decl->Range.First;
1261 i <= decl->Range.Last;
1262 i++) {
1263 if (c->stage == QSTAGE_FRAG) {
1264 if (decl->Semantic.Name ==
1265 TGSI_SEMANTIC_POSITION) {
1266 emit_fragcoord_input(c, i);
1267 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
1268 emit_face_input(c, i);
1269 } else if (decl->Semantic.Name == TGSI_SEMANTIC_GENERIC &&
1270 (c->fs_key->point_sprite_mask &
1271 (1 << decl->Semantic.Index))) {
1272 emit_point_coord_input(c, i);
1273 } else {
1274 emit_fragment_input(c, i, decl);
1275 }
1276 } else {
1277 emit_vertex_input(c, i);
1278 }
1279 }
1280 break;
1281
1282 case TGSI_FILE_OUTPUT: {
1283 for (int i = 0; i < 4; i++) {
1284 add_output(c,
1285 decl->Range.First * 4 + i,
1286 decl->Semantic.Name,
1287 decl->Semantic.Index,
1288 i);
1289 }
1290
1291 switch (decl->Semantic.Name) {
1292 case TGSI_SEMANTIC_POSITION:
1293 c->output_position_index = decl->Range.First * 4;
1294 break;
1295 case TGSI_SEMANTIC_CLIPVERTEX:
1296 c->output_clipvertex_index = decl->Range.First * 4;
1297 break;
1298 case TGSI_SEMANTIC_COLOR:
1299 c->output_color_index = decl->Range.First * 4;
1300 break;
1301 case TGSI_SEMANTIC_PSIZE:
1302 c->output_point_size_index = decl->Range.First * 4;
1303 break;
1304 }
1305
1306 break;
1307
1308 case TGSI_FILE_CONSTANT:
1309 add_array_info(c,
1310 decl->Array.ArrayID,
1311 decl->Range.First * 16,
1312 (decl->Range.Last -
1313 decl->Range.First + 1) * 16);
1314 break;
1315 }
1316 }
1317 }
1318
1319 static void
1320 emit_tgsi_instruction(struct vc4_compile *c,
1321 struct tgsi_full_instruction *tgsi_inst)
1322 {
1323 static const struct {
1324 enum qop op;
1325 struct qreg (*func)(struct vc4_compile *c,
1326 struct tgsi_full_instruction *tgsi_inst,
1327 enum qop op,
1328 struct qreg *src, int i);
1329 } op_trans[] = {
1330 [TGSI_OPCODE_MOV] = { QOP_MOV, tgsi_to_qir_alu },
1331 [TGSI_OPCODE_ABS] = { 0, tgsi_to_qir_abs },
1332 [TGSI_OPCODE_MUL] = { QOP_FMUL, tgsi_to_qir_alu },
1333 [TGSI_OPCODE_ADD] = { QOP_FADD, tgsi_to_qir_alu },
1334 [TGSI_OPCODE_SUB] = { QOP_FSUB, tgsi_to_qir_alu },
1335 [TGSI_OPCODE_MIN] = { QOP_FMIN, tgsi_to_qir_alu },
1336 [TGSI_OPCODE_MAX] = { QOP_FMAX, tgsi_to_qir_alu },
1337 [TGSI_OPCODE_F2I] = { QOP_FTOI, tgsi_to_qir_alu },
1338 [TGSI_OPCODE_I2F] = { QOP_ITOF, tgsi_to_qir_alu },
1339 [TGSI_OPCODE_UADD] = { QOP_ADD, tgsi_to_qir_alu },
1340 [TGSI_OPCODE_USHR] = { QOP_SHR, tgsi_to_qir_alu },
1341 [TGSI_OPCODE_ISHR] = { QOP_ASR, tgsi_to_qir_alu },
1342 [TGSI_OPCODE_SHL] = { QOP_SHL, tgsi_to_qir_alu },
1343 [TGSI_OPCODE_IMIN] = { QOP_MIN, tgsi_to_qir_alu },
1344 [TGSI_OPCODE_IMAX] = { QOP_MAX, tgsi_to_qir_alu },
1345 [TGSI_OPCODE_AND] = { QOP_AND, tgsi_to_qir_alu },
1346 [TGSI_OPCODE_OR] = { QOP_OR, tgsi_to_qir_alu },
1347 [TGSI_OPCODE_XOR] = { QOP_XOR, tgsi_to_qir_alu },
1348 [TGSI_OPCODE_NOT] = { QOP_NOT, tgsi_to_qir_alu },
1349
1350 [TGSI_OPCODE_UMUL] = { 0, tgsi_to_qir_umul },
1351 [TGSI_OPCODE_UMAD] = { 0, tgsi_to_qir_umad },
1352 [TGSI_OPCODE_IDIV] = { 0, tgsi_to_qir_idiv },
1353 [TGSI_OPCODE_INEG] = { 0, tgsi_to_qir_ineg },
1354
1355 [TGSI_OPCODE_SEQ] = { 0, tgsi_to_qir_seq },
1356 [TGSI_OPCODE_SNE] = { 0, tgsi_to_qir_sne },
1357 [TGSI_OPCODE_SGE] = { 0, tgsi_to_qir_sge },
1358 [TGSI_OPCODE_SLT] = { 0, tgsi_to_qir_slt },
1359 [TGSI_OPCODE_FSEQ] = { 0, tgsi_to_qir_fseq },
1360 [TGSI_OPCODE_FSNE] = { 0, tgsi_to_qir_fsne },
1361 [TGSI_OPCODE_FSGE] = { 0, tgsi_to_qir_fsge },
1362 [TGSI_OPCODE_FSLT] = { 0, tgsi_to_qir_fslt },
1363 [TGSI_OPCODE_USEQ] = { 0, tgsi_to_qir_useq },
1364 [TGSI_OPCODE_USNE] = { 0, tgsi_to_qir_usne },
1365 [TGSI_OPCODE_ISGE] = { 0, tgsi_to_qir_isge },
1366 [TGSI_OPCODE_ISLT] = { 0, tgsi_to_qir_islt },
1367
1368 [TGSI_OPCODE_CMP] = { 0, tgsi_to_qir_cmp },
1369 [TGSI_OPCODE_UCMP] = { 0, tgsi_to_qir_ucmp },
1370 [TGSI_OPCODE_MAD] = { 0, tgsi_to_qir_mad },
1371 [TGSI_OPCODE_RCP] = { QOP_RCP, tgsi_to_qir_rcp },
1372 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_rsq },
1373 [TGSI_OPCODE_EX2] = { QOP_EXP2, tgsi_to_qir_scalar },
1374 [TGSI_OPCODE_LG2] = { QOP_LOG2, tgsi_to_qir_scalar },
1375 [TGSI_OPCODE_LRP] = { 0, tgsi_to_qir_lrp },
1376 [TGSI_OPCODE_TRUNC] = { 0, tgsi_to_qir_trunc },
1377 [TGSI_OPCODE_CEIL] = { 0, tgsi_to_qir_ceil },
1378 [TGSI_OPCODE_FRC] = { 0, tgsi_to_qir_frc },
1379 [TGSI_OPCODE_FLR] = { 0, tgsi_to_qir_flr },
1380 [TGSI_OPCODE_SIN] = { 0, tgsi_to_qir_sin },
1381 [TGSI_OPCODE_COS] = { 0, tgsi_to_qir_cos },
1382 [TGSI_OPCODE_CLAMP] = { 0, tgsi_to_qir_clamp },
1383 [TGSI_OPCODE_SSG] = { 0, tgsi_to_qir_ssg },
1384 [TGSI_OPCODE_ARL] = { 0, tgsi_to_qir_arl },
1385 [TGSI_OPCODE_UARL] = { 0, tgsi_to_qir_uarl },
1386 };
1387 static int asdf = 0;
1388 uint32_t tgsi_op = tgsi_inst->Instruction.Opcode;
1389
1390 if (tgsi_op == TGSI_OPCODE_END)
1391 return;
1392
1393 struct qreg src_regs[12];
1394 for (int s = 0; s < 3; s++) {
1395 for (int i = 0; i < 4; i++) {
1396 src_regs[4 * s + i] =
1397 get_src(c, tgsi_inst->Instruction.Opcode,
1398 &tgsi_inst->Src[s], i);
1399 }
1400 }
1401
1402 switch (tgsi_op) {
1403 case TGSI_OPCODE_TEX:
1404 case TGSI_OPCODE_TXP:
1405 case TGSI_OPCODE_TXB:
1406 case TGSI_OPCODE_TXL:
1407 tgsi_to_qir_tex(c, tgsi_inst,
1408 op_trans[tgsi_op].op, src_regs);
1409 return;
1410 case TGSI_OPCODE_KILL:
1411 c->discard = qir_uniform_f(c, 1.0);
1412 return;
1413 case TGSI_OPCODE_KILL_IF:
1414 for (int i = 0; i < 4; i++)
1415 tgsi_to_qir_kill_if(c, src_regs, i);
1416 return;
1417 default:
1418 break;
1419 }
1420
1421 if (tgsi_op > ARRAY_SIZE(op_trans) || !(op_trans[tgsi_op].func)) {
1422 fprintf(stderr, "unknown tgsi inst: ");
1423 tgsi_dump_instruction(tgsi_inst, asdf++);
1424 fprintf(stderr, "\n");
1425 abort();
1426 }
1427
1428 for (int i = 0; i < 4; i++) {
1429 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
1430 continue;
1431
1432 struct qreg result;
1433
1434 result = op_trans[tgsi_op].func(c, tgsi_inst,
1435 op_trans[tgsi_op].op,
1436 src_regs, i);
1437
1438 if (tgsi_inst->Instruction.Saturate) {
1439 float low = (tgsi_inst->Instruction.Saturate ==
1440 TGSI_SAT_MINUS_PLUS_ONE ? -1.0 : 0.0);
1441 result = qir_FMAX(c,
1442 qir_FMIN(c,
1443 result,
1444 qir_uniform_f(c, 1.0)),
1445 qir_uniform_f(c, low));
1446 }
1447
1448 update_dst(c, tgsi_inst, i, result);
1449 }
1450 }
1451
1452 static void
1453 parse_tgsi_immediate(struct vc4_compile *c, struct tgsi_full_immediate *imm)
1454 {
1455 for (int i = 0; i < 4; i++) {
1456 unsigned n = c->num_consts++;
1457 resize_qreg_array(c, &c->consts, &c->consts_array_size, n + 1);
1458 c->consts[n] = qir_uniform_ui(c, imm->u[i].Uint);
1459 }
1460 }
1461
1462 static struct qreg
1463 vc4_blend_channel(struct vc4_compile *c,
1464 struct qreg *dst,
1465 struct qreg *src,
1466 struct qreg val,
1467 unsigned factor,
1468 int channel)
1469 {
1470 switch(factor) {
1471 case PIPE_BLENDFACTOR_ONE:
1472 return val;
1473 case PIPE_BLENDFACTOR_SRC_COLOR:
1474 return qir_FMUL(c, val, src[channel]);
1475 case PIPE_BLENDFACTOR_SRC_ALPHA:
1476 return qir_FMUL(c, val, src[3]);
1477 case PIPE_BLENDFACTOR_DST_ALPHA:
1478 return qir_FMUL(c, val, dst[3]);
1479 case PIPE_BLENDFACTOR_DST_COLOR:
1480 return qir_FMUL(c, val, dst[channel]);
1481 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
1482 if (channel != 3) {
1483 return qir_FMUL(c,
1484 val,
1485 qir_FMIN(c,
1486 src[3],
1487 qir_FSUB(c,
1488 qir_uniform_f(c, 1.0),
1489 dst[3])));
1490 } else {
1491 return val;
1492 }
1493 case PIPE_BLENDFACTOR_CONST_COLOR:
1494 return qir_FMUL(c, val,
1495 get_temp_for_uniform(c,
1496 QUNIFORM_BLEND_CONST_COLOR,
1497 channel));
1498 case PIPE_BLENDFACTOR_CONST_ALPHA:
1499 return qir_FMUL(c, val,
1500 get_temp_for_uniform(c,
1501 QUNIFORM_BLEND_CONST_COLOR,
1502 3));
1503 case PIPE_BLENDFACTOR_ZERO:
1504 return qir_uniform_f(c, 0.0);
1505 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
1506 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1507 src[channel]));
1508 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
1509 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1510 src[3]));
1511 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
1512 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1513 dst[3]));
1514 case PIPE_BLENDFACTOR_INV_DST_COLOR:
1515 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1516 dst[channel]));
1517 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
1518 return qir_FMUL(c, val,
1519 qir_FSUB(c, qir_uniform_f(c, 1.0),
1520 get_temp_for_uniform(c,
1521 QUNIFORM_BLEND_CONST_COLOR,
1522 channel)));
1523 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
1524 return qir_FMUL(c, val,
1525 qir_FSUB(c, qir_uniform_f(c, 1.0),
1526 get_temp_for_uniform(c,
1527 QUNIFORM_BLEND_CONST_COLOR,
1528 3)));
1529
1530 default:
1531 case PIPE_BLENDFACTOR_SRC1_COLOR:
1532 case PIPE_BLENDFACTOR_SRC1_ALPHA:
1533 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
1534 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
1535 /* Unsupported. */
1536 fprintf(stderr, "Unknown blend factor %d\n", factor);
1537 return val;
1538 }
1539 }
1540
1541 static struct qreg
1542 vc4_blend_func(struct vc4_compile *c,
1543 struct qreg src, struct qreg dst,
1544 unsigned func)
1545 {
1546 switch (func) {
1547 case PIPE_BLEND_ADD:
1548 return qir_FADD(c, src, dst);
1549 case PIPE_BLEND_SUBTRACT:
1550 return qir_FSUB(c, src, dst);
1551 case PIPE_BLEND_REVERSE_SUBTRACT:
1552 return qir_FSUB(c, dst, src);
1553 case PIPE_BLEND_MIN:
1554 return qir_FMIN(c, src, dst);
1555 case PIPE_BLEND_MAX:
1556 return qir_FMAX(c, src, dst);
1557
1558 default:
1559 /* Unsupported. */
1560 fprintf(stderr, "Unknown blend func %d\n", func);
1561 return src;
1562
1563 }
1564 }
1565
1566 /**
1567 * Implements fixed function blending in shader code.
1568 *
1569 * VC4 doesn't have any hardware support for blending. Instead, you read the
1570 * current contents of the destination from the tile buffer after having
1571 * waited for the scoreboard (which is handled by vc4_qpu_emit.c), then do
1572 * math using your output color and that destination value, and update the
1573 * output color appropriately.
1574 */
1575 static void
1576 vc4_blend(struct vc4_compile *c, struct qreg *result,
1577 struct qreg *dst_color, struct qreg *src_color)
1578 {
1579 struct pipe_rt_blend_state *blend = &c->fs_key->blend;
1580
1581 if (!blend->blend_enable) {
1582 for (int i = 0; i < 4; i++)
1583 result[i] = src_color[i];
1584 return;
1585 }
1586
1587 struct qreg src_blend[4], dst_blend[4];
1588 for (int i = 0; i < 3; i++) {
1589 src_blend[i] = vc4_blend_channel(c,
1590 dst_color, src_color,
1591 src_color[i],
1592 blend->rgb_src_factor, i);
1593 dst_blend[i] = vc4_blend_channel(c,
1594 dst_color, src_color,
1595 dst_color[i],
1596 blend->rgb_dst_factor, i);
1597 }
1598 src_blend[3] = vc4_blend_channel(c,
1599 dst_color, src_color,
1600 src_color[3],
1601 blend->alpha_src_factor, 3);
1602 dst_blend[3] = vc4_blend_channel(c,
1603 dst_color, src_color,
1604 dst_color[3],
1605 blend->alpha_dst_factor, 3);
1606
1607 for (int i = 0; i < 3; i++) {
1608 result[i] = vc4_blend_func(c,
1609 src_blend[i], dst_blend[i],
1610 blend->rgb_func);
1611 }
1612 result[3] = vc4_blend_func(c,
1613 src_blend[3], dst_blend[3],
1614 blend->alpha_func);
1615 }
1616
1617 static void
1618 clip_distance_discard(struct vc4_compile *c)
1619 {
1620 for (int i = 0; i < PIPE_MAX_CLIP_PLANES; i++) {
1621 if (!(c->key->ucp_enables & (1 << i)))
1622 continue;
1623
1624 struct qreg dist = emit_fragment_varying(c,
1625 TGSI_SEMANTIC_CLIPDIST,
1626 i,
1627 TGSI_SWIZZLE_X);
1628
1629 qir_SF(c, dist);
1630
1631 if (c->discard.file == QFILE_NULL)
1632 c->discard = qir_uniform_f(c, 0.0);
1633
1634 c->discard = qir_SEL_X_Y_NS(c, qir_uniform_f(c, 1.0),
1635 c->discard);
1636 }
1637 }
1638
1639 static void
1640 alpha_test_discard(struct vc4_compile *c)
1641 {
1642 struct qreg src_alpha;
1643 struct qreg alpha_ref = get_temp_for_uniform(c, QUNIFORM_ALPHA_REF, 0);
1644
1645 if (!c->fs_key->alpha_test)
1646 return;
1647
1648 if (c->output_color_index != -1)
1649 src_alpha = c->outputs[c->output_color_index + 3];
1650 else
1651 src_alpha = qir_uniform_f(c, 1.0);
1652
1653 if (c->discard.file == QFILE_NULL)
1654 c->discard = qir_uniform_f(c, 0.0);
1655
1656 switch (c->fs_key->alpha_test_func) {
1657 case PIPE_FUNC_NEVER:
1658 c->discard = qir_uniform_f(c, 1.0);
1659 break;
1660 case PIPE_FUNC_ALWAYS:
1661 break;
1662 case PIPE_FUNC_EQUAL:
1663 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1664 c->discard = qir_SEL_X_Y_ZS(c, c->discard,
1665 qir_uniform_f(c, 1.0));
1666 break;
1667 case PIPE_FUNC_NOTEQUAL:
1668 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1669 c->discard = qir_SEL_X_Y_ZC(c, c->discard,
1670 qir_uniform_f(c, 1.0));
1671 break;
1672 case PIPE_FUNC_GREATER:
1673 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1674 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1675 qir_uniform_f(c, 1.0));
1676 break;
1677 case PIPE_FUNC_GEQUAL:
1678 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1679 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1680 qir_uniform_f(c, 1.0));
1681 break;
1682 case PIPE_FUNC_LESS:
1683 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1684 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1685 qir_uniform_f(c, 1.0));
1686 break;
1687 case PIPE_FUNC_LEQUAL:
1688 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1689 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1690 qir_uniform_f(c, 1.0));
1691 break;
1692 }
1693 }
1694
1695 static struct qreg
1696 vc4_logicop(struct vc4_compile *c, struct qreg src, struct qreg dst)
1697 {
1698 switch (c->fs_key->logicop_func) {
1699 case PIPE_LOGICOP_CLEAR:
1700 return qir_uniform_f(c, 0.0);
1701 case PIPE_LOGICOP_NOR:
1702 return qir_NOT(c, qir_OR(c, src, dst));
1703 case PIPE_LOGICOP_AND_INVERTED:
1704 return qir_AND(c, qir_NOT(c, src), dst);
1705 case PIPE_LOGICOP_COPY_INVERTED:
1706 return qir_NOT(c, src);
1707 case PIPE_LOGICOP_AND_REVERSE:
1708 return qir_AND(c, src, qir_NOT(c, dst));
1709 case PIPE_LOGICOP_INVERT:
1710 return qir_NOT(c, dst);
1711 case PIPE_LOGICOP_XOR:
1712 return qir_XOR(c, src, dst);
1713 case PIPE_LOGICOP_NAND:
1714 return qir_NOT(c, qir_AND(c, src, dst));
1715 case PIPE_LOGICOP_AND:
1716 return qir_AND(c, src, dst);
1717 case PIPE_LOGICOP_EQUIV:
1718 return qir_NOT(c, qir_XOR(c, src, dst));
1719 case PIPE_LOGICOP_NOOP:
1720 return dst;
1721 case PIPE_LOGICOP_OR_INVERTED:
1722 return qir_OR(c, qir_NOT(c, src), dst);
1723 case PIPE_LOGICOP_OR_REVERSE:
1724 return qir_OR(c, src, qir_NOT(c, dst));
1725 case PIPE_LOGICOP_OR:
1726 return qir_OR(c, src, dst);
1727 case PIPE_LOGICOP_SET:
1728 return qir_uniform_ui(c, ~0);
1729 case PIPE_LOGICOP_COPY:
1730 default:
1731 return src;
1732 }
1733 }
1734
1735 static void
1736 emit_frag_end(struct vc4_compile *c)
1737 {
1738 clip_distance_discard(c);
1739 alpha_test_discard(c);
1740
1741 enum pipe_format color_format = c->fs_key->color_format;
1742 const uint8_t *format_swiz = vc4_get_format_swizzle(color_format);
1743 struct qreg tlb_read_color[4] = { c->undef, c->undef, c->undef, c->undef };
1744 struct qreg dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1745 struct qreg linear_dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1746 struct qreg packed_dst_color = c->undef;
1747
1748 if (c->fs_key->blend.blend_enable ||
1749 c->fs_key->blend.colormask != 0xf ||
1750 c->fs_key->logicop_func != PIPE_LOGICOP_COPY) {
1751 struct qreg r4 = qir_TLB_COLOR_READ(c);
1752 for (int i = 0; i < 4; i++)
1753 tlb_read_color[i] = qir_R4_UNPACK(c, r4, i);
1754 for (int i = 0; i < 4; i++) {
1755 dst_color[i] = get_swizzled_channel(c,
1756 tlb_read_color,
1757 format_swiz[i]);
1758 if (util_format_is_srgb(color_format) && i != 3) {
1759 linear_dst_color[i] =
1760 qir_srgb_decode(c, dst_color[i]);
1761 } else {
1762 linear_dst_color[i] = dst_color[i];
1763 }
1764 }
1765
1766 /* Save the packed value for logic ops. Can't reuse r4
1767 * becuase other things might smash it (like sRGB)
1768 */
1769 packed_dst_color = qir_MOV(c, r4);
1770 }
1771
1772 struct qreg blend_color[4];
1773 struct qreg undef_array[4] = {
1774 c->undef, c->undef, c->undef, c->undef
1775 };
1776 vc4_blend(c, blend_color, linear_dst_color,
1777 (c->output_color_index != -1 ?
1778 c->outputs + c->output_color_index :
1779 undef_array));
1780
1781 if (util_format_is_srgb(color_format)) {
1782 for (int i = 0; i < 3; i++)
1783 blend_color[i] = qir_srgb_encode(c, blend_color[i]);
1784 }
1785
1786 /* If the bit isn't set in the color mask, then just return the
1787 * original dst color, instead.
1788 */
1789 for (int i = 0; i < 4; i++) {
1790 if (!(c->fs_key->blend.colormask & (1 << i))) {
1791 blend_color[i] = dst_color[i];
1792 }
1793 }
1794
1795 /* Debug: Sometimes you're getting a black output and just want to see
1796 * if the FS is getting executed at all. Spam magenta into the color
1797 * output.
1798 */
1799 if (0) {
1800 blend_color[0] = qir_uniform_f(c, 1.0);
1801 blend_color[1] = qir_uniform_f(c, 0.0);
1802 blend_color[2] = qir_uniform_f(c, 1.0);
1803 blend_color[3] = qir_uniform_f(c, 0.5);
1804 }
1805
1806 struct qreg swizzled_outputs[4];
1807 for (int i = 0; i < 4; i++) {
1808 swizzled_outputs[i] = get_swizzled_channel(c, blend_color,
1809 format_swiz[i]);
1810 }
1811
1812 if (c->discard.file != QFILE_NULL)
1813 qir_TLB_DISCARD_SETUP(c, c->discard);
1814
1815 if (c->fs_key->stencil_enabled) {
1816 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 0));
1817 if (c->fs_key->stencil_twoside) {
1818 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 1));
1819 }
1820 if (c->fs_key->stencil_full_writemasks) {
1821 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 2));
1822 }
1823 }
1824
1825 if (c->fs_key->depth_enabled) {
1826 struct qreg z;
1827 if (c->output_position_index != -1) {
1828 z = qir_FTOI(c, qir_FMUL(c, c->outputs[c->output_position_index + 2],
1829 qir_uniform_f(c, 0xffffff)));
1830 } else {
1831 z = qir_FRAG_Z(c);
1832 }
1833 qir_TLB_Z_WRITE(c, z);
1834 }
1835
1836 bool color_written = false;
1837 for (int i = 0; i < 4; i++) {
1838 if (swizzled_outputs[i].file != QFILE_NULL)
1839 color_written = true;
1840 }
1841
1842 struct qreg packed_color;
1843 if (color_written) {
1844 /* Fill in any undefined colors. The simulator will assertion
1845 * fail if we read something that wasn't written, and I don't
1846 * know what hardware does.
1847 */
1848 for (int i = 0; i < 4; i++) {
1849 if (swizzled_outputs[i].file == QFILE_NULL)
1850 swizzled_outputs[i] = qir_uniform_f(c, 0.0);
1851 }
1852 packed_color = qir_get_temp(c);
1853 qir_emit(c, qir_inst4(QOP_PACK_COLORS, packed_color,
1854 swizzled_outputs[0],
1855 swizzled_outputs[1],
1856 swizzled_outputs[2],
1857 swizzled_outputs[3]));
1858 } else {
1859 packed_color = qir_uniform_ui(c, 0);
1860 }
1861
1862
1863 if (c->fs_key->logicop_func != PIPE_LOGICOP_COPY) {
1864 packed_color = vc4_logicop(c, packed_color, packed_dst_color);
1865 }
1866
1867 qir_emit(c, qir_inst(QOP_TLB_COLOR_WRITE, c->undef,
1868 packed_color, c->undef));
1869 }
1870
1871 static void
1872 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1873 {
1874 struct qreg xyi[2];
1875
1876 for (int i = 0; i < 2; i++) {
1877 struct qreg scale =
1878 add_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1879
1880 xyi[i] = qir_FTOI(c, qir_FMUL(c,
1881 qir_FMUL(c,
1882 c->outputs[c->output_position_index + i],
1883 scale),
1884 rcp_w));
1885 }
1886
1887 qir_VPM_WRITE(c, qir_PACK_SCALED(c, xyi[0], xyi[1]));
1888 }
1889
1890 static void
1891 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1892 {
1893 struct qreg zscale = add_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1894 struct qreg zoffset = add_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1895
1896 qir_VPM_WRITE(c, qir_FMUL(c, qir_FADD(c, qir_FMUL(c,
1897 c->outputs[c->output_position_index + 2],
1898 zscale),
1899 zoffset),
1900 rcp_w));
1901 }
1902
1903 static void
1904 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1905 {
1906 qir_VPM_WRITE(c, rcp_w);
1907 }
1908
1909 static void
1910 emit_point_size_write(struct vc4_compile *c)
1911 {
1912 struct qreg point_size;
1913
1914 if (c->output_point_size_index)
1915 point_size = c->outputs[c->output_point_size_index + 3];
1916 else
1917 point_size = qir_uniform_f(c, 1.0);
1918
1919 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1920 * BCM21553).
1921 */
1922 point_size = qir_FMAX(c, point_size, qir_uniform_f(c, .125));
1923
1924 qir_VPM_WRITE(c, point_size);
1925 }
1926
1927 /**
1928 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1929 *
1930 * The simulator insists that there be at least one vertex attribute, so
1931 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also
1932 * insists that all vertex attributes loaded get read by the VS/CS, so we have
1933 * to consume it here.
1934 */
1935 static void
1936 emit_stub_vpm_read(struct vc4_compile *c)
1937 {
1938 if (c->num_inputs)
1939 return;
1940
1941 for (int i = 0; i < 4; i++) {
1942 qir_emit(c, qir_inst(QOP_VPM_READ,
1943 qir_get_temp(c),
1944 c->undef,
1945 c->undef));
1946 c->num_inputs++;
1947 }
1948 }
1949
1950 static void
1951 emit_ucp_clipdistance(struct vc4_compile *c)
1952 {
1953 unsigned cv;
1954 if (c->output_clipvertex_index != -1)
1955 cv = c->output_clipvertex_index;
1956 else if (c->output_position_index != -1)
1957 cv = c->output_position_index;
1958 else
1959 return;
1960
1961 for (int plane = 0; plane < PIPE_MAX_CLIP_PLANES; plane++) {
1962 if (!(c->key->ucp_enables & (1 << plane)))
1963 continue;
1964
1965 /* Pick the next outputs[] that hasn't been written to, since
1966 * there are no other program writes left to be processed at
1967 * this point. If something had been declared but not written
1968 * (like a w component), we'll just smash over the top of it.
1969 */
1970 uint32_t output_index = c->num_outputs++;
1971 add_output(c, output_index,
1972 TGSI_SEMANTIC_CLIPDIST,
1973 plane,
1974 TGSI_SWIZZLE_X);
1975
1976
1977 struct qreg dist = qir_uniform_f(c, 0.0);
1978 for (int i = 0; i < 4; i++) {
1979 struct qreg pos_chan = c->outputs[cv + i];
1980 struct qreg ucp =
1981 add_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1982 plane * 4 + i);
1983 dist = qir_FADD(c, dist, qir_FMUL(c, pos_chan, ucp));
1984 }
1985
1986 c->outputs[output_index] = dist;
1987 }
1988 }
1989
1990 static void
1991 emit_vert_end(struct vc4_compile *c,
1992 struct vc4_varying_semantic *fs_inputs,
1993 uint32_t num_fs_inputs)
1994 {
1995 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1996
1997 emit_stub_vpm_read(c);
1998 emit_ucp_clipdistance(c);
1999
2000 emit_scaled_viewport_write(c, rcp_w);
2001 emit_zs_write(c, rcp_w);
2002 emit_rcp_wc_write(c, rcp_w);
2003 if (c->vs_key->per_vertex_point_size)
2004 emit_point_size_write(c);
2005
2006 for (int i = 0; i < num_fs_inputs; i++) {
2007 struct vc4_varying_semantic *input = &fs_inputs[i];
2008 int j;
2009
2010 for (j = 0; j < c->num_outputs; j++) {
2011 struct vc4_varying_semantic *output =
2012 &c->output_semantics[j];
2013
2014 if (input->semantic == output->semantic &&
2015 input->index == output->index &&
2016 input->swizzle == output->swizzle) {
2017 qir_VPM_WRITE(c, c->outputs[j]);
2018 break;
2019 }
2020 }
2021 /* Emit padding if we didn't find a declared VS output for
2022 * this FS input.
2023 */
2024 if (j == c->num_outputs)
2025 qir_VPM_WRITE(c, qir_uniform_f(c, 0.0));
2026 }
2027 }
2028
2029 static void
2030 emit_coord_end(struct vc4_compile *c)
2031 {
2032 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
2033
2034 emit_stub_vpm_read(c);
2035
2036 for (int i = 0; i < 4; i++)
2037 qir_VPM_WRITE(c, c->outputs[c->output_position_index + i]);
2038
2039 emit_scaled_viewport_write(c, rcp_w);
2040 emit_zs_write(c, rcp_w);
2041 emit_rcp_wc_write(c, rcp_w);
2042 if (c->vs_key->per_vertex_point_size)
2043 emit_point_size_write(c);
2044 }
2045
2046 static struct vc4_compile *
2047 vc4_shader_tgsi_to_qir(struct vc4_context *vc4, enum qstage stage,
2048 struct vc4_key *key)
2049 {
2050 struct vc4_compile *c = qir_compile_init();
2051 int ret;
2052
2053 c->stage = stage;
2054 for (int i = 0; i < 4; i++)
2055 c->addr[i] = qir_uniform_f(c, 0.0);
2056
2057 c->shader_state = &key->shader_state->base;
2058 c->program_id = key->shader_state->program_id;
2059 c->variant_id = key->shader_state->compiled_variant_count++;
2060
2061 c->key = key;
2062 switch (stage) {
2063 case QSTAGE_FRAG:
2064 c->fs_key = (struct vc4_fs_key *)key;
2065 if (c->fs_key->is_points) {
2066 c->point_x = emit_fragment_varying(c, ~0, ~0, 0);
2067 c->point_y = emit_fragment_varying(c, ~0, ~0, 0);
2068 } else if (c->fs_key->is_lines) {
2069 c->line_x = emit_fragment_varying(c, ~0, ~0, 0);
2070 }
2071 break;
2072 case QSTAGE_VERT:
2073 c->vs_key = (struct vc4_vs_key *)key;
2074 break;
2075 case QSTAGE_COORD:
2076 c->vs_key = (struct vc4_vs_key *)key;
2077 break;
2078 }
2079
2080 const struct tgsi_token *tokens = key->shader_state->base.tokens;
2081 if (c->fs_key && c->fs_key->light_twoside) {
2082 if (!key->shader_state->twoside_tokens) {
2083 const struct tgsi_lowering_config lowering_config = {
2084 .color_two_side = true,
2085 };
2086 struct tgsi_shader_info info;
2087 key->shader_state->twoside_tokens =
2088 tgsi_transform_lowering(&lowering_config,
2089 key->shader_state->base.tokens,
2090 &info);
2091
2092 /* If no transformation occurred, then NULL is
2093 * returned and we just use our original tokens.
2094 */
2095 if (!key->shader_state->twoside_tokens) {
2096 key->shader_state->twoside_tokens =
2097 key->shader_state->base.tokens;
2098 }
2099 }
2100 tokens = key->shader_state->twoside_tokens;
2101 }
2102
2103 ret = tgsi_parse_init(&c->parser, tokens);
2104 assert(ret == TGSI_PARSE_OK);
2105
2106 if (vc4_debug & VC4_DEBUG_TGSI) {
2107 fprintf(stderr, "%s prog %d/%d TGSI:\n",
2108 qir_get_stage_name(c->stage),
2109 c->program_id, c->variant_id);
2110 tgsi_dump(tokens, 0);
2111 }
2112
2113 while (!tgsi_parse_end_of_tokens(&c->parser)) {
2114 tgsi_parse_token(&c->parser);
2115
2116 switch (c->parser.FullToken.Token.Type) {
2117 case TGSI_TOKEN_TYPE_DECLARATION:
2118 emit_tgsi_declaration(c,
2119 &c->parser.FullToken.FullDeclaration);
2120 break;
2121
2122 case TGSI_TOKEN_TYPE_INSTRUCTION:
2123 emit_tgsi_instruction(c,
2124 &c->parser.FullToken.FullInstruction);
2125 break;
2126
2127 case TGSI_TOKEN_TYPE_IMMEDIATE:
2128 parse_tgsi_immediate(c,
2129 &c->parser.FullToken.FullImmediate);
2130 break;
2131 }
2132 }
2133
2134 switch (stage) {
2135 case QSTAGE_FRAG:
2136 emit_frag_end(c);
2137 break;
2138 case QSTAGE_VERT:
2139 emit_vert_end(c,
2140 vc4->prog.fs->input_semantics,
2141 vc4->prog.fs->num_inputs);
2142 break;
2143 case QSTAGE_COORD:
2144 emit_coord_end(c);
2145 break;
2146 }
2147
2148 tgsi_parse_free(&c->parser);
2149
2150 qir_optimize(c);
2151
2152 if (vc4_debug & VC4_DEBUG_QIR) {
2153 fprintf(stderr, "%s prog %d/%d QIR:\n",
2154 qir_get_stage_name(c->stage),
2155 c->program_id, c->variant_id);
2156 qir_dump(c);
2157 }
2158 qir_reorder_uniforms(c);
2159 vc4_generate_code(vc4, c);
2160
2161 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2162 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d instructions\n",
2163 qir_get_stage_name(c->stage),
2164 c->program_id, c->variant_id,
2165 c->qpu_inst_count);
2166 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d uniforms\n",
2167 qir_get_stage_name(c->stage),
2168 c->program_id, c->variant_id,
2169 c->num_uniforms);
2170 }
2171
2172 return c;
2173 }
2174
2175 static void *
2176 vc4_shader_state_create(struct pipe_context *pctx,
2177 const struct pipe_shader_state *cso)
2178 {
2179 struct vc4_context *vc4 = vc4_context(pctx);
2180 struct vc4_uncompiled_shader *so = CALLOC_STRUCT(vc4_uncompiled_shader);
2181 if (!so)
2182 return NULL;
2183
2184 const struct tgsi_lowering_config lowering_config = {
2185 .lower_DST = true,
2186 .lower_XPD = true,
2187 .lower_SCS = true,
2188 .lower_POW = true,
2189 .lower_LIT = true,
2190 .lower_EXP = true,
2191 .lower_LOG = true,
2192 .lower_DP4 = true,
2193 .lower_DP3 = true,
2194 .lower_DPH = true,
2195 .lower_DP2 = true,
2196 .lower_DP2A = true,
2197 };
2198
2199 struct tgsi_shader_info info;
2200 so->base.tokens = tgsi_transform_lowering(&lowering_config, cso->tokens, &info);
2201 if (!so->base.tokens)
2202 so->base.tokens = tgsi_dup_tokens(cso->tokens);
2203 so->program_id = vc4->next_uncompiled_program_id++;
2204
2205 return so;
2206 }
2207
2208 static void
2209 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
2210 struct vc4_compile *c)
2211 {
2212 int count = c->num_uniforms;
2213 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
2214
2215 uinfo->count = count;
2216 uinfo->data = ralloc_array(shader, uint32_t, count);
2217 memcpy(uinfo->data, c->uniform_data,
2218 count * sizeof(*uinfo->data));
2219 uinfo->contents = ralloc_array(shader, enum quniform_contents, count);
2220 memcpy(uinfo->contents, c->uniform_contents,
2221 count * sizeof(*uinfo->contents));
2222 uinfo->num_texture_samples = c->num_texture_samples;
2223 }
2224
2225 static struct vc4_compiled_shader *
2226 vc4_get_compiled_shader(struct vc4_context *vc4, enum qstage stage,
2227 struct vc4_key *key)
2228 {
2229 struct hash_table *ht;
2230 uint32_t key_size;
2231 if (stage == QSTAGE_FRAG) {
2232 ht = vc4->fs_cache;
2233 key_size = sizeof(struct vc4_fs_key);
2234 } else {
2235 ht = vc4->vs_cache;
2236 key_size = sizeof(struct vc4_vs_key);
2237 }
2238
2239 struct vc4_compiled_shader *shader;
2240 struct hash_entry *entry = _mesa_hash_table_search(ht, key);
2241 if (entry)
2242 return entry->data;
2243
2244 struct vc4_compile *c = vc4_shader_tgsi_to_qir(vc4, stage, key);
2245 shader = rzalloc(NULL, struct vc4_compiled_shader);
2246
2247 shader->program_id = vc4->next_compiled_program_id++;
2248 if (stage == QSTAGE_FRAG) {
2249 bool input_live[c->num_input_semantics];
2250 struct simple_node *node;
2251
2252 memset(input_live, 0, sizeof(input_live));
2253 foreach(node, &c->instructions) {
2254 struct qinst *inst = (struct qinst *)node;
2255 for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) {
2256 if (inst->src[i].file == QFILE_VARY)
2257 input_live[inst->src[i].index] = true;
2258 }
2259 }
2260
2261 shader->input_semantics = ralloc_array(shader,
2262 struct vc4_varying_semantic,
2263 c->num_input_semantics);
2264
2265 for (int i = 0; i < c->num_input_semantics; i++) {
2266 struct vc4_varying_semantic *sem = &c->input_semantics[i];
2267
2268 if (!input_live[i])
2269 continue;
2270
2271 /* Skip non-VS-output inputs. */
2272 if (sem->semantic == (uint8_t)~0)
2273 continue;
2274
2275 if (sem->semantic == TGSI_SEMANTIC_COLOR ||
2276 sem->semantic == TGSI_SEMANTIC_BCOLOR) {
2277 shader->color_inputs |= (1 << shader->num_inputs);
2278 }
2279
2280 shader->input_semantics[shader->num_inputs] = *sem;
2281 shader->num_inputs++;
2282 }
2283 } else {
2284 shader->num_inputs = c->num_inputs;
2285 }
2286
2287 copy_uniform_state_to_shader(shader, c);
2288 shader->bo = vc4_bo_alloc_mem(vc4->screen, c->qpu_insts,
2289 c->qpu_inst_count * sizeof(uint64_t),
2290 "code");
2291
2292 /* Copy the compiler UBO range state to the compiled shader, dropping
2293 * out arrays that were never referenced by an indirect load.
2294 *
2295 * (Note that QIR dead code elimination of an array access still
2296 * leaves that array alive, though)
2297 */
2298 if (c->num_ubo_ranges) {
2299 shader->num_ubo_ranges = c->num_ubo_ranges;
2300 shader->ubo_ranges = ralloc_array(shader, struct vc4_ubo_range,
2301 c->num_ubo_ranges);
2302 uint32_t j = 0;
2303 for (int i = 0; i < c->ubo_ranges_array_size; i++) {
2304 struct vc4_compiler_ubo_range *range =
2305 &c->ubo_ranges[i];
2306 if (!range->used)
2307 continue;
2308
2309 shader->ubo_ranges[j].dst_offset = range->dst_offset;
2310 shader->ubo_ranges[j].src_offset = range->src_offset;
2311 shader->ubo_ranges[j].size = range->size;
2312 shader->ubo_size += c->ubo_ranges[i].size;
2313 j++;
2314 }
2315 }
2316
2317 qir_compile_destroy(c);
2318
2319 struct vc4_key *dup_key;
2320 dup_key = ralloc_size(shader, key_size);
2321 memcpy(dup_key, key, key_size);
2322 _mesa_hash_table_insert(ht, dup_key, shader);
2323
2324 return shader;
2325 }
2326
2327 static void
2328 vc4_setup_shared_key(struct vc4_context *vc4, struct vc4_key *key,
2329 struct vc4_texture_stateobj *texstate)
2330 {
2331 for (int i = 0; i < texstate->num_textures; i++) {
2332 struct pipe_sampler_view *sampler = texstate->textures[i];
2333 struct pipe_sampler_state *sampler_state =
2334 texstate->samplers[i];
2335
2336 if (sampler) {
2337 key->tex[i].format = sampler->format;
2338 key->tex[i].swizzle[0] = sampler->swizzle_r;
2339 key->tex[i].swizzle[1] = sampler->swizzle_g;
2340 key->tex[i].swizzle[2] = sampler->swizzle_b;
2341 key->tex[i].swizzle[3] = sampler->swizzle_a;
2342 key->tex[i].compare_mode = sampler_state->compare_mode;
2343 key->tex[i].compare_func = sampler_state->compare_func;
2344 key->tex[i].wrap_s = sampler_state->wrap_s;
2345 key->tex[i].wrap_t = sampler_state->wrap_t;
2346 }
2347 }
2348
2349 key->ucp_enables = vc4->rasterizer->base.clip_plane_enable;
2350 }
2351
2352 static void
2353 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
2354 {
2355 struct vc4_fs_key local_key;
2356 struct vc4_fs_key *key = &local_key;
2357
2358 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2359 VC4_DIRTY_BLEND |
2360 VC4_DIRTY_FRAMEBUFFER |
2361 VC4_DIRTY_ZSA |
2362 VC4_DIRTY_RASTERIZER |
2363 VC4_DIRTY_FRAGTEX |
2364 VC4_DIRTY_TEXSTATE |
2365 VC4_DIRTY_PROG))) {
2366 return;
2367 }
2368
2369 memset(key, 0, sizeof(*key));
2370 vc4_setup_shared_key(vc4, &key->base, &vc4->fragtex);
2371 key->base.shader_state = vc4->prog.bind_fs;
2372 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
2373 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
2374 prim_mode <= PIPE_PRIM_LINE_STRIP);
2375 key->blend = vc4->blend->rt[0];
2376 if (vc4->blend->logicop_enable) {
2377 key->logicop_func = vc4->blend->logicop_func;
2378 } else {
2379 key->logicop_func = PIPE_LOGICOP_COPY;
2380 }
2381 if (vc4->framebuffer.cbufs[0])
2382 key->color_format = vc4->framebuffer.cbufs[0]->format;
2383
2384 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
2385 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
2386 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
2387 key->depth_enabled = (vc4->zsa->base.depth.enabled ||
2388 key->stencil_enabled);
2389 if (vc4->zsa->base.alpha.enabled) {
2390 key->alpha_test = true;
2391 key->alpha_test_func = vc4->zsa->base.alpha.func;
2392 }
2393
2394 if (key->is_points) {
2395 key->point_sprite_mask =
2396 vc4->rasterizer->base.sprite_coord_enable;
2397 key->point_coord_upper_left =
2398 (vc4->rasterizer->base.sprite_coord_mode ==
2399 PIPE_SPRITE_COORD_UPPER_LEFT);
2400 }
2401
2402 key->light_twoside = vc4->rasterizer->base.light_twoside;
2403
2404 struct vc4_compiled_shader *old_fs = vc4->prog.fs;
2405 vc4->prog.fs = vc4_get_compiled_shader(vc4, QSTAGE_FRAG, &key->base);
2406 if (vc4->prog.fs == old_fs)
2407 return;
2408
2409 if (vc4->rasterizer->base.flatshade &&
2410 old_fs && vc4->prog.fs->color_inputs != old_fs->color_inputs) {
2411 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
2412 }
2413 }
2414
2415 static void
2416 vc4_update_compiled_vs(struct vc4_context *vc4, uint8_t prim_mode)
2417 {
2418 struct vc4_vs_key local_key;
2419 struct vc4_vs_key *key = &local_key;
2420
2421 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2422 VC4_DIRTY_RASTERIZER |
2423 VC4_DIRTY_VERTTEX |
2424 VC4_DIRTY_TEXSTATE |
2425 VC4_DIRTY_VTXSTATE |
2426 VC4_DIRTY_PROG))) {
2427 return;
2428 }
2429
2430 memset(key, 0, sizeof(*key));
2431 vc4_setup_shared_key(vc4, &key->base, &vc4->verttex);
2432 key->base.shader_state = vc4->prog.bind_vs;
2433 key->compiled_fs_id = vc4->prog.fs->program_id;
2434
2435 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
2436 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
2437
2438 key->per_vertex_point_size =
2439 (prim_mode == PIPE_PRIM_POINTS &&
2440 vc4->rasterizer->base.point_size_per_vertex);
2441
2442 vc4->prog.vs = vc4_get_compiled_shader(vc4, QSTAGE_VERT, &key->base);
2443 key->is_coord = true;
2444 vc4->prog.cs = vc4_get_compiled_shader(vc4, QSTAGE_COORD, &key->base);
2445 }
2446
2447 void
2448 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
2449 {
2450 vc4_update_compiled_fs(vc4, prim_mode);
2451 vc4_update_compiled_vs(vc4, prim_mode);
2452 }
2453
2454 static uint32_t
2455 fs_cache_hash(const void *key)
2456 {
2457 return _mesa_hash_data(key, sizeof(struct vc4_fs_key));
2458 }
2459
2460 static uint32_t
2461 vs_cache_hash(const void *key)
2462 {
2463 return _mesa_hash_data(key, sizeof(struct vc4_vs_key));
2464 }
2465
2466 static bool
2467 fs_cache_compare(const void *key1, const void *key2)
2468 {
2469 return memcmp(key1, key2, sizeof(struct vc4_fs_key)) == 0;
2470 }
2471
2472 static bool
2473 vs_cache_compare(const void *key1, const void *key2)
2474 {
2475 return memcmp(key1, key2, sizeof(struct vc4_vs_key)) == 0;
2476 }
2477
2478 static void
2479 delete_from_cache_if_matches(struct hash_table *ht,
2480 struct hash_entry *entry,
2481 struct vc4_uncompiled_shader *so)
2482 {
2483 struct vc4_key *key = entry->data;
2484
2485 if (key->shader_state == so) {
2486 struct vc4_compiled_shader *shader = entry->data;
2487 _mesa_hash_table_remove(ht, entry);
2488 vc4_bo_unreference(&shader->bo);
2489 ralloc_free(shader);
2490 }
2491 }
2492
2493 static void
2494 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
2495 {
2496 struct vc4_context *vc4 = vc4_context(pctx);
2497 struct vc4_uncompiled_shader *so = hwcso;
2498
2499 struct hash_entry *entry;
2500 hash_table_foreach(vc4->fs_cache, entry)
2501 delete_from_cache_if_matches(vc4->fs_cache, entry, so);
2502 hash_table_foreach(vc4->vs_cache, entry)
2503 delete_from_cache_if_matches(vc4->vs_cache, entry, so);
2504
2505 if (so->twoside_tokens != so->base.tokens)
2506 free((void *)so->twoside_tokens);
2507 free((void *)so->base.tokens);
2508 free(so);
2509 }
2510
2511 static uint32_t translate_wrap(uint32_t p_wrap, bool using_nearest)
2512 {
2513 switch (p_wrap) {
2514 case PIPE_TEX_WRAP_REPEAT:
2515 return 0;
2516 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
2517 return 1;
2518 case PIPE_TEX_WRAP_MIRROR_REPEAT:
2519 return 2;
2520 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
2521 return 3;
2522 case PIPE_TEX_WRAP_CLAMP:
2523 return (using_nearest ? 1 : 3);
2524 default:
2525 fprintf(stderr, "Unknown wrap mode %d\n", p_wrap);
2526 assert(!"not reached");
2527 return 0;
2528 }
2529 }
2530
2531 static void
2532 write_texture_p0(struct vc4_context *vc4,
2533 struct vc4_texture_stateobj *texstate,
2534 uint32_t unit)
2535 {
2536 struct pipe_sampler_view *texture = texstate->textures[unit];
2537 struct vc4_resource *rsc = vc4_resource(texture->texture);
2538
2539 cl_reloc(vc4, &vc4->uniforms, rsc->bo,
2540 VC4_SET_FIELD(rsc->slices[0].offset >> 12, VC4_TEX_P0_OFFSET) |
2541 VC4_SET_FIELD(texture->u.tex.last_level -
2542 texture->u.tex.first_level, VC4_TEX_P0_MIPLVLS) |
2543 VC4_SET_FIELD(texture->target == PIPE_TEXTURE_CUBE,
2544 VC4_TEX_P0_CMMODE) |
2545 VC4_SET_FIELD(rsc->vc4_format & 7, VC4_TEX_P0_TYPE));
2546 }
2547
2548 static void
2549 write_texture_p1(struct vc4_context *vc4,
2550 struct vc4_texture_stateobj *texstate,
2551 uint32_t unit)
2552 {
2553 struct pipe_sampler_view *texture = texstate->textures[unit];
2554 struct vc4_resource *rsc = vc4_resource(texture->texture);
2555 struct pipe_sampler_state *sampler = texstate->samplers[unit];
2556 static const uint8_t minfilter_map[6] = {
2557 VC4_TEX_P1_MINFILT_NEAR_MIP_NEAR,
2558 VC4_TEX_P1_MINFILT_LIN_MIP_NEAR,
2559 VC4_TEX_P1_MINFILT_NEAR_MIP_LIN,
2560 VC4_TEX_P1_MINFILT_LIN_MIP_LIN,
2561 VC4_TEX_P1_MINFILT_NEAREST,
2562 VC4_TEX_P1_MINFILT_LINEAR,
2563 };
2564 static const uint32_t magfilter_map[] = {
2565 [PIPE_TEX_FILTER_NEAREST] = VC4_TEX_P1_MAGFILT_NEAREST,
2566 [PIPE_TEX_FILTER_LINEAR] = VC4_TEX_P1_MAGFILT_LINEAR,
2567 };
2568
2569 bool either_nearest =
2570 (sampler->mag_img_filter == PIPE_TEX_MIPFILTER_NEAREST ||
2571 sampler->min_img_filter == PIPE_TEX_MIPFILTER_NEAREST);
2572
2573 cl_u32(&vc4->uniforms,
2574 VC4_SET_FIELD(rsc->vc4_format >> 4, VC4_TEX_P1_TYPE4) |
2575 VC4_SET_FIELD(texture->texture->height0 & 2047,
2576 VC4_TEX_P1_HEIGHT) |
2577 VC4_SET_FIELD(texture->texture->width0 & 2047,
2578 VC4_TEX_P1_WIDTH) |
2579 VC4_SET_FIELD(magfilter_map[sampler->mag_img_filter],
2580 VC4_TEX_P1_MAGFILT) |
2581 VC4_SET_FIELD(minfilter_map[sampler->min_mip_filter * 2 +
2582 sampler->min_img_filter],
2583 VC4_TEX_P1_MINFILT) |
2584 VC4_SET_FIELD(translate_wrap(sampler->wrap_s, either_nearest),
2585 VC4_TEX_P1_WRAP_S) |
2586 VC4_SET_FIELD(translate_wrap(sampler->wrap_t, either_nearest),
2587 VC4_TEX_P1_WRAP_T));
2588 }
2589
2590 static void
2591 write_texture_p2(struct vc4_context *vc4,
2592 struct vc4_texture_stateobj *texstate,
2593 uint32_t data)
2594 {
2595 uint32_t unit = data & 0xffff;
2596 struct pipe_sampler_view *texture = texstate->textures[unit];
2597 struct vc4_resource *rsc = vc4_resource(texture->texture);
2598
2599 cl_u32(&vc4->uniforms,
2600 VC4_SET_FIELD(VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE,
2601 VC4_TEX_P2_PTYPE) |
2602 VC4_SET_FIELD(rsc->cube_map_stride >> 12, VC4_TEX_P2_CMST) |
2603 VC4_SET_FIELD((data >> 16) & 1, VC4_TEX_P2_BSLOD));
2604 }
2605
2606
2607 #define SWIZ(x,y,z,w) { \
2608 UTIL_FORMAT_SWIZZLE_##x, \
2609 UTIL_FORMAT_SWIZZLE_##y, \
2610 UTIL_FORMAT_SWIZZLE_##z, \
2611 UTIL_FORMAT_SWIZZLE_##w \
2612 }
2613
2614 static void
2615 write_texture_border_color(struct vc4_context *vc4,
2616 struct vc4_texture_stateobj *texstate,
2617 uint32_t unit)
2618 {
2619 struct pipe_sampler_state *sampler = texstate->samplers[unit];
2620 struct pipe_sampler_view *texture = texstate->textures[unit];
2621 struct vc4_resource *rsc = vc4_resource(texture->texture);
2622 union util_color uc;
2623
2624 const struct util_format_description *tex_format_desc =
2625 util_format_description(texture->format);
2626
2627 float border_color[4];
2628 for (int i = 0; i < 4; i++)
2629 border_color[i] = sampler->border_color.f[i];
2630 if (util_format_is_srgb(texture->format)) {
2631 for (int i = 0; i < 3; i++)
2632 border_color[i] =
2633 util_format_linear_to_srgb_float(border_color[i]);
2634 }
2635
2636 /* Turn the border color into the layout of channels that it would
2637 * have when stored as texture contents.
2638 */
2639 float storage_color[4];
2640 util_format_unswizzle_4f(storage_color,
2641 border_color,
2642 tex_format_desc->swizzle);
2643
2644 /* Now, pack so that when the vc4_format-sampled texture contents are
2645 * replaced with our border color, the vc4_get_format_swizzle()
2646 * swizzling will get the right channels.
2647 */
2648 if (util_format_is_depth_or_stencil(texture->format)) {
2649 uc.ui[0] = util_pack_z(PIPE_FORMAT_Z24X8_UNORM,
2650 sampler->border_color.f[0]) << 8;
2651 } else {
2652 switch (rsc->vc4_format) {
2653 default:
2654 case VC4_TEXTURE_TYPE_RGBA8888:
2655 util_pack_color(storage_color,
2656 PIPE_FORMAT_R8G8B8A8_UNORM, &uc);
2657 break;
2658 case VC4_TEXTURE_TYPE_RGBA4444:
2659 util_pack_color(storage_color,
2660 PIPE_FORMAT_A8B8G8R8_UNORM, &uc);
2661 break;
2662 case VC4_TEXTURE_TYPE_RGB565:
2663 util_pack_color(storage_color,
2664 PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
2665 break;
2666 case VC4_TEXTURE_TYPE_ALPHA:
2667 uc.ui[0] = float_to_ubyte(storage_color[0]) << 24;
2668 break;
2669 case VC4_TEXTURE_TYPE_LUMALPHA:
2670 uc.ui[0] = ((float_to_ubyte(storage_color[1]) << 24) |
2671 (float_to_ubyte(storage_color[0]) << 0));
2672 break;
2673 }
2674 }
2675
2676 cl_u32(&vc4->uniforms, uc.ui[0]);
2677 }
2678
2679 static uint32_t
2680 get_texrect_scale(struct vc4_texture_stateobj *texstate,
2681 enum quniform_contents contents,
2682 uint32_t data)
2683 {
2684 struct pipe_sampler_view *texture = texstate->textures[data];
2685 uint32_t dim;
2686
2687 if (contents == QUNIFORM_TEXRECT_SCALE_X)
2688 dim = texture->texture->width0;
2689 else
2690 dim = texture->texture->height0;
2691
2692 return fui(1.0f / dim);
2693 }
2694
2695 static struct vc4_bo *
2696 vc4_upload_ubo(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
2697 const uint32_t *gallium_uniforms)
2698 {
2699 if (!shader->ubo_size)
2700 return NULL;
2701
2702 struct vc4_bo *ubo = vc4_bo_alloc(vc4->screen, shader->ubo_size, "ubo");
2703 uint32_t *data = vc4_bo_map(ubo);
2704 for (uint32_t i = 0; i < shader->num_ubo_ranges; i++) {
2705 memcpy(data + shader->ubo_ranges[i].dst_offset,
2706 gallium_uniforms + shader->ubo_ranges[i].src_offset,
2707 shader->ubo_ranges[i].size);
2708 }
2709
2710 return ubo;
2711 }
2712
2713 void
2714 vc4_write_uniforms(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
2715 struct vc4_constbuf_stateobj *cb,
2716 struct vc4_texture_stateobj *texstate)
2717 {
2718 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
2719 const uint32_t *gallium_uniforms = cb->cb[0].user_buffer;
2720 struct vc4_bo *ubo = vc4_upload_ubo(vc4, shader, gallium_uniforms);
2721
2722 cl_start_shader_reloc(&vc4->uniforms, uinfo->num_texture_samples);
2723
2724 for (int i = 0; i < uinfo->count; i++) {
2725
2726 switch (uinfo->contents[i]) {
2727 case QUNIFORM_CONSTANT:
2728 cl_u32(&vc4->uniforms, uinfo->data[i]);
2729 break;
2730 case QUNIFORM_UNIFORM:
2731 cl_u32(&vc4->uniforms,
2732 gallium_uniforms[uinfo->data[i]]);
2733 break;
2734 case QUNIFORM_VIEWPORT_X_SCALE:
2735 cl_f(&vc4->uniforms, vc4->viewport.scale[0] * 16.0f);
2736 break;
2737 case QUNIFORM_VIEWPORT_Y_SCALE:
2738 cl_f(&vc4->uniforms, vc4->viewport.scale[1] * 16.0f);
2739 break;
2740
2741 case QUNIFORM_VIEWPORT_Z_OFFSET:
2742 cl_f(&vc4->uniforms, vc4->viewport.translate[2]);
2743 break;
2744 case QUNIFORM_VIEWPORT_Z_SCALE:
2745 cl_f(&vc4->uniforms, vc4->viewport.scale[2]);
2746 break;
2747
2748 case QUNIFORM_USER_CLIP_PLANE:
2749 cl_f(&vc4->uniforms,
2750 vc4->clip.ucp[uinfo->data[i] / 4][uinfo->data[i] % 4]);
2751 break;
2752
2753 case QUNIFORM_TEXTURE_CONFIG_P0:
2754 write_texture_p0(vc4, texstate, uinfo->data[i]);
2755 break;
2756
2757 case QUNIFORM_TEXTURE_CONFIG_P1:
2758 write_texture_p1(vc4, texstate, uinfo->data[i]);
2759 break;
2760
2761 case QUNIFORM_TEXTURE_CONFIG_P2:
2762 write_texture_p2(vc4, texstate, uinfo->data[i]);
2763 break;
2764
2765 case QUNIFORM_UBO_ADDR:
2766 cl_reloc(vc4, &vc4->uniforms, ubo, 0);
2767 break;
2768
2769 case QUNIFORM_TEXTURE_BORDER_COLOR:
2770 write_texture_border_color(vc4, texstate, uinfo->data[i]);
2771 break;
2772
2773 case QUNIFORM_TEXRECT_SCALE_X:
2774 case QUNIFORM_TEXRECT_SCALE_Y:
2775 cl_u32(&vc4->uniforms,
2776 get_texrect_scale(texstate,
2777 uinfo->contents[i],
2778 uinfo->data[i]));
2779 break;
2780
2781 case QUNIFORM_BLEND_CONST_COLOR:
2782 cl_f(&vc4->uniforms,
2783 vc4->blend_color.color[uinfo->data[i]]);
2784 break;
2785
2786 case QUNIFORM_STENCIL:
2787 cl_u32(&vc4->uniforms,
2788 vc4->zsa->stencil_uniforms[uinfo->data[i]] |
2789 (uinfo->data[i] <= 1 ?
2790 (vc4->stencil_ref.ref_value[uinfo->data[i]] << 8) :
2791 0));
2792 break;
2793
2794 case QUNIFORM_ALPHA_REF:
2795 cl_f(&vc4->uniforms, vc4->zsa->base.alpha.ref_value);
2796 break;
2797 }
2798 #if 0
2799 uint32_t written_val = *(uint32_t *)(vc4->uniforms.next - 4);
2800 fprintf(stderr, "%p: %d / 0x%08x (%f)\n",
2801 shader, i, written_val, uif(written_val));
2802 #endif
2803 }
2804 }
2805
2806 static void
2807 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
2808 {
2809 struct vc4_context *vc4 = vc4_context(pctx);
2810 vc4->prog.bind_fs = hwcso;
2811 vc4->prog.dirty |= VC4_SHADER_DIRTY_FP;
2812 vc4->dirty |= VC4_DIRTY_PROG;
2813 }
2814
2815 static void
2816 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
2817 {
2818 struct vc4_context *vc4 = vc4_context(pctx);
2819 vc4->prog.bind_vs = hwcso;
2820 vc4->prog.dirty |= VC4_SHADER_DIRTY_VP;
2821 vc4->dirty |= VC4_DIRTY_PROG;
2822 }
2823
2824 void
2825 vc4_program_init(struct pipe_context *pctx)
2826 {
2827 struct vc4_context *vc4 = vc4_context(pctx);
2828
2829 pctx->create_vs_state = vc4_shader_state_create;
2830 pctx->delete_vs_state = vc4_shader_state_delete;
2831
2832 pctx->create_fs_state = vc4_shader_state_create;
2833 pctx->delete_fs_state = vc4_shader_state_delete;
2834
2835 pctx->bind_fs_state = vc4_fp_state_bind;
2836 pctx->bind_vs_state = vc4_vp_state_bind;
2837
2838 vc4->fs_cache = _mesa_hash_table_create(pctx, fs_cache_hash,
2839 fs_cache_compare);
2840 vc4->vs_cache = _mesa_hash_table_create(pctx, vs_cache_hash,
2841 vs_cache_compare);
2842 }
2843
2844 void
2845 vc4_program_fini(struct pipe_context *pctx)
2846 {
2847 struct vc4_context *vc4 = vc4_context(pctx);
2848
2849 struct hash_entry *entry;
2850 hash_table_foreach(vc4->fs_cache, entry) {
2851 struct vc4_compiled_shader *shader = entry->data;
2852 vc4_bo_unreference(&shader->bo);
2853 ralloc_free(shader);
2854 _mesa_hash_table_remove(vc4->fs_cache, entry);
2855 }
2856
2857 hash_table_foreach(vc4->vs_cache, entry) {
2858 struct vc4_compiled_shader *shader = entry->data;
2859 vc4_bo_unreference(&shader->bo);
2860 ralloc_free(shader);
2861 _mesa_hash_table_remove(vc4->vs_cache, entry);
2862 }
2863 }