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vc4: Merge qcompile and tgsi_to_qir
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "pipe/p_state.h"
27 #include "util/u_format.h"
28 #include "util/u_hash_table.h"
29 #include "util/u_hash.h"
30 #include "util/u_memory.h"
31 #include "tgsi/tgsi_dump.h"
32 #include "tgsi/tgsi_info.h"
33
34 #include "vc4_context.h"
35 #include "vc4_qpu.h"
36 #include "vc4_qir.h"
37 #ifdef USE_VC4_SIMULATOR
38 #include "simpenrose/simpenrose.h"
39 #endif
40
41 struct vc4_key {
42 struct pipe_shader_state *shader_state;
43 enum pipe_format tex_format[VC4_MAX_TEXTURE_SAMPLERS];
44 };
45
46 struct vc4_fs_key {
47 struct vc4_key base;
48 enum pipe_format color_format;
49 bool depth_enabled;
50 bool is_points;
51 bool is_lines;
52
53 struct pipe_rt_blend_state blend;
54 };
55
56 struct vc4_vs_key {
57 struct vc4_key base;
58 enum pipe_format attr_formats[8];
59 };
60
61 static struct qreg
62 add_uniform(struct vc4_compile *c,
63 enum quniform_contents contents,
64 uint32_t data)
65 {
66 uint32_t uniform = c->num_uniforms++;
67 struct qreg u = { QFILE_UNIF, uniform };
68
69 c->uniform_contents[uniform] = contents;
70 c->uniform_data[uniform] = data;
71
72 return u;
73 }
74
75 static struct qreg
76 get_temp_for_uniform(struct vc4_compile *c, enum quniform_contents contents,
77 uint32_t data)
78 {
79 for (int i = 0; i < c->num_uniforms; i++) {
80 if (c->uniform_contents[i] == contents &&
81 c->uniform_data[i] == data)
82 return c->uniforms[i];
83 }
84
85 struct qreg u = add_uniform(c, contents, data);
86 struct qreg t = qir_MOV(c, u);
87
88 c->uniforms[u.index] = t;
89 return t;
90 }
91
92 static struct qreg
93 qir_uniform_ui(struct vc4_compile *c, uint32_t ui)
94 {
95 return get_temp_for_uniform(c, QUNIFORM_CONSTANT, ui);
96 }
97
98 static struct qreg
99 qir_uniform_f(struct vc4_compile *c, float f)
100 {
101 return qir_uniform_ui(c, fui(f));
102 }
103
104 static struct qreg
105 get_src(struct vc4_compile *c, unsigned tgsi_op,
106 struct tgsi_src_register *src, int i)
107 {
108 struct qreg r = c->undef;
109
110 uint32_t s = i;
111 switch (i) {
112 case TGSI_SWIZZLE_X:
113 s = src->SwizzleX;
114 break;
115 case TGSI_SWIZZLE_Y:
116 s = src->SwizzleY;
117 break;
118 case TGSI_SWIZZLE_Z:
119 s = src->SwizzleZ;
120 break;
121 case TGSI_SWIZZLE_W:
122 s = src->SwizzleW;
123 break;
124 default:
125 abort();
126 }
127
128 assert(!src->Indirect);
129
130 switch (src->File) {
131 case TGSI_FILE_NULL:
132 return r;
133 case TGSI_FILE_TEMPORARY:
134 r = c->temps[src->Index * 4 + s];
135 break;
136 case TGSI_FILE_IMMEDIATE:
137 r = c->consts[src->Index * 4 + s];
138 break;
139 case TGSI_FILE_CONSTANT:
140 r = get_temp_for_uniform(c, QUNIFORM_UNIFORM,
141 src->Index * 4 + s);
142 break;
143 case TGSI_FILE_INPUT:
144 r = c->inputs[src->Index * 4 + s];
145 break;
146 case TGSI_FILE_SAMPLER:
147 case TGSI_FILE_SAMPLER_VIEW:
148 r = c->undef;
149 break;
150 default:
151 fprintf(stderr, "unknown src file %d\n", src->File);
152 abort();
153 }
154
155 if (src->Absolute)
156 r = qir_FMAXABS(c, r, r);
157
158 if (src->Negate) {
159 switch (tgsi_opcode_infer_src_type(tgsi_op)) {
160 case TGSI_TYPE_SIGNED:
161 case TGSI_TYPE_UNSIGNED:
162 r = qir_SUB(c, qir_uniform_ui(c, 0), r);
163 break;
164 default:
165 r = qir_FSUB(c, qir_uniform_f(c, 0.0), r);
166 break;
167 }
168 }
169
170 return r;
171 };
172
173
174 static void
175 update_dst(struct vc4_compile *c, struct tgsi_full_instruction *tgsi_inst,
176 int i, struct qreg val)
177 {
178 struct tgsi_dst_register *tgsi_dst = &tgsi_inst->Dst[0].Register;
179
180 assert(!tgsi_dst->Indirect);
181
182 switch (tgsi_dst->File) {
183 case TGSI_FILE_TEMPORARY:
184 c->temps[tgsi_dst->Index * 4 + i] = val;
185 break;
186 case TGSI_FILE_OUTPUT:
187 c->outputs[tgsi_dst->Index * 4 + i] = val;
188 c->num_outputs = MAX2(c->num_outputs,
189 tgsi_dst->Index * 4 + i + 1);
190 break;
191 default:
192 fprintf(stderr, "unknown dst file %d\n", tgsi_dst->File);
193 abort();
194 }
195 };
196
197 static struct qreg
198 get_swizzled_channel(struct vc4_compile *c,
199 struct qreg *srcs, int swiz)
200 {
201 switch (swiz) {
202 default:
203 case UTIL_FORMAT_SWIZZLE_NONE:
204 fprintf(stderr, "warning: unknown swizzle\n");
205 /* FALLTHROUGH */
206 case UTIL_FORMAT_SWIZZLE_0:
207 return qir_uniform_f(c, 0.0);
208 case UTIL_FORMAT_SWIZZLE_1:
209 return qir_uniform_f(c, 1.0);
210 case UTIL_FORMAT_SWIZZLE_X:
211 case UTIL_FORMAT_SWIZZLE_Y:
212 case UTIL_FORMAT_SWIZZLE_Z:
213 case UTIL_FORMAT_SWIZZLE_W:
214 return srcs[swiz];
215 }
216 }
217
218 static struct qreg
219 tgsi_to_qir_alu(struct vc4_compile *c,
220 struct tgsi_full_instruction *tgsi_inst,
221 enum qop op, struct qreg *src, int i)
222 {
223 struct qreg dst = qir_get_temp(c);
224 qir_emit(c, qir_inst4(op, dst,
225 src[0 * 4 + i],
226 src[1 * 4 + i],
227 src[2 * 4 + i],
228 c->undef));
229 return dst;
230 }
231
232 static struct qreg
233 tgsi_to_qir_umul(struct vc4_compile *c,
234 struct tgsi_full_instruction *tgsi_inst,
235 enum qop op, struct qreg *src, int i)
236 {
237 struct qreg src0_hi = qir_SHR(c, src[0 * 4 + i],
238 qir_uniform_ui(c, 16));
239 struct qreg src0_lo = qir_AND(c, src[0 * 4 + i],
240 qir_uniform_ui(c, 0xffff));
241 struct qreg src1_hi = qir_SHR(c, src[1 * 4 + i],
242 qir_uniform_ui(c, 16));
243 struct qreg src1_lo = qir_AND(c, src[1 * 4 + i],
244 qir_uniform_ui(c, 0xffff));
245
246 struct qreg hilo = qir_MUL24(c, src0_hi, src1_lo);
247 struct qreg lohi = qir_MUL24(c, src0_lo, src1_hi);
248 struct qreg lolo = qir_MUL24(c, src0_lo, src1_lo);
249
250 return qir_ADD(c, lolo, qir_SHL(c,
251 qir_ADD(c, hilo, lohi),
252 qir_uniform_ui(c, 16)));
253 }
254
255 static struct qreg
256 tgsi_to_qir_idiv(struct vc4_compile *c,
257 struct tgsi_full_instruction *tgsi_inst,
258 enum qop op, struct qreg *src, int i)
259 {
260 return qir_FTOI(c, qir_FMUL(c,
261 qir_ITOF(c, src[0 * 4 + i]),
262 qir_RCP(c, qir_ITOF(c, src[1 * 4 + i]))));
263 }
264
265 static struct qreg
266 tgsi_to_qir_ineg(struct vc4_compile *c,
267 struct tgsi_full_instruction *tgsi_inst,
268 enum qop op, struct qreg *src, int i)
269 {
270 return qir_SUB(c, qir_uniform_ui(c, 0), src[0 * 4 + i]);
271 }
272
273 static struct qreg
274 tgsi_to_qir_seq(struct vc4_compile *c,
275 struct tgsi_full_instruction *tgsi_inst,
276 enum qop op, struct qreg *src, int i)
277 {
278 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
279 return qir_SEL_X_0_ZS(c, qir_uniform_f(c, 1.0));
280 }
281
282 static struct qreg
283 tgsi_to_qir_sne(struct vc4_compile *c,
284 struct tgsi_full_instruction *tgsi_inst,
285 enum qop op, struct qreg *src, int i)
286 {
287 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
288 return qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0));
289 }
290
291 static struct qreg
292 tgsi_to_qir_slt(struct vc4_compile *c,
293 struct tgsi_full_instruction *tgsi_inst,
294 enum qop op, struct qreg *src, int i)
295 {
296 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
297 return qir_SEL_X_0_NS(c, qir_uniform_f(c, 1.0));
298 }
299
300 static struct qreg
301 tgsi_to_qir_sge(struct vc4_compile *c,
302 struct tgsi_full_instruction *tgsi_inst,
303 enum qop op, struct qreg *src, int i)
304 {
305 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
306 return qir_SEL_X_0_NC(c, qir_uniform_f(c, 1.0));
307 }
308
309 static struct qreg
310 tgsi_to_qir_fseq(struct vc4_compile *c,
311 struct tgsi_full_instruction *tgsi_inst,
312 enum qop op, struct qreg *src, int i)
313 {
314 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
315 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
316 }
317
318 static struct qreg
319 tgsi_to_qir_fsne(struct vc4_compile *c,
320 struct tgsi_full_instruction *tgsi_inst,
321 enum qop op, struct qreg *src, int i)
322 {
323 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
324 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
325 }
326
327 static struct qreg
328 tgsi_to_qir_fslt(struct vc4_compile *c,
329 struct tgsi_full_instruction *tgsi_inst,
330 enum qop op, struct qreg *src, int i)
331 {
332 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
333 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
334 }
335
336 static struct qreg
337 tgsi_to_qir_fsge(struct vc4_compile *c,
338 struct tgsi_full_instruction *tgsi_inst,
339 enum qop op, struct qreg *src, int i)
340 {
341 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
342 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
343 }
344
345 static struct qreg
346 tgsi_to_qir_useq(struct vc4_compile *c,
347 struct tgsi_full_instruction *tgsi_inst,
348 enum qop op, struct qreg *src, int i)
349 {
350 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
351 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
352 }
353
354 static struct qreg
355 tgsi_to_qir_usne(struct vc4_compile *c,
356 struct tgsi_full_instruction *tgsi_inst,
357 enum qop op, struct qreg *src, int i)
358 {
359 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
360 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
361 }
362
363 static struct qreg
364 tgsi_to_qir_islt(struct vc4_compile *c,
365 struct tgsi_full_instruction *tgsi_inst,
366 enum qop op, struct qreg *src, int i)
367 {
368 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
369 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
370 }
371
372 static struct qreg
373 tgsi_to_qir_isge(struct vc4_compile *c,
374 struct tgsi_full_instruction *tgsi_inst,
375 enum qop op, struct qreg *src, int i)
376 {
377 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
378 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
379 }
380
381 static struct qreg
382 tgsi_to_qir_cmp(struct vc4_compile *c,
383 struct tgsi_full_instruction *tgsi_inst,
384 enum qop op, struct qreg *src, int i)
385 {
386 qir_SF(c, src[0 * 4 + i]);
387 return qir_SEL_X_Y_NS(c,
388 src[1 * 4 + i],
389 src[2 * 4 + i]);
390 }
391
392 static struct qreg
393 tgsi_to_qir_mad(struct vc4_compile *c,
394 struct tgsi_full_instruction *tgsi_inst,
395 enum qop op, struct qreg *src, int i)
396 {
397 return qir_FADD(c,
398 qir_FMUL(c,
399 src[0 * 4 + i],
400 src[1 * 4 + i]),
401 src[2 * 4 + i]);
402 }
403
404 static struct qreg
405 tgsi_to_qir_lit(struct vc4_compile *c,
406 struct tgsi_full_instruction *tgsi_inst,
407 enum qop op, struct qreg *src, int i)
408 {
409 struct qreg x = src[0 * 4 + 0];
410 struct qreg y = src[0 * 4 + 1];
411 struct qreg w = src[0 * 4 + 3];
412
413 switch (i) {
414 case 0:
415 case 3:
416 return qir_uniform_f(c, 1.0);
417 case 1:
418 return qir_FMAX(c, src[0 * 4 + 0], qir_uniform_f(c, 0.0));
419 case 2: {
420 struct qreg zero = qir_uniform_f(c, 0.0);
421
422 qir_SF(c, x);
423 /* XXX: Clamp w to -128..128 */
424 return qir_SEL_X_0_NC(c,
425 qir_EXP2(c, qir_FMUL(c,
426 w,
427 qir_LOG2(c,
428 qir_FMAX(c,
429 y,
430 zero)))));
431 }
432 default:
433 assert(!"not reached");
434 return c->undef;
435 }
436 }
437
438 static struct qreg
439 tgsi_to_qir_lrp(struct vc4_compile *c,
440 struct tgsi_full_instruction *tgsi_inst,
441 enum qop op, struct qreg *src, int i)
442 {
443 struct qreg src0 = src[0 * 4 + i];
444 struct qreg src1 = src[1 * 4 + i];
445 struct qreg src2 = src[2 * 4 + i];
446
447 /* LRP is:
448 * src0 * src1 + (1 - src0) * src2.
449 * -> src0 * src1 + src2 - src0 * src2
450 * -> src2 + src0 * (src1 - src2)
451 */
452 return qir_FADD(c, src2, qir_FMUL(c, src0, qir_FSUB(c, src1, src2)));
453
454 }
455
456 static void
457 tgsi_to_qir_tex(struct vc4_compile *c,
458 struct tgsi_full_instruction *tgsi_inst,
459 enum qop op, struct qreg *src)
460 {
461 assert(!tgsi_inst->Instruction.Saturate);
462
463 struct qreg s = src[0 * 4 + 0];
464 struct qreg t = src[0 * 4 + 1];
465 uint32_t unit = tgsi_inst->Src[1].Register.Index;
466
467 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
468 struct qreg proj = qir_RCP(c, src[0 * 4 + 3]);
469 s = qir_FMUL(c, s, proj);
470 t = qir_FMUL(c, t, proj);
471 }
472
473 /* There is no native support for GL texture rectangle coordinates, so
474 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
475 * 1]).
476 */
477 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_RECT) {
478 s = qir_FMUL(c, s,
479 get_temp_for_uniform(c,
480 QUNIFORM_TEXRECT_SCALE_X,
481 unit));
482 t = qir_FMUL(c, t,
483 get_temp_for_uniform(c,
484 QUNIFORM_TEXRECT_SCALE_Y,
485 unit));
486 }
487
488 qir_TEX_T(c, t, add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit));
489
490 struct qreg sampler_p1 = add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1,
491 unit);
492 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB) {
493 qir_TEX_B(c, src[0 * 4 + 3], sampler_p1);
494 qir_TEX_S(c, s, add_uniform(c, QUNIFORM_CONSTANT, 0));
495 } else {
496 qir_TEX_S(c, s, sampler_p1);
497 }
498
499 c->num_texture_samples++;
500 qir_emit(c, qir_inst(QOP_TEX_RESULT, c->undef, c->undef, c->undef));
501
502 struct qreg unpacked[4];
503 for (int i = 0; i < 4; i++)
504 unpacked[i] = qir_R4_UNPACK(c, i);
505
506 enum pipe_format format = c->key->tex_format[unit];
507 const uint8_t *swiz = vc4_get_format_swizzle(format);
508 for (int i = 0; i < 4; i++) {
509 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
510 continue;
511
512 update_dst(c, tgsi_inst, i,
513 get_swizzled_channel(c, unpacked, swiz[i]));
514 }
515 }
516
517 static struct qreg
518 tgsi_to_qir_pow(struct vc4_compile *c,
519 struct tgsi_full_instruction *tgsi_inst,
520 enum qop op, struct qreg *src, int i)
521 {
522 /* Note that this instruction replicates its result from the x channel
523 */
524 return qir_EXP2(c, qir_FMUL(c,
525 src[1 * 4 + 0],
526 qir_LOG2(c, src[0 * 4 + 0])));
527 }
528
529 static struct qreg
530 tgsi_to_qir_trunc(struct vc4_compile *c,
531 struct tgsi_full_instruction *tgsi_inst,
532 enum qop op, struct qreg *src, int i)
533 {
534 return qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
535 }
536
537 /**
538 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
539 * to zero).
540 */
541 static struct qreg
542 tgsi_to_qir_frc(struct vc4_compile *c,
543 struct tgsi_full_instruction *tgsi_inst,
544 enum qop op, struct qreg *src, int i)
545 {
546 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
547 struct qreg diff = qir_FSUB(c, src[0 * 4 + i], trunc);
548 qir_SF(c, diff);
549 return qir_SEL_X_Y_NS(c,
550 qir_FADD(c, diff, qir_uniform_f(c, 1.0)),
551 diff);
552 }
553
554 /**
555 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
556 * zero).
557 */
558 static struct qreg
559 tgsi_to_qir_flr(struct vc4_compile *c,
560 struct tgsi_full_instruction *tgsi_inst,
561 enum qop op, struct qreg *src, int i)
562 {
563 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
564
565 /* This will be < 0 if we truncated and the truncation was of a value
566 * that was < 0 in the first place.
567 */
568 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], trunc));
569
570 return qir_SEL_X_Y_NS(c,
571 qir_FSUB(c, trunc, qir_uniform_f(c, 1.0)),
572 trunc);
573 }
574
575 static struct qreg
576 tgsi_to_qir_dp(struct vc4_compile *c,
577 struct tgsi_full_instruction *tgsi_inst,
578 int num, struct qreg *src, int i)
579 {
580 struct qreg sum = qir_FMUL(c, src[0 * 4 + 0], src[1 * 4 + 0]);
581 for (int j = 1; j < num; j++) {
582 sum = qir_FADD(c, sum, qir_FMUL(c,
583 src[0 * 4 + j],
584 src[1 * 4 + j]));
585 }
586 return sum;
587 }
588
589 static struct qreg
590 tgsi_to_qir_dp2(struct vc4_compile *c,
591 struct tgsi_full_instruction *tgsi_inst,
592 enum qop op, struct qreg *src, int i)
593 {
594 return tgsi_to_qir_dp(c, tgsi_inst, 2, src, i);
595 }
596
597 static struct qreg
598 tgsi_to_qir_dp3(struct vc4_compile *c,
599 struct tgsi_full_instruction *tgsi_inst,
600 enum qop op, struct qreg *src, int i)
601 {
602 return tgsi_to_qir_dp(c, tgsi_inst, 3, src, i);
603 }
604
605 static struct qreg
606 tgsi_to_qir_dp4(struct vc4_compile *c,
607 struct tgsi_full_instruction *tgsi_inst,
608 enum qop op, struct qreg *src, int i)
609 {
610 return tgsi_to_qir_dp(c, tgsi_inst, 4, src, i);
611 }
612
613 static struct qreg
614 tgsi_to_qir_abs(struct vc4_compile *c,
615 struct tgsi_full_instruction *tgsi_inst,
616 enum qop op, struct qreg *src, int i)
617 {
618 struct qreg arg = src[0 * 4 + i];
619 return qir_FMAXABS(c, arg, arg);
620 }
621
622 /* Note that this instruction replicates its result from the x channel */
623 static struct qreg
624 tgsi_to_qir_sin(struct vc4_compile *c,
625 struct tgsi_full_instruction *tgsi_inst,
626 enum qop op, struct qreg *src, int i)
627 {
628 float coeff[] = {
629 2.0 * M_PI,
630 -pow(2.0 * M_PI, 3) / (3 * 2 * 1),
631 pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
632 -pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
633 };
634
635 struct qreg scaled_x =
636 qir_FMUL(c,
637 src[0 * 4 + 0],
638 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
639
640
641 struct qreg x = tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0);
642 struct qreg x2 = qir_FMUL(c, x, x);
643 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
644 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
645 x = qir_FMUL(c, x, x2);
646 sum = qir_FADD(c,
647 sum,
648 qir_FMUL(c,
649 x,
650 qir_uniform_f(c, coeff[i])));
651 }
652 return sum;
653 }
654
655 /* Note that this instruction replicates its result from the x channel */
656 static struct qreg
657 tgsi_to_qir_cos(struct vc4_compile *c,
658 struct tgsi_full_instruction *tgsi_inst,
659 enum qop op, struct qreg *src, int i)
660 {
661 float coeff[] = {
662 1.0f,
663 -pow(2.0 * M_PI, 2) / (2 * 1),
664 pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
665 -pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
666 };
667
668 struct qreg scaled_x =
669 qir_FMUL(c, src[0 * 4 + 0],
670 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
671 struct qreg x_frac = tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0);
672
673 struct qreg sum = qir_uniform_f(c, coeff[0]);
674 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
675 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
676 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
677 if (i != 1)
678 x = qir_FMUL(c, x, x2);
679
680 struct qreg mul = qir_FMUL(c,
681 x,
682 qir_uniform_f(c, coeff[i]));
683 if (i == 0)
684 sum = mul;
685 else
686 sum = qir_FADD(c, sum, mul);
687 }
688 return sum;
689 }
690
691 static void
692 emit_vertex_input(struct vc4_compile *c, int attr)
693 {
694 enum pipe_format format = c->vs_key->attr_formats[attr];
695 struct qreg vpm_reads[4];
696
697 /* Right now, we're setting the VPM offsets to be 16 bytes wide every
698 * time, so we always read 4 32-bit VPM entries.
699 */
700 for (int i = 0; i < 4; i++) {
701 vpm_reads[i] = qir_get_temp(c);
702 qir_emit(c, qir_inst(QOP_VPM_READ,
703 vpm_reads[i],
704 c->undef,
705 c->undef));
706 c->num_inputs++;
707 }
708
709 bool format_warned = false;
710 const struct util_format_description *desc =
711 util_format_description(format);
712
713 for (int i = 0; i < 4; i++) {
714 uint8_t swiz = desc->swizzle[i];
715
716 if (swiz <= UTIL_FORMAT_SWIZZLE_W &&
717 !format_warned &&
718 (desc->channel[swiz].type != UTIL_FORMAT_TYPE_FLOAT ||
719 desc->channel[swiz].size != 32)) {
720 fprintf(stderr,
721 "vtx element %d unsupported type: %s\n",
722 attr, util_format_name(format));
723 format_warned = true;
724 }
725
726 c->inputs[attr * 4 + i] =
727 get_swizzled_channel(c, vpm_reads, swiz);
728 }
729 }
730
731 static void
732 tgsi_to_qir_kill_if(struct vc4_compile *c, struct qreg *src, int i)
733 {
734 if (c->discard.file == QFILE_NULL)
735 c->discard = qir_uniform_f(c, 0.0);
736 qir_SF(c, src[0 * 4 + i]);
737 c->discard = qir_SEL_X_Y_NS(c, qir_uniform_f(c, 1.0),
738 c->discard);
739 }
740
741 static void
742 emit_fragcoord_input(struct vc4_compile *c, int attr)
743 {
744 c->inputs[attr * 4 + 0] = qir_FRAG_X(c);
745 c->inputs[attr * 4 + 1] = qir_FRAG_Y(c);
746 c->inputs[attr * 4 + 2] =
747 qir_FMUL(c,
748 qir_FRAG_Z(c),
749 qir_uniform_f(c, 1.0 / 0xffffff));
750 c->inputs[attr * 4 + 3] = qir_FRAG_RCP_W(c);
751 }
752
753 static struct qreg
754 emit_fragment_varying(struct vc4_compile *c, int index)
755 {
756 struct qreg vary = {
757 QFILE_VARY,
758 index
759 };
760
761 /* XXX: multiply by W */
762 return qir_VARY_ADD_C(c, qir_MOV(c, vary));
763 }
764
765 static void
766 emit_fragment_input(struct vc4_compile *c, int attr)
767 {
768 for (int i = 0; i < 4; i++) {
769 c->inputs[attr * 4 + i] =
770 emit_fragment_varying(c, attr * 4 + i);
771 c->num_inputs++;
772 }
773 }
774
775 static void
776 emit_tgsi_declaration(struct vc4_compile *c,
777 struct tgsi_full_declaration *decl)
778 {
779 switch (decl->Declaration.File) {
780 case TGSI_FILE_INPUT:
781 for (int i = decl->Range.First;
782 i <= decl->Range.Last;
783 i++) {
784 if (c->stage == QSTAGE_FRAG) {
785 if (decl->Semantic.Name ==
786 TGSI_SEMANTIC_POSITION) {
787 emit_fragcoord_input(c, i);
788 } else {
789 emit_fragment_input(c, i);
790 }
791 } else {
792 emit_vertex_input(c, i);
793 }
794 }
795 break;
796 }
797 }
798
799 static void
800 emit_tgsi_instruction(struct vc4_compile *c,
801 struct tgsi_full_instruction *tgsi_inst)
802 {
803 struct {
804 enum qop op;
805 struct qreg (*func)(struct vc4_compile *c,
806 struct tgsi_full_instruction *tgsi_inst,
807 enum qop op,
808 struct qreg *src, int i);
809 } op_trans[] = {
810 [TGSI_OPCODE_MOV] = { QOP_MOV, tgsi_to_qir_alu },
811 [TGSI_OPCODE_ABS] = { 0, tgsi_to_qir_abs },
812 [TGSI_OPCODE_MUL] = { QOP_FMUL, tgsi_to_qir_alu },
813 [TGSI_OPCODE_ADD] = { QOP_FADD, tgsi_to_qir_alu },
814 [TGSI_OPCODE_SUB] = { QOP_FSUB, tgsi_to_qir_alu },
815 [TGSI_OPCODE_MIN] = { QOP_FMIN, tgsi_to_qir_alu },
816 [TGSI_OPCODE_MAX] = { QOP_FMAX, tgsi_to_qir_alu },
817 [TGSI_OPCODE_F2I] = { QOP_FTOI, tgsi_to_qir_alu },
818 [TGSI_OPCODE_I2F] = { QOP_ITOF, tgsi_to_qir_alu },
819 [TGSI_OPCODE_UADD] = { QOP_ADD, tgsi_to_qir_alu },
820 [TGSI_OPCODE_USHR] = { QOP_SHR, tgsi_to_qir_alu },
821 [TGSI_OPCODE_ISHR] = { QOP_ASR, tgsi_to_qir_alu },
822 [TGSI_OPCODE_SHL] = { QOP_SHL, tgsi_to_qir_alu },
823 [TGSI_OPCODE_IMIN] = { QOP_MIN, tgsi_to_qir_alu },
824 [TGSI_OPCODE_IMAX] = { QOP_MAX, tgsi_to_qir_alu },
825 [TGSI_OPCODE_AND] = { QOP_AND, tgsi_to_qir_alu },
826 [TGSI_OPCODE_OR] = { QOP_OR, tgsi_to_qir_alu },
827 [TGSI_OPCODE_XOR] = { QOP_XOR, tgsi_to_qir_alu },
828 [TGSI_OPCODE_NOT] = { QOP_NOT, tgsi_to_qir_alu },
829
830 [TGSI_OPCODE_UMUL] = { 0, tgsi_to_qir_umul },
831 [TGSI_OPCODE_IDIV] = { 0, tgsi_to_qir_idiv },
832 [TGSI_OPCODE_INEG] = { 0, tgsi_to_qir_ineg },
833
834 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_alu },
835 [TGSI_OPCODE_SEQ] = { 0, tgsi_to_qir_seq },
836 [TGSI_OPCODE_SNE] = { 0, tgsi_to_qir_sne },
837 [TGSI_OPCODE_SGE] = { 0, tgsi_to_qir_sge },
838 [TGSI_OPCODE_SLT] = { 0, tgsi_to_qir_slt },
839 [TGSI_OPCODE_FSEQ] = { 0, tgsi_to_qir_fseq },
840 [TGSI_OPCODE_FSNE] = { 0, tgsi_to_qir_fsne },
841 [TGSI_OPCODE_FSGE] = { 0, tgsi_to_qir_fsge },
842 [TGSI_OPCODE_FSLT] = { 0, tgsi_to_qir_fslt },
843 [TGSI_OPCODE_USEQ] = { 0, tgsi_to_qir_useq },
844 [TGSI_OPCODE_USNE] = { 0, tgsi_to_qir_usne },
845 [TGSI_OPCODE_ISGE] = { 0, tgsi_to_qir_isge },
846 [TGSI_OPCODE_ISLT] = { 0, tgsi_to_qir_islt },
847
848 [TGSI_OPCODE_CMP] = { 0, tgsi_to_qir_cmp },
849 [TGSI_OPCODE_MAD] = { 0, tgsi_to_qir_mad },
850 [TGSI_OPCODE_DP2] = { 0, tgsi_to_qir_dp2 },
851 [TGSI_OPCODE_DP3] = { 0, tgsi_to_qir_dp3 },
852 [TGSI_OPCODE_DP4] = { 0, tgsi_to_qir_dp4 },
853 [TGSI_OPCODE_RCP] = { QOP_RCP, tgsi_to_qir_alu },
854 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_alu },
855 [TGSI_OPCODE_EX2] = { QOP_EXP2, tgsi_to_qir_alu },
856 [TGSI_OPCODE_LG2] = { QOP_LOG2, tgsi_to_qir_alu },
857 [TGSI_OPCODE_LIT] = { 0, tgsi_to_qir_lit },
858 [TGSI_OPCODE_LRP] = { 0, tgsi_to_qir_lrp },
859 [TGSI_OPCODE_POW] = { 0, tgsi_to_qir_pow },
860 [TGSI_OPCODE_TRUNC] = { 0, tgsi_to_qir_trunc },
861 [TGSI_OPCODE_FRC] = { 0, tgsi_to_qir_frc },
862 [TGSI_OPCODE_FLR] = { 0, tgsi_to_qir_flr },
863 [TGSI_OPCODE_SIN] = { 0, tgsi_to_qir_sin },
864 [TGSI_OPCODE_COS] = { 0, tgsi_to_qir_cos },
865 };
866 static int asdf = 0;
867 uint32_t tgsi_op = tgsi_inst->Instruction.Opcode;
868
869 if (tgsi_op == TGSI_OPCODE_END)
870 return;
871
872 struct qreg src_regs[12];
873 for (int s = 0; s < 3; s++) {
874 for (int i = 0; i < 4; i++) {
875 src_regs[4 * s + i] =
876 get_src(c, tgsi_inst->Instruction.Opcode,
877 &tgsi_inst->Src[s].Register, i);
878 }
879 }
880
881 switch (tgsi_op) {
882 case TGSI_OPCODE_TEX:
883 case TGSI_OPCODE_TXP:
884 case TGSI_OPCODE_TXB:
885 tgsi_to_qir_tex(c, tgsi_inst,
886 op_trans[tgsi_op].op, src_regs);
887 return;
888 case TGSI_OPCODE_KILL:
889 c->discard = qir_uniform_f(c, 1.0);
890 return;
891 case TGSI_OPCODE_KILL_IF:
892 for (int i = 0; i < 4; i++)
893 tgsi_to_qir_kill_if(c, src_regs, i);
894 return;
895 default:
896 break;
897 }
898
899 if (tgsi_op > ARRAY_SIZE(op_trans) || !(op_trans[tgsi_op].func)) {
900 fprintf(stderr, "unknown tgsi inst: ");
901 tgsi_dump_instruction(tgsi_inst, asdf++);
902 fprintf(stderr, "\n");
903 abort();
904 }
905
906 for (int i = 0; i < 4; i++) {
907 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
908 continue;
909
910 struct qreg result;
911
912 result = op_trans[tgsi_op].func(c, tgsi_inst,
913 op_trans[tgsi_op].op,
914 src_regs, i);
915
916 if (tgsi_inst->Instruction.Saturate) {
917 float low = (tgsi_inst->Instruction.Saturate ==
918 TGSI_SAT_MINUS_PLUS_ONE ? -1.0 : 0.0);
919 result = qir_FMAX(c,
920 qir_FMIN(c,
921 result,
922 qir_uniform_f(c, 1.0)),
923 qir_uniform_f(c, low));
924 }
925
926 update_dst(c, tgsi_inst, i, result);
927 }
928 }
929
930 static void
931 parse_tgsi_immediate(struct vc4_compile *c, struct tgsi_full_immediate *imm)
932 {
933 for (int i = 0; i < 4; i++) {
934 unsigned n = c->num_consts++;
935 c->consts[n] = qir_uniform_ui(c, imm->u[i].Uint);
936 }
937 }
938
939 static struct qreg
940 vc4_blend_channel(struct vc4_compile *c,
941 struct qreg *dst,
942 struct qreg *src,
943 struct qreg val,
944 unsigned factor,
945 int channel)
946 {
947 switch(factor) {
948 case PIPE_BLENDFACTOR_ONE:
949 return val;
950 case PIPE_BLENDFACTOR_SRC_COLOR:
951 return qir_FMUL(c, val, src[channel]);
952 case PIPE_BLENDFACTOR_SRC_ALPHA:
953 return qir_FMUL(c, val, src[3]);
954 case PIPE_BLENDFACTOR_DST_ALPHA:
955 return qir_FMUL(c, val, dst[3]);
956 case PIPE_BLENDFACTOR_DST_COLOR:
957 return qir_FMUL(c, val, dst[channel]);
958 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
959 return qir_FMIN(c, src[3], qir_FSUB(c,
960 qir_uniform_f(c, 1.0),
961 dst[3]));
962 case PIPE_BLENDFACTOR_CONST_COLOR:
963 return qir_FMUL(c, val,
964 get_temp_for_uniform(c,
965 QUNIFORM_BLEND_CONST_COLOR,
966 channel));
967 case PIPE_BLENDFACTOR_CONST_ALPHA:
968 return qir_FMUL(c, val,
969 get_temp_for_uniform(c,
970 QUNIFORM_BLEND_CONST_COLOR,
971 3));
972 case PIPE_BLENDFACTOR_ZERO:
973 return qir_uniform_f(c, 0.0);
974 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
975 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
976 src[channel]));
977 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
978 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
979 src[3]));
980 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
981 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
982 dst[3]));
983 case PIPE_BLENDFACTOR_INV_DST_COLOR:
984 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
985 dst[channel]));
986 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
987 return qir_FMUL(c, val,
988 qir_FSUB(c, qir_uniform_f(c, 1.0),
989 get_temp_for_uniform(c,
990 QUNIFORM_BLEND_CONST_COLOR,
991 channel)));
992 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
993 return qir_FMUL(c, val,
994 qir_FSUB(c, qir_uniform_f(c, 1.0),
995 get_temp_for_uniform(c,
996 QUNIFORM_BLEND_CONST_COLOR,
997 3)));
998
999 default:
1000 case PIPE_BLENDFACTOR_SRC1_COLOR:
1001 case PIPE_BLENDFACTOR_SRC1_ALPHA:
1002 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
1003 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
1004 /* Unsupported. */
1005 fprintf(stderr, "Unknown blend factor %d\n", factor);
1006 return val;
1007 }
1008 }
1009
1010 static struct qreg
1011 vc4_blend_func(struct vc4_compile *c,
1012 struct qreg src, struct qreg dst,
1013 unsigned func)
1014 {
1015 switch (func) {
1016 case PIPE_BLEND_ADD:
1017 return qir_FADD(c, src, dst);
1018 case PIPE_BLEND_SUBTRACT:
1019 return qir_FSUB(c, src, dst);
1020 case PIPE_BLEND_REVERSE_SUBTRACT:
1021 return qir_FSUB(c, dst, src);
1022 case PIPE_BLEND_MIN:
1023 return qir_FMIN(c, src, dst);
1024 case PIPE_BLEND_MAX:
1025 return qir_FMAX(c, src, dst);
1026
1027 default:
1028 /* Unsupported. */
1029 fprintf(stderr, "Unknown blend func %d\n", func);
1030 return src;
1031
1032 }
1033 }
1034
1035 /**
1036 * Implements fixed function blending in shader code.
1037 *
1038 * VC4 doesn't have any hardware support for blending. Instead, you read the
1039 * current contents of the destination from the tile buffer after having
1040 * waited for the scoreboard (which is handled by vc4_qpu_emit.c), then do
1041 * math using your output color and that destination value, and update the
1042 * output color appropriately.
1043 */
1044 static void
1045 vc4_blend(struct vc4_compile *c, struct qreg *result,
1046 struct qreg *dst_color, struct qreg *src_color)
1047 {
1048 struct pipe_rt_blend_state *blend = &c->fs_key->blend;
1049
1050 if (!blend->blend_enable) {
1051 for (int i = 0; i < 4; i++)
1052 result[i] = src_color[i];
1053 return;
1054 }
1055
1056 struct qreg src_blend[4], dst_blend[4];
1057 for (int i = 0; i < 3; i++) {
1058 src_blend[i] = vc4_blend_channel(c,
1059 dst_color, src_color,
1060 src_color[i],
1061 blend->rgb_src_factor, i);
1062 dst_blend[i] = vc4_blend_channel(c,
1063 dst_color, src_color,
1064 dst_color[i],
1065 blend->rgb_dst_factor, i);
1066 }
1067 src_blend[3] = vc4_blend_channel(c,
1068 dst_color, src_color,
1069 src_color[3],
1070 blend->alpha_src_factor, 3);
1071 dst_blend[3] = vc4_blend_channel(c,
1072 dst_color, src_color,
1073 dst_color[3],
1074 blend->alpha_dst_factor, 3);
1075
1076 for (int i = 0; i < 3; i++) {
1077 result[i] = vc4_blend_func(c,
1078 src_blend[i], dst_blend[i],
1079 blend->rgb_func);
1080 }
1081 result[3] = vc4_blend_func(c,
1082 src_blend[3], dst_blend[3],
1083 blend->alpha_func);
1084 }
1085
1086 static void
1087 emit_frag_end(struct vc4_compile *c)
1088 {
1089 struct qreg src_color[4] = {
1090 c->outputs[0], c->outputs[1], c->outputs[2], c->outputs[3],
1091 };
1092
1093 enum pipe_format color_format = c->fs_key->color_format;
1094 const uint8_t *format_swiz = vc4_get_format_swizzle(color_format);
1095 struct qreg tlb_read_color[4] = { c->undef, c->undef, c->undef, c->undef };
1096 struct qreg dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1097 if (c->fs_key->blend.blend_enable ||
1098 c->fs_key->blend.colormask != 0xf) {
1099 qir_emit(c, qir_inst(QOP_TLB_COLOR_READ, c->undef,
1100 c->undef, c->undef));
1101 for (int i = 0; i < 4; i++)
1102 tlb_read_color[i] = qir_R4_UNPACK(c, i);
1103 for (int i = 0; i < 4; i++)
1104 dst_color[i] = get_swizzled_channel(c,
1105 tlb_read_color,
1106 format_swiz[i]);
1107 }
1108
1109 struct qreg blend_color[4];
1110 vc4_blend(c, blend_color, dst_color, src_color);
1111
1112 /* If the bit isn't set in the color mask, then just return the
1113 * original dst color, instead.
1114 */
1115 for (int i = 0; i < 4; i++) {
1116 if (!(c->fs_key->blend.colormask & (1 << i))) {
1117 blend_color[i] = dst_color[i];
1118 }
1119 }
1120
1121 /* Debug: Sometimes you're getting a black output and just want to see
1122 * if the FS is getting executed at all. Spam magenta into the color
1123 * output.
1124 */
1125 if (0) {
1126 blend_color[0] = qir_uniform_f(c, 1.0);
1127 blend_color[1] = qir_uniform_f(c, 0.0);
1128 blend_color[2] = qir_uniform_f(c, 1.0);
1129 blend_color[3] = qir_uniform_f(c, 0.5);
1130 }
1131
1132 struct qreg swizzled_outputs[4];
1133 for (int i = 0; i < 4; i++) {
1134 swizzled_outputs[i] = get_swizzled_channel(c, blend_color,
1135 format_swiz[i]);
1136 }
1137
1138 if (c->discard.file != QFILE_NULL)
1139 qir_TLB_DISCARD_SETUP(c, c->discard);
1140
1141 if (c->fs_key->depth_enabled) {
1142 qir_emit(c, qir_inst(QOP_TLB_PASSTHROUGH_Z_WRITE, c->undef,
1143 c->undef, c->undef));
1144 }
1145
1146 bool color_written = false;
1147 for (int i = 0; i < 4; i++) {
1148 if (swizzled_outputs[i].file != QFILE_NULL)
1149 color_written = true;
1150 }
1151
1152 struct qreg packed_color;
1153 if (color_written) {
1154 /* Fill in any undefined colors. The simulator will assertion
1155 * fail if we read something that wasn't written, and I don't
1156 * know what hardware does.
1157 */
1158 for (int i = 0; i < 4; i++) {
1159 if (swizzled_outputs[i].file == QFILE_NULL)
1160 swizzled_outputs[i] = qir_uniform_f(c, 0.0);
1161 }
1162 packed_color = qir_get_temp(c);
1163 qir_emit(c, qir_inst4(QOP_PACK_COLORS, packed_color,
1164 swizzled_outputs[0],
1165 swizzled_outputs[1],
1166 swizzled_outputs[2],
1167 swizzled_outputs[3]));
1168 } else {
1169 packed_color = qir_uniform_ui(c, 0);
1170 }
1171
1172 qir_emit(c, qir_inst(QOP_TLB_COLOR_WRITE, c->undef,
1173 packed_color, c->undef));
1174 }
1175
1176 static void
1177 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1178 {
1179 struct qreg xyi[2];
1180
1181 for (int i = 0; i < 2; i++) {
1182 struct qreg scale =
1183 add_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1184
1185 xyi[i] = qir_FTOI(c, qir_FMUL(c,
1186 qir_FMUL(c,
1187 c->outputs[i],
1188 scale),
1189 rcp_w));
1190 }
1191
1192 qir_VPM_WRITE(c, qir_PACK_SCALED(c, xyi[0], xyi[1]));
1193 }
1194
1195 static void
1196 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1197 {
1198 struct qreg zscale = add_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1199 struct qreg zoffset = add_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1200
1201 qir_VPM_WRITE(c, qir_FMUL(c, qir_FADD(c, qir_FMUL(c,
1202 c->outputs[2],
1203 zscale),
1204 zoffset),
1205 rcp_w));
1206 }
1207
1208 static void
1209 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1210 {
1211 qir_VPM_WRITE(c, rcp_w);
1212 }
1213
1214 static void
1215 emit_vert_end(struct vc4_compile *c)
1216 {
1217 struct qreg rcp_w = qir_RCP(c, c->outputs[3]);
1218
1219 emit_scaled_viewport_write(c, rcp_w);
1220 emit_zs_write(c, rcp_w);
1221 emit_rcp_wc_write(c, rcp_w);
1222
1223 for (int i = 4; i < c->num_outputs; i++) {
1224 qir_VPM_WRITE(c, c->outputs[i]);
1225 }
1226 }
1227
1228 static void
1229 emit_coord_end(struct vc4_compile *c)
1230 {
1231 struct qreg rcp_w = qir_RCP(c, c->outputs[3]);
1232
1233 for (int i = 0; i < 4; i++)
1234 qir_VPM_WRITE(c, c->outputs[i]);
1235
1236 emit_scaled_viewport_write(c, rcp_w);
1237 emit_zs_write(c, rcp_w);
1238 emit_rcp_wc_write(c, rcp_w);
1239 }
1240
1241 static struct vc4_compile *
1242 vc4_shader_tgsi_to_qir(struct vc4_compiled_shader *shader, enum qstage stage,
1243 struct vc4_key *key)
1244 {
1245 struct vc4_compile *c = qir_compile_init();
1246 int ret;
1247
1248 c->stage = stage;
1249
1250 /* XXX sizing */
1251 c->temps = calloc(sizeof(struct qreg), 1024);
1252 c->inputs = calloc(sizeof(struct qreg), 8 * 4);
1253 c->outputs = calloc(sizeof(struct qreg), 1024);
1254 c->uniforms = calloc(sizeof(struct qreg), 1024);
1255 c->consts = calloc(sizeof(struct qreg), 1024);
1256
1257 c->uniform_data = calloc(sizeof(uint32_t), 1024);
1258 c->uniform_contents = calloc(sizeof(enum quniform_contents), 1024);
1259
1260 c->shader_state = key->shader_state;
1261 ret = tgsi_parse_init(&c->parser, c->shader_state->tokens);
1262 assert(ret == TGSI_PARSE_OK);
1263
1264 if (vc4_debug & VC4_DEBUG_TGSI) {
1265 fprintf(stderr, "TGSI:\n");
1266 tgsi_dump(c->shader_state->tokens, 0);
1267 }
1268
1269 c->key = key;
1270 switch (stage) {
1271 case QSTAGE_FRAG:
1272 c->fs_key = (struct vc4_fs_key *)key;
1273 if (c->fs_key->is_points) {
1274 c->point_x = emit_fragment_varying(c, 0);
1275 c->point_y = emit_fragment_varying(c, 0);
1276 } else if (c->fs_key->is_lines) {
1277 c->line_x = emit_fragment_varying(c, 0);
1278 }
1279 break;
1280 case QSTAGE_VERT:
1281 c->vs_key = (struct vc4_vs_key *)key;
1282 break;
1283 case QSTAGE_COORD:
1284 c->vs_key = (struct vc4_vs_key *)key;
1285 break;
1286 }
1287
1288 while (!tgsi_parse_end_of_tokens(&c->parser)) {
1289 tgsi_parse_token(&c->parser);
1290
1291 switch (c->parser.FullToken.Token.Type) {
1292 case TGSI_TOKEN_TYPE_DECLARATION:
1293 emit_tgsi_declaration(c,
1294 &c->parser.FullToken.FullDeclaration);
1295 break;
1296
1297 case TGSI_TOKEN_TYPE_INSTRUCTION:
1298 emit_tgsi_instruction(c,
1299 &c->parser.FullToken.FullInstruction);
1300 break;
1301
1302 case TGSI_TOKEN_TYPE_IMMEDIATE:
1303 parse_tgsi_immediate(c,
1304 &c->parser.FullToken.FullImmediate);
1305 break;
1306 }
1307 }
1308
1309 switch (stage) {
1310 case QSTAGE_FRAG:
1311 emit_frag_end(c);
1312 break;
1313 case QSTAGE_VERT:
1314 emit_vert_end(c);
1315 break;
1316 case QSTAGE_COORD:
1317 emit_coord_end(c);
1318 break;
1319 }
1320
1321 tgsi_parse_free(&c->parser);
1322 free(c->temps);
1323
1324 qir_optimize(c);
1325
1326 if (vc4_debug & VC4_DEBUG_QIR) {
1327 fprintf(stderr, "QIR:\n");
1328 qir_dump(c);
1329 }
1330 vc4_generate_code(c);
1331
1332 if (vc4_debug & VC4_DEBUG_SHADERDB) {
1333 fprintf(stderr, "SHADER-DB: %s: %d instructions\n",
1334 qir_get_stage_name(c->stage), c->qpu_inst_count);
1335 fprintf(stderr, "SHADER-DB: %s: %d uniforms\n",
1336 qir_get_stage_name(c->stage), c->num_uniforms);
1337 }
1338
1339 return c;
1340 }
1341
1342 static void *
1343 vc4_shader_state_create(struct pipe_context *pctx,
1344 const struct pipe_shader_state *cso)
1345 {
1346 struct pipe_shader_state *so = CALLOC_STRUCT(pipe_shader_state);
1347 if (!so)
1348 return NULL;
1349
1350 so->tokens = tgsi_dup_tokens(cso->tokens);
1351
1352 return so;
1353 }
1354
1355 static void
1356 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
1357 int shader_index,
1358 struct vc4_compile *c)
1359 {
1360 int count = c->num_uniforms;
1361 struct vc4_shader_uniform_info *uinfo = &shader->uniforms[shader_index];
1362
1363 uinfo->count = count;
1364 uinfo->data = malloc(count * sizeof(*uinfo->data));
1365 memcpy(uinfo->data, c->uniform_data,
1366 count * sizeof(*uinfo->data));
1367 uinfo->contents = malloc(count * sizeof(*uinfo->contents));
1368 memcpy(uinfo->contents, c->uniform_contents,
1369 count * sizeof(*uinfo->contents));
1370 uinfo->num_texture_samples = c->num_texture_samples;
1371 }
1372
1373 static void
1374 vc4_fs_compile(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1375 struct vc4_fs_key *key)
1376 {
1377 struct vc4_compile *c = vc4_shader_tgsi_to_qir(shader, QSTAGE_FRAG,
1378 &key->base);
1379 shader->num_inputs = c->num_inputs;
1380 copy_uniform_state_to_shader(shader, 0, c);
1381 shader->bo = vc4_bo_alloc_mem(vc4->screen, c->qpu_insts,
1382 c->qpu_inst_count * sizeof(uint64_t),
1383 "fs_code");
1384
1385 qir_compile_destroy(c);
1386 }
1387
1388 static void
1389 vc4_vs_compile(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1390 struct vc4_vs_key *key)
1391 {
1392 struct vc4_compile *vs_c = vc4_shader_tgsi_to_qir(shader,
1393 QSTAGE_VERT,
1394 &key->base);
1395 copy_uniform_state_to_shader(shader, 0, vs_c);
1396
1397 struct vc4_compile *cs_c = vc4_shader_tgsi_to_qir(shader,
1398 QSTAGE_COORD,
1399 &key->base);
1400 copy_uniform_state_to_shader(shader, 1, cs_c);
1401
1402 uint32_t vs_size = vs_c->qpu_inst_count * sizeof(uint64_t);
1403 uint32_t cs_size = cs_c->qpu_inst_count * sizeof(uint64_t);
1404 shader->coord_shader_offset = vs_size; /* XXX: alignment? */
1405 shader->bo = vc4_bo_alloc(vc4->screen,
1406 shader->coord_shader_offset + cs_size,
1407 "vs_code");
1408
1409 void *map = vc4_bo_map(shader->bo);
1410 memcpy(map, vs_c->qpu_insts, vs_size);
1411 memcpy(map + shader->coord_shader_offset,
1412 cs_c->qpu_insts, cs_size);
1413
1414 qir_compile_destroy(vs_c);
1415 qir_compile_destroy(cs_c);
1416 }
1417
1418 static void
1419 vc4_setup_shared_key(struct vc4_key *key, struct vc4_texture_stateobj *texstate)
1420 {
1421 for (int i = 0; i < texstate->num_textures; i++) {
1422 struct pipe_sampler_view *sampler = texstate->textures[i];
1423 if (sampler) {
1424 struct pipe_resource *prsc = sampler->texture;
1425 key->tex_format[i] = prsc->format;
1426 }
1427 }
1428 }
1429
1430 static void
1431 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
1432 {
1433 struct vc4_fs_key local_key;
1434 struct vc4_fs_key *key = &local_key;
1435
1436 memset(key, 0, sizeof(*key));
1437 vc4_setup_shared_key(&key->base, &vc4->fragtex);
1438 key->base.shader_state = vc4->prog.bind_fs;
1439 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
1440 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
1441 prim_mode <= PIPE_PRIM_LINE_STRIP);
1442 key->blend = vc4->blend->rt[0];
1443
1444 if (vc4->framebuffer.cbufs[0])
1445 key->color_format = vc4->framebuffer.cbufs[0]->format;
1446
1447 key->depth_enabled = vc4->zsa->base.depth.enabled;
1448
1449 vc4->prog.fs = util_hash_table_get(vc4->fs_cache, key);
1450 if (vc4->prog.fs)
1451 return;
1452
1453 key = malloc(sizeof(*key));
1454 memcpy(key, &local_key, sizeof(*key));
1455
1456 struct vc4_compiled_shader *shader = CALLOC_STRUCT(vc4_compiled_shader);
1457 vc4_fs_compile(vc4, shader, key);
1458 util_hash_table_set(vc4->fs_cache, key, shader);
1459
1460 vc4->prog.fs = shader;
1461 }
1462
1463 static void
1464 vc4_update_compiled_vs(struct vc4_context *vc4)
1465 {
1466 struct vc4_vs_key local_key;
1467 struct vc4_vs_key *key = &local_key;
1468
1469 memset(key, 0, sizeof(*key));
1470 vc4_setup_shared_key(&key->base, &vc4->verttex);
1471 key->base.shader_state = vc4->prog.bind_vs;
1472
1473 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
1474 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
1475
1476 vc4->prog.vs = util_hash_table_get(vc4->vs_cache, key);
1477 if (vc4->prog.vs)
1478 return;
1479
1480 key = malloc(sizeof(*key));
1481 memcpy(key, &local_key, sizeof(*key));
1482
1483 struct vc4_compiled_shader *shader = CALLOC_STRUCT(vc4_compiled_shader);
1484 vc4_vs_compile(vc4, shader, key);
1485 util_hash_table_set(vc4->vs_cache, key, shader);
1486
1487 vc4->prog.vs = shader;
1488 }
1489
1490 void
1491 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
1492 {
1493 vc4_update_compiled_fs(vc4, prim_mode);
1494 vc4_update_compiled_vs(vc4);
1495 }
1496
1497 static unsigned
1498 fs_cache_hash(void *key)
1499 {
1500 return util_hash_crc32(key, sizeof(struct vc4_fs_key));
1501 }
1502
1503 static unsigned
1504 vs_cache_hash(void *key)
1505 {
1506 return util_hash_crc32(key, sizeof(struct vc4_vs_key));
1507 }
1508
1509 static int
1510 fs_cache_compare(void *key1, void *key2)
1511 {
1512 return memcmp(key1, key2, sizeof(struct vc4_fs_key));
1513 }
1514
1515 static int
1516 vs_cache_compare(void *key1, void *key2)
1517 {
1518 return memcmp(key1, key2, sizeof(struct vc4_vs_key));
1519 }
1520
1521 struct delete_state {
1522 struct vc4_context *vc4;
1523 struct pipe_shader_state *shader_state;
1524 };
1525
1526 static enum pipe_error
1527 fs_delete_from_cache(void *in_key, void *in_value, void *data)
1528 {
1529 struct delete_state *del = data;
1530 struct vc4_fs_key *key = in_key;
1531 struct vc4_compiled_shader *shader = in_value;
1532
1533 if (key->base.shader_state == data) {
1534 util_hash_table_remove(del->vc4->fs_cache, key);
1535 vc4_bo_unreference(&shader->bo);
1536 free(shader);
1537 }
1538
1539 return 0;
1540 }
1541
1542 static enum pipe_error
1543 vs_delete_from_cache(void *in_key, void *in_value, void *data)
1544 {
1545 struct delete_state *del = data;
1546 struct vc4_vs_key *key = in_key;
1547 struct vc4_compiled_shader *shader = in_value;
1548
1549 if (key->base.shader_state == data) {
1550 util_hash_table_remove(del->vc4->vs_cache, key);
1551 vc4_bo_unreference(&shader->bo);
1552 free(shader);
1553 }
1554
1555 return 0;
1556 }
1557
1558 static void
1559 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
1560 {
1561 struct vc4_context *vc4 = vc4_context(pctx);
1562 struct pipe_shader_state *so = hwcso;
1563 struct delete_state del;
1564
1565 del.vc4 = vc4;
1566 del.shader_state = so;
1567 util_hash_table_foreach(vc4->fs_cache, fs_delete_from_cache, &del);
1568 util_hash_table_foreach(vc4->vs_cache, vs_delete_from_cache, &del);
1569
1570 free((void *)so->tokens);
1571 free(so);
1572 }
1573
1574 static uint32_t translate_wrap(uint32_t p_wrap)
1575 {
1576 switch (p_wrap) {
1577 case PIPE_TEX_WRAP_REPEAT:
1578 return 0;
1579 case PIPE_TEX_WRAP_CLAMP:
1580 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1581 return 1;
1582 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1583 return 2;
1584 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1585 return 3;
1586 default:
1587 fprintf(stderr, "Unknown wrap mode %d\n", p_wrap);
1588 assert(!"not reached");
1589 return 0;
1590 }
1591 }
1592
1593 static void
1594 write_texture_p0(struct vc4_context *vc4,
1595 struct vc4_texture_stateobj *texstate,
1596 uint32_t unit)
1597 {
1598 struct pipe_sampler_view *texture = texstate->textures[unit];
1599 struct vc4_resource *rsc = vc4_resource(texture->texture);
1600
1601 cl_reloc(vc4, &vc4->uniforms, rsc->bo,
1602 rsc->slices[0].offset | texture->u.tex.last_level |
1603 ((rsc->vc4_format & 7) << 4));
1604 }
1605
1606 static void
1607 write_texture_p1(struct vc4_context *vc4,
1608 struct vc4_texture_stateobj *texstate,
1609 uint32_t unit)
1610 {
1611 struct pipe_sampler_view *texture = texstate->textures[unit];
1612 struct vc4_resource *rsc = vc4_resource(texture->texture);
1613 struct pipe_sampler_state *sampler = texstate->samplers[unit];
1614 static const uint32_t mipfilter_map[] = {
1615 [PIPE_TEX_MIPFILTER_NEAREST] = 2,
1616 [PIPE_TEX_MIPFILTER_LINEAR] = 4,
1617 [PIPE_TEX_MIPFILTER_NONE] = 0
1618 };
1619 static const uint32_t imgfilter_map[] = {
1620 [PIPE_TEX_FILTER_NEAREST] = 1,
1621 [PIPE_TEX_FILTER_LINEAR] = 0,
1622 };
1623
1624 cl_u32(&vc4->uniforms,
1625 ((rsc->vc4_format >> 4) << 31) |
1626 (texture->texture->height0 << 20) |
1627 (texture->texture->width0 << 8) |
1628 (imgfilter_map[sampler->mag_img_filter] << 7) |
1629 ((imgfilter_map[sampler->min_img_filter] +
1630 mipfilter_map[sampler->min_mip_filter]) << 4) |
1631 (translate_wrap(sampler->wrap_t) << 2) |
1632 (translate_wrap(sampler->wrap_s) << 0));
1633 }
1634
1635 static uint32_t
1636 get_texrect_scale(struct vc4_texture_stateobj *texstate,
1637 enum quniform_contents contents,
1638 uint32_t data)
1639 {
1640 struct pipe_sampler_view *texture = texstate->textures[data];
1641 uint32_t dim;
1642
1643 if (contents == QUNIFORM_TEXRECT_SCALE_X)
1644 dim = texture->texture->width0;
1645 else
1646 dim = texture->texture->height0;
1647
1648 return fui(1.0f / dim);
1649 }
1650
1651 void
1652 vc4_write_uniforms(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1653 struct vc4_constbuf_stateobj *cb,
1654 struct vc4_texture_stateobj *texstate,
1655 int shader_index)
1656 {
1657 struct vc4_shader_uniform_info *uinfo = &shader->uniforms[shader_index];
1658 const uint32_t *gallium_uniforms = cb->cb[0].user_buffer;
1659
1660 cl_start_shader_reloc(&vc4->uniforms, uinfo->num_texture_samples);
1661
1662 for (int i = 0; i < uinfo->count; i++) {
1663
1664 switch (uinfo->contents[i]) {
1665 case QUNIFORM_CONSTANT:
1666 cl_u32(&vc4->uniforms, uinfo->data[i]);
1667 break;
1668 case QUNIFORM_UNIFORM:
1669 cl_u32(&vc4->uniforms,
1670 gallium_uniforms[uinfo->data[i]]);
1671 break;
1672 case QUNIFORM_VIEWPORT_X_SCALE:
1673 cl_f(&vc4->uniforms, vc4->viewport.scale[0] * 16.0f);
1674 break;
1675 case QUNIFORM_VIEWPORT_Y_SCALE:
1676 cl_f(&vc4->uniforms, vc4->viewport.scale[1] * 16.0f);
1677 break;
1678
1679 case QUNIFORM_VIEWPORT_Z_OFFSET:
1680 cl_f(&vc4->uniforms, vc4->viewport.translate[2]);
1681 break;
1682 case QUNIFORM_VIEWPORT_Z_SCALE:
1683 cl_f(&vc4->uniforms, vc4->viewport.scale[2]);
1684 break;
1685
1686 case QUNIFORM_TEXTURE_CONFIG_P0:
1687 write_texture_p0(vc4, texstate, uinfo->data[i]);
1688 break;
1689
1690 case QUNIFORM_TEXTURE_CONFIG_P1:
1691 write_texture_p1(vc4, texstate, uinfo->data[i]);
1692 break;
1693
1694 case QUNIFORM_TEXRECT_SCALE_X:
1695 case QUNIFORM_TEXRECT_SCALE_Y:
1696 cl_u32(&vc4->uniforms,
1697 get_texrect_scale(texstate,
1698 uinfo->contents[i],
1699 uinfo->data[i]));
1700 break;
1701
1702 case QUNIFORM_BLEND_CONST_COLOR:
1703 cl_f(&vc4->uniforms,
1704 vc4->blend_color.color[uinfo->data[i]]);
1705 break;
1706 }
1707 #if 0
1708 uint32_t written_val = *(uint32_t *)(vc4->uniforms.next - 4);
1709 fprintf(stderr, "%p/%d: %d: 0x%08x (%f)\n",
1710 shader, shader_index, i, written_val, uif(written_val));
1711 #endif
1712 }
1713 }
1714
1715 static void
1716 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
1717 {
1718 struct vc4_context *vc4 = vc4_context(pctx);
1719 vc4->prog.bind_fs = hwcso;
1720 vc4->prog.dirty |= VC4_SHADER_DIRTY_FP;
1721 vc4->dirty |= VC4_DIRTY_PROG;
1722 }
1723
1724 static void
1725 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
1726 {
1727 struct vc4_context *vc4 = vc4_context(pctx);
1728 vc4->prog.bind_vs = hwcso;
1729 vc4->prog.dirty |= VC4_SHADER_DIRTY_VP;
1730 vc4->dirty |= VC4_DIRTY_PROG;
1731 }
1732
1733 void
1734 vc4_program_init(struct pipe_context *pctx)
1735 {
1736 struct vc4_context *vc4 = vc4_context(pctx);
1737
1738 pctx->create_vs_state = vc4_shader_state_create;
1739 pctx->delete_vs_state = vc4_shader_state_delete;
1740
1741 pctx->create_fs_state = vc4_shader_state_create;
1742 pctx->delete_fs_state = vc4_shader_state_delete;
1743
1744 pctx->bind_fs_state = vc4_fp_state_bind;
1745 pctx->bind_vs_state = vc4_vp_state_bind;
1746
1747 vc4->fs_cache = util_hash_table_create(fs_cache_hash, fs_cache_compare);
1748 vc4->vs_cache = util_hash_table_create(vs_cache_hash, vs_cache_compare);
1749 }