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vc4: Start using tgsi_lowering for opcodes we haven't supported before.
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "pipe/p_state.h"
27 #include "util/u_format.h"
28 #include "util/u_hash_table.h"
29 #include "util/u_hash.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include "util/format_srgb.h"
33 #include "util/ralloc.h"
34 #include "tgsi/tgsi_dump.h"
35 #include "tgsi/tgsi_info.h"
36 #include "tgsi/tgsi_lowering.h"
37
38 #include "vc4_context.h"
39 #include "vc4_qpu.h"
40 #include "vc4_qir.h"
41 #ifdef USE_VC4_SIMULATOR
42 #include "simpenrose/simpenrose.h"
43 #endif
44
45 struct vc4_key {
46 struct pipe_shader_state *shader_state;
47 struct {
48 enum pipe_format format;
49 unsigned compare_mode:1;
50 unsigned compare_func:3;
51 unsigned wrap_s:3;
52 unsigned wrap_t:3;
53 uint8_t swizzle[4];
54 } tex[VC4_MAX_TEXTURE_SAMPLERS];
55 };
56
57 struct vc4_fs_key {
58 struct vc4_key base;
59 enum pipe_format color_format;
60 bool depth_enabled;
61 bool stencil_enabled;
62 bool stencil_twoside;
63 bool stencil_full_writemasks;
64 bool is_points;
65 bool is_lines;
66 bool alpha_test;
67 bool point_coord_upper_left;
68 uint8_t alpha_test_func;
69 uint32_t point_sprite_mask;
70
71 struct pipe_rt_blend_state blend;
72 };
73
74 struct vc4_vs_key {
75 struct vc4_key base;
76 enum pipe_format attr_formats[8];
77 bool per_vertex_point_size;
78 };
79
80 static void
81 resize_qreg_array(struct vc4_compile *c,
82 struct qreg **regs,
83 uint32_t *size,
84 uint32_t decl_size)
85 {
86 if (*size >= decl_size)
87 return;
88
89 uint32_t old_size = *size;
90 *size = MAX2(*size * 2, decl_size);
91 *regs = reralloc(c, *regs, struct qreg, *size);
92 if (!*regs) {
93 fprintf(stderr, "Malloc failure\n");
94 abort();
95 }
96
97 for (uint32_t i = old_size; i < *size; i++)
98 (*regs)[i] = c->undef;
99 }
100
101 static struct qreg
102 add_uniform(struct vc4_compile *c,
103 enum quniform_contents contents,
104 uint32_t data)
105 {
106 uint32_t uniform = c->num_uniforms++;
107 struct qreg u = { QFILE_UNIF, uniform };
108
109 if (uniform >= c->uniform_array_size) {
110 c->uniform_array_size = MAX2(MAX2(16, uniform + 1),
111 c->uniform_array_size * 2);
112
113 c->uniform_data = reralloc(c, c->uniform_data,
114 uint32_t,
115 c->uniform_array_size);
116 c->uniform_contents = reralloc(c, c->uniform_contents,
117 enum quniform_contents,
118 c->uniform_array_size);
119 }
120
121 c->uniform_contents[uniform] = contents;
122 c->uniform_data[uniform] = data;
123
124 return u;
125 }
126
127 static struct qreg
128 get_temp_for_uniform(struct vc4_compile *c, enum quniform_contents contents,
129 uint32_t data)
130 {
131 struct qreg u = add_uniform(c, contents, data);
132 struct qreg t = qir_MOV(c, u);
133 return t;
134 }
135
136 static struct qreg
137 qir_uniform_ui(struct vc4_compile *c, uint32_t ui)
138 {
139 return get_temp_for_uniform(c, QUNIFORM_CONSTANT, ui);
140 }
141
142 static struct qreg
143 qir_uniform_f(struct vc4_compile *c, float f)
144 {
145 return qir_uniform_ui(c, fui(f));
146 }
147
148 static struct qreg
149 get_src(struct vc4_compile *c, unsigned tgsi_op,
150 struct tgsi_src_register *src, int i)
151 {
152 struct qreg r = c->undef;
153
154 uint32_t s = i;
155 switch (i) {
156 case TGSI_SWIZZLE_X:
157 s = src->SwizzleX;
158 break;
159 case TGSI_SWIZZLE_Y:
160 s = src->SwizzleY;
161 break;
162 case TGSI_SWIZZLE_Z:
163 s = src->SwizzleZ;
164 break;
165 case TGSI_SWIZZLE_W:
166 s = src->SwizzleW;
167 break;
168 default:
169 abort();
170 }
171
172 assert(!src->Indirect);
173
174 switch (src->File) {
175 case TGSI_FILE_NULL:
176 return r;
177 case TGSI_FILE_TEMPORARY:
178 r = c->temps[src->Index * 4 + s];
179 break;
180 case TGSI_FILE_IMMEDIATE:
181 r = c->consts[src->Index * 4 + s];
182 break;
183 case TGSI_FILE_CONSTANT:
184 r = get_temp_for_uniform(c, QUNIFORM_UNIFORM,
185 src->Index * 4 + s);
186 break;
187 case TGSI_FILE_INPUT:
188 r = c->inputs[src->Index * 4 + s];
189 break;
190 case TGSI_FILE_SAMPLER:
191 case TGSI_FILE_SAMPLER_VIEW:
192 r = c->undef;
193 break;
194 default:
195 fprintf(stderr, "unknown src file %d\n", src->File);
196 abort();
197 }
198
199 if (src->Absolute)
200 r = qir_FMAXABS(c, r, r);
201
202 if (src->Negate) {
203 switch (tgsi_opcode_infer_src_type(tgsi_op)) {
204 case TGSI_TYPE_SIGNED:
205 case TGSI_TYPE_UNSIGNED:
206 r = qir_SUB(c, qir_uniform_ui(c, 0), r);
207 break;
208 default:
209 r = qir_FSUB(c, qir_uniform_f(c, 0.0), r);
210 break;
211 }
212 }
213
214 return r;
215 };
216
217
218 static void
219 update_dst(struct vc4_compile *c, struct tgsi_full_instruction *tgsi_inst,
220 int i, struct qreg val)
221 {
222 struct tgsi_dst_register *tgsi_dst = &tgsi_inst->Dst[0].Register;
223
224 assert(!tgsi_dst->Indirect);
225
226 switch (tgsi_dst->File) {
227 case TGSI_FILE_TEMPORARY:
228 c->temps[tgsi_dst->Index * 4 + i] = val;
229 break;
230 case TGSI_FILE_OUTPUT:
231 c->outputs[tgsi_dst->Index * 4 + i] = val;
232 c->num_outputs = MAX2(c->num_outputs,
233 tgsi_dst->Index * 4 + i + 1);
234 break;
235 default:
236 fprintf(stderr, "unknown dst file %d\n", tgsi_dst->File);
237 abort();
238 }
239 };
240
241 static struct qreg
242 get_swizzled_channel(struct vc4_compile *c,
243 struct qreg *srcs, int swiz)
244 {
245 switch (swiz) {
246 default:
247 case UTIL_FORMAT_SWIZZLE_NONE:
248 fprintf(stderr, "warning: unknown swizzle\n");
249 /* FALLTHROUGH */
250 case UTIL_FORMAT_SWIZZLE_0:
251 return qir_uniform_f(c, 0.0);
252 case UTIL_FORMAT_SWIZZLE_1:
253 return qir_uniform_f(c, 1.0);
254 case UTIL_FORMAT_SWIZZLE_X:
255 case UTIL_FORMAT_SWIZZLE_Y:
256 case UTIL_FORMAT_SWIZZLE_Z:
257 case UTIL_FORMAT_SWIZZLE_W:
258 return srcs[swiz];
259 }
260 }
261
262 static struct qreg
263 tgsi_to_qir_alu(struct vc4_compile *c,
264 struct tgsi_full_instruction *tgsi_inst,
265 enum qop op, struct qreg *src, int i)
266 {
267 struct qreg dst = qir_get_temp(c);
268 qir_emit(c, qir_inst4(op, dst,
269 src[0 * 4 + i],
270 src[1 * 4 + i],
271 src[2 * 4 + i],
272 c->undef));
273 return dst;
274 }
275
276 static struct qreg
277 qir_srgb_decode(struct vc4_compile *c, struct qreg srgb)
278 {
279 struct qreg low = qir_FMUL(c, srgb, qir_uniform_f(c, 1.0 / 12.92));
280 struct qreg high = qir_POW(c,
281 qir_FMUL(c,
282 qir_FADD(c,
283 srgb,
284 qir_uniform_f(c, 0.055)),
285 qir_uniform_f(c, 1.0 / 1.055)),
286 qir_uniform_f(c, 2.4));
287
288 qir_SF(c, qir_FSUB(c, srgb, qir_uniform_f(c, 0.04045)));
289 return qir_SEL_X_Y_NS(c, low, high);
290 }
291
292 static struct qreg
293 qir_srgb_encode(struct vc4_compile *c, struct qreg linear)
294 {
295 struct qreg low = qir_FMUL(c, linear, qir_uniform_f(c, 12.92));
296 struct qreg high = qir_FSUB(c,
297 qir_FMUL(c,
298 qir_uniform_f(c, 1.055),
299 qir_POW(c,
300 linear,
301 qir_uniform_f(c, 0.41666))),
302 qir_uniform_f(c, 0.055));
303
304 qir_SF(c, qir_FSUB(c, linear, qir_uniform_f(c, 0.0031308)));
305 return qir_SEL_X_Y_NS(c, low, high);
306 }
307
308 static struct qreg
309 tgsi_to_qir_umul(struct vc4_compile *c,
310 struct tgsi_full_instruction *tgsi_inst,
311 enum qop op, struct qreg *src, int i)
312 {
313 struct qreg src0_hi = qir_SHR(c, src[0 * 4 + i],
314 qir_uniform_ui(c, 16));
315 struct qreg src0_lo = qir_AND(c, src[0 * 4 + i],
316 qir_uniform_ui(c, 0xffff));
317 struct qreg src1_hi = qir_SHR(c, src[1 * 4 + i],
318 qir_uniform_ui(c, 16));
319 struct qreg src1_lo = qir_AND(c, src[1 * 4 + i],
320 qir_uniform_ui(c, 0xffff));
321
322 struct qreg hilo = qir_MUL24(c, src0_hi, src1_lo);
323 struct qreg lohi = qir_MUL24(c, src0_lo, src1_hi);
324 struct qreg lolo = qir_MUL24(c, src0_lo, src1_lo);
325
326 return qir_ADD(c, lolo, qir_SHL(c,
327 qir_ADD(c, hilo, lohi),
328 qir_uniform_ui(c, 16)));
329 }
330
331 static struct qreg
332 tgsi_to_qir_idiv(struct vc4_compile *c,
333 struct tgsi_full_instruction *tgsi_inst,
334 enum qop op, struct qreg *src, int i)
335 {
336 return qir_FTOI(c, qir_FMUL(c,
337 qir_ITOF(c, src[0 * 4 + i]),
338 qir_RCP(c, qir_ITOF(c, src[1 * 4 + i]))));
339 }
340
341 static struct qreg
342 tgsi_to_qir_ineg(struct vc4_compile *c,
343 struct tgsi_full_instruction *tgsi_inst,
344 enum qop op, struct qreg *src, int i)
345 {
346 return qir_SUB(c, qir_uniform_ui(c, 0), src[0 * 4 + i]);
347 }
348
349 static struct qreg
350 tgsi_to_qir_seq(struct vc4_compile *c,
351 struct tgsi_full_instruction *tgsi_inst,
352 enum qop op, struct qreg *src, int i)
353 {
354 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
355 return qir_SEL_X_0_ZS(c, qir_uniform_f(c, 1.0));
356 }
357
358 static struct qreg
359 tgsi_to_qir_sne(struct vc4_compile *c,
360 struct tgsi_full_instruction *tgsi_inst,
361 enum qop op, struct qreg *src, int i)
362 {
363 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
364 return qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0));
365 }
366
367 static struct qreg
368 tgsi_to_qir_slt(struct vc4_compile *c,
369 struct tgsi_full_instruction *tgsi_inst,
370 enum qop op, struct qreg *src, int i)
371 {
372 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
373 return qir_SEL_X_0_NS(c, qir_uniform_f(c, 1.0));
374 }
375
376 static struct qreg
377 tgsi_to_qir_sge(struct vc4_compile *c,
378 struct tgsi_full_instruction *tgsi_inst,
379 enum qop op, struct qreg *src, int i)
380 {
381 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
382 return qir_SEL_X_0_NC(c, qir_uniform_f(c, 1.0));
383 }
384
385 static struct qreg
386 tgsi_to_qir_fseq(struct vc4_compile *c,
387 struct tgsi_full_instruction *tgsi_inst,
388 enum qop op, struct qreg *src, int i)
389 {
390 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
391 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
392 }
393
394 static struct qreg
395 tgsi_to_qir_fsne(struct vc4_compile *c,
396 struct tgsi_full_instruction *tgsi_inst,
397 enum qop op, struct qreg *src, int i)
398 {
399 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
400 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
401 }
402
403 static struct qreg
404 tgsi_to_qir_fslt(struct vc4_compile *c,
405 struct tgsi_full_instruction *tgsi_inst,
406 enum qop op, struct qreg *src, int i)
407 {
408 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
409 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
410 }
411
412 static struct qreg
413 tgsi_to_qir_fsge(struct vc4_compile *c,
414 struct tgsi_full_instruction *tgsi_inst,
415 enum qop op, struct qreg *src, int i)
416 {
417 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
418 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
419 }
420
421 static struct qreg
422 tgsi_to_qir_useq(struct vc4_compile *c,
423 struct tgsi_full_instruction *tgsi_inst,
424 enum qop op, struct qreg *src, int i)
425 {
426 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
427 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
428 }
429
430 static struct qreg
431 tgsi_to_qir_usne(struct vc4_compile *c,
432 struct tgsi_full_instruction *tgsi_inst,
433 enum qop op, struct qreg *src, int i)
434 {
435 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
436 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
437 }
438
439 static struct qreg
440 tgsi_to_qir_islt(struct vc4_compile *c,
441 struct tgsi_full_instruction *tgsi_inst,
442 enum qop op, struct qreg *src, int i)
443 {
444 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
445 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
446 }
447
448 static struct qreg
449 tgsi_to_qir_isge(struct vc4_compile *c,
450 struct tgsi_full_instruction *tgsi_inst,
451 enum qop op, struct qreg *src, int i)
452 {
453 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
454 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
455 }
456
457 static struct qreg
458 tgsi_to_qir_cmp(struct vc4_compile *c,
459 struct tgsi_full_instruction *tgsi_inst,
460 enum qop op, struct qreg *src, int i)
461 {
462 qir_SF(c, src[0 * 4 + i]);
463 return qir_SEL_X_Y_NS(c,
464 src[1 * 4 + i],
465 src[2 * 4 + i]);
466 }
467
468 static struct qreg
469 tgsi_to_qir_mad(struct vc4_compile *c,
470 struct tgsi_full_instruction *tgsi_inst,
471 enum qop op, struct qreg *src, int i)
472 {
473 return qir_FADD(c,
474 qir_FMUL(c,
475 src[0 * 4 + i],
476 src[1 * 4 + i]),
477 src[2 * 4 + i]);
478 }
479
480 static struct qreg
481 tgsi_to_qir_lit(struct vc4_compile *c,
482 struct tgsi_full_instruction *tgsi_inst,
483 enum qop op, struct qreg *src, int i)
484 {
485 struct qreg x = src[0 * 4 + 0];
486 struct qreg y = src[0 * 4 + 1];
487 struct qreg w = src[0 * 4 + 3];
488
489 switch (i) {
490 case 0:
491 case 3:
492 return qir_uniform_f(c, 1.0);
493 case 1:
494 return qir_FMAX(c, src[0 * 4 + 0], qir_uniform_f(c, 0.0));
495 case 2: {
496 struct qreg zero = qir_uniform_f(c, 0.0);
497
498 qir_SF(c, x);
499 /* XXX: Clamp w to -128..128 */
500 return qir_SEL_X_0_NC(c,
501 qir_EXP2(c, qir_FMUL(c,
502 w,
503 qir_LOG2(c,
504 qir_FMAX(c,
505 y,
506 zero)))));
507 }
508 default:
509 assert(!"not reached");
510 return c->undef;
511 }
512 }
513
514 static struct qreg
515 tgsi_to_qir_lrp(struct vc4_compile *c,
516 struct tgsi_full_instruction *tgsi_inst,
517 enum qop op, struct qreg *src, int i)
518 {
519 struct qreg src0 = src[0 * 4 + i];
520 struct qreg src1 = src[1 * 4 + i];
521 struct qreg src2 = src[2 * 4 + i];
522
523 /* LRP is:
524 * src0 * src1 + (1 - src0) * src2.
525 * -> src0 * src1 + src2 - src0 * src2
526 * -> src2 + src0 * (src1 - src2)
527 */
528 return qir_FADD(c, src2, qir_FMUL(c, src0, qir_FSUB(c, src1, src2)));
529
530 }
531
532 static void
533 tgsi_to_qir_tex(struct vc4_compile *c,
534 struct tgsi_full_instruction *tgsi_inst,
535 enum qop op, struct qreg *src)
536 {
537 assert(!tgsi_inst->Instruction.Saturate);
538
539 struct qreg s = src[0 * 4 + 0];
540 struct qreg t = src[0 * 4 + 1];
541 struct qreg r = src[0 * 4 + 2];
542 uint32_t unit = tgsi_inst->Src[1].Register.Index;
543
544 struct qreg proj = c->undef;
545 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
546 proj = qir_RCP(c, src[0 * 4 + 3]);
547 s = qir_FMUL(c, s, proj);
548 t = qir_FMUL(c, t, proj);
549 }
550
551 struct qreg texture_u[] = {
552 add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit),
553 add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
554 add_uniform(c, QUNIFORM_CONSTANT, 0),
555 add_uniform(c, QUNIFORM_CONSTANT, 0),
556 };
557 uint32_t next_texture_u = 0;
558
559 /* There is no native support for GL texture rectangle coordinates, so
560 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
561 * 1]).
562 */
563 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_RECT ||
564 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT) {
565 s = qir_FMUL(c, s,
566 get_temp_for_uniform(c,
567 QUNIFORM_TEXRECT_SCALE_X,
568 unit));
569 t = qir_FMUL(c, t,
570 get_temp_for_uniform(c,
571 QUNIFORM_TEXRECT_SCALE_Y,
572 unit));
573 }
574
575 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
576 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE) {
577 struct qreg ma = qir_FMAXABS(c, qir_FMAXABS(c, s, t), r);
578 struct qreg rcp_ma = qir_RCP(c, ma);
579 s = qir_FMUL(c, s, rcp_ma);
580 t = qir_FMUL(c, t, rcp_ma);
581 r = qir_FMUL(c, r, rcp_ma);
582
583 texture_u[2] = add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P2, unit);
584
585 qir_TEX_R(c, r, texture_u[next_texture_u++]);
586 } else if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
587 c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP ||
588 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
589 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
590 qir_TEX_R(c, get_temp_for_uniform(c, QUNIFORM_TEXTURE_BORDER_COLOR, unit),
591 texture_u[next_texture_u++]);
592 }
593
594 if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP) {
595 s = qir_FMIN(c, qir_FMAX(c, s, qir_uniform_f(c, 0.0)),
596 qir_uniform_f(c, 1.0));
597 }
598
599 if (c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
600 t = qir_FMIN(c, qir_FMAX(c, t, qir_uniform_f(c, 0.0)),
601 qir_uniform_f(c, 1.0));
602 }
603
604 qir_TEX_T(c, t, texture_u[next_texture_u++]);
605
606 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB)
607 qir_TEX_B(c, src[0 * 4 + 3], texture_u[next_texture_u++]);
608
609 qir_TEX_S(c, s, texture_u[next_texture_u++]);
610
611 c->num_texture_samples++;
612 struct qreg r4 = qir_TEX_RESULT(c);
613
614 enum pipe_format format = c->key->tex[unit].format;
615
616 struct qreg unpacked[4];
617 if (util_format_is_depth_or_stencil(format)) {
618 struct qreg depthf = qir_ITOF(c, qir_SHR(c, r4,
619 qir_uniform_ui(c, 8)));
620 struct qreg normalized = qir_FMUL(c, depthf,
621 qir_uniform_f(c, 1.0f/0xffffff));
622
623 struct qreg depth_output;
624
625 struct qreg one = qir_uniform_f(c, 1.0f);
626 if (c->key->tex[unit].compare_mode) {
627 struct qreg compare = src[0 * 4 + 2];
628
629 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP)
630 compare = qir_FMUL(c, compare, proj);
631
632 switch (c->key->tex[unit].compare_func) {
633 case PIPE_FUNC_NEVER:
634 depth_output = qir_uniform_f(c, 0.0f);
635 break;
636 case PIPE_FUNC_ALWAYS:
637 depth_output = one;
638 break;
639 case PIPE_FUNC_EQUAL:
640 qir_SF(c, qir_FSUB(c, compare, normalized));
641 depth_output = qir_SEL_X_0_ZS(c, one);
642 break;
643 case PIPE_FUNC_NOTEQUAL:
644 qir_SF(c, qir_FSUB(c, compare, normalized));
645 depth_output = qir_SEL_X_0_ZC(c, one);
646 break;
647 case PIPE_FUNC_GREATER:
648 qir_SF(c, qir_FSUB(c, compare, normalized));
649 depth_output = qir_SEL_X_0_NC(c, one);
650 break;
651 case PIPE_FUNC_GEQUAL:
652 qir_SF(c, qir_FSUB(c, normalized, compare));
653 depth_output = qir_SEL_X_0_NS(c, one);
654 break;
655 case PIPE_FUNC_LESS:
656 qir_SF(c, qir_FSUB(c, compare, normalized));
657 depth_output = qir_SEL_X_0_NS(c, one);
658 break;
659 case PIPE_FUNC_LEQUAL:
660 qir_SF(c, qir_FSUB(c, normalized, compare));
661 depth_output = qir_SEL_X_0_NC(c, one);
662 break;
663 }
664 } else {
665 depth_output = normalized;
666 }
667
668 for (int i = 0; i < 4; i++)
669 unpacked[i] = depth_output;
670 } else {
671 for (int i = 0; i < 4; i++)
672 unpacked[i] = qir_R4_UNPACK(c, r4, i);
673 }
674
675 const uint8_t *format_swiz = vc4_get_format_swizzle(format);
676 struct qreg texture_output[4];
677 for (int i = 0; i < 4; i++) {
678 texture_output[i] = get_swizzled_channel(c, unpacked,
679 format_swiz[i]);
680 }
681
682 if (util_format_is_srgb(format)) {
683 for (int i = 0; i < 3; i++)
684 texture_output[i] = qir_srgb_decode(c,
685 texture_output[i]);
686 }
687
688 for (int i = 0; i < 4; i++) {
689 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
690 continue;
691
692 update_dst(c, tgsi_inst, i,
693 get_swizzled_channel(c, texture_output,
694 c->key->tex[unit].swizzle[i]));
695 }
696 }
697
698 static struct qreg
699 tgsi_to_qir_pow(struct vc4_compile *c,
700 struct tgsi_full_instruction *tgsi_inst,
701 enum qop op, struct qreg *src, int i)
702 {
703 /* Note that this instruction replicates its result from the x channel
704 */
705 return qir_POW(c, src[0 * 4 + 0], src[1 * 4 + 0]);
706 }
707
708 static struct qreg
709 tgsi_to_qir_trunc(struct vc4_compile *c,
710 struct tgsi_full_instruction *tgsi_inst,
711 enum qop op, struct qreg *src, int i)
712 {
713 return qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
714 }
715
716 /**
717 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
718 * to zero).
719 */
720 static struct qreg
721 tgsi_to_qir_frc(struct vc4_compile *c,
722 struct tgsi_full_instruction *tgsi_inst,
723 enum qop op, struct qreg *src, int i)
724 {
725 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
726 struct qreg diff = qir_FSUB(c, src[0 * 4 + i], trunc);
727 qir_SF(c, diff);
728 return qir_SEL_X_Y_NS(c,
729 qir_FADD(c, diff, qir_uniform_f(c, 1.0)),
730 diff);
731 }
732
733 /**
734 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
735 * zero).
736 */
737 static struct qreg
738 tgsi_to_qir_flr(struct vc4_compile *c,
739 struct tgsi_full_instruction *tgsi_inst,
740 enum qop op, struct qreg *src, int i)
741 {
742 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
743
744 /* This will be < 0 if we truncated and the truncation was of a value
745 * that was < 0 in the first place.
746 */
747 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], trunc));
748
749 return qir_SEL_X_Y_NS(c,
750 qir_FSUB(c, trunc, qir_uniform_f(c, 1.0)),
751 trunc);
752 }
753
754 static struct qreg
755 tgsi_to_qir_dp(struct vc4_compile *c,
756 struct tgsi_full_instruction *tgsi_inst,
757 int num, struct qreg *src, int i)
758 {
759 struct qreg sum = qir_FMUL(c, src[0 * 4 + 0], src[1 * 4 + 0]);
760 for (int j = 1; j < num; j++) {
761 sum = qir_FADD(c, sum, qir_FMUL(c,
762 src[0 * 4 + j],
763 src[1 * 4 + j]));
764 }
765 return sum;
766 }
767
768 static struct qreg
769 tgsi_to_qir_dp2(struct vc4_compile *c,
770 struct tgsi_full_instruction *tgsi_inst,
771 enum qop op, struct qreg *src, int i)
772 {
773 return tgsi_to_qir_dp(c, tgsi_inst, 2, src, i);
774 }
775
776 static struct qreg
777 tgsi_to_qir_dp3(struct vc4_compile *c,
778 struct tgsi_full_instruction *tgsi_inst,
779 enum qop op, struct qreg *src, int i)
780 {
781 return tgsi_to_qir_dp(c, tgsi_inst, 3, src, i);
782 }
783
784 static struct qreg
785 tgsi_to_qir_dp4(struct vc4_compile *c,
786 struct tgsi_full_instruction *tgsi_inst,
787 enum qop op, struct qreg *src, int i)
788 {
789 return tgsi_to_qir_dp(c, tgsi_inst, 4, src, i);
790 }
791
792 static struct qreg
793 tgsi_to_qir_abs(struct vc4_compile *c,
794 struct tgsi_full_instruction *tgsi_inst,
795 enum qop op, struct qreg *src, int i)
796 {
797 struct qreg arg = src[0 * 4 + i];
798 return qir_FMAXABS(c, arg, arg);
799 }
800
801 /* Note that this instruction replicates its result from the x channel */
802 static struct qreg
803 tgsi_to_qir_sin(struct vc4_compile *c,
804 struct tgsi_full_instruction *tgsi_inst,
805 enum qop op, struct qreg *src, int i)
806 {
807 float coeff[] = {
808 2.0 * M_PI,
809 -pow(2.0 * M_PI, 3) / (3 * 2 * 1),
810 pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
811 -pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
812 };
813
814 struct qreg scaled_x =
815 qir_FMUL(c,
816 src[0 * 4 + 0],
817 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
818
819
820 struct qreg x = tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0);
821 struct qreg x2 = qir_FMUL(c, x, x);
822 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
823 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
824 x = qir_FMUL(c, x, x2);
825 sum = qir_FADD(c,
826 sum,
827 qir_FMUL(c,
828 x,
829 qir_uniform_f(c, coeff[i])));
830 }
831 return sum;
832 }
833
834 /* Note that this instruction replicates its result from the x channel */
835 static struct qreg
836 tgsi_to_qir_cos(struct vc4_compile *c,
837 struct tgsi_full_instruction *tgsi_inst,
838 enum qop op, struct qreg *src, int i)
839 {
840 float coeff[] = {
841 1.0f,
842 -pow(2.0 * M_PI, 2) / (2 * 1),
843 pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
844 -pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
845 };
846
847 struct qreg scaled_x =
848 qir_FMUL(c, src[0 * 4 + 0],
849 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
850 struct qreg x_frac = tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0);
851
852 struct qreg sum = qir_uniform_f(c, coeff[0]);
853 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
854 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
855 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
856 if (i != 1)
857 x = qir_FMUL(c, x, x2);
858
859 struct qreg mul = qir_FMUL(c,
860 x,
861 qir_uniform_f(c, coeff[i]));
862 if (i == 0)
863 sum = mul;
864 else
865 sum = qir_FADD(c, sum, mul);
866 }
867 return sum;
868 }
869
870 static struct qreg
871 tgsi_to_qir_clamp(struct vc4_compile *c,
872 struct tgsi_full_instruction *tgsi_inst,
873 enum qop op, struct qreg *src, int i)
874 {
875 return qir_FMAX(c, qir_FMIN(c,
876 src[0 * 4 + i],
877 src[2 * 4 + i]),
878 src[1 * 4 + i]);
879 }
880
881 static void
882 emit_vertex_input(struct vc4_compile *c, int attr)
883 {
884 enum pipe_format format = c->vs_key->attr_formats[attr];
885 struct qreg vpm_reads[4];
886
887 /* Right now, we're setting the VPM offsets to be 16 bytes wide every
888 * time, so we always read 4 32-bit VPM entries.
889 */
890 for (int i = 0; i < 4; i++) {
891 vpm_reads[i] = qir_get_temp(c);
892 qir_emit(c, qir_inst(QOP_VPM_READ,
893 vpm_reads[i],
894 c->undef,
895 c->undef));
896 c->num_inputs++;
897 }
898
899 bool format_warned = false;
900 const struct util_format_description *desc =
901 util_format_description(format);
902
903 for (int i = 0; i < 4; i++) {
904 uint8_t swiz = desc->swizzle[i];
905 struct qreg result;
906
907 if (swiz > UTIL_FORMAT_SWIZZLE_W)
908 result = get_swizzled_channel(c, vpm_reads, swiz);
909 else if (desc->channel[swiz].size == 32 &&
910 desc->channel[swiz].type == UTIL_FORMAT_TYPE_FLOAT) {
911 result = get_swizzled_channel(c, vpm_reads, swiz);
912 } else if (desc->channel[swiz].size == 8 &&
913 (desc->channel[swiz].type == UTIL_FORMAT_TYPE_UNSIGNED ||
914 desc->channel[swiz].type == UTIL_FORMAT_TYPE_SIGNED) &&
915 desc->channel[swiz].normalized) {
916 struct qreg vpm = vpm_reads[0];
917 if (desc->channel[swiz].type == UTIL_FORMAT_TYPE_SIGNED)
918 vpm = qir_XOR(c, vpm, qir_uniform_ui(c, 0x80808080));
919 result = qir_UNPACK_8(c, vpm, swiz);
920 } else {
921 if (!format_warned) {
922 fprintf(stderr,
923 "vtx element %d unsupported type: %s\n",
924 attr, util_format_name(format));
925 format_warned = true;
926 }
927 result = qir_uniform_f(c, 0.0);
928 }
929
930 if (desc->channel[swiz].normalized &&
931 desc->channel[swiz].type == UTIL_FORMAT_TYPE_SIGNED) {
932 result = qir_FSUB(c,
933 qir_FMUL(c,
934 result,
935 qir_uniform_f(c, 2.0)),
936 qir_uniform_f(c, 1.0));
937 }
938
939 c->inputs[attr * 4 + i] = result;
940 }
941 }
942
943 static void
944 tgsi_to_qir_kill_if(struct vc4_compile *c, struct qreg *src, int i)
945 {
946 if (c->discard.file == QFILE_NULL)
947 c->discard = qir_uniform_f(c, 0.0);
948 qir_SF(c, src[0 * 4 + i]);
949 c->discard = qir_SEL_X_Y_NS(c, qir_uniform_f(c, 1.0),
950 c->discard);
951 }
952
953 static void
954 emit_fragcoord_input(struct vc4_compile *c, int attr)
955 {
956 c->inputs[attr * 4 + 0] = qir_FRAG_X(c);
957 c->inputs[attr * 4 + 1] = qir_FRAG_Y(c);
958 c->inputs[attr * 4 + 2] =
959 qir_FMUL(c,
960 qir_ITOF(c, qir_FRAG_Z(c)),
961 qir_uniform_f(c, 1.0 / 0xffffff));
962 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
963 }
964
965 static void
966 emit_point_coord_input(struct vc4_compile *c, int attr)
967 {
968 if (c->point_x.file == QFILE_NULL) {
969 c->point_x = qir_uniform_f(c, 0.0);
970 c->point_y = qir_uniform_f(c, 0.0);
971 }
972
973 c->inputs[attr * 4 + 0] = c->point_x;
974 if (c->fs_key->point_coord_upper_left) {
975 c->inputs[attr * 4 + 1] = qir_FSUB(c,
976 qir_uniform_f(c, 1.0),
977 c->point_y);
978 } else {
979 c->inputs[attr * 4 + 1] = c->point_y;
980 }
981 c->inputs[attr * 4 + 2] = qir_uniform_f(c, 0.0);
982 c->inputs[attr * 4 + 3] = qir_uniform_f(c, 1.0);
983 }
984
985 static struct qreg
986 emit_fragment_varying(struct vc4_compile *c, int index)
987 {
988 struct qreg vary = {
989 QFILE_VARY,
990 index
991 };
992
993 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
994 }
995
996 static void
997 emit_fragment_input(struct vc4_compile *c, int attr,
998 struct tgsi_full_declaration *decl)
999 {
1000 for (int i = 0; i < 4; i++) {
1001 c->inputs[attr * 4 + i] =
1002 emit_fragment_varying(c, attr * 4 + i);
1003 c->num_inputs++;
1004
1005 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR ||
1006 decl->Semantic.Name == TGSI_SEMANTIC_BCOLOR)
1007 c->color_inputs |= 1 << i;
1008 }
1009 }
1010
1011 static void
1012 emit_face_input(struct vc4_compile *c, int attr)
1013 {
1014 c->inputs[attr * 4 + 0] = qir_FSUB(c,
1015 qir_uniform_f(c, 1.0),
1016 qir_FMUL(c,
1017 qir_ITOF(c, qir_FRAG_REV_FLAG(c)),
1018 qir_uniform_f(c, 2.0)));
1019 c->inputs[attr * 4 + 1] = qir_uniform_f(c, 0.0);
1020 c->inputs[attr * 4 + 2] = qir_uniform_f(c, 0.0);
1021 c->inputs[attr * 4 + 3] = qir_uniform_f(c, 1.0);
1022 }
1023
1024 static void
1025 emit_tgsi_declaration(struct vc4_compile *c,
1026 struct tgsi_full_declaration *decl)
1027 {
1028 switch (decl->Declaration.File) {
1029 case TGSI_FILE_TEMPORARY:
1030 resize_qreg_array(c, &c->temps, &c->temps_array_size,
1031 (decl->Range.Last + 1) * 4);
1032 break;
1033
1034 case TGSI_FILE_INPUT:
1035 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1036 (decl->Range.Last + 1) * 4);
1037
1038 for (int i = decl->Range.First;
1039 i <= decl->Range.Last;
1040 i++) {
1041 if (c->stage == QSTAGE_FRAG) {
1042 if (decl->Semantic.Name ==
1043 TGSI_SEMANTIC_POSITION) {
1044 emit_fragcoord_input(c, i);
1045 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
1046 emit_face_input(c, i);
1047 } else if (decl->Semantic.Name == TGSI_SEMANTIC_GENERIC &&
1048 (c->fs_key->point_sprite_mask &
1049 (1 << decl->Semantic.Index))) {
1050 emit_point_coord_input(c, i);
1051 } else {
1052 emit_fragment_input(c, i, decl);
1053 }
1054 } else {
1055 emit_vertex_input(c, i);
1056 }
1057 }
1058 break;
1059
1060 case TGSI_FILE_OUTPUT:
1061 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
1062 (decl->Range.Last + 1) * 4);
1063
1064 switch (decl->Semantic.Name) {
1065 case TGSI_SEMANTIC_POSITION:
1066 c->output_position_index = decl->Range.First * 4;
1067 break;
1068 case TGSI_SEMANTIC_COLOR:
1069 c->output_color_index = decl->Range.First * 4;
1070 break;
1071 case TGSI_SEMANTIC_PSIZE:
1072 c->output_point_size_index = decl->Range.First * 4;
1073 break;
1074 }
1075
1076 break;
1077 }
1078 }
1079
1080 static void
1081 emit_tgsi_instruction(struct vc4_compile *c,
1082 struct tgsi_full_instruction *tgsi_inst)
1083 {
1084 struct {
1085 enum qop op;
1086 struct qreg (*func)(struct vc4_compile *c,
1087 struct tgsi_full_instruction *tgsi_inst,
1088 enum qop op,
1089 struct qreg *src, int i);
1090 } op_trans[] = {
1091 [TGSI_OPCODE_MOV] = { QOP_MOV, tgsi_to_qir_alu },
1092 [TGSI_OPCODE_ABS] = { 0, tgsi_to_qir_abs },
1093 [TGSI_OPCODE_MUL] = { QOP_FMUL, tgsi_to_qir_alu },
1094 [TGSI_OPCODE_ADD] = { QOP_FADD, tgsi_to_qir_alu },
1095 [TGSI_OPCODE_SUB] = { QOP_FSUB, tgsi_to_qir_alu },
1096 [TGSI_OPCODE_MIN] = { QOP_FMIN, tgsi_to_qir_alu },
1097 [TGSI_OPCODE_MAX] = { QOP_FMAX, tgsi_to_qir_alu },
1098 [TGSI_OPCODE_F2I] = { QOP_FTOI, tgsi_to_qir_alu },
1099 [TGSI_OPCODE_I2F] = { QOP_ITOF, tgsi_to_qir_alu },
1100 [TGSI_OPCODE_UADD] = { QOP_ADD, tgsi_to_qir_alu },
1101 [TGSI_OPCODE_USHR] = { QOP_SHR, tgsi_to_qir_alu },
1102 [TGSI_OPCODE_ISHR] = { QOP_ASR, tgsi_to_qir_alu },
1103 [TGSI_OPCODE_SHL] = { QOP_SHL, tgsi_to_qir_alu },
1104 [TGSI_OPCODE_IMIN] = { QOP_MIN, tgsi_to_qir_alu },
1105 [TGSI_OPCODE_IMAX] = { QOP_MAX, tgsi_to_qir_alu },
1106 [TGSI_OPCODE_AND] = { QOP_AND, tgsi_to_qir_alu },
1107 [TGSI_OPCODE_OR] = { QOP_OR, tgsi_to_qir_alu },
1108 [TGSI_OPCODE_XOR] = { QOP_XOR, tgsi_to_qir_alu },
1109 [TGSI_OPCODE_NOT] = { QOP_NOT, tgsi_to_qir_alu },
1110
1111 [TGSI_OPCODE_UMUL] = { 0, tgsi_to_qir_umul },
1112 [TGSI_OPCODE_IDIV] = { 0, tgsi_to_qir_idiv },
1113 [TGSI_OPCODE_INEG] = { 0, tgsi_to_qir_ineg },
1114
1115 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_alu },
1116 [TGSI_OPCODE_SEQ] = { 0, tgsi_to_qir_seq },
1117 [TGSI_OPCODE_SNE] = { 0, tgsi_to_qir_sne },
1118 [TGSI_OPCODE_SGE] = { 0, tgsi_to_qir_sge },
1119 [TGSI_OPCODE_SLT] = { 0, tgsi_to_qir_slt },
1120 [TGSI_OPCODE_FSEQ] = { 0, tgsi_to_qir_fseq },
1121 [TGSI_OPCODE_FSNE] = { 0, tgsi_to_qir_fsne },
1122 [TGSI_OPCODE_FSGE] = { 0, tgsi_to_qir_fsge },
1123 [TGSI_OPCODE_FSLT] = { 0, tgsi_to_qir_fslt },
1124 [TGSI_OPCODE_USEQ] = { 0, tgsi_to_qir_useq },
1125 [TGSI_OPCODE_USNE] = { 0, tgsi_to_qir_usne },
1126 [TGSI_OPCODE_ISGE] = { 0, tgsi_to_qir_isge },
1127 [TGSI_OPCODE_ISLT] = { 0, tgsi_to_qir_islt },
1128
1129 [TGSI_OPCODE_CMP] = { 0, tgsi_to_qir_cmp },
1130 [TGSI_OPCODE_MAD] = { 0, tgsi_to_qir_mad },
1131 [TGSI_OPCODE_DP2] = { 0, tgsi_to_qir_dp2 },
1132 [TGSI_OPCODE_DP3] = { 0, tgsi_to_qir_dp3 },
1133 [TGSI_OPCODE_DP4] = { 0, tgsi_to_qir_dp4 },
1134 [TGSI_OPCODE_RCP] = { QOP_RCP, tgsi_to_qir_alu },
1135 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_alu },
1136 [TGSI_OPCODE_EX2] = { QOP_EXP2, tgsi_to_qir_alu },
1137 [TGSI_OPCODE_LG2] = { QOP_LOG2, tgsi_to_qir_alu },
1138 [TGSI_OPCODE_LIT] = { 0, tgsi_to_qir_lit },
1139 [TGSI_OPCODE_LRP] = { 0, tgsi_to_qir_lrp },
1140 [TGSI_OPCODE_POW] = { 0, tgsi_to_qir_pow },
1141 [TGSI_OPCODE_TRUNC] = { 0, tgsi_to_qir_trunc },
1142 [TGSI_OPCODE_FRC] = { 0, tgsi_to_qir_frc },
1143 [TGSI_OPCODE_FLR] = { 0, tgsi_to_qir_flr },
1144 [TGSI_OPCODE_SIN] = { 0, tgsi_to_qir_sin },
1145 [TGSI_OPCODE_COS] = { 0, tgsi_to_qir_cos },
1146 [TGSI_OPCODE_CLAMP] = { 0, tgsi_to_qir_clamp },
1147 };
1148 static int asdf = 0;
1149 uint32_t tgsi_op = tgsi_inst->Instruction.Opcode;
1150
1151 if (tgsi_op == TGSI_OPCODE_END)
1152 return;
1153
1154 struct qreg src_regs[12];
1155 for (int s = 0; s < 3; s++) {
1156 for (int i = 0; i < 4; i++) {
1157 src_regs[4 * s + i] =
1158 get_src(c, tgsi_inst->Instruction.Opcode,
1159 &tgsi_inst->Src[s].Register, i);
1160 }
1161 }
1162
1163 switch (tgsi_op) {
1164 case TGSI_OPCODE_TEX:
1165 case TGSI_OPCODE_TXP:
1166 case TGSI_OPCODE_TXB:
1167 tgsi_to_qir_tex(c, tgsi_inst,
1168 op_trans[tgsi_op].op, src_regs);
1169 return;
1170 case TGSI_OPCODE_KILL:
1171 c->discard = qir_uniform_f(c, 1.0);
1172 return;
1173 case TGSI_OPCODE_KILL_IF:
1174 for (int i = 0; i < 4; i++)
1175 tgsi_to_qir_kill_if(c, src_regs, i);
1176 return;
1177 default:
1178 break;
1179 }
1180
1181 if (tgsi_op > ARRAY_SIZE(op_trans) || !(op_trans[tgsi_op].func)) {
1182 fprintf(stderr, "unknown tgsi inst: ");
1183 tgsi_dump_instruction(tgsi_inst, asdf++);
1184 fprintf(stderr, "\n");
1185 abort();
1186 }
1187
1188 for (int i = 0; i < 4; i++) {
1189 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
1190 continue;
1191
1192 struct qreg result;
1193
1194 result = op_trans[tgsi_op].func(c, tgsi_inst,
1195 op_trans[tgsi_op].op,
1196 src_regs, i);
1197
1198 if (tgsi_inst->Instruction.Saturate) {
1199 float low = (tgsi_inst->Instruction.Saturate ==
1200 TGSI_SAT_MINUS_PLUS_ONE ? -1.0 : 0.0);
1201 result = qir_FMAX(c,
1202 qir_FMIN(c,
1203 result,
1204 qir_uniform_f(c, 1.0)),
1205 qir_uniform_f(c, low));
1206 }
1207
1208 update_dst(c, tgsi_inst, i, result);
1209 }
1210 }
1211
1212 static void
1213 parse_tgsi_immediate(struct vc4_compile *c, struct tgsi_full_immediate *imm)
1214 {
1215 for (int i = 0; i < 4; i++) {
1216 unsigned n = c->num_consts++;
1217 resize_qreg_array(c, &c->consts, &c->consts_array_size, n + 1);
1218 c->consts[n] = qir_uniform_ui(c, imm->u[i].Uint);
1219 }
1220 }
1221
1222 static struct qreg
1223 vc4_blend_channel(struct vc4_compile *c,
1224 struct qreg *dst,
1225 struct qreg *src,
1226 struct qreg val,
1227 unsigned factor,
1228 int channel)
1229 {
1230 switch(factor) {
1231 case PIPE_BLENDFACTOR_ONE:
1232 return val;
1233 case PIPE_BLENDFACTOR_SRC_COLOR:
1234 return qir_FMUL(c, val, src[channel]);
1235 case PIPE_BLENDFACTOR_SRC_ALPHA:
1236 return qir_FMUL(c, val, src[3]);
1237 case PIPE_BLENDFACTOR_DST_ALPHA:
1238 return qir_FMUL(c, val, dst[3]);
1239 case PIPE_BLENDFACTOR_DST_COLOR:
1240 return qir_FMUL(c, val, dst[channel]);
1241 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
1242 return qir_FMIN(c, src[3], qir_FSUB(c,
1243 qir_uniform_f(c, 1.0),
1244 dst[3]));
1245 case PIPE_BLENDFACTOR_CONST_COLOR:
1246 return qir_FMUL(c, val,
1247 get_temp_for_uniform(c,
1248 QUNIFORM_BLEND_CONST_COLOR,
1249 channel));
1250 case PIPE_BLENDFACTOR_CONST_ALPHA:
1251 return qir_FMUL(c, val,
1252 get_temp_for_uniform(c,
1253 QUNIFORM_BLEND_CONST_COLOR,
1254 3));
1255 case PIPE_BLENDFACTOR_ZERO:
1256 return qir_uniform_f(c, 0.0);
1257 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
1258 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1259 src[channel]));
1260 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
1261 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1262 src[3]));
1263 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
1264 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1265 dst[3]));
1266 case PIPE_BLENDFACTOR_INV_DST_COLOR:
1267 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1268 dst[channel]));
1269 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
1270 return qir_FMUL(c, val,
1271 qir_FSUB(c, qir_uniform_f(c, 1.0),
1272 get_temp_for_uniform(c,
1273 QUNIFORM_BLEND_CONST_COLOR,
1274 channel)));
1275 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
1276 return qir_FMUL(c, val,
1277 qir_FSUB(c, qir_uniform_f(c, 1.0),
1278 get_temp_for_uniform(c,
1279 QUNIFORM_BLEND_CONST_COLOR,
1280 3)));
1281
1282 default:
1283 case PIPE_BLENDFACTOR_SRC1_COLOR:
1284 case PIPE_BLENDFACTOR_SRC1_ALPHA:
1285 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
1286 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
1287 /* Unsupported. */
1288 fprintf(stderr, "Unknown blend factor %d\n", factor);
1289 return val;
1290 }
1291 }
1292
1293 static struct qreg
1294 vc4_blend_func(struct vc4_compile *c,
1295 struct qreg src, struct qreg dst,
1296 unsigned func)
1297 {
1298 switch (func) {
1299 case PIPE_BLEND_ADD:
1300 return qir_FADD(c, src, dst);
1301 case PIPE_BLEND_SUBTRACT:
1302 return qir_FSUB(c, src, dst);
1303 case PIPE_BLEND_REVERSE_SUBTRACT:
1304 return qir_FSUB(c, dst, src);
1305 case PIPE_BLEND_MIN:
1306 return qir_FMIN(c, src, dst);
1307 case PIPE_BLEND_MAX:
1308 return qir_FMAX(c, src, dst);
1309
1310 default:
1311 /* Unsupported. */
1312 fprintf(stderr, "Unknown blend func %d\n", func);
1313 return src;
1314
1315 }
1316 }
1317
1318 /**
1319 * Implements fixed function blending in shader code.
1320 *
1321 * VC4 doesn't have any hardware support for blending. Instead, you read the
1322 * current contents of the destination from the tile buffer after having
1323 * waited for the scoreboard (which is handled by vc4_qpu_emit.c), then do
1324 * math using your output color and that destination value, and update the
1325 * output color appropriately.
1326 */
1327 static void
1328 vc4_blend(struct vc4_compile *c, struct qreg *result,
1329 struct qreg *dst_color, struct qreg *src_color)
1330 {
1331 struct pipe_rt_blend_state *blend = &c->fs_key->blend;
1332
1333 if (!blend->blend_enable) {
1334 for (int i = 0; i < 4; i++)
1335 result[i] = src_color[i];
1336 return;
1337 }
1338
1339 struct qreg src_blend[4], dst_blend[4];
1340 for (int i = 0; i < 3; i++) {
1341 src_blend[i] = vc4_blend_channel(c,
1342 dst_color, src_color,
1343 src_color[i],
1344 blend->rgb_src_factor, i);
1345 dst_blend[i] = vc4_blend_channel(c,
1346 dst_color, src_color,
1347 dst_color[i],
1348 blend->rgb_dst_factor, i);
1349 }
1350 src_blend[3] = vc4_blend_channel(c,
1351 dst_color, src_color,
1352 src_color[3],
1353 blend->alpha_src_factor, 3);
1354 dst_blend[3] = vc4_blend_channel(c,
1355 dst_color, src_color,
1356 dst_color[3],
1357 blend->alpha_dst_factor, 3);
1358
1359 for (int i = 0; i < 3; i++) {
1360 result[i] = vc4_blend_func(c,
1361 src_blend[i], dst_blend[i],
1362 blend->rgb_func);
1363 }
1364 result[3] = vc4_blend_func(c,
1365 src_blend[3], dst_blend[3],
1366 blend->alpha_func);
1367 }
1368
1369 static void
1370 alpha_test_discard(struct vc4_compile *c)
1371 {
1372 struct qreg src_alpha;
1373 struct qreg alpha_ref = get_temp_for_uniform(c, QUNIFORM_ALPHA_REF, 0);
1374
1375 if (!c->fs_key->alpha_test)
1376 return;
1377
1378 if (c->output_color_index != -1)
1379 src_alpha = c->outputs[c->output_color_index + 3];
1380 else
1381 src_alpha = qir_uniform_f(c, 1.0);
1382
1383 if (c->discard.file == QFILE_NULL)
1384 c->discard = qir_uniform_f(c, 0.0);
1385
1386 switch (c->fs_key->alpha_test_func) {
1387 case PIPE_FUNC_NEVER:
1388 c->discard = qir_uniform_f(c, 1.0);
1389 break;
1390 case PIPE_FUNC_ALWAYS:
1391 break;
1392 case PIPE_FUNC_EQUAL:
1393 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1394 c->discard = qir_SEL_X_Y_ZS(c, c->discard,
1395 qir_uniform_f(c, 1.0));
1396 break;
1397 case PIPE_FUNC_NOTEQUAL:
1398 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1399 c->discard = qir_SEL_X_Y_ZC(c, c->discard,
1400 qir_uniform_f(c, 1.0));
1401 break;
1402 case PIPE_FUNC_GREATER:
1403 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1404 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1405 qir_uniform_f(c, 1.0));
1406 break;
1407 case PIPE_FUNC_GEQUAL:
1408 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1409 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1410 qir_uniform_f(c, 1.0));
1411 break;
1412 case PIPE_FUNC_LESS:
1413 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1414 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1415 qir_uniform_f(c, 1.0));
1416 break;
1417 case PIPE_FUNC_LEQUAL:
1418 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1419 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1420 qir_uniform_f(c, 1.0));
1421 break;
1422 }
1423 }
1424
1425 static void
1426 emit_frag_end(struct vc4_compile *c)
1427 {
1428 alpha_test_discard(c);
1429
1430 enum pipe_format color_format = c->fs_key->color_format;
1431 const uint8_t *format_swiz = vc4_get_format_swizzle(color_format);
1432 struct qreg tlb_read_color[4] = { c->undef, c->undef, c->undef, c->undef };
1433 struct qreg dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1434 struct qreg linear_dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1435 if (c->fs_key->blend.blend_enable ||
1436 c->fs_key->blend.colormask != 0xf) {
1437 struct qreg r4 = qir_TLB_COLOR_READ(c);
1438 for (int i = 0; i < 4; i++)
1439 tlb_read_color[i] = qir_R4_UNPACK(c, r4, i);
1440 for (int i = 0; i < 4; i++) {
1441 dst_color[i] = get_swizzled_channel(c,
1442 tlb_read_color,
1443 format_swiz[i]);
1444 if (util_format_is_srgb(color_format) && i != 3) {
1445 linear_dst_color[i] =
1446 qir_srgb_decode(c, dst_color[i]);
1447 } else {
1448 linear_dst_color[i] = dst_color[i];
1449 }
1450 }
1451 }
1452
1453 struct qreg blend_color[4];
1454 struct qreg undef_array[4] = {
1455 c->undef, c->undef, c->undef, c->undef
1456 };
1457 vc4_blend(c, blend_color, linear_dst_color,
1458 (c->output_color_index != -1 ?
1459 c->outputs + c->output_color_index :
1460 undef_array));
1461
1462 if (util_format_is_srgb(color_format)) {
1463 for (int i = 0; i < 3; i++)
1464 blend_color[i] = qir_srgb_encode(c, blend_color[i]);
1465 }
1466
1467 /* If the bit isn't set in the color mask, then just return the
1468 * original dst color, instead.
1469 */
1470 for (int i = 0; i < 4; i++) {
1471 if (!(c->fs_key->blend.colormask & (1 << i))) {
1472 blend_color[i] = dst_color[i];
1473 }
1474 }
1475
1476 /* Debug: Sometimes you're getting a black output and just want to see
1477 * if the FS is getting executed at all. Spam magenta into the color
1478 * output.
1479 */
1480 if (0) {
1481 blend_color[0] = qir_uniform_f(c, 1.0);
1482 blend_color[1] = qir_uniform_f(c, 0.0);
1483 blend_color[2] = qir_uniform_f(c, 1.0);
1484 blend_color[3] = qir_uniform_f(c, 0.5);
1485 }
1486
1487 struct qreg swizzled_outputs[4];
1488 for (int i = 0; i < 4; i++) {
1489 swizzled_outputs[i] = get_swizzled_channel(c, blend_color,
1490 format_swiz[i]);
1491 }
1492
1493 if (c->discard.file != QFILE_NULL)
1494 qir_TLB_DISCARD_SETUP(c, c->discard);
1495
1496 if (c->fs_key->stencil_enabled) {
1497 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 0));
1498 if (c->fs_key->stencil_twoside) {
1499 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 1));
1500 }
1501 if (c->fs_key->stencil_full_writemasks) {
1502 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 2));
1503 }
1504 }
1505
1506 if (c->fs_key->depth_enabled) {
1507 struct qreg z;
1508 if (c->output_position_index != -1) {
1509 z = qir_FTOI(c, qir_FMUL(c, c->outputs[c->output_position_index + 2],
1510 qir_uniform_f(c, 0xffffff)));
1511 } else {
1512 z = qir_FRAG_Z(c);
1513 }
1514 qir_TLB_Z_WRITE(c, z);
1515 }
1516
1517 bool color_written = false;
1518 for (int i = 0; i < 4; i++) {
1519 if (swizzled_outputs[i].file != QFILE_NULL)
1520 color_written = true;
1521 }
1522
1523 struct qreg packed_color;
1524 if (color_written) {
1525 /* Fill in any undefined colors. The simulator will assertion
1526 * fail if we read something that wasn't written, and I don't
1527 * know what hardware does.
1528 */
1529 for (int i = 0; i < 4; i++) {
1530 if (swizzled_outputs[i].file == QFILE_NULL)
1531 swizzled_outputs[i] = qir_uniform_f(c, 0.0);
1532 }
1533 packed_color = qir_get_temp(c);
1534 qir_emit(c, qir_inst4(QOP_PACK_COLORS, packed_color,
1535 swizzled_outputs[0],
1536 swizzled_outputs[1],
1537 swizzled_outputs[2],
1538 swizzled_outputs[3]));
1539 } else {
1540 packed_color = qir_uniform_ui(c, 0);
1541 }
1542
1543 qir_emit(c, qir_inst(QOP_TLB_COLOR_WRITE, c->undef,
1544 packed_color, c->undef));
1545 }
1546
1547 static void
1548 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1549 {
1550 struct qreg xyi[2];
1551
1552 for (int i = 0; i < 2; i++) {
1553 struct qreg scale =
1554 add_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1555
1556 xyi[i] = qir_FTOI(c, qir_FMUL(c,
1557 qir_FMUL(c,
1558 c->outputs[i],
1559 scale),
1560 rcp_w));
1561 }
1562
1563 qir_VPM_WRITE(c, qir_PACK_SCALED(c, xyi[0], xyi[1]));
1564 }
1565
1566 static void
1567 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1568 {
1569 struct qreg zscale = add_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1570 struct qreg zoffset = add_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1571
1572 qir_VPM_WRITE(c, qir_FMUL(c, qir_FADD(c, qir_FMUL(c,
1573 c->outputs[2],
1574 zscale),
1575 zoffset),
1576 rcp_w));
1577 }
1578
1579 static void
1580 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1581 {
1582 qir_VPM_WRITE(c, rcp_w);
1583 }
1584
1585 static void
1586 emit_point_size_write(struct vc4_compile *c)
1587 {
1588 struct qreg point_size;
1589
1590 if (c->output_point_size_index)
1591 point_size = c->outputs[c->output_point_size_index + 3];
1592 else
1593 point_size = qir_uniform_f(c, 1.0);
1594
1595 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1596 * BCM21553).
1597 */
1598 point_size = qir_FMAX(c, point_size, qir_uniform_f(c, .125));
1599
1600 qir_VPM_WRITE(c, point_size);
1601 }
1602
1603 static void
1604 emit_vert_end(struct vc4_compile *c)
1605 {
1606 struct qreg rcp_w = qir_RCP(c, c->outputs[3]);
1607
1608 emit_scaled_viewport_write(c, rcp_w);
1609 emit_zs_write(c, rcp_w);
1610 emit_rcp_wc_write(c, rcp_w);
1611 if (c->vs_key->per_vertex_point_size)
1612 emit_point_size_write(c);
1613
1614 for (int i = 4; i < c->num_outputs; i++) {
1615 qir_VPM_WRITE(c, c->outputs[i]);
1616 }
1617 }
1618
1619 static void
1620 emit_coord_end(struct vc4_compile *c)
1621 {
1622 struct qreg rcp_w = qir_RCP(c, c->outputs[3]);
1623
1624 for (int i = 0; i < 4; i++)
1625 qir_VPM_WRITE(c, c->outputs[i]);
1626
1627 emit_scaled_viewport_write(c, rcp_w);
1628 emit_zs_write(c, rcp_w);
1629 emit_rcp_wc_write(c, rcp_w);
1630 if (c->vs_key->per_vertex_point_size)
1631 emit_point_size_write(c);
1632 }
1633
1634 static struct vc4_compile *
1635 vc4_shader_tgsi_to_qir(struct vc4_context *vc4,
1636 struct vc4_compiled_shader *shader, enum qstage stage,
1637 struct vc4_key *key)
1638 {
1639 struct vc4_compile *c = qir_compile_init();
1640 int ret;
1641
1642 c->stage = stage;
1643
1644 c->shader_state = key->shader_state;
1645 ret = tgsi_parse_init(&c->parser, c->shader_state->tokens);
1646 assert(ret == TGSI_PARSE_OK);
1647
1648 if (vc4_debug & VC4_DEBUG_TGSI) {
1649 fprintf(stderr, "TGSI:\n");
1650 tgsi_dump(c->shader_state->tokens, 0);
1651 }
1652
1653 c->key = key;
1654 switch (stage) {
1655 case QSTAGE_FRAG:
1656 c->fs_key = (struct vc4_fs_key *)key;
1657 if (c->fs_key->is_points) {
1658 c->point_x = emit_fragment_varying(c, 0);
1659 c->point_y = emit_fragment_varying(c, 0);
1660 } else if (c->fs_key->is_lines) {
1661 c->line_x = emit_fragment_varying(c, 0);
1662 }
1663 break;
1664 case QSTAGE_VERT:
1665 c->vs_key = (struct vc4_vs_key *)key;
1666 break;
1667 case QSTAGE_COORD:
1668 c->vs_key = (struct vc4_vs_key *)key;
1669 break;
1670 }
1671
1672 while (!tgsi_parse_end_of_tokens(&c->parser)) {
1673 tgsi_parse_token(&c->parser);
1674
1675 switch (c->parser.FullToken.Token.Type) {
1676 case TGSI_TOKEN_TYPE_DECLARATION:
1677 emit_tgsi_declaration(c,
1678 &c->parser.FullToken.FullDeclaration);
1679 break;
1680
1681 case TGSI_TOKEN_TYPE_INSTRUCTION:
1682 emit_tgsi_instruction(c,
1683 &c->parser.FullToken.FullInstruction);
1684 break;
1685
1686 case TGSI_TOKEN_TYPE_IMMEDIATE:
1687 parse_tgsi_immediate(c,
1688 &c->parser.FullToken.FullImmediate);
1689 break;
1690 }
1691 }
1692
1693 switch (stage) {
1694 case QSTAGE_FRAG:
1695 emit_frag_end(c);
1696 break;
1697 case QSTAGE_VERT:
1698 emit_vert_end(c);
1699 break;
1700 case QSTAGE_COORD:
1701 emit_coord_end(c);
1702 break;
1703 }
1704
1705 tgsi_parse_free(&c->parser);
1706
1707 qir_optimize(c);
1708
1709 if (vc4_debug & VC4_DEBUG_QIR) {
1710 fprintf(stderr, "QIR:\n");
1711 qir_dump(c);
1712 }
1713 qir_reorder_uniforms(c);
1714 vc4_generate_code(vc4, c);
1715
1716 if (vc4_debug & VC4_DEBUG_SHADERDB) {
1717 fprintf(stderr, "SHADER-DB: %s: %d instructions\n",
1718 qir_get_stage_name(c->stage), c->qpu_inst_count);
1719 fprintf(stderr, "SHADER-DB: %s: %d uniforms\n",
1720 qir_get_stage_name(c->stage), c->num_uniforms);
1721 }
1722
1723 return c;
1724 }
1725
1726 static void *
1727 vc4_shader_state_create(struct pipe_context *pctx,
1728 const struct pipe_shader_state *cso)
1729 {
1730 struct pipe_shader_state *so = CALLOC_STRUCT(pipe_shader_state);
1731 if (!so)
1732 return NULL;
1733
1734 const struct tgsi_lowering_config lowering_config = {
1735 .lower_DST = true,
1736 .lower_XPD = true,
1737 .lower_SCS = true,
1738 .lower_EXP = true,
1739 .lower_LOG = true,
1740 .lower_DPH = true,
1741 .lower_DP2A = true,
1742 };
1743
1744 struct tgsi_shader_info info;
1745 so->tokens = tgsi_transform_lowering(&lowering_config, cso->tokens, &info);
1746 if (!so->tokens)
1747 so->tokens = tgsi_dup_tokens(cso->tokens);
1748
1749 return so;
1750 }
1751
1752 static void
1753 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
1754 int shader_index,
1755 struct vc4_compile *c)
1756 {
1757 int count = c->num_uniforms;
1758 struct vc4_shader_uniform_info *uinfo = &shader->uniforms[shader_index];
1759
1760 uinfo->count = count;
1761 uinfo->data = malloc(count * sizeof(*uinfo->data));
1762 memcpy(uinfo->data, c->uniform_data,
1763 count * sizeof(*uinfo->data));
1764 uinfo->contents = malloc(count * sizeof(*uinfo->contents));
1765 memcpy(uinfo->contents, c->uniform_contents,
1766 count * sizeof(*uinfo->contents));
1767 uinfo->num_texture_samples = c->num_texture_samples;
1768 }
1769
1770 static void
1771 vc4_fs_compile(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1772 struct vc4_fs_key *key)
1773 {
1774 struct vc4_compile *c = vc4_shader_tgsi_to_qir(vc4, shader,
1775 QSTAGE_FRAG,
1776 &key->base);
1777 shader->num_inputs = c->num_inputs;
1778 shader->color_inputs = c->color_inputs;
1779 copy_uniform_state_to_shader(shader, 0, c);
1780 shader->bo = vc4_bo_alloc_mem(vc4->screen, c->qpu_insts,
1781 c->qpu_inst_count * sizeof(uint64_t),
1782 "fs_code");
1783
1784 qir_compile_destroy(c);
1785 }
1786
1787 static void
1788 vc4_vs_compile(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1789 struct vc4_vs_key *key)
1790 {
1791 struct vc4_compile *vs_c = vc4_shader_tgsi_to_qir(vc4, shader,
1792 QSTAGE_VERT,
1793 &key->base);
1794 copy_uniform_state_to_shader(shader, 0, vs_c);
1795
1796 struct vc4_compile *cs_c = vc4_shader_tgsi_to_qir(vc4, shader,
1797 QSTAGE_COORD,
1798 &key->base);
1799 copy_uniform_state_to_shader(shader, 1, cs_c);
1800
1801 uint32_t vs_size = vs_c->qpu_inst_count * sizeof(uint64_t);
1802 uint32_t cs_size = cs_c->qpu_inst_count * sizeof(uint64_t);
1803 shader->coord_shader_offset = vs_size; /* XXX: alignment? */
1804 shader->bo = vc4_bo_alloc(vc4->screen,
1805 shader->coord_shader_offset + cs_size,
1806 "vs_code");
1807
1808 void *map = vc4_bo_map(shader->bo);
1809 memcpy(map, vs_c->qpu_insts, vs_size);
1810 memcpy(map + shader->coord_shader_offset,
1811 cs_c->qpu_insts, cs_size);
1812
1813 qir_compile_destroy(vs_c);
1814 qir_compile_destroy(cs_c);
1815 }
1816
1817 static void
1818 vc4_setup_shared_key(struct vc4_key *key, struct vc4_texture_stateobj *texstate)
1819 {
1820 for (int i = 0; i < texstate->num_textures; i++) {
1821 struct pipe_sampler_view *sampler = texstate->textures[i];
1822 struct pipe_sampler_state *sampler_state =
1823 texstate->samplers[i];
1824
1825 if (sampler) {
1826 key->tex[i].format = sampler->format;
1827 key->tex[i].swizzle[0] = sampler->swizzle_r;
1828 key->tex[i].swizzle[1] = sampler->swizzle_g;
1829 key->tex[i].swizzle[2] = sampler->swizzle_b;
1830 key->tex[i].swizzle[3] = sampler->swizzle_a;
1831 key->tex[i].compare_mode = sampler_state->compare_mode;
1832 key->tex[i].compare_func = sampler_state->compare_func;
1833 key->tex[i].wrap_s = sampler_state->wrap_s;
1834 key->tex[i].wrap_t = sampler_state->wrap_t;
1835 }
1836 }
1837 }
1838
1839 static void
1840 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
1841 {
1842 struct vc4_fs_key local_key;
1843 struct vc4_fs_key *key = &local_key;
1844
1845 memset(key, 0, sizeof(*key));
1846 vc4_setup_shared_key(&key->base, &vc4->fragtex);
1847 key->base.shader_state = vc4->prog.bind_fs;
1848 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
1849 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
1850 prim_mode <= PIPE_PRIM_LINE_STRIP);
1851 key->blend = vc4->blend->rt[0];
1852
1853 if (vc4->framebuffer.cbufs[0])
1854 key->color_format = vc4->framebuffer.cbufs[0]->format;
1855
1856 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
1857 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
1858 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
1859 key->depth_enabled = (vc4->zsa->base.depth.enabled ||
1860 key->stencil_enabled);
1861 if (vc4->zsa->base.alpha.enabled) {
1862 key->alpha_test = true;
1863 key->alpha_test_func = vc4->zsa->base.alpha.func;
1864 }
1865
1866 if (key->is_points) {
1867 key->point_sprite_mask =
1868 vc4->rasterizer->base.sprite_coord_enable;
1869 key->point_coord_upper_left =
1870 (vc4->rasterizer->base.sprite_coord_mode ==
1871 PIPE_SPRITE_COORD_UPPER_LEFT);
1872 }
1873
1874 vc4->prog.fs = util_hash_table_get(vc4->fs_cache, key);
1875 if (vc4->prog.fs)
1876 return;
1877
1878 key = malloc(sizeof(*key));
1879 memcpy(key, &local_key, sizeof(*key));
1880
1881 struct vc4_compiled_shader *shader = CALLOC_STRUCT(vc4_compiled_shader);
1882 vc4_fs_compile(vc4, shader, key);
1883 util_hash_table_set(vc4->fs_cache, key, shader);
1884
1885 if (vc4->rasterizer->base.flatshade &&
1886 vc4->prog.fs &&
1887 vc4->prog.fs->color_inputs != shader->color_inputs) {
1888 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
1889 }
1890
1891 vc4->prog.fs = shader;
1892 }
1893
1894 static void
1895 vc4_update_compiled_vs(struct vc4_context *vc4, uint8_t prim_mode)
1896 {
1897 struct vc4_vs_key local_key;
1898 struct vc4_vs_key *key = &local_key;
1899
1900 memset(key, 0, sizeof(*key));
1901 vc4_setup_shared_key(&key->base, &vc4->verttex);
1902 key->base.shader_state = vc4->prog.bind_vs;
1903
1904 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
1905 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
1906
1907 key->per_vertex_point_size =
1908 (prim_mode == PIPE_PRIM_POINTS &&
1909 vc4->rasterizer->base.point_size_per_vertex);
1910
1911 vc4->prog.vs = util_hash_table_get(vc4->vs_cache, key);
1912 if (vc4->prog.vs)
1913 return;
1914
1915 key = malloc(sizeof(*key));
1916 memcpy(key, &local_key, sizeof(*key));
1917
1918 struct vc4_compiled_shader *shader = CALLOC_STRUCT(vc4_compiled_shader);
1919 vc4_vs_compile(vc4, shader, key);
1920 util_hash_table_set(vc4->vs_cache, key, shader);
1921
1922 vc4->prog.vs = shader;
1923 }
1924
1925 void
1926 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
1927 {
1928 vc4_update_compiled_fs(vc4, prim_mode);
1929 vc4_update_compiled_vs(vc4, prim_mode);
1930 }
1931
1932 static unsigned
1933 fs_cache_hash(void *key)
1934 {
1935 return util_hash_crc32(key, sizeof(struct vc4_fs_key));
1936 }
1937
1938 static unsigned
1939 vs_cache_hash(void *key)
1940 {
1941 return util_hash_crc32(key, sizeof(struct vc4_vs_key));
1942 }
1943
1944 static int
1945 fs_cache_compare(void *key1, void *key2)
1946 {
1947 return memcmp(key1, key2, sizeof(struct vc4_fs_key));
1948 }
1949
1950 static int
1951 vs_cache_compare(void *key1, void *key2)
1952 {
1953 return memcmp(key1, key2, sizeof(struct vc4_vs_key));
1954 }
1955
1956 struct delete_state {
1957 struct vc4_context *vc4;
1958 struct pipe_shader_state *shader_state;
1959 };
1960
1961 static enum pipe_error
1962 fs_delete_from_cache(void *in_key, void *in_value, void *data)
1963 {
1964 struct delete_state *del = data;
1965 struct vc4_fs_key *key = in_key;
1966 struct vc4_compiled_shader *shader = in_value;
1967
1968 if (key->base.shader_state == data) {
1969 util_hash_table_remove(del->vc4->fs_cache, key);
1970 vc4_bo_unreference(&shader->bo);
1971 free(shader);
1972 }
1973
1974 return 0;
1975 }
1976
1977 static enum pipe_error
1978 vs_delete_from_cache(void *in_key, void *in_value, void *data)
1979 {
1980 struct delete_state *del = data;
1981 struct vc4_vs_key *key = in_key;
1982 struct vc4_compiled_shader *shader = in_value;
1983
1984 if (key->base.shader_state == data) {
1985 util_hash_table_remove(del->vc4->vs_cache, key);
1986 vc4_bo_unreference(&shader->bo);
1987 free(shader);
1988 }
1989
1990 return 0;
1991 }
1992
1993 static void
1994 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
1995 {
1996 struct vc4_context *vc4 = vc4_context(pctx);
1997 struct pipe_shader_state *so = hwcso;
1998 struct delete_state del;
1999
2000 del.vc4 = vc4;
2001 del.shader_state = so;
2002 util_hash_table_foreach(vc4->fs_cache, fs_delete_from_cache, &del);
2003 util_hash_table_foreach(vc4->vs_cache, vs_delete_from_cache, &del);
2004
2005 free((void *)so->tokens);
2006 free(so);
2007 }
2008
2009 static uint32_t translate_wrap(uint32_t p_wrap, bool using_nearest)
2010 {
2011 switch (p_wrap) {
2012 case PIPE_TEX_WRAP_REPEAT:
2013 return 0;
2014 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
2015 return 1;
2016 case PIPE_TEX_WRAP_MIRROR_REPEAT:
2017 return 2;
2018 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
2019 return 3;
2020 case PIPE_TEX_WRAP_CLAMP:
2021 return (using_nearest ? 1 : 3);
2022 default:
2023 fprintf(stderr, "Unknown wrap mode %d\n", p_wrap);
2024 assert(!"not reached");
2025 return 0;
2026 }
2027 }
2028
2029 static void
2030 write_texture_p0(struct vc4_context *vc4,
2031 struct vc4_texture_stateobj *texstate,
2032 uint32_t unit)
2033 {
2034 struct pipe_sampler_view *texture = texstate->textures[unit];
2035 struct vc4_resource *rsc = vc4_resource(texture->texture);
2036
2037 bool is_cube = texture->target == PIPE_TEXTURE_CUBE;
2038
2039 cl_reloc(vc4, &vc4->uniforms, rsc->bo,
2040 rsc->slices[0].offset | texture->u.tex.last_level |
2041 is_cube << 9 |
2042 ((rsc->vc4_format & 7) << 4));
2043 }
2044
2045 static void
2046 write_texture_p1(struct vc4_context *vc4,
2047 struct vc4_texture_stateobj *texstate,
2048 uint32_t unit)
2049 {
2050 struct pipe_sampler_view *texture = texstate->textures[unit];
2051 struct vc4_resource *rsc = vc4_resource(texture->texture);
2052 struct pipe_sampler_state *sampler = texstate->samplers[unit];
2053 static const uint8_t minfilter_map[6] = {
2054 2, 4, /* mipfilter nearest */
2055 3, 5, /* mipfilter linear */
2056 1, 0, /* mipfilter none */
2057 };
2058 static const uint32_t magfilter_map[] = {
2059 [PIPE_TEX_FILTER_NEAREST] = 1,
2060 [PIPE_TEX_FILTER_LINEAR] = 0,
2061 };
2062
2063 bool either_nearest =
2064 (sampler->mag_img_filter == PIPE_TEX_MIPFILTER_NEAREST ||
2065 sampler->min_img_filter == PIPE_TEX_MIPFILTER_NEAREST);
2066
2067 cl_u32(&vc4->uniforms,
2068 ((rsc->vc4_format >> 4) << 31) |
2069 (texture->texture->height0 << 20) |
2070 (texture->texture->width0 << 8) |
2071 (magfilter_map[sampler->mag_img_filter] << 7) |
2072 (minfilter_map[sampler->min_mip_filter * 2 +
2073 sampler->min_img_filter] << 4) |
2074 (translate_wrap(sampler->wrap_t, either_nearest) << 2) |
2075 (translate_wrap(sampler->wrap_s, either_nearest) << 0));
2076 }
2077
2078 static void
2079 write_texture_p2(struct vc4_context *vc4,
2080 struct vc4_texture_stateobj *texstate,
2081 uint32_t unit)
2082 {
2083 struct pipe_sampler_view *texture = texstate->textures[unit];
2084 struct vc4_resource *rsc = vc4_resource(texture->texture);
2085
2086 cl_u32(&vc4->uniforms, (1 << 30) | rsc->cube_map_stride);
2087 }
2088
2089
2090 #define SWIZ(x,y,z,w) { \
2091 UTIL_FORMAT_SWIZZLE_##x, \
2092 UTIL_FORMAT_SWIZZLE_##y, \
2093 UTIL_FORMAT_SWIZZLE_##z, \
2094 UTIL_FORMAT_SWIZZLE_##w \
2095 }
2096
2097 static void
2098 write_texture_border_color(struct vc4_context *vc4,
2099 struct vc4_texture_stateobj *texstate,
2100 uint32_t unit)
2101 {
2102 struct pipe_sampler_state *sampler = texstate->samplers[unit];
2103 struct pipe_sampler_view *texture = texstate->textures[unit];
2104 struct vc4_resource *rsc = vc4_resource(texture->texture);
2105 union util_color uc;
2106
2107 const struct util_format_description *tex_format_desc =
2108 util_format_description(texture->format);
2109
2110 float border_color[4];
2111 for (int i = 0; i < 4; i++)
2112 border_color[i] = sampler->border_color.f[i];
2113 if (util_format_is_srgb(texture->format)) {
2114 for (int i = 0; i < 3; i++)
2115 border_color[i] =
2116 util_format_linear_to_srgb_float(border_color[i]);
2117 }
2118
2119 /* Turn the border color into the layout of channels that it would
2120 * have when stored as texture contents.
2121 */
2122 float storage_color[4];
2123 util_format_unswizzle_4f(storage_color,
2124 border_color,
2125 tex_format_desc->swizzle);
2126
2127 /* Now, pack so that when the vc4_format-sampled texture contents are
2128 * replaced with our border color, the vc4_get_format_swizzle()
2129 * swizzling will get the right channels.
2130 */
2131 if (util_format_is_depth_or_stencil(texture->format)) {
2132 uc.ui[0] = util_pack_z(PIPE_FORMAT_Z24X8_UNORM,
2133 sampler->border_color.f[0]) << 8;
2134 } else {
2135 switch (rsc->vc4_format) {
2136 default:
2137 case VC4_TEXTURE_TYPE_RGBA8888:
2138 util_pack_color(storage_color,
2139 PIPE_FORMAT_R8G8B8A8_UNORM, &uc);
2140 break;
2141 case VC4_TEXTURE_TYPE_RGBA4444:
2142 util_pack_color(storage_color,
2143 PIPE_FORMAT_A8B8G8R8_UNORM, &uc);
2144 break;
2145 case VC4_TEXTURE_TYPE_RGB565:
2146 util_pack_color(storage_color,
2147 PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
2148 break;
2149 case VC4_TEXTURE_TYPE_ALPHA:
2150 uc.ui[0] = float_to_ubyte(storage_color[0]) << 24;
2151 break;
2152 case VC4_TEXTURE_TYPE_LUMALPHA:
2153 uc.ui[0] = ((float_to_ubyte(storage_color[1]) << 24) |
2154 (float_to_ubyte(storage_color[0]) << 0));
2155 break;
2156 }
2157 }
2158
2159 cl_u32(&vc4->uniforms, uc.ui[0]);
2160 }
2161
2162 static uint32_t
2163 get_texrect_scale(struct vc4_texture_stateobj *texstate,
2164 enum quniform_contents contents,
2165 uint32_t data)
2166 {
2167 struct pipe_sampler_view *texture = texstate->textures[data];
2168 uint32_t dim;
2169
2170 if (contents == QUNIFORM_TEXRECT_SCALE_X)
2171 dim = texture->texture->width0;
2172 else
2173 dim = texture->texture->height0;
2174
2175 return fui(1.0f / dim);
2176 }
2177
2178 void
2179 vc4_write_uniforms(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
2180 struct vc4_constbuf_stateobj *cb,
2181 struct vc4_texture_stateobj *texstate,
2182 int shader_index)
2183 {
2184 struct vc4_shader_uniform_info *uinfo = &shader->uniforms[shader_index];
2185 const uint32_t *gallium_uniforms = cb->cb[0].user_buffer;
2186
2187 cl_start_shader_reloc(&vc4->uniforms, uinfo->num_texture_samples);
2188
2189 for (int i = 0; i < uinfo->count; i++) {
2190
2191 switch (uinfo->contents[i]) {
2192 case QUNIFORM_CONSTANT:
2193 cl_u32(&vc4->uniforms, uinfo->data[i]);
2194 break;
2195 case QUNIFORM_UNIFORM:
2196 cl_u32(&vc4->uniforms,
2197 gallium_uniforms[uinfo->data[i]]);
2198 break;
2199 case QUNIFORM_VIEWPORT_X_SCALE:
2200 cl_f(&vc4->uniforms, vc4->viewport.scale[0] * 16.0f);
2201 break;
2202 case QUNIFORM_VIEWPORT_Y_SCALE:
2203 cl_f(&vc4->uniforms, vc4->viewport.scale[1] * 16.0f);
2204 break;
2205
2206 case QUNIFORM_VIEWPORT_Z_OFFSET:
2207 cl_f(&vc4->uniforms, vc4->viewport.translate[2]);
2208 break;
2209 case QUNIFORM_VIEWPORT_Z_SCALE:
2210 cl_f(&vc4->uniforms, vc4->viewport.scale[2]);
2211 break;
2212
2213 case QUNIFORM_TEXTURE_CONFIG_P0:
2214 write_texture_p0(vc4, texstate, uinfo->data[i]);
2215 break;
2216
2217 case QUNIFORM_TEXTURE_CONFIG_P1:
2218 write_texture_p1(vc4, texstate, uinfo->data[i]);
2219 break;
2220
2221 case QUNIFORM_TEXTURE_CONFIG_P2:
2222 write_texture_p2(vc4, texstate, uinfo->data[i]);
2223 break;
2224
2225 case QUNIFORM_TEXTURE_BORDER_COLOR:
2226 write_texture_border_color(vc4, texstate, uinfo->data[i]);
2227 break;
2228
2229 case QUNIFORM_TEXRECT_SCALE_X:
2230 case QUNIFORM_TEXRECT_SCALE_Y:
2231 cl_u32(&vc4->uniforms,
2232 get_texrect_scale(texstate,
2233 uinfo->contents[i],
2234 uinfo->data[i]));
2235 break;
2236
2237 case QUNIFORM_BLEND_CONST_COLOR:
2238 cl_f(&vc4->uniforms,
2239 vc4->blend_color.color[uinfo->data[i]]);
2240 break;
2241
2242 case QUNIFORM_STENCIL:
2243 cl_u32(&vc4->uniforms,
2244 vc4->zsa->stencil_uniforms[uinfo->data[i]] |
2245 (uinfo->data[i] <= 1 ?
2246 (vc4->stencil_ref.ref_value[uinfo->data[i]] << 8) :
2247 0));
2248 break;
2249
2250 case QUNIFORM_ALPHA_REF:
2251 cl_f(&vc4->uniforms, vc4->zsa->base.alpha.ref_value);
2252 break;
2253 }
2254 #if 0
2255 uint32_t written_val = *(uint32_t *)(vc4->uniforms.next - 4);
2256 fprintf(stderr, "%p/%d: %d: 0x%08x (%f)\n",
2257 shader, shader_index, i, written_val, uif(written_val));
2258 #endif
2259 }
2260 }
2261
2262 static void
2263 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
2264 {
2265 struct vc4_context *vc4 = vc4_context(pctx);
2266 vc4->prog.bind_fs = hwcso;
2267 vc4->prog.dirty |= VC4_SHADER_DIRTY_FP;
2268 vc4->dirty |= VC4_DIRTY_PROG;
2269 }
2270
2271 static void
2272 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
2273 {
2274 struct vc4_context *vc4 = vc4_context(pctx);
2275 vc4->prog.bind_vs = hwcso;
2276 vc4->prog.dirty |= VC4_SHADER_DIRTY_VP;
2277 vc4->dirty |= VC4_DIRTY_PROG;
2278 }
2279
2280 void
2281 vc4_program_init(struct pipe_context *pctx)
2282 {
2283 struct vc4_context *vc4 = vc4_context(pctx);
2284
2285 pctx->create_vs_state = vc4_shader_state_create;
2286 pctx->delete_vs_state = vc4_shader_state_delete;
2287
2288 pctx->create_fs_state = vc4_shader_state_create;
2289 pctx->delete_fs_state = vc4_shader_state_delete;
2290
2291 pctx->bind_fs_state = vc4_fp_state_bind;
2292 pctx->bind_vs_state = vc4_vp_state_bind;
2293
2294 vc4->fs_cache = util_hash_table_create(fs_cache_hash, fs_cache_compare);
2295 vc4->vs_cache = util_hash_table_create(vs_cache_hash, vs_cache_compare);
2296 }