2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "util/u_format.h"
27 #include "util/u_hash.h"
28 #include "util/u_math.h"
29 #include "util/u_memory.h"
30 #include "util/ralloc.h"
31 #include "util/hash_table.h"
32 #include "tgsi/tgsi_dump.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "compiler/nir/nir.h"
35 #include "compiler/nir/nir_builder.h"
36 #include "nir/tgsi_to_nir.h"
37 #include "vc4_context.h"
40 #ifdef USE_VC4_SIMULATOR
41 #include "simpenrose/simpenrose.h"
45 ntq_get_src(struct vc4_compile
*c
, nir_src src
, int i
);
47 ntq_emit_cf_list(struct vc4_compile
*c
, struct exec_list
*list
);
50 resize_qreg_array(struct vc4_compile
*c
,
55 if (*size
>= decl_size
)
58 uint32_t old_size
= *size
;
59 *size
= MAX2(*size
* 2, decl_size
);
60 *regs
= reralloc(c
, *regs
, struct qreg
, *size
);
62 fprintf(stderr
, "Malloc failure\n");
66 for (uint32_t i
= old_size
; i
< *size
; i
++)
67 (*regs
)[i
] = c
->undef
;
71 indirect_uniform_load(struct vc4_compile
*c
, nir_intrinsic_instr
*intr
)
73 struct qreg indirect_offset
= ntq_get_src(c
, intr
->src
[0], 0);
74 uint32_t offset
= nir_intrinsic_base(intr
);
75 struct vc4_compiler_ubo_range
*range
= NULL
;
77 for (i
= 0; i
< c
->num_uniform_ranges
; i
++) {
78 range
= &c
->ubo_ranges
[i
];
79 if (offset
>= range
->src_offset
&&
80 offset
< range
->src_offset
+ range
->size
) {
84 /* The driver-location-based offset always has to be within a declared
90 range
->dst_offset
= c
->next_ubo_dst_offset
;
91 c
->next_ubo_dst_offset
+= range
->size
;
95 offset
-= range
->src_offset
;
97 /* Adjust for where we stored the TGSI register base. */
98 indirect_offset
= qir_ADD(c
, indirect_offset
,
99 qir_uniform_ui(c
, (range
->dst_offset
+
102 /* Clamp to [0, array size). Note that MIN/MAX are signed. */
103 indirect_offset
= qir_MAX(c
, indirect_offset
, qir_uniform_ui(c
, 0));
104 indirect_offset
= qir_MIN(c
, indirect_offset
,
105 qir_uniform_ui(c
, (range
->dst_offset
+
108 qir_TEX_DIRECT(c
, indirect_offset
, qir_uniform(c
, QUNIFORM_UBO_ADDR
, 0));
109 c
->num_texture_samples
++;
110 return qir_TEX_RESULT(c
);
113 nir_ssa_def
*vc4_nir_get_state_uniform(struct nir_builder
*b
,
114 enum quniform_contents contents
)
116 nir_intrinsic_instr
*intr
=
117 nir_intrinsic_instr_create(b
->shader
,
118 nir_intrinsic_load_uniform
);
119 nir_intrinsic_set_base(intr
,
120 (VC4_NIR_STATE_UNIFORM_OFFSET
+ contents
) * 4);
121 intr
->num_components
= 1;
122 intr
->src
[0] = nir_src_for_ssa(nir_imm_int(b
, 0));
123 nir_ssa_dest_init(&intr
->instr
, &intr
->dest
, 1, 32, NULL
);
124 nir_builder_instr_insert(b
, &intr
->instr
);
125 return &intr
->dest
.ssa
;
129 vc4_nir_get_swizzled_channel(nir_builder
*b
, nir_ssa_def
**srcs
, int swiz
)
133 case PIPE_SWIZZLE_NONE
:
134 fprintf(stderr
, "warning: unknown swizzle\n");
137 return nir_imm_float(b
, 0.0);
139 return nir_imm_float(b
, 1.0);
149 ntq_init_ssa_def(struct vc4_compile
*c
, nir_ssa_def
*def
)
151 struct qreg
*qregs
= ralloc_array(c
->def_ht
, struct qreg
,
152 def
->num_components
);
153 _mesa_hash_table_insert(c
->def_ht
, def
, qregs
);
158 ntq_store_dest(struct vc4_compile
*c
, nir_dest
*dest
, int chan
,
162 assert(chan
< dest
->ssa
.num_components
);
165 struct hash_entry
*entry
=
166 _mesa_hash_table_search(c
->def_ht
, &dest
->ssa
);
171 qregs
= ntq_init_ssa_def(c
, &dest
->ssa
);
173 qregs
[chan
] = result
;
175 nir_register
*reg
= dest
->reg
.reg
;
176 assert(dest
->reg
.base_offset
== 0);
177 assert(reg
->num_array_elems
== 0);
178 struct hash_entry
*entry
=
179 _mesa_hash_table_search(c
->def_ht
, reg
);
180 struct qreg
*qregs
= entry
->data
;
182 /* Conditionally move the result to the destination if the
185 if (c
->execute
.file
!= QFILE_NULL
) {
186 qir_SF(c
, c
->execute
);
187 qir_MOV_cond(c
, QPU_COND_ZS
, qregs
[chan
], result
);
189 qir_MOV_dest(c
, qregs
[chan
], result
);
195 ntq_get_dest(struct vc4_compile
*c
, nir_dest
*dest
)
198 struct qreg
*qregs
= ntq_init_ssa_def(c
, &dest
->ssa
);
199 for (int i
= 0; i
< dest
->ssa
.num_components
; i
++)
203 nir_register
*reg
= dest
->reg
.reg
;
204 assert(dest
->reg
.base_offset
== 0);
205 assert(reg
->num_array_elems
== 0);
206 struct hash_entry
*entry
=
207 _mesa_hash_table_search(c
->def_ht
, reg
);
213 ntq_get_src(struct vc4_compile
*c
, nir_src src
, int i
)
215 struct hash_entry
*entry
;
217 entry
= _mesa_hash_table_search(c
->def_ht
, src
.ssa
);
218 assert(i
< src
.ssa
->num_components
);
220 nir_register
*reg
= src
.reg
.reg
;
221 entry
= _mesa_hash_table_search(c
->def_ht
, reg
);
222 assert(reg
->num_array_elems
== 0);
223 assert(src
.reg
.base_offset
== 0);
224 assert(i
< reg
->num_components
);
227 struct qreg
*qregs
= entry
->data
;
232 ntq_get_alu_src(struct vc4_compile
*c
, nir_alu_instr
*instr
,
235 assert(util_is_power_of_two(instr
->dest
.write_mask
));
236 unsigned chan
= ffs(instr
->dest
.write_mask
) - 1;
237 struct qreg r
= ntq_get_src(c
, instr
->src
[src
].src
,
238 instr
->src
[src
].swizzle
[chan
]);
240 assert(!instr
->src
[src
].abs
);
241 assert(!instr
->src
[src
].negate
);
246 static inline struct qreg
247 qir_SAT(struct vc4_compile
*c
, struct qreg val
)
250 qir_FMIN(c
, val
, qir_uniform_f(c
, 1.0)),
251 qir_uniform_f(c
, 0.0));
255 ntq_rcp(struct vc4_compile
*c
, struct qreg x
)
257 struct qreg r
= qir_RCP(c
, x
);
259 /* Apply a Newton-Raphson step to improve the accuracy. */
260 r
= qir_FMUL(c
, r
, qir_FSUB(c
,
261 qir_uniform_f(c
, 2.0),
268 ntq_rsq(struct vc4_compile
*c
, struct qreg x
)
270 struct qreg r
= qir_RSQ(c
, x
);
272 /* Apply a Newton-Raphson step to improve the accuracy. */
273 r
= qir_FMUL(c
, r
, qir_FSUB(c
,
274 qir_uniform_f(c
, 1.5),
276 qir_uniform_f(c
, 0.5),
278 qir_FMUL(c
, r
, r
)))));
284 ntq_umul(struct vc4_compile
*c
, struct qreg src0
, struct qreg src1
)
286 struct qreg src0_hi
= qir_SHR(c
, src0
,
287 qir_uniform_ui(c
, 24));
288 struct qreg src1_hi
= qir_SHR(c
, src1
,
289 qir_uniform_ui(c
, 24));
291 struct qreg hilo
= qir_MUL24(c
, src0_hi
, src1
);
292 struct qreg lohi
= qir_MUL24(c
, src0
, src1_hi
);
293 struct qreg lolo
= qir_MUL24(c
, src0
, src1
);
295 return qir_ADD(c
, lolo
, qir_SHL(c
,
296 qir_ADD(c
, hilo
, lohi
),
297 qir_uniform_ui(c
, 24)));
301 ntq_scale_depth_texture(struct vc4_compile
*c
, struct qreg src
)
303 struct qreg depthf
= qir_ITOF(c
, qir_SHR(c
, src
,
304 qir_uniform_ui(c
, 8)));
305 return qir_FMUL(c
, depthf
, qir_uniform_f(c
, 1.0f
/0xffffff));
309 * Emits a lowered TXF_MS from an MSAA texture.
311 * The addressing math has been lowered in NIR, and now we just need to read
315 ntq_emit_txf(struct vc4_compile
*c
, nir_tex_instr
*instr
)
317 uint32_t tile_width
= 32;
318 uint32_t tile_height
= 32;
319 uint32_t tile_size
= (tile_height
* tile_width
*
320 VC4_MAX_SAMPLES
* sizeof(uint32_t));
322 unsigned unit
= instr
->texture_index
;
323 uint32_t w
= align(c
->key
->tex
[unit
].msaa_width
, tile_width
);
324 uint32_t w_tiles
= w
/ tile_width
;
325 uint32_t h
= align(c
->key
->tex
[unit
].msaa_height
, tile_height
);
326 uint32_t h_tiles
= h
/ tile_height
;
327 uint32_t size
= w_tiles
* h_tiles
* tile_size
;
330 assert(instr
->num_srcs
== 1);
331 assert(instr
->src
[0].src_type
== nir_tex_src_coord
);
332 addr
= ntq_get_src(c
, instr
->src
[0].src
, 0);
334 /* Perform the clamping required by kernel validation. */
335 addr
= qir_MAX(c
, addr
, qir_uniform_ui(c
, 0));
336 addr
= qir_MIN(c
, addr
, qir_uniform_ui(c
, size
- 4));
338 qir_TEX_DIRECT(c
, addr
, qir_uniform(c
, QUNIFORM_TEXTURE_MSAA_ADDR
, unit
));
340 struct qreg tex
= qir_TEX_RESULT(c
);
341 c
->num_texture_samples
++;
344 enum pipe_format format
= c
->key
->tex
[unit
].format
;
345 if (util_format_is_depth_or_stencil(format
)) {
346 struct qreg scaled
= ntq_scale_depth_texture(c
, tex
);
347 for (int i
= 0; i
< 4; i
++)
350 for (int i
= 0; i
< 4; i
++)
351 dest
[i
] = qir_UNPACK_8_F(c
, tex
, i
);
354 for (int i
= 0; i
< 4; i
++)
355 ntq_store_dest(c
, &instr
->dest
, i
, dest
[i
]);
359 ntq_emit_tex(struct vc4_compile
*c
, nir_tex_instr
*instr
)
361 struct qreg s
, t
, r
, lod
, compare
;
362 bool is_txb
= false, is_txl
= false;
363 unsigned unit
= instr
->texture_index
;
365 if (instr
->op
== nir_texop_txf
) {
366 ntq_emit_txf(c
, instr
);
370 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
371 switch (instr
->src
[i
].src_type
) {
372 case nir_tex_src_coord
:
373 s
= ntq_get_src(c
, instr
->src
[i
].src
, 0);
374 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
)
375 t
= qir_uniform_f(c
, 0.5);
377 t
= ntq_get_src(c
, instr
->src
[i
].src
, 1);
378 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
379 r
= ntq_get_src(c
, instr
->src
[i
].src
, 2);
381 case nir_tex_src_bias
:
382 lod
= ntq_get_src(c
, instr
->src
[i
].src
, 0);
385 case nir_tex_src_lod
:
386 lod
= ntq_get_src(c
, instr
->src
[i
].src
, 0);
389 case nir_tex_src_comparitor
:
390 compare
= ntq_get_src(c
, instr
->src
[i
].src
, 0);
393 unreachable("unknown texture source");
397 if (c
->key
->tex
[unit
].force_first_level
) {
398 lod
= qir_uniform(c
, QUNIFORM_TEXTURE_FIRST_LEVEL
, unit
);
403 struct qreg texture_u
[] = {
404 qir_uniform(c
, QUNIFORM_TEXTURE_CONFIG_P0
, unit
),
405 qir_uniform(c
, QUNIFORM_TEXTURE_CONFIG_P1
, unit
),
406 qir_uniform(c
, QUNIFORM_CONSTANT
, 0),
407 qir_uniform(c
, QUNIFORM_CONSTANT
, 0),
409 uint32_t next_texture_u
= 0;
411 /* There is no native support for GL texture rectangle coordinates, so
412 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
415 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_RECT
) {
417 qir_uniform(c
, QUNIFORM_TEXRECT_SCALE_X
, unit
));
419 qir_uniform(c
, QUNIFORM_TEXRECT_SCALE_Y
, unit
));
422 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
|| is_txl
) {
423 texture_u
[2] = qir_uniform(c
, QUNIFORM_TEXTURE_CONFIG_P2
,
424 unit
| (is_txl
<< 16));
427 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
428 qir_TEX_R(c
, r
, texture_u
[next_texture_u
++]);
429 } else if (c
->key
->tex
[unit
].wrap_s
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
430 c
->key
->tex
[unit
].wrap_s
== PIPE_TEX_WRAP_CLAMP
||
431 c
->key
->tex
[unit
].wrap_t
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
432 c
->key
->tex
[unit
].wrap_t
== PIPE_TEX_WRAP_CLAMP
) {
433 qir_TEX_R(c
, qir_uniform(c
, QUNIFORM_TEXTURE_BORDER_COLOR
, unit
),
434 texture_u
[next_texture_u
++]);
437 if (c
->key
->tex
[unit
].wrap_s
== PIPE_TEX_WRAP_CLAMP
) {
441 if (c
->key
->tex
[unit
].wrap_t
== PIPE_TEX_WRAP_CLAMP
) {
445 qir_TEX_T(c
, t
, texture_u
[next_texture_u
++]);
447 if (is_txl
|| is_txb
)
448 qir_TEX_B(c
, lod
, texture_u
[next_texture_u
++]);
450 qir_TEX_S(c
, s
, texture_u
[next_texture_u
++]);
452 c
->num_texture_samples
++;
453 struct qreg tex
= qir_TEX_RESULT(c
);
455 enum pipe_format format
= c
->key
->tex
[unit
].format
;
457 struct qreg
*dest
= ntq_get_dest(c
, &instr
->dest
);
458 if (util_format_is_depth_or_stencil(format
)) {
459 struct qreg normalized
= ntq_scale_depth_texture(c
, tex
);
460 struct qreg depth_output
;
462 struct qreg u0
= qir_uniform_f(c
, 0.0f
);
463 struct qreg u1
= qir_uniform_f(c
, 1.0f
);
464 if (c
->key
->tex
[unit
].compare_mode
) {
465 switch (c
->key
->tex
[unit
].compare_func
) {
466 case PIPE_FUNC_NEVER
:
467 depth_output
= qir_uniform_f(c
, 0.0f
);
469 case PIPE_FUNC_ALWAYS
:
472 case PIPE_FUNC_EQUAL
:
473 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
474 depth_output
= qir_SEL(c
, QPU_COND_ZS
, u1
, u0
);
476 case PIPE_FUNC_NOTEQUAL
:
477 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
478 depth_output
= qir_SEL(c
, QPU_COND_ZC
, u1
, u0
);
480 case PIPE_FUNC_GREATER
:
481 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
482 depth_output
= qir_SEL(c
, QPU_COND_NC
, u1
, u0
);
484 case PIPE_FUNC_GEQUAL
:
485 qir_SF(c
, qir_FSUB(c
, normalized
, compare
));
486 depth_output
= qir_SEL(c
, QPU_COND_NS
, u1
, u0
);
489 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
490 depth_output
= qir_SEL(c
, QPU_COND_NS
, u1
, u0
);
492 case PIPE_FUNC_LEQUAL
:
493 qir_SF(c
, qir_FSUB(c
, normalized
, compare
));
494 depth_output
= qir_SEL(c
, QPU_COND_NC
, u1
, u0
);
498 depth_output
= normalized
;
501 for (int i
= 0; i
< 4; i
++)
502 dest
[i
] = depth_output
;
504 for (int i
= 0; i
< 4; i
++)
505 dest
[i
] = qir_UNPACK_8_F(c
, tex
, i
);
510 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
514 ntq_ffract(struct vc4_compile
*c
, struct qreg src
)
516 struct qreg trunc
= qir_ITOF(c
, qir_FTOI(c
, src
));
517 struct qreg diff
= qir_FSUB(c
, src
, trunc
);
519 return qir_SEL(c
, QPU_COND_NS
,
520 qir_FADD(c
, diff
, qir_uniform_f(c
, 1.0)), diff
);
524 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
528 ntq_ffloor(struct vc4_compile
*c
, struct qreg src
)
530 struct qreg trunc
= qir_ITOF(c
, qir_FTOI(c
, src
));
532 /* This will be < 0 if we truncated and the truncation was of a value
533 * that was < 0 in the first place.
535 qir_SF(c
, qir_FSUB(c
, src
, trunc
));
537 return qir_SEL(c
, QPU_COND_NS
,
538 qir_FSUB(c
, trunc
, qir_uniform_f(c
, 1.0)), trunc
);
542 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
546 ntq_fceil(struct vc4_compile
*c
, struct qreg src
)
548 struct qreg trunc
= qir_ITOF(c
, qir_FTOI(c
, src
));
550 /* This will be < 0 if we truncated and the truncation was of a value
551 * that was > 0 in the first place.
553 qir_SF(c
, qir_FSUB(c
, trunc
, src
));
555 return qir_SEL(c
, QPU_COND_NS
,
556 qir_FADD(c
, trunc
, qir_uniform_f(c
, 1.0)), trunc
);
560 ntq_fsin(struct vc4_compile
*c
, struct qreg src
)
564 pow(2.0 * M_PI
, 3) / (3 * 2 * 1),
565 -pow(2.0 * M_PI
, 5) / (5 * 4 * 3 * 2 * 1),
566 pow(2.0 * M_PI
, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
567 -pow(2.0 * M_PI
, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
570 struct qreg scaled_x
=
573 qir_uniform_f(c
, 1.0 / (M_PI
* 2.0)));
575 struct qreg x
= qir_FADD(c
,
576 ntq_ffract(c
, scaled_x
),
577 qir_uniform_f(c
, -0.5));
578 struct qreg x2
= qir_FMUL(c
, x
, x
);
579 struct qreg sum
= qir_FMUL(c
, x
, qir_uniform_f(c
, coeff
[0]));
580 for (int i
= 1; i
< ARRAY_SIZE(coeff
); i
++) {
581 x
= qir_FMUL(c
, x
, x2
);
586 qir_uniform_f(c
, coeff
[i
])));
592 ntq_fcos(struct vc4_compile
*c
, struct qreg src
)
596 pow(2.0 * M_PI
, 2) / (2 * 1),
597 -pow(2.0 * M_PI
, 4) / (4 * 3 * 2 * 1),
598 pow(2.0 * M_PI
, 6) / (6 * 5 * 4 * 3 * 2 * 1),
599 -pow(2.0 * M_PI
, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
600 pow(2.0 * M_PI
, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
603 struct qreg scaled_x
=
605 qir_uniform_f(c
, 1.0f
/ (M_PI
* 2.0f
)));
606 struct qreg x_frac
= qir_FADD(c
,
607 ntq_ffract(c
, scaled_x
),
608 qir_uniform_f(c
, -0.5));
610 struct qreg sum
= qir_uniform_f(c
, coeff
[0]);
611 struct qreg x2
= qir_FMUL(c
, x_frac
, x_frac
);
612 struct qreg x
= x2
; /* Current x^2, x^4, or x^6 */
613 for (int i
= 1; i
< ARRAY_SIZE(coeff
); i
++) {
615 x
= qir_FMUL(c
, x
, x2
);
617 struct qreg mul
= qir_FMUL(c
,
619 qir_uniform_f(c
, coeff
[i
]));
623 sum
= qir_FADD(c
, sum
, mul
);
629 ntq_fsign(struct vc4_compile
*c
, struct qreg src
)
631 struct qreg t
= qir_get_temp(c
);
634 qir_MOV_dest(c
, t
, qir_uniform_f(c
, 0.0));
635 qir_MOV_dest(c
, t
, qir_uniform_f(c
, 1.0))->cond
= QPU_COND_ZC
;
636 qir_MOV_dest(c
, t
, qir_uniform_f(c
, -1.0))->cond
= QPU_COND_NS
;
641 emit_vertex_input(struct vc4_compile
*c
, int attr
)
643 enum pipe_format format
= c
->vs_key
->attr_formats
[attr
];
644 uint32_t attr_size
= util_format_get_blocksize(format
);
646 c
->vattr_sizes
[attr
] = align(attr_size
, 4);
647 for (int i
= 0; i
< align(attr_size
, 4) / 4; i
++) {
648 c
->inputs
[attr
* 4 + i
] =
649 qir_MOV(c
, qir_reg(QFILE_VPM
, attr
* 4 + i
));
655 emit_fragcoord_input(struct vc4_compile
*c
, int attr
)
657 c
->inputs
[attr
* 4 + 0] = qir_ITOF(c
, qir_reg(QFILE_FRAG_X
, 0));
658 c
->inputs
[attr
* 4 + 1] = qir_ITOF(c
, qir_reg(QFILE_FRAG_Y
, 0));
659 c
->inputs
[attr
* 4 + 2] =
661 qir_ITOF(c
, qir_FRAG_Z(c
)),
662 qir_uniform_f(c
, 1.0 / 0xffffff));
663 c
->inputs
[attr
* 4 + 3] = qir_RCP(c
, qir_FRAG_W(c
));
667 emit_fragment_varying(struct vc4_compile
*c
, gl_varying_slot slot
,
670 uint32_t i
= c
->num_input_slots
++;
676 if (c
->num_input_slots
>= c
->input_slots_array_size
) {
677 c
->input_slots_array_size
=
678 MAX2(4, c
->input_slots_array_size
* 2);
680 c
->input_slots
= reralloc(c
, c
->input_slots
,
681 struct vc4_varying_slot
,
682 c
->input_slots_array_size
);
685 c
->input_slots
[i
].slot
= slot
;
686 c
->input_slots
[i
].swizzle
= swizzle
;
688 return qir_VARY_ADD_C(c
, qir_FMUL(c
, vary
, qir_FRAG_W(c
)));
692 emit_fragment_input(struct vc4_compile
*c
, int attr
, gl_varying_slot slot
)
694 for (int i
= 0; i
< 4; i
++) {
695 c
->inputs
[attr
* 4 + i
] =
696 emit_fragment_varying(c
, slot
, i
);
702 add_output(struct vc4_compile
*c
,
703 uint32_t decl_offset
,
707 uint32_t old_array_size
= c
->outputs_array_size
;
708 resize_qreg_array(c
, &c
->outputs
, &c
->outputs_array_size
,
711 if (old_array_size
!= c
->outputs_array_size
) {
712 c
->output_slots
= reralloc(c
,
714 struct vc4_varying_slot
,
715 c
->outputs_array_size
);
718 c
->output_slots
[decl_offset
].slot
= slot
;
719 c
->output_slots
[decl_offset
].swizzle
= swizzle
;
723 declare_uniform_range(struct vc4_compile
*c
, uint32_t start
, uint32_t size
)
725 unsigned array_id
= c
->num_uniform_ranges
++;
726 if (array_id
>= c
->ubo_ranges_array_size
) {
727 c
->ubo_ranges_array_size
= MAX2(c
->ubo_ranges_array_size
* 2,
729 c
->ubo_ranges
= reralloc(c
, c
->ubo_ranges
,
730 struct vc4_compiler_ubo_range
,
731 c
->ubo_ranges_array_size
);
734 c
->ubo_ranges
[array_id
].dst_offset
= 0;
735 c
->ubo_ranges
[array_id
].src_offset
= start
;
736 c
->ubo_ranges
[array_id
].size
= size
;
737 c
->ubo_ranges
[array_id
].used
= false;
741 ntq_src_is_only_ssa_def_user(nir_src
*src
)
746 if (!list_empty(&src
->ssa
->if_uses
))
749 return (src
->ssa
->uses
.next
== &src
->use_link
&&
750 src
->ssa
->uses
.next
->next
== &src
->ssa
->uses
);
754 * In general, emits a nir_pack_unorm_4x8 as a series of MOVs with the pack
757 * However, as an optimization, it tries to find the instructions generating
758 * the sources to be packed and just emit the pack flag there, if possible.
761 ntq_emit_pack_unorm_4x8(struct vc4_compile
*c
, nir_alu_instr
*instr
)
763 struct qreg result
= qir_get_temp(c
);
764 struct nir_alu_instr
*vec4
= NULL
;
766 /* If packing from a vec4 op (as expected), identify it so that we can
767 * peek back at what generated its sources.
769 if (instr
->src
[0].src
.is_ssa
&&
770 instr
->src
[0].src
.ssa
->parent_instr
->type
== nir_instr_type_alu
&&
771 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
)->op
==
773 vec4
= nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
776 /* If the pack is replicating the same channel 4 times, use the 8888
777 * pack flag. This is common for blending using the alpha
780 if (instr
->src
[0].swizzle
[0] == instr
->src
[0].swizzle
[1] &&
781 instr
->src
[0].swizzle
[0] == instr
->src
[0].swizzle
[2] &&
782 instr
->src
[0].swizzle
[0] == instr
->src
[0].swizzle
[3]) {
783 struct qreg rep
= ntq_get_src(c
,
785 instr
->src
[0].swizzle
[0]);
786 ntq_store_dest(c
, &instr
->dest
.dest
, 0, qir_PACK_8888_F(c
, rep
));
790 for (int i
= 0; i
< 4; i
++) {
791 int swiz
= instr
->src
[0].swizzle
[i
];
794 src
= ntq_get_src(c
, vec4
->src
[swiz
].src
,
795 vec4
->src
[swiz
].swizzle
[0]);
797 src
= ntq_get_src(c
, instr
->src
[0].src
, swiz
);
801 ntq_src_is_only_ssa_def_user(&vec4
->src
[swiz
].src
) &&
802 src
.file
== QFILE_TEMP
&&
803 c
->defs
[src
.index
] &&
804 qir_is_mul(c
->defs
[src
.index
]) &&
805 !c
->defs
[src
.index
]->dst
.pack
) {
806 struct qinst
*rewrite
= c
->defs
[src
.index
];
807 c
->defs
[src
.index
] = NULL
;
808 rewrite
->dst
= result
;
809 rewrite
->dst
.pack
= QPU_PACK_MUL_8A
+ i
;
813 qir_PACK_8_F(c
, result
, src
, i
);
816 ntq_store_dest(c
, &instr
->dest
.dest
, 0, result
);
819 /** Handles sign-extended bitfield extracts for 16 bits. */
821 ntq_emit_ibfe(struct vc4_compile
*c
, struct qreg base
, struct qreg offset
,
824 assert(bits
.file
== QFILE_UNIF
&&
825 c
->uniform_contents
[bits
.index
] == QUNIFORM_CONSTANT
&&
826 c
->uniform_data
[bits
.index
] == 16);
828 assert(offset
.file
== QFILE_UNIF
&&
829 c
->uniform_contents
[offset
.index
] == QUNIFORM_CONSTANT
);
830 int offset_bit
= c
->uniform_data
[offset
.index
];
831 assert(offset_bit
% 16 == 0);
833 return qir_UNPACK_16_I(c
, base
, offset_bit
/ 16);
836 /** Handles unsigned bitfield extracts for 8 bits. */
838 ntq_emit_ubfe(struct vc4_compile
*c
, struct qreg base
, struct qreg offset
,
841 assert(bits
.file
== QFILE_UNIF
&&
842 c
->uniform_contents
[bits
.index
] == QUNIFORM_CONSTANT
&&
843 c
->uniform_data
[bits
.index
] == 8);
845 assert(offset
.file
== QFILE_UNIF
&&
846 c
->uniform_contents
[offset
.index
] == QUNIFORM_CONSTANT
);
847 int offset_bit
= c
->uniform_data
[offset
.index
];
848 assert(offset_bit
% 8 == 0);
850 return qir_UNPACK_8_I(c
, base
, offset_bit
/ 8);
854 * If compare_instr is a valid comparison instruction, emits the
855 * compare_instr's comparison and returns the sel_instr's return value based
856 * on the compare_instr's result.
859 ntq_emit_comparison(struct vc4_compile
*c
, struct qreg
*dest
,
860 nir_alu_instr
*compare_instr
,
861 nir_alu_instr
*sel_instr
)
865 switch (compare_instr
->op
) {
891 struct qreg src0
= ntq_get_alu_src(c
, compare_instr
, 0);
892 struct qreg src1
= ntq_get_alu_src(c
, compare_instr
, 1);
894 unsigned unsized_type
=
895 nir_alu_type_get_base_type(nir_op_infos
[compare_instr
->op
].input_types
[0]);
896 if (unsized_type
== nir_type_float
)
897 qir_SF(c
, qir_FSUB(c
, src0
, src1
));
899 qir_SF(c
, qir_SUB(c
, src0
, src1
));
901 switch (sel_instr
->op
) {
906 *dest
= qir_SEL(c
, cond
,
907 qir_uniform_f(c
, 1.0), qir_uniform_f(c
, 0.0));
911 *dest
= qir_SEL(c
, cond
,
912 ntq_get_alu_src(c
, sel_instr
, 1),
913 ntq_get_alu_src(c
, sel_instr
, 2));
917 *dest
= qir_SEL(c
, cond
,
918 qir_uniform_ui(c
, ~0), qir_uniform_ui(c
, 0));
926 * Attempts to fold a comparison generating a boolean result into the
927 * condition code for selecting between two values, instead of comparing the
928 * boolean result against 0 to generate the condition code.
930 static struct qreg
ntq_emit_bcsel(struct vc4_compile
*c
, nir_alu_instr
*instr
,
933 if (!instr
->src
[0].src
.is_ssa
)
935 nir_alu_instr
*compare
=
936 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
941 if (ntq_emit_comparison(c
, &dest
, compare
, instr
))
946 return qir_SEL(c
, QPU_COND_NS
, src
[1], src
[2]);
950 ntq_emit_alu(struct vc4_compile
*c
, nir_alu_instr
*instr
)
952 /* This should always be lowered to ALU operations for VC4. */
953 assert(!instr
->dest
.saturate
);
955 /* Vectors are special in that they have non-scalarized writemasks,
956 * and just take the first swizzle channel for each argument in order
957 * into each writemask channel.
959 if (instr
->op
== nir_op_vec2
||
960 instr
->op
== nir_op_vec3
||
961 instr
->op
== nir_op_vec4
) {
963 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
964 srcs
[i
] = ntq_get_src(c
, instr
->src
[i
].src
,
965 instr
->src
[i
].swizzle
[0]);
966 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
967 ntq_store_dest(c
, &instr
->dest
.dest
, i
, srcs
[i
]);
971 if (instr
->op
== nir_op_pack_unorm_4x8
) {
972 ntq_emit_pack_unorm_4x8(c
, instr
);
976 if (instr
->op
== nir_op_unpack_unorm_4x8
) {
977 struct qreg src
= ntq_get_src(c
, instr
->src
[0].src
,
978 instr
->src
[0].swizzle
[0]);
979 for (int i
= 0; i
< 4; i
++) {
980 if (instr
->dest
.write_mask
& (1 << i
))
981 ntq_store_dest(c
, &instr
->dest
.dest
, i
,
982 qir_UNPACK_8_F(c
, src
, i
));
987 /* General case: We can just grab the one used channel per src. */
988 struct qreg src
[nir_op_infos
[instr
->op
].num_inputs
];
989 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
990 src
[i
] = ntq_get_alu_src(c
, instr
, i
);
998 result
= qir_MOV(c
, src
[0]);
1001 result
= qir_FMUL(c
, src
[0], src
[1]);
1004 result
= qir_FADD(c
, src
[0], src
[1]);
1007 result
= qir_FSUB(c
, src
[0], src
[1]);
1010 result
= qir_FMIN(c
, src
[0], src
[1]);
1013 result
= qir_FMAX(c
, src
[0], src
[1]);
1018 result
= qir_FTOI(c
, src
[0]);
1022 result
= qir_ITOF(c
, src
[0]);
1025 result
= qir_AND(c
, src
[0], qir_uniform_f(c
, 1.0));
1028 result
= qir_AND(c
, src
[0], qir_uniform_ui(c
, 1));
1033 result
= qir_SEL(c
, QPU_COND_ZC
,
1034 qir_uniform_ui(c
, ~0),
1035 qir_uniform_ui(c
, 0));
1039 result
= qir_ADD(c
, src
[0], src
[1]);
1042 result
= qir_SHR(c
, src
[0], src
[1]);
1045 result
= qir_SUB(c
, src
[0], src
[1]);
1048 result
= qir_ASR(c
, src
[0], src
[1]);
1051 result
= qir_SHL(c
, src
[0], src
[1]);
1054 result
= qir_MIN(c
, src
[0], src
[1]);
1057 result
= qir_MAX(c
, src
[0], src
[1]);
1060 result
= qir_AND(c
, src
[0], src
[1]);
1063 result
= qir_OR(c
, src
[0], src
[1]);
1066 result
= qir_XOR(c
, src
[0], src
[1]);
1069 result
= qir_NOT(c
, src
[0]);
1073 result
= ntq_umul(c
, src
[0], src
[1]);
1089 if (!ntq_emit_comparison(c
, &result
, instr
, instr
)) {
1090 fprintf(stderr
, "Bad comparison instruction\n");
1095 result
= ntq_emit_bcsel(c
, instr
, src
);
1099 result
= qir_SEL(c
, QPU_COND_ZC
, src
[1], src
[2]);
1103 result
= ntq_rcp(c
, src
[0]);
1106 result
= ntq_rsq(c
, src
[0]);
1109 result
= qir_EXP2(c
, src
[0]);
1112 result
= qir_LOG2(c
, src
[0]);
1116 result
= qir_ITOF(c
, qir_FTOI(c
, src
[0]));
1119 result
= ntq_fceil(c
, src
[0]);
1122 result
= ntq_ffract(c
, src
[0]);
1125 result
= ntq_ffloor(c
, src
[0]);
1129 result
= ntq_fsin(c
, src
[0]);
1132 result
= ntq_fcos(c
, src
[0]);
1136 result
= ntq_fsign(c
, src
[0]);
1140 result
= qir_FMAXABS(c
, src
[0], src
[0]);
1143 result
= qir_MAX(c
, src
[0],
1144 qir_SUB(c
, qir_uniform_ui(c
, 0), src
[0]));
1147 case nir_op_ibitfield_extract
:
1148 result
= ntq_emit_ibfe(c
, src
[0], src
[1], src
[2]);
1151 case nir_op_ubitfield_extract
:
1152 result
= ntq_emit_ubfe(c
, src
[0], src
[1], src
[2]);
1155 case nir_op_usadd_4x8
:
1156 result
= qir_V8ADDS(c
, src
[0], src
[1]);
1159 case nir_op_ussub_4x8
:
1160 result
= qir_V8SUBS(c
, src
[0], src
[1]);
1163 case nir_op_umin_4x8
:
1164 result
= qir_V8MIN(c
, src
[0], src
[1]);
1167 case nir_op_umax_4x8
:
1168 result
= qir_V8MAX(c
, src
[0], src
[1]);
1171 case nir_op_umul_unorm_4x8
:
1172 result
= qir_V8MULD(c
, src
[0], src
[1]);
1176 fprintf(stderr
, "unknown NIR ALU inst: ");
1177 nir_print_instr(&instr
->instr
, stderr
);
1178 fprintf(stderr
, "\n");
1182 /* We have a scalar result, so the instruction should only have a
1183 * single channel written to.
1185 assert(util_is_power_of_two(instr
->dest
.write_mask
));
1186 ntq_store_dest(c
, &instr
->dest
.dest
,
1187 ffs(instr
->dest
.write_mask
) - 1, result
);
1191 emit_frag_end(struct vc4_compile
*c
)
1194 if (c
->output_color_index
!= -1) {
1195 color
= c
->outputs
[c
->output_color_index
];
1197 color
= qir_uniform_ui(c
, 0);
1200 uint32_t discard_cond
= QPU_COND_ALWAYS
;
1201 if (c
->discard
.file
!= QFILE_NULL
) {
1202 qir_SF(c
, c
->discard
);
1203 discard_cond
= QPU_COND_ZS
;
1206 if (c
->fs_key
->stencil_enabled
) {
1207 qir_MOV_dest(c
, qir_reg(QFILE_TLB_STENCIL_SETUP
, 0),
1208 qir_uniform(c
, QUNIFORM_STENCIL
, 0));
1209 if (c
->fs_key
->stencil_twoside
) {
1210 qir_MOV_dest(c
, qir_reg(QFILE_TLB_STENCIL_SETUP
, 0),
1211 qir_uniform(c
, QUNIFORM_STENCIL
, 1));
1213 if (c
->fs_key
->stencil_full_writemasks
) {
1214 qir_MOV_dest(c
, qir_reg(QFILE_TLB_STENCIL_SETUP
, 0),
1215 qir_uniform(c
, QUNIFORM_STENCIL
, 2));
1219 if (c
->output_sample_mask_index
!= -1) {
1220 qir_MS_MASK(c
, c
->outputs
[c
->output_sample_mask_index
]);
1223 if (c
->fs_key
->depth_enabled
) {
1224 if (c
->output_position_index
!= -1) {
1225 qir_FTOI_dest(c
, qir_reg(QFILE_TLB_Z_WRITE
, 0),
1227 c
->outputs
[c
->output_position_index
],
1228 qir_uniform_f(c
, 0xffffff)))->cond
= discard_cond
;
1230 qir_MOV_dest(c
, qir_reg(QFILE_TLB_Z_WRITE
, 0),
1231 qir_FRAG_Z(c
))->cond
= discard_cond
;
1235 if (!c
->msaa_per_sample_output
) {
1236 qir_MOV_dest(c
, qir_reg(QFILE_TLB_COLOR_WRITE
, 0),
1237 color
)->cond
= discard_cond
;
1239 for (int i
= 0; i
< VC4_MAX_SAMPLES
; i
++) {
1240 qir_MOV_dest(c
, qir_reg(QFILE_TLB_COLOR_WRITE_MS
, 0),
1241 c
->sample_colors
[i
])->cond
= discard_cond
;
1247 emit_scaled_viewport_write(struct vc4_compile
*c
, struct qreg rcp_w
)
1249 struct qreg packed
= qir_get_temp(c
);
1251 for (int i
= 0; i
< 2; i
++) {
1253 qir_uniform(c
, QUNIFORM_VIEWPORT_X_SCALE
+ i
, 0);
1255 struct qreg packed_chan
= packed
;
1256 packed_chan
.pack
= QPU_PACK_A_16A
+ i
;
1258 qir_FTOI_dest(c
, packed_chan
,
1261 c
->outputs
[c
->output_position_index
+ i
],
1266 qir_VPM_WRITE(c
, packed
);
1270 emit_zs_write(struct vc4_compile
*c
, struct qreg rcp_w
)
1272 struct qreg zscale
= qir_uniform(c
, QUNIFORM_VIEWPORT_Z_SCALE
, 0);
1273 struct qreg zoffset
= qir_uniform(c
, QUNIFORM_VIEWPORT_Z_OFFSET
, 0);
1275 qir_VPM_WRITE(c
, qir_FADD(c
, qir_FMUL(c
, qir_FMUL(c
,
1276 c
->outputs
[c
->output_position_index
+ 2],
1283 emit_rcp_wc_write(struct vc4_compile
*c
, struct qreg rcp_w
)
1285 qir_VPM_WRITE(c
, rcp_w
);
1289 emit_point_size_write(struct vc4_compile
*c
)
1291 struct qreg point_size
;
1293 if (c
->output_point_size_index
!= -1)
1294 point_size
= c
->outputs
[c
->output_point_size_index
];
1296 point_size
= qir_uniform_f(c
, 1.0);
1298 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1301 point_size
= qir_FMAX(c
, point_size
, qir_uniform_f(c
, .125));
1303 qir_VPM_WRITE(c
, point_size
);
1307 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1309 * The simulator insists that there be at least one vertex attribute, so
1310 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also
1311 * insists that all vertex attributes loaded get read by the VS/CS, so we have
1312 * to consume it here.
1315 emit_stub_vpm_read(struct vc4_compile
*c
)
1320 c
->vattr_sizes
[0] = 4;
1321 (void)qir_MOV(c
, qir_reg(QFILE_VPM
, 0));
1326 emit_vert_end(struct vc4_compile
*c
,
1327 struct vc4_varying_slot
*fs_inputs
,
1328 uint32_t num_fs_inputs
)
1330 struct qreg rcp_w
= qir_RCP(c
, c
->outputs
[c
->output_position_index
+ 3]);
1332 emit_stub_vpm_read(c
);
1334 emit_scaled_viewport_write(c
, rcp_w
);
1335 emit_zs_write(c
, rcp_w
);
1336 emit_rcp_wc_write(c
, rcp_w
);
1337 if (c
->vs_key
->per_vertex_point_size
)
1338 emit_point_size_write(c
);
1340 for (int i
= 0; i
< num_fs_inputs
; i
++) {
1341 struct vc4_varying_slot
*input
= &fs_inputs
[i
];
1344 for (j
= 0; j
< c
->num_outputs
; j
++) {
1345 struct vc4_varying_slot
*output
=
1346 &c
->output_slots
[j
];
1348 if (input
->slot
== output
->slot
&&
1349 input
->swizzle
== output
->swizzle
) {
1350 qir_VPM_WRITE(c
, c
->outputs
[j
]);
1354 /* Emit padding if we didn't find a declared VS output for
1357 if (j
== c
->num_outputs
)
1358 qir_VPM_WRITE(c
, qir_uniform_f(c
, 0.0));
1363 emit_coord_end(struct vc4_compile
*c
)
1365 struct qreg rcp_w
= qir_RCP(c
, c
->outputs
[c
->output_position_index
+ 3]);
1367 emit_stub_vpm_read(c
);
1369 for (int i
= 0; i
< 4; i
++)
1370 qir_VPM_WRITE(c
, c
->outputs
[c
->output_position_index
+ i
]);
1372 emit_scaled_viewport_write(c
, rcp_w
);
1373 emit_zs_write(c
, rcp_w
);
1374 emit_rcp_wc_write(c
, rcp_w
);
1375 if (c
->vs_key
->per_vertex_point_size
)
1376 emit_point_size_write(c
);
1380 vc4_optimize_nir(struct nir_shader
*s
)
1387 NIR_PASS_V(s
, nir_lower_vars_to_ssa
);
1388 NIR_PASS_V(s
, nir_lower_alu_to_scalar
);
1389 NIR_PASS_V(s
, nir_lower_phis_to_scalar
);
1391 NIR_PASS(progress
, s
, nir_copy_prop
);
1392 NIR_PASS(progress
, s
, nir_opt_remove_phis
);
1393 NIR_PASS(progress
, s
, nir_opt_dce
);
1394 NIR_PASS(progress
, s
, nir_opt_dead_cf
);
1395 NIR_PASS(progress
, s
, nir_opt_cse
);
1396 NIR_PASS(progress
, s
, nir_opt_peephole_select
);
1397 NIR_PASS(progress
, s
, nir_opt_algebraic
);
1398 NIR_PASS(progress
, s
, nir_opt_constant_folding
);
1399 NIR_PASS(progress
, s
, nir_opt_undef
);
1404 driver_location_compare(const void *in_a
, const void *in_b
)
1406 const nir_variable
*const *a
= in_a
;
1407 const nir_variable
*const *b
= in_b
;
1409 return (*a
)->data
.driver_location
- (*b
)->data
.driver_location
;
1413 ntq_setup_inputs(struct vc4_compile
*c
)
1415 unsigned num_entries
= 0;
1416 nir_foreach_variable(var
, &c
->s
->inputs
)
1419 nir_variable
*vars
[num_entries
];
1422 nir_foreach_variable(var
, &c
->s
->inputs
)
1425 /* Sort the variables so that we emit the input setup in
1426 * driver_location order. This is required for VPM reads, whose data
1427 * is fetched into the VPM in driver_location (TGSI register index)
1430 qsort(&vars
, num_entries
, sizeof(*vars
), driver_location_compare
);
1432 for (unsigned i
= 0; i
< num_entries
; i
++) {
1433 nir_variable
*var
= vars
[i
];
1434 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1435 unsigned loc
= var
->data
.driver_location
;
1437 assert(array_len
== 1);
1439 resize_qreg_array(c
, &c
->inputs
, &c
->inputs_array_size
,
1442 if (c
->stage
== QSTAGE_FRAG
) {
1443 if (var
->data
.location
== VARYING_SLOT_POS
) {
1444 emit_fragcoord_input(c
, loc
);
1445 } else if (var
->data
.location
>= VARYING_SLOT_VAR0
&&
1446 (c
->fs_key
->point_sprite_mask
&
1447 (1 << (var
->data
.location
-
1448 VARYING_SLOT_VAR0
)))) {
1449 c
->inputs
[loc
* 4 + 0] = c
->point_x
;
1450 c
->inputs
[loc
* 4 + 1] = c
->point_y
;
1452 emit_fragment_input(c
, loc
, var
->data
.location
);
1455 emit_vertex_input(c
, loc
);
1461 ntq_setup_outputs(struct vc4_compile
*c
)
1463 nir_foreach_variable(var
, &c
->s
->outputs
) {
1464 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1465 unsigned loc
= var
->data
.driver_location
* 4;
1467 assert(array_len
== 1);
1470 for (int i
= 0; i
< 4; i
++)
1471 add_output(c
, loc
+ i
, var
->data
.location
, i
);
1473 if (c
->stage
== QSTAGE_FRAG
) {
1474 switch (var
->data
.location
) {
1475 case FRAG_RESULT_COLOR
:
1476 case FRAG_RESULT_DATA0
:
1477 c
->output_color_index
= loc
;
1479 case FRAG_RESULT_DEPTH
:
1480 c
->output_position_index
= loc
;
1482 case FRAG_RESULT_SAMPLE_MASK
:
1483 c
->output_sample_mask_index
= loc
;
1487 switch (var
->data
.location
) {
1488 case VARYING_SLOT_POS
:
1489 c
->output_position_index
= loc
;
1491 case VARYING_SLOT_PSIZ
:
1492 c
->output_point_size_index
= loc
;
1500 ntq_setup_uniforms(struct vc4_compile
*c
)
1502 nir_foreach_variable(var
, &c
->s
->uniforms
) {
1503 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1504 unsigned array_elem_size
= 4 * sizeof(float);
1506 declare_uniform_range(c
, var
->data
.driver_location
* array_elem_size
,
1507 array_len
* array_elem_size
);
1513 * Sets up the mapping from nir_register to struct qreg *.
1515 * Each nir_register gets a struct qreg per 32-bit component being stored.
1518 ntq_setup_registers(struct vc4_compile
*c
, struct exec_list
*list
)
1520 foreach_list_typed(nir_register
, nir_reg
, node
, list
) {
1521 unsigned array_len
= MAX2(nir_reg
->num_array_elems
, 1);
1522 struct qreg
*qregs
= ralloc_array(c
->def_ht
, struct qreg
,
1524 nir_reg
->num_components
);
1526 _mesa_hash_table_insert(c
->def_ht
, nir_reg
, qregs
);
1528 for (int i
= 0; i
< array_len
* nir_reg
->num_components
; i
++)
1529 qregs
[i
] = qir_get_temp(c
);
1534 ntq_emit_load_const(struct vc4_compile
*c
, nir_load_const_instr
*instr
)
1536 struct qreg
*qregs
= ntq_init_ssa_def(c
, &instr
->def
);
1537 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1538 qregs
[i
] = qir_uniform_ui(c
, instr
->value
.u32
[i
]);
1540 _mesa_hash_table_insert(c
->def_ht
, &instr
->def
, qregs
);
1544 ntq_emit_ssa_undef(struct vc4_compile
*c
, nir_ssa_undef_instr
*instr
)
1546 struct qreg
*qregs
= ntq_init_ssa_def(c
, &instr
->def
);
1548 /* QIR needs there to be *some* value, so pick 0 (same as for
1549 * ntq_setup_registers().
1551 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1552 qregs
[i
] = qir_uniform_ui(c
, 0);
1556 ntq_emit_intrinsic(struct vc4_compile
*c
, nir_intrinsic_instr
*instr
)
1558 nir_const_value
*const_offset
;
1561 switch (instr
->intrinsic
) {
1562 case nir_intrinsic_load_uniform
:
1563 assert(instr
->num_components
== 1);
1564 const_offset
= nir_src_as_const_value(instr
->src
[0]);
1566 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1567 assert(offset
% 4 == 0);
1568 /* We need dwords */
1569 offset
= offset
/ 4;
1570 if (offset
< VC4_NIR_STATE_UNIFORM_OFFSET
) {
1571 ntq_store_dest(c
, &instr
->dest
, 0,
1572 qir_uniform(c
, QUNIFORM_UNIFORM
,
1575 ntq_store_dest(c
, &instr
->dest
, 0,
1576 qir_uniform(c
, offset
-
1577 VC4_NIR_STATE_UNIFORM_OFFSET
,
1581 ntq_store_dest(c
, &instr
->dest
, 0,
1582 indirect_uniform_load(c
, instr
));
1586 case nir_intrinsic_load_user_clip_plane
:
1587 for (int i
= 0; i
< instr
->num_components
; i
++) {
1588 ntq_store_dest(c
, &instr
->dest
, i
,
1589 qir_uniform(c
, QUNIFORM_USER_CLIP_PLANE
,
1590 nir_intrinsic_ucp_id(instr
) *
1595 case nir_intrinsic_load_sample_mask_in
:
1596 ntq_store_dest(c
, &instr
->dest
, 0,
1597 qir_uniform(c
, QUNIFORM_SAMPLE_MASK
, 0));
1600 case nir_intrinsic_load_front_face
:
1601 /* The register contains 0 (front) or 1 (back), and we need to
1602 * turn it into a NIR bool where true means front.
1604 ntq_store_dest(c
, &instr
->dest
, 0,
1606 qir_uniform_ui(c
, -1),
1607 qir_reg(QFILE_FRAG_REV_FLAG
, 0)));
1610 case nir_intrinsic_load_input
:
1611 assert(instr
->num_components
== 1);
1612 const_offset
= nir_src_as_const_value(instr
->src
[0]);
1613 assert(const_offset
&& "vc4 doesn't support indirect inputs");
1614 if (c
->stage
== QSTAGE_FRAG
&&
1615 nir_intrinsic_base(instr
) >= VC4_NIR_TLB_COLOR_READ_INPUT
) {
1616 assert(const_offset
->u32
[0] == 0);
1617 /* Reads of the per-sample color need to be done in
1620 int sample_index
= (nir_intrinsic_base(instr
) -
1621 VC4_NIR_TLB_COLOR_READ_INPUT
);
1622 for (int i
= 0; i
<= sample_index
; i
++) {
1623 if (c
->color_reads
[i
].file
== QFILE_NULL
) {
1625 qir_TLB_COLOR_READ(c
);
1628 ntq_store_dest(c
, &instr
->dest
, 0,
1629 c
->color_reads
[sample_index
]);
1631 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1632 int comp
= nir_intrinsic_component(instr
);
1633 ntq_store_dest(c
, &instr
->dest
, 0,
1634 c
->inputs
[offset
* 4 + comp
]);
1638 case nir_intrinsic_store_output
:
1639 const_offset
= nir_src_as_const_value(instr
->src
[1]);
1640 assert(const_offset
&& "vc4 doesn't support indirect outputs");
1641 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1643 /* MSAA color outputs are the only case where we have an
1644 * output that's not lowered to being a store of a single 32
1647 if (c
->stage
== QSTAGE_FRAG
&& instr
->num_components
== 4) {
1648 assert(offset
== c
->output_color_index
);
1649 for (int i
= 0; i
< 4; i
++) {
1650 c
->sample_colors
[i
] =
1651 qir_MOV(c
, ntq_get_src(c
, instr
->src
[0],
1655 offset
= offset
* 4 + nir_intrinsic_component(instr
);
1656 assert(instr
->num_components
== 1);
1657 c
->outputs
[offset
] =
1658 qir_MOV(c
, ntq_get_src(c
, instr
->src
[0], 0));
1659 c
->num_outputs
= MAX2(c
->num_outputs
, offset
+ 1);
1663 case nir_intrinsic_discard
:
1664 c
->discard
= qir_uniform_ui(c
, ~0);
1667 case nir_intrinsic_discard_if
:
1668 if (c
->discard
.file
== QFILE_NULL
)
1669 c
->discard
= qir_uniform_ui(c
, 0);
1670 c
->discard
= qir_OR(c
, c
->discard
,
1671 ntq_get_src(c
, instr
->src
[0], 0));
1675 fprintf(stderr
, "Unknown intrinsic: ");
1676 nir_print_instr(&instr
->instr
, stderr
);
1677 fprintf(stderr
, "\n");
1682 /* Clears (activates) the execute flags for any channels whose jump target
1683 * matches this block.
1686 ntq_activate_execute_for_block(struct vc4_compile
*c
)
1688 qir_SF(c
, qir_SUB(c
,
1690 qir_uniform_ui(c
, c
->cur_block
->index
)));
1691 qir_MOV_cond(c
, QPU_COND_ZS
, c
->execute
, qir_uniform_ui(c
, 0));
1695 ntq_emit_if(struct vc4_compile
*c
, nir_if
*if_stmt
)
1697 if (!c
->vc4
->screen
->has_control_flow
) {
1699 "IF statement support requires updated kernel.\n");
1703 nir_cf_node
*nir_first_else_node
= nir_if_first_else_node(if_stmt
);
1704 nir_cf_node
*nir_last_else_node
= nir_if_last_else_node(if_stmt
);
1705 nir_block
*nir_else_block
= nir_cf_node_as_block(nir_first_else_node
);
1706 bool empty_else_block
=
1707 (nir_first_else_node
== nir_last_else_node
&&
1708 exec_list_is_empty(&nir_else_block
->instr_list
));
1710 struct qblock
*then_block
= qir_new_block(c
);
1711 struct qblock
*after_block
= qir_new_block(c
);
1712 struct qblock
*else_block
;
1713 if (empty_else_block
)
1714 else_block
= after_block
;
1716 else_block
= qir_new_block(c
);
1718 bool was_top_level
= false;
1719 if (c
->execute
.file
== QFILE_NULL
) {
1720 c
->execute
= qir_MOV(c
, qir_uniform_ui(c
, 0));
1721 was_top_level
= true;
1724 /* Set ZS for executing (execute == 0) and jumping (if->condition ==
1725 * 0) channels, and then update execute flags for those to point to
1730 ntq_get_src(c
, if_stmt
->condition
, 0)));
1731 qir_MOV_cond(c
, QPU_COND_ZS
, c
->execute
,
1732 qir_uniform_ui(c
, else_block
->index
));
1734 /* Jump to ELSE if nothing is active for THEN, otherwise fall
1737 qir_SF(c
, c
->execute
);
1738 qir_BRANCH(c
, QPU_COND_BRANCH_ALL_ZC
);
1739 qir_link_blocks(c
->cur_block
, else_block
);
1740 qir_link_blocks(c
->cur_block
, then_block
);
1742 /* Process the THEN block. */
1743 qir_set_emit_block(c
, then_block
);
1744 ntq_emit_cf_list(c
, &if_stmt
->then_list
);
1746 if (!empty_else_block
) {
1747 /* Handle the end of the THEN block. First, all currently
1748 * active channels update their execute flags to point to
1751 qir_SF(c
, c
->execute
);
1752 qir_MOV_cond(c
, QPU_COND_ZS
, c
->execute
,
1753 qir_uniform_ui(c
, after_block
->index
));
1755 /* If everything points at ENDIF, then jump there immediately. */
1756 qir_SF(c
, qir_SUB(c
, c
->execute
, qir_uniform_ui(c
, after_block
->index
)));
1757 qir_BRANCH(c
, QPU_COND_BRANCH_ALL_ZS
);
1758 qir_link_blocks(c
->cur_block
, after_block
);
1759 qir_link_blocks(c
->cur_block
, else_block
);
1761 qir_set_emit_block(c
, else_block
);
1762 ntq_activate_execute_for_block(c
);
1763 ntq_emit_cf_list(c
, &if_stmt
->else_list
);
1766 qir_link_blocks(c
->cur_block
, after_block
);
1768 qir_set_emit_block(c
, after_block
);
1770 c
->execute
= c
->undef
;
1772 ntq_activate_execute_for_block(c
);
1777 ntq_emit_jump(struct vc4_compile
*c
, nir_jump_instr
*jump
)
1779 switch (jump
->type
) {
1780 case nir_jump_break
:
1781 qir_SF(c
, c
->execute
);
1782 qir_MOV_cond(c
, QPU_COND_ZS
, c
->execute
,
1783 qir_uniform_ui(c
, c
->loop_break_block
->index
));
1786 case nir_jump_continue
:
1787 qir_SF(c
, c
->execute
);
1788 qir_MOV_cond(c
, QPU_COND_ZS
, c
->execute
,
1789 qir_uniform_ui(c
, c
->loop_cont_block
->index
));
1792 case nir_jump_return
:
1793 unreachable("All returns shouold be lowered\n");
1798 ntq_emit_instr(struct vc4_compile
*c
, nir_instr
*instr
)
1800 switch (instr
->type
) {
1801 case nir_instr_type_alu
:
1802 ntq_emit_alu(c
, nir_instr_as_alu(instr
));
1805 case nir_instr_type_intrinsic
:
1806 ntq_emit_intrinsic(c
, nir_instr_as_intrinsic(instr
));
1809 case nir_instr_type_load_const
:
1810 ntq_emit_load_const(c
, nir_instr_as_load_const(instr
));
1813 case nir_instr_type_ssa_undef
:
1814 ntq_emit_ssa_undef(c
, nir_instr_as_ssa_undef(instr
));
1817 case nir_instr_type_tex
:
1818 ntq_emit_tex(c
, nir_instr_as_tex(instr
));
1821 case nir_instr_type_jump
:
1822 ntq_emit_jump(c
, nir_instr_as_jump(instr
));
1826 fprintf(stderr
, "Unknown NIR instr type: ");
1827 nir_print_instr(instr
, stderr
);
1828 fprintf(stderr
, "\n");
1834 ntq_emit_block(struct vc4_compile
*c
, nir_block
*block
)
1836 nir_foreach_instr(instr
, block
) {
1837 ntq_emit_instr(c
, instr
);
1841 static void ntq_emit_cf_list(struct vc4_compile
*c
, struct exec_list
*list
);
1844 ntq_emit_loop(struct vc4_compile
*c
, nir_loop
*loop
)
1846 if (!c
->vc4
->screen
->has_control_flow
) {
1848 "loop support requires updated kernel.\n");
1849 ntq_emit_cf_list(c
, &loop
->body
);
1853 bool was_top_level
= false;
1854 if (c
->execute
.file
== QFILE_NULL
) {
1855 c
->execute
= qir_MOV(c
, qir_uniform_ui(c
, 0));
1856 was_top_level
= true;
1859 struct qblock
*save_loop_cont_block
= c
->loop_cont_block
;
1860 struct qblock
*save_loop_break_block
= c
->loop_break_block
;
1862 c
->loop_cont_block
= qir_new_block(c
);
1863 c
->loop_break_block
= qir_new_block(c
);
1865 qir_link_blocks(c
->cur_block
, c
->loop_cont_block
);
1866 qir_set_emit_block(c
, c
->loop_cont_block
);
1867 ntq_activate_execute_for_block(c
);
1869 ntq_emit_cf_list(c
, &loop
->body
);
1871 /* If anything had explicitly continued, or is here at the end of the
1872 * loop, then we need to loop again. SF updates are masked by the
1873 * instruction's condition, so we can do the OR of the two conditions
1876 qir_SF(c
, c
->execute
);
1877 struct qinst
*cont_check
=
1881 qir_uniform_ui(c
, c
->loop_cont_block
->index
));
1882 cont_check
->cond
= QPU_COND_ZC
;
1883 cont_check
->sf
= true;
1885 qir_BRANCH(c
, QPU_COND_BRANCH_ANY_ZS
);
1886 qir_link_blocks(c
->cur_block
, c
->loop_cont_block
);
1887 qir_link_blocks(c
->cur_block
, c
->loop_break_block
);
1889 qir_set_emit_block(c
, c
->loop_break_block
);
1891 c
->execute
= c
->undef
;
1893 ntq_activate_execute_for_block(c
);
1895 c
->loop_break_block
= save_loop_break_block
;
1896 c
->loop_cont_block
= save_loop_cont_block
;
1900 ntq_emit_function(struct vc4_compile
*c
, nir_function_impl
*func
)
1902 fprintf(stderr
, "FUNCTIONS not handled.\n");
1907 ntq_emit_cf_list(struct vc4_compile
*c
, struct exec_list
*list
)
1909 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
1910 switch (node
->type
) {
1911 case nir_cf_node_block
:
1912 ntq_emit_block(c
, nir_cf_node_as_block(node
));
1915 case nir_cf_node_if
:
1916 ntq_emit_if(c
, nir_cf_node_as_if(node
));
1919 case nir_cf_node_loop
:
1920 ntq_emit_loop(c
, nir_cf_node_as_loop(node
));
1923 case nir_cf_node_function
:
1924 ntq_emit_function(c
, nir_cf_node_as_function(node
));
1928 fprintf(stderr
, "Unknown NIR node type\n");
1935 ntq_emit_impl(struct vc4_compile
*c
, nir_function_impl
*impl
)
1937 ntq_setup_registers(c
, &impl
->registers
);
1938 ntq_emit_cf_list(c
, &impl
->body
);
1942 nir_to_qir(struct vc4_compile
*c
)
1944 ntq_setup_inputs(c
);
1945 ntq_setup_outputs(c
);
1946 ntq_setup_uniforms(c
);
1947 ntq_setup_registers(c
, &c
->s
->registers
);
1949 /* Find the main function and emit the body. */
1950 nir_foreach_function(function
, c
->s
) {
1951 assert(strcmp(function
->name
, "main") == 0);
1952 assert(function
->impl
);
1953 ntq_emit_impl(c
, function
->impl
);
1957 static const nir_shader_compiler_options nir_options
= {
1958 .lower_extract_byte
= true,
1959 .lower_extract_word
= true,
1961 .lower_flrp32
= true,
1964 .lower_fsqrt
= true,
1965 .lower_negate
= true,
1969 count_nir_instrs(nir_shader
*nir
)
1972 nir_foreach_function(function
, nir
) {
1973 if (!function
->impl
)
1975 nir_foreach_block(block
, function
->impl
) {
1976 nir_foreach_instr(instr
, block
)
1983 static struct vc4_compile
*
1984 vc4_shader_ntq(struct vc4_context
*vc4
, enum qstage stage
,
1985 struct vc4_key
*key
)
1987 struct vc4_compile
*c
= qir_compile_init();
1991 c
->shader_state
= &key
->shader_state
->base
;
1992 c
->program_id
= key
->shader_state
->program_id
;
1994 p_atomic_inc_return(&key
->shader_state
->compiled_variant_count
);
1999 c
->fs_key
= (struct vc4_fs_key
*)key
;
2000 if (c
->fs_key
->is_points
) {
2001 c
->point_x
= emit_fragment_varying(c
, ~0, 0);
2002 c
->point_y
= emit_fragment_varying(c
, ~0, 0);
2003 } else if (c
->fs_key
->is_lines
) {
2004 c
->line_x
= emit_fragment_varying(c
, ~0, 0);
2008 c
->vs_key
= (struct vc4_vs_key
*)key
;
2011 c
->vs_key
= (struct vc4_vs_key
*)key
;
2015 c
->s
= nir_shader_clone(c
, key
->shader_state
->base
.ir
.nir
);
2017 if (stage
== QSTAGE_FRAG
)
2018 NIR_PASS_V(c
->s
, vc4_nir_lower_blend
, c
);
2020 struct nir_lower_tex_options tex_options
= {
2021 /* We would need to implement txs, but we don't want the
2022 * int/float conversions
2024 .lower_rect
= false,
2028 /* Apply swizzles to all samplers. */
2029 .swizzle_result
= ~0,
2032 /* Lower the format swizzle and ARB_texture_swizzle-style swizzle.
2033 * The format swizzling applies before sRGB decode, and
2034 * ARB_texture_swizzle is the last thing before returning the sample.
2036 for (int i
= 0; i
< ARRAY_SIZE(key
->tex
); i
++) {
2037 enum pipe_format format
= c
->key
->tex
[i
].format
;
2042 const uint8_t *format_swizzle
= vc4_get_format_swizzle(format
);
2044 for (int j
= 0; j
< 4; j
++) {
2045 uint8_t arb_swiz
= c
->key
->tex
[i
].swizzle
[j
];
2047 if (arb_swiz
<= 3) {
2048 tex_options
.swizzles
[i
][j
] =
2049 format_swizzle
[arb_swiz
];
2051 tex_options
.swizzles
[i
][j
] = arb_swiz
;
2055 if (util_format_is_srgb(format
))
2056 tex_options
.lower_srgb
|= (1 << i
);
2059 NIR_PASS_V(c
->s
, nir_lower_tex
, &tex_options
);
2061 if (c
->fs_key
&& c
->fs_key
->light_twoside
)
2062 NIR_PASS_V(c
->s
, nir_lower_two_sided_color
);
2064 if (c
->vs_key
&& c
->vs_key
->clamp_color
)
2065 NIR_PASS_V(c
->s
, nir_lower_clamp_color_outputs
);
2067 if (c
->key
->ucp_enables
) {
2068 if (stage
== QSTAGE_FRAG
) {
2069 NIR_PASS_V(c
->s
, nir_lower_clip_fs
, c
->key
->ucp_enables
);
2071 NIR_PASS_V(c
->s
, nir_lower_clip_vs
, c
->key
->ucp_enables
);
2072 NIR_PASS_V(c
->s
, nir_lower_io_to_scalar
,
2073 nir_var_shader_out
);
2077 /* FS input scalarizing must happen after nir_lower_two_sided_color,
2078 * which only handles a vec4 at a time. Similarly, VS output
2079 * scalarizing must happen after nir_lower_clip_vs.
2081 if (c
->stage
== QSTAGE_FRAG
)
2082 NIR_PASS_V(c
->s
, nir_lower_io_to_scalar
, nir_var_shader_in
);
2084 NIR_PASS_V(c
->s
, nir_lower_io_to_scalar
, nir_var_shader_out
);
2086 NIR_PASS_V(c
->s
, vc4_nir_lower_io
, c
);
2087 NIR_PASS_V(c
->s
, vc4_nir_lower_txf_ms
, c
);
2088 NIR_PASS_V(c
->s
, nir_lower_idiv
);
2090 vc4_optimize_nir(c
->s
);
2092 NIR_PASS_V(c
->s
, nir_convert_from_ssa
, true);
2094 if (vc4_debug
& VC4_DEBUG_SHADERDB
) {
2095 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %d NIR instructions\n",
2096 qir_get_stage_name(c
->stage
),
2097 c
->program_id
, c
->variant_id
,
2098 count_nir_instrs(c
->s
));
2101 if (vc4_debug
& VC4_DEBUG_NIR
) {
2102 fprintf(stderr
, "%s prog %d/%d NIR:\n",
2103 qir_get_stage_name(c
->stage
),
2104 c
->program_id
, c
->variant_id
);
2105 nir_print_shader(c
->s
, stderr
);
2116 c
->vs_key
->fs_inputs
->input_slots
,
2117 c
->vs_key
->fs_inputs
->num_inputs
);
2124 if (vc4_debug
& VC4_DEBUG_QIR
) {
2125 fprintf(stderr
, "%s prog %d/%d pre-opt QIR:\n",
2126 qir_get_stage_name(c
->stage
),
2127 c
->program_id
, c
->variant_id
);
2129 fprintf(stderr
, "\n");
2133 qir_lower_uniforms(c
);
2135 qir_schedule_instructions(c
);
2136 qir_emit_uniform_stream_resets(c
);
2138 if (vc4_debug
& VC4_DEBUG_QIR
) {
2139 fprintf(stderr
, "%s prog %d/%d QIR:\n",
2140 qir_get_stage_name(c
->stage
),
2141 c
->program_id
, c
->variant_id
);
2143 fprintf(stderr
, "\n");
2146 qir_reorder_uniforms(c
);
2147 vc4_generate_code(vc4
, c
);
2149 if (vc4_debug
& VC4_DEBUG_SHADERDB
) {
2150 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %d instructions\n",
2151 qir_get_stage_name(c
->stage
),
2152 c
->program_id
, c
->variant_id
,
2154 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %d uniforms\n",
2155 qir_get_stage_name(c
->stage
),
2156 c
->program_id
, c
->variant_id
,
2166 vc4_shader_state_create(struct pipe_context
*pctx
,
2167 const struct pipe_shader_state
*cso
)
2169 struct vc4_context
*vc4
= vc4_context(pctx
);
2170 struct vc4_uncompiled_shader
*so
= CALLOC_STRUCT(vc4_uncompiled_shader
);
2174 so
->program_id
= vc4
->next_uncompiled_program_id
++;
2176 if (vc4_debug
& VC4_DEBUG_TGSI
) {
2177 fprintf(stderr
, "prog %d TGSI:\n",
2179 tgsi_dump(cso
->tokens
, 0);
2180 fprintf(stderr
, "\n");
2183 nir_shader
*s
= tgsi_to_nir(cso
->tokens
, &nir_options
);
2185 NIR_PASS_V(s
, nir_opt_global_to_local
);
2186 NIR_PASS_V(s
, nir_convert_to_ssa
);
2187 NIR_PASS_V(s
, nir_normalize_cubemap_coords
);
2189 NIR_PASS_V(s
, nir_lower_load_const_to_scalar
);
2191 vc4_optimize_nir(s
);
2193 NIR_PASS_V(s
, nir_remove_dead_variables
, nir_var_local
);
2195 /* Garbage collect dead instructions */
2198 so
->base
.type
= PIPE_SHADER_IR_NIR
;
2199 so
->base
.ir
.nir
= s
;
2201 if (vc4_debug
& VC4_DEBUG_NIR
) {
2202 fprintf(stderr
, "%s prog %d NIR:\n",
2203 gl_shader_stage_name(s
->stage
),
2205 nir_print_shader(s
, stderr
);
2206 fprintf(stderr
, "\n");
2213 copy_uniform_state_to_shader(struct vc4_compiled_shader
*shader
,
2214 struct vc4_compile
*c
)
2216 int count
= c
->num_uniforms
;
2217 struct vc4_shader_uniform_info
*uinfo
= &shader
->uniforms
;
2219 uinfo
->count
= count
;
2220 uinfo
->data
= ralloc_array(shader
, uint32_t, count
);
2221 memcpy(uinfo
->data
, c
->uniform_data
,
2222 count
* sizeof(*uinfo
->data
));
2223 uinfo
->contents
= ralloc_array(shader
, enum quniform_contents
, count
);
2224 memcpy(uinfo
->contents
, c
->uniform_contents
,
2225 count
* sizeof(*uinfo
->contents
));
2226 uinfo
->num_texture_samples
= c
->num_texture_samples
;
2228 vc4_set_shader_uniform_dirty_flags(shader
);
2232 vc4_setup_compiled_fs_inputs(struct vc4_context
*vc4
, struct vc4_compile
*c
,
2233 struct vc4_compiled_shader
*shader
)
2235 struct vc4_fs_inputs inputs
;
2237 memset(&inputs
, 0, sizeof(inputs
));
2238 inputs
.input_slots
= ralloc_array(shader
,
2239 struct vc4_varying_slot
,
2240 c
->num_input_slots
);
2242 bool input_live
[c
->num_input_slots
];
2244 memset(input_live
, 0, sizeof(input_live
));
2245 qir_for_each_inst_inorder(inst
, c
) {
2246 for (int i
= 0; i
< qir_get_op_nsrc(inst
->op
); i
++) {
2247 if (inst
->src
[i
].file
== QFILE_VARY
)
2248 input_live
[inst
->src
[i
].index
] = true;
2252 for (int i
= 0; i
< c
->num_input_slots
; i
++) {
2253 struct vc4_varying_slot
*slot
= &c
->input_slots
[i
];
2258 /* Skip non-VS-output inputs. */
2259 if (slot
->slot
== (uint8_t)~0)
2262 if (slot
->slot
== VARYING_SLOT_COL0
||
2263 slot
->slot
== VARYING_SLOT_COL1
||
2264 slot
->slot
== VARYING_SLOT_BFC0
||
2265 slot
->slot
== VARYING_SLOT_BFC1
) {
2266 shader
->color_inputs
|= (1 << inputs
.num_inputs
);
2269 inputs
.input_slots
[inputs
.num_inputs
] = *slot
;
2270 inputs
.num_inputs
++;
2272 shader
->num_inputs
= inputs
.num_inputs
;
2274 /* Add our set of inputs to the set of all inputs seen. This way, we
2275 * can have a single pointer that identifies an FS inputs set,
2276 * allowing VS to avoid recompiling when the FS is recompiled (or a
2277 * new one is bound using separate shader objects) but the inputs
2280 struct set_entry
*entry
= _mesa_set_search(vc4
->fs_inputs_set
, &inputs
);
2282 shader
->fs_inputs
= entry
->key
;
2283 ralloc_free(inputs
.input_slots
);
2285 struct vc4_fs_inputs
*alloc_inputs
;
2287 alloc_inputs
= rzalloc(vc4
->fs_inputs_set
, struct vc4_fs_inputs
);
2288 memcpy(alloc_inputs
, &inputs
, sizeof(inputs
));
2289 ralloc_steal(alloc_inputs
, inputs
.input_slots
);
2290 _mesa_set_add(vc4
->fs_inputs_set
, alloc_inputs
);
2292 shader
->fs_inputs
= alloc_inputs
;
2296 static struct vc4_compiled_shader
*
2297 vc4_get_compiled_shader(struct vc4_context
*vc4
, enum qstage stage
,
2298 struct vc4_key
*key
)
2300 struct hash_table
*ht
;
2302 if (stage
== QSTAGE_FRAG
) {
2304 key_size
= sizeof(struct vc4_fs_key
);
2307 key_size
= sizeof(struct vc4_vs_key
);
2310 struct vc4_compiled_shader
*shader
;
2311 struct hash_entry
*entry
= _mesa_hash_table_search(ht
, key
);
2315 struct vc4_compile
*c
= vc4_shader_ntq(vc4
, stage
, key
);
2316 shader
= rzalloc(NULL
, struct vc4_compiled_shader
);
2318 shader
->program_id
= vc4
->next_compiled_program_id
++;
2319 if (stage
== QSTAGE_FRAG
) {
2320 vc4_setup_compiled_fs_inputs(vc4
, c
, shader
);
2322 /* Note: the temporary clone in c->s has been freed. */
2323 nir_shader
*orig_shader
= key
->shader_state
->base
.ir
.nir
;
2324 if (orig_shader
->info
.outputs_written
& (1 << FRAG_RESULT_DEPTH
))
2325 shader
->disable_early_z
= true;
2327 shader
->num_inputs
= c
->num_inputs
;
2329 shader
->vattr_offsets
[0] = 0;
2330 for (int i
= 0; i
< 8; i
++) {
2331 shader
->vattr_offsets
[i
+ 1] =
2332 shader
->vattr_offsets
[i
] + c
->vattr_sizes
[i
];
2334 if (c
->vattr_sizes
[i
])
2335 shader
->vattrs_live
|= (1 << i
);
2339 copy_uniform_state_to_shader(shader
, c
);
2340 shader
->bo
= vc4_bo_alloc_shader(vc4
->screen
, c
->qpu_insts
,
2341 c
->qpu_inst_count
* sizeof(uint64_t));
2343 /* Copy the compiler UBO range state to the compiled shader, dropping
2344 * out arrays that were never referenced by an indirect load.
2346 * (Note that QIR dead code elimination of an array access still
2347 * leaves that array alive, though)
2349 if (c
->num_ubo_ranges
) {
2350 shader
->num_ubo_ranges
= c
->num_ubo_ranges
;
2351 shader
->ubo_ranges
= ralloc_array(shader
, struct vc4_ubo_range
,
2354 for (int i
= 0; i
< c
->num_uniform_ranges
; i
++) {
2355 struct vc4_compiler_ubo_range
*range
=
2360 shader
->ubo_ranges
[j
].dst_offset
= range
->dst_offset
;
2361 shader
->ubo_ranges
[j
].src_offset
= range
->src_offset
;
2362 shader
->ubo_ranges
[j
].size
= range
->size
;
2363 shader
->ubo_size
+= c
->ubo_ranges
[i
].size
;
2367 if (shader
->ubo_size
) {
2368 if (vc4_debug
& VC4_DEBUG_SHADERDB
) {
2369 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %d UBO uniforms\n",
2370 qir_get_stage_name(c
->stage
),
2371 c
->program_id
, c
->variant_id
,
2372 shader
->ubo_size
/ 4);
2376 qir_compile_destroy(c
);
2378 struct vc4_key
*dup_key
;
2379 dup_key
= ralloc_size(shader
, key_size
);
2380 memcpy(dup_key
, key
, key_size
);
2381 _mesa_hash_table_insert(ht
, dup_key
, shader
);
2387 vc4_setup_shared_key(struct vc4_context
*vc4
, struct vc4_key
*key
,
2388 struct vc4_texture_stateobj
*texstate
)
2390 for (int i
= 0; i
< texstate
->num_textures
; i
++) {
2391 struct pipe_sampler_view
*sampler
= texstate
->textures
[i
];
2392 struct vc4_sampler_view
*vc4_sampler
= vc4_sampler_view(sampler
);
2393 struct pipe_sampler_state
*sampler_state
=
2394 texstate
->samplers
[i
];
2399 key
->tex
[i
].format
= sampler
->format
;
2400 key
->tex
[i
].swizzle
[0] = sampler
->swizzle_r
;
2401 key
->tex
[i
].swizzle
[1] = sampler
->swizzle_g
;
2402 key
->tex
[i
].swizzle
[2] = sampler
->swizzle_b
;
2403 key
->tex
[i
].swizzle
[3] = sampler
->swizzle_a
;
2405 if (sampler
->texture
->nr_samples
> 1) {
2406 key
->tex
[i
].msaa_width
= sampler
->texture
->width0
;
2407 key
->tex
[i
].msaa_height
= sampler
->texture
->height0
;
2408 } else if (sampler
){
2409 key
->tex
[i
].compare_mode
= sampler_state
->compare_mode
;
2410 key
->tex
[i
].compare_func
= sampler_state
->compare_func
;
2411 key
->tex
[i
].wrap_s
= sampler_state
->wrap_s
;
2412 key
->tex
[i
].wrap_t
= sampler_state
->wrap_t
;
2413 key
->tex
[i
].force_first_level
=
2414 vc4_sampler
->force_first_level
;
2418 key
->ucp_enables
= vc4
->rasterizer
->base
.clip_plane_enable
;
2422 vc4_update_compiled_fs(struct vc4_context
*vc4
, uint8_t prim_mode
)
2424 struct vc4_fs_key local_key
;
2425 struct vc4_fs_key
*key
= &local_key
;
2427 if (!(vc4
->dirty
& (VC4_DIRTY_PRIM_MODE
|
2429 VC4_DIRTY_FRAMEBUFFER
|
2431 VC4_DIRTY_RASTERIZER
|
2432 VC4_DIRTY_SAMPLE_MASK
|
2434 VC4_DIRTY_UNCOMPILED_FS
))) {
2438 memset(key
, 0, sizeof(*key
));
2439 vc4_setup_shared_key(vc4
, &key
->base
, &vc4
->fragtex
);
2440 key
->base
.shader_state
= vc4
->prog
.bind_fs
;
2441 key
->is_points
= (prim_mode
== PIPE_PRIM_POINTS
);
2442 key
->is_lines
= (prim_mode
>= PIPE_PRIM_LINES
&&
2443 prim_mode
<= PIPE_PRIM_LINE_STRIP
);
2444 key
->blend
= vc4
->blend
->rt
[0];
2445 if (vc4
->blend
->logicop_enable
) {
2446 key
->logicop_func
= vc4
->blend
->logicop_func
;
2448 key
->logicop_func
= PIPE_LOGICOP_COPY
;
2451 key
->msaa
= vc4
->rasterizer
->base
.multisample
;
2452 key
->sample_coverage
= (vc4
->rasterizer
->base
.multisample
&&
2453 vc4
->sample_mask
!= (1 << VC4_MAX_SAMPLES
) - 1);
2454 key
->sample_alpha_to_coverage
= vc4
->blend
->alpha_to_coverage
;
2455 key
->sample_alpha_to_one
= vc4
->blend
->alpha_to_one
;
2458 if (vc4
->framebuffer
.cbufs
[0])
2459 key
->color_format
= vc4
->framebuffer
.cbufs
[0]->format
;
2461 key
->stencil_enabled
= vc4
->zsa
->stencil_uniforms
[0] != 0;
2462 key
->stencil_twoside
= vc4
->zsa
->stencil_uniforms
[1] != 0;
2463 key
->stencil_full_writemasks
= vc4
->zsa
->stencil_uniforms
[2] != 0;
2464 key
->depth_enabled
= (vc4
->zsa
->base
.depth
.enabled
||
2465 key
->stencil_enabled
);
2466 if (vc4
->zsa
->base
.alpha
.enabled
) {
2467 key
->alpha_test
= true;
2468 key
->alpha_test_func
= vc4
->zsa
->base
.alpha
.func
;
2471 if (key
->is_points
) {
2472 key
->point_sprite_mask
=
2473 vc4
->rasterizer
->base
.sprite_coord_enable
;
2474 key
->point_coord_upper_left
=
2475 (vc4
->rasterizer
->base
.sprite_coord_mode
==
2476 PIPE_SPRITE_COORD_UPPER_LEFT
);
2479 key
->light_twoside
= vc4
->rasterizer
->base
.light_twoside
;
2481 struct vc4_compiled_shader
*old_fs
= vc4
->prog
.fs
;
2482 vc4
->prog
.fs
= vc4_get_compiled_shader(vc4
, QSTAGE_FRAG
, &key
->base
);
2483 if (vc4
->prog
.fs
== old_fs
)
2486 vc4
->dirty
|= VC4_DIRTY_COMPILED_FS
;
2488 if (vc4
->rasterizer
->base
.flatshade
&&
2489 old_fs
&& vc4
->prog
.fs
->color_inputs
!= old_fs
->color_inputs
) {
2490 vc4
->dirty
|= VC4_DIRTY_FLAT_SHADE_FLAGS
;
2493 if (old_fs
&& vc4
->prog
.fs
->fs_inputs
!= old_fs
->fs_inputs
)
2494 vc4
->dirty
|= VC4_DIRTY_FS_INPUTS
;
2498 vc4_update_compiled_vs(struct vc4_context
*vc4
, uint8_t prim_mode
)
2500 struct vc4_vs_key local_key
;
2501 struct vc4_vs_key
*key
= &local_key
;
2503 if (!(vc4
->dirty
& (VC4_DIRTY_PRIM_MODE
|
2504 VC4_DIRTY_RASTERIZER
|
2506 VC4_DIRTY_VTXSTATE
|
2507 VC4_DIRTY_UNCOMPILED_VS
|
2508 VC4_DIRTY_FS_INPUTS
))) {
2512 memset(key
, 0, sizeof(*key
));
2513 vc4_setup_shared_key(vc4
, &key
->base
, &vc4
->verttex
);
2514 key
->base
.shader_state
= vc4
->prog
.bind_vs
;
2515 key
->fs_inputs
= vc4
->prog
.fs
->fs_inputs
;
2516 key
->clamp_color
= vc4
->rasterizer
->base
.clamp_vertex_color
;
2518 for (int i
= 0; i
< ARRAY_SIZE(key
->attr_formats
); i
++)
2519 key
->attr_formats
[i
] = vc4
->vtx
->pipe
[i
].src_format
;
2521 key
->per_vertex_point_size
=
2522 (prim_mode
== PIPE_PRIM_POINTS
&&
2523 vc4
->rasterizer
->base
.point_size_per_vertex
);
2525 struct vc4_compiled_shader
*vs
=
2526 vc4_get_compiled_shader(vc4
, QSTAGE_VERT
, &key
->base
);
2527 if (vs
!= vc4
->prog
.vs
) {
2529 vc4
->dirty
|= VC4_DIRTY_COMPILED_VS
;
2532 key
->is_coord
= true;
2533 /* Coord shaders don't care what the FS inputs are. */
2534 key
->fs_inputs
= NULL
;
2535 struct vc4_compiled_shader
*cs
=
2536 vc4_get_compiled_shader(vc4
, QSTAGE_COORD
, &key
->base
);
2537 if (cs
!= vc4
->prog
.cs
) {
2539 vc4
->dirty
|= VC4_DIRTY_COMPILED_CS
;
2544 vc4_update_compiled_shaders(struct vc4_context
*vc4
, uint8_t prim_mode
)
2546 vc4_update_compiled_fs(vc4
, prim_mode
);
2547 vc4_update_compiled_vs(vc4
, prim_mode
);
2551 fs_cache_hash(const void *key
)
2553 return _mesa_hash_data(key
, sizeof(struct vc4_fs_key
));
2557 vs_cache_hash(const void *key
)
2559 return _mesa_hash_data(key
, sizeof(struct vc4_vs_key
));
2563 fs_cache_compare(const void *key1
, const void *key2
)
2565 return memcmp(key1
, key2
, sizeof(struct vc4_fs_key
)) == 0;
2569 vs_cache_compare(const void *key1
, const void *key2
)
2571 return memcmp(key1
, key2
, sizeof(struct vc4_vs_key
)) == 0;
2575 fs_inputs_hash(const void *key
)
2577 const struct vc4_fs_inputs
*inputs
= key
;
2579 return _mesa_hash_data(inputs
->input_slots
,
2580 sizeof(*inputs
->input_slots
) *
2581 inputs
->num_inputs
);
2585 fs_inputs_compare(const void *key1
, const void *key2
)
2587 const struct vc4_fs_inputs
*inputs1
= key1
;
2588 const struct vc4_fs_inputs
*inputs2
= key2
;
2590 return (inputs1
->num_inputs
== inputs2
->num_inputs
&&
2591 memcmp(inputs1
->input_slots
,
2592 inputs2
->input_slots
,
2593 sizeof(*inputs1
->input_slots
) *
2594 inputs1
->num_inputs
) == 0);
2598 delete_from_cache_if_matches(struct hash_table
*ht
,
2599 struct hash_entry
*entry
,
2600 struct vc4_uncompiled_shader
*so
)
2602 const struct vc4_key
*key
= entry
->key
;
2604 if (key
->shader_state
== so
) {
2605 struct vc4_compiled_shader
*shader
= entry
->data
;
2606 _mesa_hash_table_remove(ht
, entry
);
2607 vc4_bo_unreference(&shader
->bo
);
2608 ralloc_free(shader
);
2613 vc4_shader_state_delete(struct pipe_context
*pctx
, void *hwcso
)
2615 struct vc4_context
*vc4
= vc4_context(pctx
);
2616 struct vc4_uncompiled_shader
*so
= hwcso
;
2618 struct hash_entry
*entry
;
2619 hash_table_foreach(vc4
->fs_cache
, entry
)
2620 delete_from_cache_if_matches(vc4
->fs_cache
, entry
, so
);
2621 hash_table_foreach(vc4
->vs_cache
, entry
)
2622 delete_from_cache_if_matches(vc4
->vs_cache
, entry
, so
);
2624 ralloc_free(so
->base
.ir
.nir
);
2629 vc4_fp_state_bind(struct pipe_context
*pctx
, void *hwcso
)
2631 struct vc4_context
*vc4
= vc4_context(pctx
);
2632 vc4
->prog
.bind_fs
= hwcso
;
2633 vc4
->dirty
|= VC4_DIRTY_UNCOMPILED_FS
;
2637 vc4_vp_state_bind(struct pipe_context
*pctx
, void *hwcso
)
2639 struct vc4_context
*vc4
= vc4_context(pctx
);
2640 vc4
->prog
.bind_vs
= hwcso
;
2641 vc4
->dirty
|= VC4_DIRTY_UNCOMPILED_VS
;
2645 vc4_program_init(struct pipe_context
*pctx
)
2647 struct vc4_context
*vc4
= vc4_context(pctx
);
2649 pctx
->create_vs_state
= vc4_shader_state_create
;
2650 pctx
->delete_vs_state
= vc4_shader_state_delete
;
2652 pctx
->create_fs_state
= vc4_shader_state_create
;
2653 pctx
->delete_fs_state
= vc4_shader_state_delete
;
2655 pctx
->bind_fs_state
= vc4_fp_state_bind
;
2656 pctx
->bind_vs_state
= vc4_vp_state_bind
;
2658 vc4
->fs_cache
= _mesa_hash_table_create(pctx
, fs_cache_hash
,
2660 vc4
->vs_cache
= _mesa_hash_table_create(pctx
, vs_cache_hash
,
2662 vc4
->fs_inputs_set
= _mesa_set_create(pctx
, fs_inputs_hash
,
2667 vc4_program_fini(struct pipe_context
*pctx
)
2669 struct vc4_context
*vc4
= vc4_context(pctx
);
2671 struct hash_entry
*entry
;
2672 hash_table_foreach(vc4
->fs_cache
, entry
) {
2673 struct vc4_compiled_shader
*shader
= entry
->data
;
2674 vc4_bo_unreference(&shader
->bo
);
2675 ralloc_free(shader
);
2676 _mesa_hash_table_remove(vc4
->fs_cache
, entry
);
2679 hash_table_foreach(vc4
->vs_cache
, entry
) {
2680 struct vc4_compiled_shader
*shader
= entry
->data
;
2681 vc4_bo_unreference(&shader
->bo
);
2682 ralloc_free(shader
);
2683 _mesa_hash_table_remove(vc4
->vs_cache
, entry
);