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vc4: Improve the accuracy of SIN and COS.
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "pipe/p_state.h"
27 #include "util/u_format.h"
28 #include "util/u_hash_table.h"
29 #include "util/u_hash.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include "util/format_srgb.h"
33 #include "util/ralloc.h"
34 #include "util/hash_table.h"
35 #include "tgsi/tgsi_dump.h"
36 #include "tgsi/tgsi_info.h"
37 #include "tgsi/tgsi_lowering.h"
38
39 #include "vc4_context.h"
40 #include "vc4_qpu.h"
41 #include "vc4_qir.h"
42 #ifdef USE_VC4_SIMULATOR
43 #include "simpenrose/simpenrose.h"
44 #endif
45
46 struct vc4_key {
47 struct vc4_uncompiled_shader *shader_state;
48 struct {
49 enum pipe_format format;
50 unsigned compare_mode:1;
51 unsigned compare_func:3;
52 unsigned wrap_s:3;
53 unsigned wrap_t:3;
54 uint8_t swizzle[4];
55 } tex[VC4_MAX_TEXTURE_SAMPLERS];
56 };
57
58 struct vc4_fs_key {
59 struct vc4_key base;
60 enum pipe_format color_format;
61 bool depth_enabled;
62 bool stencil_enabled;
63 bool stencil_twoside;
64 bool stencil_full_writemasks;
65 bool is_points;
66 bool is_lines;
67 bool alpha_test;
68 bool point_coord_upper_left;
69 bool light_twoside;
70 uint8_t alpha_test_func;
71 uint32_t point_sprite_mask;
72
73 struct pipe_rt_blend_state blend;
74 };
75
76 struct vc4_vs_key {
77 struct vc4_key base;
78
79 /**
80 * This is a proxy for the array of FS input semantics, which is
81 * larger than we would want to put in the key.
82 */
83 uint64_t compiled_fs_id;
84
85 enum pipe_format attr_formats[8];
86 bool is_coord;
87 bool per_vertex_point_size;
88 };
89
90 static void
91 resize_qreg_array(struct vc4_compile *c,
92 struct qreg **regs,
93 uint32_t *size,
94 uint32_t decl_size)
95 {
96 if (*size >= decl_size)
97 return;
98
99 uint32_t old_size = *size;
100 *size = MAX2(*size * 2, decl_size);
101 *regs = reralloc(c, *regs, struct qreg, *size);
102 if (!*regs) {
103 fprintf(stderr, "Malloc failure\n");
104 abort();
105 }
106
107 for (uint32_t i = old_size; i < *size; i++)
108 (*regs)[i] = c->undef;
109 }
110
111 static struct qreg
112 add_uniform(struct vc4_compile *c,
113 enum quniform_contents contents,
114 uint32_t data)
115 {
116 uint32_t uniform = c->num_uniforms++;
117 struct qreg u = { QFILE_UNIF, uniform };
118
119 if (uniform >= c->uniform_array_size) {
120 c->uniform_array_size = MAX2(MAX2(16, uniform + 1),
121 c->uniform_array_size * 2);
122
123 c->uniform_data = reralloc(c, c->uniform_data,
124 uint32_t,
125 c->uniform_array_size);
126 c->uniform_contents = reralloc(c, c->uniform_contents,
127 enum quniform_contents,
128 c->uniform_array_size);
129 }
130
131 c->uniform_contents[uniform] = contents;
132 c->uniform_data[uniform] = data;
133
134 return u;
135 }
136
137 static struct qreg
138 get_temp_for_uniform(struct vc4_compile *c, enum quniform_contents contents,
139 uint32_t data)
140 {
141 struct qreg u = add_uniform(c, contents, data);
142 struct qreg t = qir_MOV(c, u);
143 return t;
144 }
145
146 static struct qreg
147 qir_uniform_ui(struct vc4_compile *c, uint32_t ui)
148 {
149 return get_temp_for_uniform(c, QUNIFORM_CONSTANT, ui);
150 }
151
152 static struct qreg
153 qir_uniform_f(struct vc4_compile *c, float f)
154 {
155 return qir_uniform_ui(c, fui(f));
156 }
157
158 static struct qreg
159 get_src(struct vc4_compile *c, unsigned tgsi_op,
160 struct tgsi_src_register *src, int i)
161 {
162 struct qreg r = c->undef;
163
164 uint32_t s = i;
165 switch (i) {
166 case TGSI_SWIZZLE_X:
167 s = src->SwizzleX;
168 break;
169 case TGSI_SWIZZLE_Y:
170 s = src->SwizzleY;
171 break;
172 case TGSI_SWIZZLE_Z:
173 s = src->SwizzleZ;
174 break;
175 case TGSI_SWIZZLE_W:
176 s = src->SwizzleW;
177 break;
178 default:
179 abort();
180 }
181
182 assert(!src->Indirect);
183
184 switch (src->File) {
185 case TGSI_FILE_NULL:
186 return r;
187 case TGSI_FILE_TEMPORARY:
188 r = c->temps[src->Index * 4 + s];
189 break;
190 case TGSI_FILE_IMMEDIATE:
191 r = c->consts[src->Index * 4 + s];
192 break;
193 case TGSI_FILE_CONSTANT:
194 r = get_temp_for_uniform(c, QUNIFORM_UNIFORM,
195 src->Index * 4 + s);
196 break;
197 case TGSI_FILE_INPUT:
198 r = c->inputs[src->Index * 4 + s];
199 break;
200 case TGSI_FILE_SAMPLER:
201 case TGSI_FILE_SAMPLER_VIEW:
202 r = c->undef;
203 break;
204 default:
205 fprintf(stderr, "unknown src file %d\n", src->File);
206 abort();
207 }
208
209 if (src->Absolute)
210 r = qir_FMAXABS(c, r, r);
211
212 if (src->Negate) {
213 switch (tgsi_opcode_infer_src_type(tgsi_op)) {
214 case TGSI_TYPE_SIGNED:
215 case TGSI_TYPE_UNSIGNED:
216 r = qir_SUB(c, qir_uniform_ui(c, 0), r);
217 break;
218 default:
219 r = qir_FSUB(c, qir_uniform_f(c, 0.0), r);
220 break;
221 }
222 }
223
224 return r;
225 };
226
227
228 static void
229 update_dst(struct vc4_compile *c, struct tgsi_full_instruction *tgsi_inst,
230 int i, struct qreg val)
231 {
232 struct tgsi_dst_register *tgsi_dst = &tgsi_inst->Dst[0].Register;
233
234 assert(!tgsi_dst->Indirect);
235
236 switch (tgsi_dst->File) {
237 case TGSI_FILE_TEMPORARY:
238 c->temps[tgsi_dst->Index * 4 + i] = val;
239 break;
240 case TGSI_FILE_OUTPUT:
241 c->outputs[tgsi_dst->Index * 4 + i] = val;
242 c->num_outputs = MAX2(c->num_outputs,
243 tgsi_dst->Index * 4 + i + 1);
244 break;
245 default:
246 fprintf(stderr, "unknown dst file %d\n", tgsi_dst->File);
247 abort();
248 }
249 };
250
251 static struct qreg
252 get_swizzled_channel(struct vc4_compile *c,
253 struct qreg *srcs, int swiz)
254 {
255 switch (swiz) {
256 default:
257 case UTIL_FORMAT_SWIZZLE_NONE:
258 fprintf(stderr, "warning: unknown swizzle\n");
259 /* FALLTHROUGH */
260 case UTIL_FORMAT_SWIZZLE_0:
261 return qir_uniform_f(c, 0.0);
262 case UTIL_FORMAT_SWIZZLE_1:
263 return qir_uniform_f(c, 1.0);
264 case UTIL_FORMAT_SWIZZLE_X:
265 case UTIL_FORMAT_SWIZZLE_Y:
266 case UTIL_FORMAT_SWIZZLE_Z:
267 case UTIL_FORMAT_SWIZZLE_W:
268 return srcs[swiz];
269 }
270 }
271
272 static struct qreg
273 tgsi_to_qir_alu(struct vc4_compile *c,
274 struct tgsi_full_instruction *tgsi_inst,
275 enum qop op, struct qreg *src, int i)
276 {
277 struct qreg dst = qir_get_temp(c);
278 qir_emit(c, qir_inst4(op, dst,
279 src[0 * 4 + i],
280 src[1 * 4 + i],
281 src[2 * 4 + i],
282 c->undef));
283 return dst;
284 }
285
286 static struct qreg
287 tgsi_to_qir_scalar(struct vc4_compile *c,
288 struct tgsi_full_instruction *tgsi_inst,
289 enum qop op, struct qreg *src, int i)
290 {
291 struct qreg dst = qir_get_temp(c);
292 qir_emit(c, qir_inst(op, dst,
293 src[0 * 4 + 0],
294 c->undef));
295 return dst;
296 }
297
298 static struct qreg
299 qir_srgb_decode(struct vc4_compile *c, struct qreg srgb)
300 {
301 struct qreg low = qir_FMUL(c, srgb, qir_uniform_f(c, 1.0 / 12.92));
302 struct qreg high = qir_POW(c,
303 qir_FMUL(c,
304 qir_FADD(c,
305 srgb,
306 qir_uniform_f(c, 0.055)),
307 qir_uniform_f(c, 1.0 / 1.055)),
308 qir_uniform_f(c, 2.4));
309
310 qir_SF(c, qir_FSUB(c, srgb, qir_uniform_f(c, 0.04045)));
311 return qir_SEL_X_Y_NS(c, low, high);
312 }
313
314 static struct qreg
315 qir_srgb_encode(struct vc4_compile *c, struct qreg linear)
316 {
317 struct qreg low = qir_FMUL(c, linear, qir_uniform_f(c, 12.92));
318 struct qreg high = qir_FSUB(c,
319 qir_FMUL(c,
320 qir_uniform_f(c, 1.055),
321 qir_POW(c,
322 linear,
323 qir_uniform_f(c, 0.41666))),
324 qir_uniform_f(c, 0.055));
325
326 qir_SF(c, qir_FSUB(c, linear, qir_uniform_f(c, 0.0031308)));
327 return qir_SEL_X_Y_NS(c, low, high);
328 }
329
330 static struct qreg
331 tgsi_to_qir_umul(struct vc4_compile *c,
332 struct tgsi_full_instruction *tgsi_inst,
333 enum qop op, struct qreg *src, int i)
334 {
335 struct qreg src0_hi = qir_SHR(c, src[0 * 4 + i],
336 qir_uniform_ui(c, 16));
337 struct qreg src0_lo = qir_AND(c, src[0 * 4 + i],
338 qir_uniform_ui(c, 0xffff));
339 struct qreg src1_hi = qir_SHR(c, src[1 * 4 + i],
340 qir_uniform_ui(c, 16));
341 struct qreg src1_lo = qir_AND(c, src[1 * 4 + i],
342 qir_uniform_ui(c, 0xffff));
343
344 struct qreg hilo = qir_MUL24(c, src0_hi, src1_lo);
345 struct qreg lohi = qir_MUL24(c, src0_lo, src1_hi);
346 struct qreg lolo = qir_MUL24(c, src0_lo, src1_lo);
347
348 return qir_ADD(c, lolo, qir_SHL(c,
349 qir_ADD(c, hilo, lohi),
350 qir_uniform_ui(c, 16)));
351 }
352
353 static struct qreg
354 tgsi_to_qir_idiv(struct vc4_compile *c,
355 struct tgsi_full_instruction *tgsi_inst,
356 enum qop op, struct qreg *src, int i)
357 {
358 return qir_FTOI(c, qir_FMUL(c,
359 qir_ITOF(c, src[0 * 4 + i]),
360 qir_RCP(c, qir_ITOF(c, src[1 * 4 + i]))));
361 }
362
363 static struct qreg
364 tgsi_to_qir_ineg(struct vc4_compile *c,
365 struct tgsi_full_instruction *tgsi_inst,
366 enum qop op, struct qreg *src, int i)
367 {
368 return qir_SUB(c, qir_uniform_ui(c, 0), src[0 * 4 + i]);
369 }
370
371 static struct qreg
372 tgsi_to_qir_seq(struct vc4_compile *c,
373 struct tgsi_full_instruction *tgsi_inst,
374 enum qop op, struct qreg *src, int i)
375 {
376 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
377 return qir_SEL_X_0_ZS(c, qir_uniform_f(c, 1.0));
378 }
379
380 static struct qreg
381 tgsi_to_qir_sne(struct vc4_compile *c,
382 struct tgsi_full_instruction *tgsi_inst,
383 enum qop op, struct qreg *src, int i)
384 {
385 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
386 return qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0));
387 }
388
389 static struct qreg
390 tgsi_to_qir_slt(struct vc4_compile *c,
391 struct tgsi_full_instruction *tgsi_inst,
392 enum qop op, struct qreg *src, int i)
393 {
394 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
395 return qir_SEL_X_0_NS(c, qir_uniform_f(c, 1.0));
396 }
397
398 static struct qreg
399 tgsi_to_qir_sge(struct vc4_compile *c,
400 struct tgsi_full_instruction *tgsi_inst,
401 enum qop op, struct qreg *src, int i)
402 {
403 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
404 return qir_SEL_X_0_NC(c, qir_uniform_f(c, 1.0));
405 }
406
407 static struct qreg
408 tgsi_to_qir_fseq(struct vc4_compile *c,
409 struct tgsi_full_instruction *tgsi_inst,
410 enum qop op, struct qreg *src, int i)
411 {
412 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
413 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
414 }
415
416 static struct qreg
417 tgsi_to_qir_fsne(struct vc4_compile *c,
418 struct tgsi_full_instruction *tgsi_inst,
419 enum qop op, struct qreg *src, int i)
420 {
421 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
422 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
423 }
424
425 static struct qreg
426 tgsi_to_qir_fslt(struct vc4_compile *c,
427 struct tgsi_full_instruction *tgsi_inst,
428 enum qop op, struct qreg *src, int i)
429 {
430 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
431 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
432 }
433
434 static struct qreg
435 tgsi_to_qir_fsge(struct vc4_compile *c,
436 struct tgsi_full_instruction *tgsi_inst,
437 enum qop op, struct qreg *src, int i)
438 {
439 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
440 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
441 }
442
443 static struct qreg
444 tgsi_to_qir_useq(struct vc4_compile *c,
445 struct tgsi_full_instruction *tgsi_inst,
446 enum qop op, struct qreg *src, int i)
447 {
448 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
449 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
450 }
451
452 static struct qreg
453 tgsi_to_qir_usne(struct vc4_compile *c,
454 struct tgsi_full_instruction *tgsi_inst,
455 enum qop op, struct qreg *src, int i)
456 {
457 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
458 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
459 }
460
461 static struct qreg
462 tgsi_to_qir_islt(struct vc4_compile *c,
463 struct tgsi_full_instruction *tgsi_inst,
464 enum qop op, struct qreg *src, int i)
465 {
466 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
467 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
468 }
469
470 static struct qreg
471 tgsi_to_qir_isge(struct vc4_compile *c,
472 struct tgsi_full_instruction *tgsi_inst,
473 enum qop op, struct qreg *src, int i)
474 {
475 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
476 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
477 }
478
479 static struct qreg
480 tgsi_to_qir_cmp(struct vc4_compile *c,
481 struct tgsi_full_instruction *tgsi_inst,
482 enum qop op, struct qreg *src, int i)
483 {
484 qir_SF(c, src[0 * 4 + i]);
485 return qir_SEL_X_Y_NS(c,
486 src[1 * 4 + i],
487 src[2 * 4 + i]);
488 }
489
490 static struct qreg
491 tgsi_to_qir_mad(struct vc4_compile *c,
492 struct tgsi_full_instruction *tgsi_inst,
493 enum qop op, struct qreg *src, int i)
494 {
495 return qir_FADD(c,
496 qir_FMUL(c,
497 src[0 * 4 + i],
498 src[1 * 4 + i]),
499 src[2 * 4 + i]);
500 }
501
502 static struct qreg
503 tgsi_to_qir_lrp(struct vc4_compile *c,
504 struct tgsi_full_instruction *tgsi_inst,
505 enum qop op, struct qreg *src, int i)
506 {
507 struct qreg src0 = src[0 * 4 + i];
508 struct qreg src1 = src[1 * 4 + i];
509 struct qreg src2 = src[2 * 4 + i];
510
511 /* LRP is:
512 * src0 * src1 + (1 - src0) * src2.
513 * -> src0 * src1 + src2 - src0 * src2
514 * -> src2 + src0 * (src1 - src2)
515 */
516 return qir_FADD(c, src2, qir_FMUL(c, src0, qir_FSUB(c, src1, src2)));
517
518 }
519
520 static void
521 tgsi_to_qir_tex(struct vc4_compile *c,
522 struct tgsi_full_instruction *tgsi_inst,
523 enum qop op, struct qreg *src)
524 {
525 assert(!tgsi_inst->Instruction.Saturate);
526
527 struct qreg s = src[0 * 4 + 0];
528 struct qreg t = src[0 * 4 + 1];
529 struct qreg r = src[0 * 4 + 2];
530 uint32_t unit = tgsi_inst->Src[1].Register.Index;
531
532 struct qreg proj = c->undef;
533 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
534 proj = qir_RCP(c, src[0 * 4 + 3]);
535 s = qir_FMUL(c, s, proj);
536 t = qir_FMUL(c, t, proj);
537 }
538
539 struct qreg texture_u[] = {
540 add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit),
541 add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
542 add_uniform(c, QUNIFORM_CONSTANT, 0),
543 add_uniform(c, QUNIFORM_CONSTANT, 0),
544 };
545 uint32_t next_texture_u = 0;
546
547 /* There is no native support for GL texture rectangle coordinates, so
548 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
549 * 1]).
550 */
551 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_RECT ||
552 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT) {
553 s = qir_FMUL(c, s,
554 get_temp_for_uniform(c,
555 QUNIFORM_TEXRECT_SCALE_X,
556 unit));
557 t = qir_FMUL(c, t,
558 get_temp_for_uniform(c,
559 QUNIFORM_TEXRECT_SCALE_Y,
560 unit));
561 }
562
563 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
564 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE) {
565 struct qreg ma = qir_FMAXABS(c, qir_FMAXABS(c, s, t), r);
566 struct qreg rcp_ma = qir_RCP(c, ma);
567 s = qir_FMUL(c, s, rcp_ma);
568 t = qir_FMUL(c, t, rcp_ma);
569 r = qir_FMUL(c, r, rcp_ma);
570
571 texture_u[2] = add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P2, unit);
572
573 qir_TEX_R(c, r, texture_u[next_texture_u++]);
574 } else if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
575 c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP ||
576 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
577 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
578 qir_TEX_R(c, get_temp_for_uniform(c, QUNIFORM_TEXTURE_BORDER_COLOR, unit),
579 texture_u[next_texture_u++]);
580 }
581
582 if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP) {
583 s = qir_FMIN(c, qir_FMAX(c, s, qir_uniform_f(c, 0.0)),
584 qir_uniform_f(c, 1.0));
585 }
586
587 if (c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
588 t = qir_FMIN(c, qir_FMAX(c, t, qir_uniform_f(c, 0.0)),
589 qir_uniform_f(c, 1.0));
590 }
591
592 qir_TEX_T(c, t, texture_u[next_texture_u++]);
593
594 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB)
595 qir_TEX_B(c, src[0 * 4 + 3], texture_u[next_texture_u++]);
596
597 qir_TEX_S(c, s, texture_u[next_texture_u++]);
598
599 c->num_texture_samples++;
600 struct qreg r4 = qir_TEX_RESULT(c);
601
602 enum pipe_format format = c->key->tex[unit].format;
603
604 struct qreg unpacked[4];
605 if (util_format_is_depth_or_stencil(format)) {
606 struct qreg depthf = qir_ITOF(c, qir_SHR(c, r4,
607 qir_uniform_ui(c, 8)));
608 struct qreg normalized = qir_FMUL(c, depthf,
609 qir_uniform_f(c, 1.0f/0xffffff));
610
611 struct qreg depth_output;
612
613 struct qreg one = qir_uniform_f(c, 1.0f);
614 if (c->key->tex[unit].compare_mode) {
615 struct qreg compare = src[0 * 4 + 2];
616
617 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP)
618 compare = qir_FMUL(c, compare, proj);
619
620 switch (c->key->tex[unit].compare_func) {
621 case PIPE_FUNC_NEVER:
622 depth_output = qir_uniform_f(c, 0.0f);
623 break;
624 case PIPE_FUNC_ALWAYS:
625 depth_output = one;
626 break;
627 case PIPE_FUNC_EQUAL:
628 qir_SF(c, qir_FSUB(c, compare, normalized));
629 depth_output = qir_SEL_X_0_ZS(c, one);
630 break;
631 case PIPE_FUNC_NOTEQUAL:
632 qir_SF(c, qir_FSUB(c, compare, normalized));
633 depth_output = qir_SEL_X_0_ZC(c, one);
634 break;
635 case PIPE_FUNC_GREATER:
636 qir_SF(c, qir_FSUB(c, compare, normalized));
637 depth_output = qir_SEL_X_0_NC(c, one);
638 break;
639 case PIPE_FUNC_GEQUAL:
640 qir_SF(c, qir_FSUB(c, normalized, compare));
641 depth_output = qir_SEL_X_0_NS(c, one);
642 break;
643 case PIPE_FUNC_LESS:
644 qir_SF(c, qir_FSUB(c, compare, normalized));
645 depth_output = qir_SEL_X_0_NS(c, one);
646 break;
647 case PIPE_FUNC_LEQUAL:
648 qir_SF(c, qir_FSUB(c, normalized, compare));
649 depth_output = qir_SEL_X_0_NC(c, one);
650 break;
651 }
652 } else {
653 depth_output = normalized;
654 }
655
656 for (int i = 0; i < 4; i++)
657 unpacked[i] = depth_output;
658 } else {
659 for (int i = 0; i < 4; i++)
660 unpacked[i] = qir_R4_UNPACK(c, r4, i);
661 }
662
663 const uint8_t *format_swiz = vc4_get_format_swizzle(format);
664 struct qreg texture_output[4];
665 for (int i = 0; i < 4; i++) {
666 texture_output[i] = get_swizzled_channel(c, unpacked,
667 format_swiz[i]);
668 }
669
670 if (util_format_is_srgb(format)) {
671 for (int i = 0; i < 3; i++)
672 texture_output[i] = qir_srgb_decode(c,
673 texture_output[i]);
674 }
675
676 for (int i = 0; i < 4; i++) {
677 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
678 continue;
679
680 update_dst(c, tgsi_inst, i,
681 get_swizzled_channel(c, texture_output,
682 c->key->tex[unit].swizzle[i]));
683 }
684 }
685
686 static struct qreg
687 tgsi_to_qir_trunc(struct vc4_compile *c,
688 struct tgsi_full_instruction *tgsi_inst,
689 enum qop op, struct qreg *src, int i)
690 {
691 return qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
692 }
693
694 /**
695 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
696 * to zero).
697 */
698 static struct qreg
699 tgsi_to_qir_frc(struct vc4_compile *c,
700 struct tgsi_full_instruction *tgsi_inst,
701 enum qop op, struct qreg *src, int i)
702 {
703 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
704 struct qreg diff = qir_FSUB(c, src[0 * 4 + i], trunc);
705 qir_SF(c, diff);
706 return qir_SEL_X_Y_NS(c,
707 qir_FADD(c, diff, qir_uniform_f(c, 1.0)),
708 diff);
709 }
710
711 /**
712 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
713 * zero).
714 */
715 static struct qreg
716 tgsi_to_qir_flr(struct vc4_compile *c,
717 struct tgsi_full_instruction *tgsi_inst,
718 enum qop op, struct qreg *src, int i)
719 {
720 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
721
722 /* This will be < 0 if we truncated and the truncation was of a value
723 * that was < 0 in the first place.
724 */
725 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], trunc));
726
727 return qir_SEL_X_Y_NS(c,
728 qir_FSUB(c, trunc, qir_uniform_f(c, 1.0)),
729 trunc);
730 }
731
732 /**
733 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
734 * zero).
735 */
736 static struct qreg
737 tgsi_to_qir_ceil(struct vc4_compile *c,
738 struct tgsi_full_instruction *tgsi_inst,
739 enum qop op, struct qreg *src, int i)
740 {
741 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
742
743 /* This will be < 0 if we truncated and the truncation was of a value
744 * that was > 0 in the first place.
745 */
746 qir_SF(c, qir_FSUB(c, trunc, src[0 * 4 + i]));
747
748 return qir_SEL_X_Y_NS(c,
749 qir_FADD(c, trunc, qir_uniform_f(c, 1.0)),
750 trunc);
751 }
752
753 static struct qreg
754 tgsi_to_qir_abs(struct vc4_compile *c,
755 struct tgsi_full_instruction *tgsi_inst,
756 enum qop op, struct qreg *src, int i)
757 {
758 struct qreg arg = src[0 * 4 + i];
759 return qir_FMAXABS(c, arg, arg);
760 }
761
762 /* Note that this instruction replicates its result from the x channel */
763 static struct qreg
764 tgsi_to_qir_sin(struct vc4_compile *c,
765 struct tgsi_full_instruction *tgsi_inst,
766 enum qop op, struct qreg *src, int i)
767 {
768 float coeff[] = {
769 -2.0 * M_PI,
770 pow(2.0 * M_PI, 3) / (3 * 2 * 1),
771 -pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
772 pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
773 -pow(2.0 * M_PI, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
774 };
775
776 struct qreg scaled_x =
777 qir_FMUL(c,
778 src[0 * 4 + 0],
779 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
780
781 struct qreg x = qir_FADD(c,
782 tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0),
783 qir_uniform_f(c, -0.5));
784 struct qreg x2 = qir_FMUL(c, x, x);
785 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
786 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
787 x = qir_FMUL(c, x, x2);
788 sum = qir_FADD(c,
789 sum,
790 qir_FMUL(c,
791 x,
792 qir_uniform_f(c, coeff[i])));
793 }
794 return sum;
795 }
796
797 /* Note that this instruction replicates its result from the x channel */
798 static struct qreg
799 tgsi_to_qir_cos(struct vc4_compile *c,
800 struct tgsi_full_instruction *tgsi_inst,
801 enum qop op, struct qreg *src, int i)
802 {
803 float coeff[] = {
804 -1.0f,
805 pow(2.0 * M_PI, 2) / (2 * 1),
806 -pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
807 pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
808 -pow(2.0 * M_PI, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
809 pow(2.0 * M_PI, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
810 };
811
812 struct qreg scaled_x =
813 qir_FMUL(c, src[0 * 4 + 0],
814 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
815 struct qreg x_frac = qir_FADD(c,
816 tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0),
817 qir_uniform_f(c, -0.5));
818
819 struct qreg sum = qir_uniform_f(c, coeff[0]);
820 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
821 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
822 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
823 if (i != 1)
824 x = qir_FMUL(c, x, x2);
825
826 struct qreg mul = qir_FMUL(c,
827 x,
828 qir_uniform_f(c, coeff[i]));
829 if (i == 0)
830 sum = mul;
831 else
832 sum = qir_FADD(c, sum, mul);
833 }
834 return sum;
835 }
836
837 static struct qreg
838 tgsi_to_qir_clamp(struct vc4_compile *c,
839 struct tgsi_full_instruction *tgsi_inst,
840 enum qop op, struct qreg *src, int i)
841 {
842 return qir_FMAX(c, qir_FMIN(c,
843 src[0 * 4 + i],
844 src[2 * 4 + i]),
845 src[1 * 4 + i]);
846 }
847
848 static struct qreg
849 tgsi_to_qir_ssg(struct vc4_compile *c,
850 struct tgsi_full_instruction *tgsi_inst,
851 enum qop op, struct qreg *src, int i)
852 {
853 qir_SF(c, src[0 * 4 + i]);
854 return qir_SEL_X_Y_NC(c,
855 qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0)),
856 qir_uniform_f(c, -1.0));
857 }
858
859 static void
860 emit_vertex_input(struct vc4_compile *c, int attr)
861 {
862 enum pipe_format format = c->vs_key->attr_formats[attr];
863 struct qreg vpm_reads[4];
864
865 /* Right now, we're setting the VPM offsets to be 16 bytes wide every
866 * time, so we always read 4 32-bit VPM entries.
867 */
868 for (int i = 0; i < 4; i++) {
869 vpm_reads[i] = qir_get_temp(c);
870 qir_emit(c, qir_inst(QOP_VPM_READ,
871 vpm_reads[i],
872 c->undef,
873 c->undef));
874 c->num_inputs++;
875 }
876
877 bool format_warned = false;
878 const struct util_format_description *desc =
879 util_format_description(format);
880
881 for (int i = 0; i < 4; i++) {
882 uint8_t swiz = desc->swizzle[i];
883 struct qreg result;
884
885 if (swiz > UTIL_FORMAT_SWIZZLE_W)
886 result = get_swizzled_channel(c, vpm_reads, swiz);
887 else if (desc->channel[swiz].size == 32 &&
888 desc->channel[swiz].type == UTIL_FORMAT_TYPE_FLOAT) {
889 result = get_swizzled_channel(c, vpm_reads, swiz);
890 } else if (desc->channel[swiz].size == 8 &&
891 (desc->channel[swiz].type == UTIL_FORMAT_TYPE_UNSIGNED ||
892 desc->channel[swiz].type == UTIL_FORMAT_TYPE_SIGNED) &&
893 desc->channel[swiz].normalized) {
894 struct qreg vpm = vpm_reads[0];
895 if (desc->channel[swiz].type == UTIL_FORMAT_TYPE_SIGNED)
896 vpm = qir_XOR(c, vpm, qir_uniform_ui(c, 0x80808080));
897 result = qir_UNPACK_8(c, vpm, swiz);
898 } else {
899 if (!format_warned) {
900 fprintf(stderr,
901 "vtx element %d unsupported type: %s\n",
902 attr, util_format_name(format));
903 format_warned = true;
904 }
905 result = qir_uniform_f(c, 0.0);
906 }
907
908 if (desc->channel[swiz].normalized &&
909 desc->channel[swiz].type == UTIL_FORMAT_TYPE_SIGNED) {
910 result = qir_FSUB(c,
911 qir_FMUL(c,
912 result,
913 qir_uniform_f(c, 2.0)),
914 qir_uniform_f(c, 1.0));
915 }
916
917 c->inputs[attr * 4 + i] = result;
918 }
919 }
920
921 static void
922 tgsi_to_qir_kill_if(struct vc4_compile *c, struct qreg *src, int i)
923 {
924 if (c->discard.file == QFILE_NULL)
925 c->discard = qir_uniform_f(c, 0.0);
926 qir_SF(c, src[0 * 4 + i]);
927 c->discard = qir_SEL_X_Y_NS(c, qir_uniform_f(c, 1.0),
928 c->discard);
929 }
930
931 static void
932 emit_fragcoord_input(struct vc4_compile *c, int attr)
933 {
934 c->inputs[attr * 4 + 0] = qir_FRAG_X(c);
935 c->inputs[attr * 4 + 1] = qir_FRAG_Y(c);
936 c->inputs[attr * 4 + 2] =
937 qir_FMUL(c,
938 qir_ITOF(c, qir_FRAG_Z(c)),
939 qir_uniform_f(c, 1.0 / 0xffffff));
940 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
941 }
942
943 static void
944 emit_point_coord_input(struct vc4_compile *c, int attr)
945 {
946 if (c->point_x.file == QFILE_NULL) {
947 c->point_x = qir_uniform_f(c, 0.0);
948 c->point_y = qir_uniform_f(c, 0.0);
949 }
950
951 c->inputs[attr * 4 + 0] = c->point_x;
952 if (c->fs_key->point_coord_upper_left) {
953 c->inputs[attr * 4 + 1] = qir_FSUB(c,
954 qir_uniform_f(c, 1.0),
955 c->point_y);
956 } else {
957 c->inputs[attr * 4 + 1] = c->point_y;
958 }
959 c->inputs[attr * 4 + 2] = qir_uniform_f(c, 0.0);
960 c->inputs[attr * 4 + 3] = qir_uniform_f(c, 1.0);
961 }
962
963 static struct qreg
964 emit_fragment_varying(struct vc4_compile *c, uint8_t semantic,
965 uint8_t index, uint8_t swizzle)
966 {
967 uint32_t i = c->num_input_semantics++;
968 struct qreg vary = {
969 QFILE_VARY,
970 i
971 };
972
973 if (c->num_input_semantics >= c->input_semantics_array_size) {
974 c->input_semantics_array_size =
975 MAX2(4, c->input_semantics_array_size * 2);
976
977 c->input_semantics = reralloc(c, c->input_semantics,
978 struct vc4_varying_semantic,
979 c->input_semantics_array_size);
980 }
981
982 c->input_semantics[i].semantic = semantic;
983 c->input_semantics[i].index = index;
984 c->input_semantics[i].swizzle = swizzle;
985
986 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
987 }
988
989 static void
990 emit_fragment_input(struct vc4_compile *c, int attr,
991 struct tgsi_full_declaration *decl)
992 {
993 for (int i = 0; i < 4; i++) {
994 c->inputs[attr * 4 + i] =
995 emit_fragment_varying(c,
996 decl->Semantic.Name,
997 decl->Semantic.Index,
998 i);
999 c->num_inputs++;
1000 }
1001 }
1002
1003 static void
1004 emit_face_input(struct vc4_compile *c, int attr)
1005 {
1006 c->inputs[attr * 4 + 0] = qir_FSUB(c,
1007 qir_uniform_f(c, 1.0),
1008 qir_FMUL(c,
1009 qir_ITOF(c, qir_FRAG_REV_FLAG(c)),
1010 qir_uniform_f(c, 2.0)));
1011 c->inputs[attr * 4 + 1] = qir_uniform_f(c, 0.0);
1012 c->inputs[attr * 4 + 2] = qir_uniform_f(c, 0.0);
1013 c->inputs[attr * 4 + 3] = qir_uniform_f(c, 1.0);
1014 }
1015
1016 static void
1017 emit_tgsi_declaration(struct vc4_compile *c,
1018 struct tgsi_full_declaration *decl)
1019 {
1020 switch (decl->Declaration.File) {
1021 case TGSI_FILE_TEMPORARY: {
1022 uint32_t old_size = c->temps_array_size;
1023 resize_qreg_array(c, &c->temps, &c->temps_array_size,
1024 (decl->Range.Last + 1) * 4);
1025
1026 for (int i = old_size; i < c->temps_array_size; i++)
1027 c->temps[i] = qir_uniform_ui(c, 0);
1028 break;
1029 }
1030
1031 case TGSI_FILE_INPUT:
1032 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1033 (decl->Range.Last + 1) * 4);
1034
1035 for (int i = decl->Range.First;
1036 i <= decl->Range.Last;
1037 i++) {
1038 if (c->stage == QSTAGE_FRAG) {
1039 if (decl->Semantic.Name ==
1040 TGSI_SEMANTIC_POSITION) {
1041 emit_fragcoord_input(c, i);
1042 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
1043 emit_face_input(c, i);
1044 } else if (decl->Semantic.Name == TGSI_SEMANTIC_GENERIC &&
1045 (c->fs_key->point_sprite_mask &
1046 (1 << decl->Semantic.Index))) {
1047 emit_point_coord_input(c, i);
1048 } else {
1049 emit_fragment_input(c, i, decl);
1050 }
1051 } else {
1052 emit_vertex_input(c, i);
1053 }
1054 }
1055 break;
1056
1057 case TGSI_FILE_OUTPUT: {
1058 uint32_t old_array_size = c->outputs_array_size;
1059 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
1060 (decl->Range.Last + 1) * 4);
1061
1062 if (old_array_size != c->outputs_array_size) {
1063 c->output_semantics = reralloc(c,
1064 c->output_semantics,
1065 struct vc4_varying_semantic,
1066 c->outputs_array_size);
1067 }
1068
1069 struct vc4_varying_semantic *sem =
1070 &c->output_semantics[decl->Range.First * 4];
1071 for (int i = 0; i < 4; i++) {
1072 sem[i].semantic = decl->Semantic.Name;
1073 sem[i].index = decl->Semantic.Index;
1074 sem[i].swizzle = i;
1075 }
1076
1077 switch (decl->Semantic.Name) {
1078 case TGSI_SEMANTIC_POSITION:
1079 c->output_position_index = decl->Range.First * 4;
1080 break;
1081 case TGSI_SEMANTIC_COLOR:
1082 c->output_color_index = decl->Range.First * 4;
1083 break;
1084 case TGSI_SEMANTIC_PSIZE:
1085 c->output_point_size_index = decl->Range.First * 4;
1086 break;
1087 }
1088
1089 break;
1090 }
1091 }
1092 }
1093
1094 static void
1095 emit_tgsi_instruction(struct vc4_compile *c,
1096 struct tgsi_full_instruction *tgsi_inst)
1097 {
1098 struct {
1099 enum qop op;
1100 struct qreg (*func)(struct vc4_compile *c,
1101 struct tgsi_full_instruction *tgsi_inst,
1102 enum qop op,
1103 struct qreg *src, int i);
1104 } op_trans[] = {
1105 [TGSI_OPCODE_MOV] = { QOP_MOV, tgsi_to_qir_alu },
1106 [TGSI_OPCODE_ABS] = { 0, tgsi_to_qir_abs },
1107 [TGSI_OPCODE_MUL] = { QOP_FMUL, tgsi_to_qir_alu },
1108 [TGSI_OPCODE_ADD] = { QOP_FADD, tgsi_to_qir_alu },
1109 [TGSI_OPCODE_SUB] = { QOP_FSUB, tgsi_to_qir_alu },
1110 [TGSI_OPCODE_MIN] = { QOP_FMIN, tgsi_to_qir_alu },
1111 [TGSI_OPCODE_MAX] = { QOP_FMAX, tgsi_to_qir_alu },
1112 [TGSI_OPCODE_F2I] = { QOP_FTOI, tgsi_to_qir_alu },
1113 [TGSI_OPCODE_I2F] = { QOP_ITOF, tgsi_to_qir_alu },
1114 [TGSI_OPCODE_UADD] = { QOP_ADD, tgsi_to_qir_alu },
1115 [TGSI_OPCODE_USHR] = { QOP_SHR, tgsi_to_qir_alu },
1116 [TGSI_OPCODE_ISHR] = { QOP_ASR, tgsi_to_qir_alu },
1117 [TGSI_OPCODE_SHL] = { QOP_SHL, tgsi_to_qir_alu },
1118 [TGSI_OPCODE_IMIN] = { QOP_MIN, tgsi_to_qir_alu },
1119 [TGSI_OPCODE_IMAX] = { QOP_MAX, tgsi_to_qir_alu },
1120 [TGSI_OPCODE_AND] = { QOP_AND, tgsi_to_qir_alu },
1121 [TGSI_OPCODE_OR] = { QOP_OR, tgsi_to_qir_alu },
1122 [TGSI_OPCODE_XOR] = { QOP_XOR, tgsi_to_qir_alu },
1123 [TGSI_OPCODE_NOT] = { QOP_NOT, tgsi_to_qir_alu },
1124
1125 [TGSI_OPCODE_UMUL] = { 0, tgsi_to_qir_umul },
1126 [TGSI_OPCODE_IDIV] = { 0, tgsi_to_qir_idiv },
1127 [TGSI_OPCODE_INEG] = { 0, tgsi_to_qir_ineg },
1128
1129 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_alu },
1130 [TGSI_OPCODE_SEQ] = { 0, tgsi_to_qir_seq },
1131 [TGSI_OPCODE_SNE] = { 0, tgsi_to_qir_sne },
1132 [TGSI_OPCODE_SGE] = { 0, tgsi_to_qir_sge },
1133 [TGSI_OPCODE_SLT] = { 0, tgsi_to_qir_slt },
1134 [TGSI_OPCODE_FSEQ] = { 0, tgsi_to_qir_fseq },
1135 [TGSI_OPCODE_FSNE] = { 0, tgsi_to_qir_fsne },
1136 [TGSI_OPCODE_FSGE] = { 0, tgsi_to_qir_fsge },
1137 [TGSI_OPCODE_FSLT] = { 0, tgsi_to_qir_fslt },
1138 [TGSI_OPCODE_USEQ] = { 0, tgsi_to_qir_useq },
1139 [TGSI_OPCODE_USNE] = { 0, tgsi_to_qir_usne },
1140 [TGSI_OPCODE_ISGE] = { 0, tgsi_to_qir_isge },
1141 [TGSI_OPCODE_ISLT] = { 0, tgsi_to_qir_islt },
1142
1143 [TGSI_OPCODE_CMP] = { 0, tgsi_to_qir_cmp },
1144 [TGSI_OPCODE_MAD] = { 0, tgsi_to_qir_mad },
1145 [TGSI_OPCODE_RCP] = { QOP_RCP, tgsi_to_qir_scalar },
1146 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_scalar },
1147 [TGSI_OPCODE_EX2] = { QOP_EXP2, tgsi_to_qir_scalar },
1148 [TGSI_OPCODE_LG2] = { QOP_LOG2, tgsi_to_qir_scalar },
1149 [TGSI_OPCODE_LRP] = { 0, tgsi_to_qir_lrp },
1150 [TGSI_OPCODE_TRUNC] = { 0, tgsi_to_qir_trunc },
1151 [TGSI_OPCODE_CEIL] = { 0, tgsi_to_qir_ceil },
1152 [TGSI_OPCODE_FRC] = { 0, tgsi_to_qir_frc },
1153 [TGSI_OPCODE_FLR] = { 0, tgsi_to_qir_flr },
1154 [TGSI_OPCODE_SIN] = { 0, tgsi_to_qir_sin },
1155 [TGSI_OPCODE_COS] = { 0, tgsi_to_qir_cos },
1156 [TGSI_OPCODE_CLAMP] = { 0, tgsi_to_qir_clamp },
1157 [TGSI_OPCODE_SSG] = { 0, tgsi_to_qir_ssg },
1158 };
1159 static int asdf = 0;
1160 uint32_t tgsi_op = tgsi_inst->Instruction.Opcode;
1161
1162 if (tgsi_op == TGSI_OPCODE_END)
1163 return;
1164
1165 struct qreg src_regs[12];
1166 for (int s = 0; s < 3; s++) {
1167 for (int i = 0; i < 4; i++) {
1168 src_regs[4 * s + i] =
1169 get_src(c, tgsi_inst->Instruction.Opcode,
1170 &tgsi_inst->Src[s].Register, i);
1171 }
1172 }
1173
1174 switch (tgsi_op) {
1175 case TGSI_OPCODE_TEX:
1176 case TGSI_OPCODE_TXP:
1177 case TGSI_OPCODE_TXB:
1178 tgsi_to_qir_tex(c, tgsi_inst,
1179 op_trans[tgsi_op].op, src_regs);
1180 return;
1181 case TGSI_OPCODE_KILL:
1182 c->discard = qir_uniform_f(c, 1.0);
1183 return;
1184 case TGSI_OPCODE_KILL_IF:
1185 for (int i = 0; i < 4; i++)
1186 tgsi_to_qir_kill_if(c, src_regs, i);
1187 return;
1188 default:
1189 break;
1190 }
1191
1192 if (tgsi_op > ARRAY_SIZE(op_trans) || !(op_trans[tgsi_op].func)) {
1193 fprintf(stderr, "unknown tgsi inst: ");
1194 tgsi_dump_instruction(tgsi_inst, asdf++);
1195 fprintf(stderr, "\n");
1196 abort();
1197 }
1198
1199 for (int i = 0; i < 4; i++) {
1200 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
1201 continue;
1202
1203 struct qreg result;
1204
1205 result = op_trans[tgsi_op].func(c, tgsi_inst,
1206 op_trans[tgsi_op].op,
1207 src_regs, i);
1208
1209 if (tgsi_inst->Instruction.Saturate) {
1210 float low = (tgsi_inst->Instruction.Saturate ==
1211 TGSI_SAT_MINUS_PLUS_ONE ? -1.0 : 0.0);
1212 result = qir_FMAX(c,
1213 qir_FMIN(c,
1214 result,
1215 qir_uniform_f(c, 1.0)),
1216 qir_uniform_f(c, low));
1217 }
1218
1219 update_dst(c, tgsi_inst, i, result);
1220 }
1221 }
1222
1223 static void
1224 parse_tgsi_immediate(struct vc4_compile *c, struct tgsi_full_immediate *imm)
1225 {
1226 for (int i = 0; i < 4; i++) {
1227 unsigned n = c->num_consts++;
1228 resize_qreg_array(c, &c->consts, &c->consts_array_size, n + 1);
1229 c->consts[n] = qir_uniform_ui(c, imm->u[i].Uint);
1230 }
1231 }
1232
1233 static struct qreg
1234 vc4_blend_channel(struct vc4_compile *c,
1235 struct qreg *dst,
1236 struct qreg *src,
1237 struct qreg val,
1238 unsigned factor,
1239 int channel)
1240 {
1241 switch(factor) {
1242 case PIPE_BLENDFACTOR_ONE:
1243 return val;
1244 case PIPE_BLENDFACTOR_SRC_COLOR:
1245 return qir_FMUL(c, val, src[channel]);
1246 case PIPE_BLENDFACTOR_SRC_ALPHA:
1247 return qir_FMUL(c, val, src[3]);
1248 case PIPE_BLENDFACTOR_DST_ALPHA:
1249 return qir_FMUL(c, val, dst[3]);
1250 case PIPE_BLENDFACTOR_DST_COLOR:
1251 return qir_FMUL(c, val, dst[channel]);
1252 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
1253 return qir_FMIN(c, src[3], qir_FSUB(c,
1254 qir_uniform_f(c, 1.0),
1255 dst[3]));
1256 case PIPE_BLENDFACTOR_CONST_COLOR:
1257 return qir_FMUL(c, val,
1258 get_temp_for_uniform(c,
1259 QUNIFORM_BLEND_CONST_COLOR,
1260 channel));
1261 case PIPE_BLENDFACTOR_CONST_ALPHA:
1262 return qir_FMUL(c, val,
1263 get_temp_for_uniform(c,
1264 QUNIFORM_BLEND_CONST_COLOR,
1265 3));
1266 case PIPE_BLENDFACTOR_ZERO:
1267 return qir_uniform_f(c, 0.0);
1268 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
1269 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1270 src[channel]));
1271 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
1272 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1273 src[3]));
1274 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
1275 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1276 dst[3]));
1277 case PIPE_BLENDFACTOR_INV_DST_COLOR:
1278 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1279 dst[channel]));
1280 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
1281 return qir_FMUL(c, val,
1282 qir_FSUB(c, qir_uniform_f(c, 1.0),
1283 get_temp_for_uniform(c,
1284 QUNIFORM_BLEND_CONST_COLOR,
1285 channel)));
1286 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
1287 return qir_FMUL(c, val,
1288 qir_FSUB(c, qir_uniform_f(c, 1.0),
1289 get_temp_for_uniform(c,
1290 QUNIFORM_BLEND_CONST_COLOR,
1291 3)));
1292
1293 default:
1294 case PIPE_BLENDFACTOR_SRC1_COLOR:
1295 case PIPE_BLENDFACTOR_SRC1_ALPHA:
1296 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
1297 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
1298 /* Unsupported. */
1299 fprintf(stderr, "Unknown blend factor %d\n", factor);
1300 return val;
1301 }
1302 }
1303
1304 static struct qreg
1305 vc4_blend_func(struct vc4_compile *c,
1306 struct qreg src, struct qreg dst,
1307 unsigned func)
1308 {
1309 switch (func) {
1310 case PIPE_BLEND_ADD:
1311 return qir_FADD(c, src, dst);
1312 case PIPE_BLEND_SUBTRACT:
1313 return qir_FSUB(c, src, dst);
1314 case PIPE_BLEND_REVERSE_SUBTRACT:
1315 return qir_FSUB(c, dst, src);
1316 case PIPE_BLEND_MIN:
1317 return qir_FMIN(c, src, dst);
1318 case PIPE_BLEND_MAX:
1319 return qir_FMAX(c, src, dst);
1320
1321 default:
1322 /* Unsupported. */
1323 fprintf(stderr, "Unknown blend func %d\n", func);
1324 return src;
1325
1326 }
1327 }
1328
1329 /**
1330 * Implements fixed function blending in shader code.
1331 *
1332 * VC4 doesn't have any hardware support for blending. Instead, you read the
1333 * current contents of the destination from the tile buffer after having
1334 * waited for the scoreboard (which is handled by vc4_qpu_emit.c), then do
1335 * math using your output color and that destination value, and update the
1336 * output color appropriately.
1337 */
1338 static void
1339 vc4_blend(struct vc4_compile *c, struct qreg *result,
1340 struct qreg *dst_color, struct qreg *src_color)
1341 {
1342 struct pipe_rt_blend_state *blend = &c->fs_key->blend;
1343
1344 if (!blend->blend_enable) {
1345 for (int i = 0; i < 4; i++)
1346 result[i] = src_color[i];
1347 return;
1348 }
1349
1350 struct qreg src_blend[4], dst_blend[4];
1351 for (int i = 0; i < 3; i++) {
1352 src_blend[i] = vc4_blend_channel(c,
1353 dst_color, src_color,
1354 src_color[i],
1355 blend->rgb_src_factor, i);
1356 dst_blend[i] = vc4_blend_channel(c,
1357 dst_color, src_color,
1358 dst_color[i],
1359 blend->rgb_dst_factor, i);
1360 }
1361 src_blend[3] = vc4_blend_channel(c,
1362 dst_color, src_color,
1363 src_color[3],
1364 blend->alpha_src_factor, 3);
1365 dst_blend[3] = vc4_blend_channel(c,
1366 dst_color, src_color,
1367 dst_color[3],
1368 blend->alpha_dst_factor, 3);
1369
1370 for (int i = 0; i < 3; i++) {
1371 result[i] = vc4_blend_func(c,
1372 src_blend[i], dst_blend[i],
1373 blend->rgb_func);
1374 }
1375 result[3] = vc4_blend_func(c,
1376 src_blend[3], dst_blend[3],
1377 blend->alpha_func);
1378 }
1379
1380 static void
1381 alpha_test_discard(struct vc4_compile *c)
1382 {
1383 struct qreg src_alpha;
1384 struct qreg alpha_ref = get_temp_for_uniform(c, QUNIFORM_ALPHA_REF, 0);
1385
1386 if (!c->fs_key->alpha_test)
1387 return;
1388
1389 if (c->output_color_index != -1)
1390 src_alpha = c->outputs[c->output_color_index + 3];
1391 else
1392 src_alpha = qir_uniform_f(c, 1.0);
1393
1394 if (c->discard.file == QFILE_NULL)
1395 c->discard = qir_uniform_f(c, 0.0);
1396
1397 switch (c->fs_key->alpha_test_func) {
1398 case PIPE_FUNC_NEVER:
1399 c->discard = qir_uniform_f(c, 1.0);
1400 break;
1401 case PIPE_FUNC_ALWAYS:
1402 break;
1403 case PIPE_FUNC_EQUAL:
1404 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1405 c->discard = qir_SEL_X_Y_ZS(c, c->discard,
1406 qir_uniform_f(c, 1.0));
1407 break;
1408 case PIPE_FUNC_NOTEQUAL:
1409 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1410 c->discard = qir_SEL_X_Y_ZC(c, c->discard,
1411 qir_uniform_f(c, 1.0));
1412 break;
1413 case PIPE_FUNC_GREATER:
1414 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1415 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1416 qir_uniform_f(c, 1.0));
1417 break;
1418 case PIPE_FUNC_GEQUAL:
1419 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1420 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1421 qir_uniform_f(c, 1.0));
1422 break;
1423 case PIPE_FUNC_LESS:
1424 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1425 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1426 qir_uniform_f(c, 1.0));
1427 break;
1428 case PIPE_FUNC_LEQUAL:
1429 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1430 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1431 qir_uniform_f(c, 1.0));
1432 break;
1433 }
1434 }
1435
1436 static void
1437 emit_frag_end(struct vc4_compile *c)
1438 {
1439 alpha_test_discard(c);
1440
1441 enum pipe_format color_format = c->fs_key->color_format;
1442 const uint8_t *format_swiz = vc4_get_format_swizzle(color_format);
1443 struct qreg tlb_read_color[4] = { c->undef, c->undef, c->undef, c->undef };
1444 struct qreg dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1445 struct qreg linear_dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1446 if (c->fs_key->blend.blend_enable ||
1447 c->fs_key->blend.colormask != 0xf) {
1448 struct qreg r4 = qir_TLB_COLOR_READ(c);
1449 for (int i = 0; i < 4; i++)
1450 tlb_read_color[i] = qir_R4_UNPACK(c, r4, i);
1451 for (int i = 0; i < 4; i++) {
1452 dst_color[i] = get_swizzled_channel(c,
1453 tlb_read_color,
1454 format_swiz[i]);
1455 if (util_format_is_srgb(color_format) && i != 3) {
1456 linear_dst_color[i] =
1457 qir_srgb_decode(c, dst_color[i]);
1458 } else {
1459 linear_dst_color[i] = dst_color[i];
1460 }
1461 }
1462 }
1463
1464 struct qreg blend_color[4];
1465 struct qreg undef_array[4] = {
1466 c->undef, c->undef, c->undef, c->undef
1467 };
1468 vc4_blend(c, blend_color, linear_dst_color,
1469 (c->output_color_index != -1 ?
1470 c->outputs + c->output_color_index :
1471 undef_array));
1472
1473 if (util_format_is_srgb(color_format)) {
1474 for (int i = 0; i < 3; i++)
1475 blend_color[i] = qir_srgb_encode(c, blend_color[i]);
1476 }
1477
1478 /* If the bit isn't set in the color mask, then just return the
1479 * original dst color, instead.
1480 */
1481 for (int i = 0; i < 4; i++) {
1482 if (!(c->fs_key->blend.colormask & (1 << i))) {
1483 blend_color[i] = dst_color[i];
1484 }
1485 }
1486
1487 /* Debug: Sometimes you're getting a black output and just want to see
1488 * if the FS is getting executed at all. Spam magenta into the color
1489 * output.
1490 */
1491 if (0) {
1492 blend_color[0] = qir_uniform_f(c, 1.0);
1493 blend_color[1] = qir_uniform_f(c, 0.0);
1494 blend_color[2] = qir_uniform_f(c, 1.0);
1495 blend_color[3] = qir_uniform_f(c, 0.5);
1496 }
1497
1498 struct qreg swizzled_outputs[4];
1499 for (int i = 0; i < 4; i++) {
1500 swizzled_outputs[i] = get_swizzled_channel(c, blend_color,
1501 format_swiz[i]);
1502 }
1503
1504 if (c->discard.file != QFILE_NULL)
1505 qir_TLB_DISCARD_SETUP(c, c->discard);
1506
1507 if (c->fs_key->stencil_enabled) {
1508 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 0));
1509 if (c->fs_key->stencil_twoside) {
1510 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 1));
1511 }
1512 if (c->fs_key->stencil_full_writemasks) {
1513 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 2));
1514 }
1515 }
1516
1517 if (c->fs_key->depth_enabled) {
1518 struct qreg z;
1519 if (c->output_position_index != -1) {
1520 z = qir_FTOI(c, qir_FMUL(c, c->outputs[c->output_position_index + 2],
1521 qir_uniform_f(c, 0xffffff)));
1522 } else {
1523 z = qir_FRAG_Z(c);
1524 }
1525 qir_TLB_Z_WRITE(c, z);
1526 }
1527
1528 bool color_written = false;
1529 for (int i = 0; i < 4; i++) {
1530 if (swizzled_outputs[i].file != QFILE_NULL)
1531 color_written = true;
1532 }
1533
1534 struct qreg packed_color;
1535 if (color_written) {
1536 /* Fill in any undefined colors. The simulator will assertion
1537 * fail if we read something that wasn't written, and I don't
1538 * know what hardware does.
1539 */
1540 for (int i = 0; i < 4; i++) {
1541 if (swizzled_outputs[i].file == QFILE_NULL)
1542 swizzled_outputs[i] = qir_uniform_f(c, 0.0);
1543 }
1544 packed_color = qir_get_temp(c);
1545 qir_emit(c, qir_inst4(QOP_PACK_COLORS, packed_color,
1546 swizzled_outputs[0],
1547 swizzled_outputs[1],
1548 swizzled_outputs[2],
1549 swizzled_outputs[3]));
1550 } else {
1551 packed_color = qir_uniform_ui(c, 0);
1552 }
1553
1554 qir_emit(c, qir_inst(QOP_TLB_COLOR_WRITE, c->undef,
1555 packed_color, c->undef));
1556 }
1557
1558 static void
1559 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1560 {
1561 struct qreg xyi[2];
1562
1563 for (int i = 0; i < 2; i++) {
1564 struct qreg scale =
1565 add_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1566
1567 xyi[i] = qir_FTOI(c, qir_FMUL(c,
1568 qir_FMUL(c,
1569 c->outputs[i],
1570 scale),
1571 rcp_w));
1572 }
1573
1574 qir_VPM_WRITE(c, qir_PACK_SCALED(c, xyi[0], xyi[1]));
1575 }
1576
1577 static void
1578 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1579 {
1580 struct qreg zscale = add_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1581 struct qreg zoffset = add_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1582
1583 qir_VPM_WRITE(c, qir_FMUL(c, qir_FADD(c, qir_FMUL(c,
1584 c->outputs[2],
1585 zscale),
1586 zoffset),
1587 rcp_w));
1588 }
1589
1590 static void
1591 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1592 {
1593 qir_VPM_WRITE(c, rcp_w);
1594 }
1595
1596 static void
1597 emit_point_size_write(struct vc4_compile *c)
1598 {
1599 struct qreg point_size;
1600
1601 if (c->output_point_size_index)
1602 point_size = c->outputs[c->output_point_size_index + 3];
1603 else
1604 point_size = qir_uniform_f(c, 1.0);
1605
1606 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1607 * BCM21553).
1608 */
1609 point_size = qir_FMAX(c, point_size, qir_uniform_f(c, .125));
1610
1611 qir_VPM_WRITE(c, point_size);
1612 }
1613
1614 static void
1615 emit_vert_end(struct vc4_compile *c,
1616 struct vc4_varying_semantic *fs_inputs,
1617 uint32_t num_fs_inputs)
1618 {
1619 struct qreg rcp_w = qir_RCP(c, c->outputs[3]);
1620
1621 emit_scaled_viewport_write(c, rcp_w);
1622 emit_zs_write(c, rcp_w);
1623 emit_rcp_wc_write(c, rcp_w);
1624 if (c->vs_key->per_vertex_point_size)
1625 emit_point_size_write(c);
1626
1627 for (int i = 0; i < num_fs_inputs; i++) {
1628 struct vc4_varying_semantic *input = &fs_inputs[i];
1629 int j;
1630 for (j = 0; j < c->num_outputs; j++) {
1631 struct vc4_varying_semantic *output =
1632 &c->output_semantics[j];
1633 if (input->semantic == output->semantic &&
1634 input->index == output->index &&
1635 input->swizzle == output->swizzle) {
1636 qir_VPM_WRITE(c, c->outputs[j]);
1637 break;
1638 }
1639 }
1640 /* Emit padding if we didn't find a declared VS output for
1641 * this FS input.
1642 */
1643 if (j == c->num_outputs)
1644 qir_VPM_WRITE(c, qir_uniform_f(c, 0.0));
1645 }
1646 }
1647
1648 static void
1649 emit_coord_end(struct vc4_compile *c)
1650 {
1651 struct qreg rcp_w = qir_RCP(c, c->outputs[3]);
1652
1653 for (int i = 0; i < 4; i++)
1654 qir_VPM_WRITE(c, c->outputs[i]);
1655
1656 emit_scaled_viewport_write(c, rcp_w);
1657 emit_zs_write(c, rcp_w);
1658 emit_rcp_wc_write(c, rcp_w);
1659 if (c->vs_key->per_vertex_point_size)
1660 emit_point_size_write(c);
1661 }
1662
1663 static struct vc4_compile *
1664 vc4_shader_tgsi_to_qir(struct vc4_context *vc4, enum qstage stage,
1665 struct vc4_key *key)
1666 {
1667 struct vc4_compile *c = qir_compile_init();
1668 int ret;
1669
1670 c->stage = stage;
1671 c->shader_state = &key->shader_state->base;
1672
1673 c->key = key;
1674 switch (stage) {
1675 case QSTAGE_FRAG:
1676 c->fs_key = (struct vc4_fs_key *)key;
1677 if (c->fs_key->is_points) {
1678 c->point_x = emit_fragment_varying(c, ~0, ~0, 0);
1679 c->point_y = emit_fragment_varying(c, ~0, ~0, 0);
1680 } else if (c->fs_key->is_lines) {
1681 c->line_x = emit_fragment_varying(c, ~0, ~0, 0);
1682 }
1683 break;
1684 case QSTAGE_VERT:
1685 c->vs_key = (struct vc4_vs_key *)key;
1686 break;
1687 case QSTAGE_COORD:
1688 c->vs_key = (struct vc4_vs_key *)key;
1689 break;
1690 }
1691
1692 const struct tgsi_token *tokens = key->shader_state->base.tokens;
1693 if (c->fs_key && c->fs_key->light_twoside) {
1694 if (!key->shader_state->twoside_tokens) {
1695 const struct tgsi_lowering_config lowering_config = {
1696 .color_two_side = true,
1697 };
1698 struct tgsi_shader_info info;
1699 key->shader_state->twoside_tokens =
1700 tgsi_transform_lowering(&lowering_config,
1701 key->shader_state->base.tokens,
1702 &info);
1703
1704 /* If no transformation occurred, then NULL is
1705 * returned and we just use our original tokens.
1706 */
1707 if (!key->shader_state->twoside_tokens) {
1708 key->shader_state->twoside_tokens =
1709 key->shader_state->base.tokens;
1710 }
1711 }
1712 tokens = key->shader_state->twoside_tokens;
1713 }
1714
1715 ret = tgsi_parse_init(&c->parser, tokens);
1716 assert(ret == TGSI_PARSE_OK);
1717
1718 if (vc4_debug & VC4_DEBUG_TGSI) {
1719 fprintf(stderr, "TGSI:\n");
1720 tgsi_dump(tokens, 0);
1721 }
1722
1723 while (!tgsi_parse_end_of_tokens(&c->parser)) {
1724 tgsi_parse_token(&c->parser);
1725
1726 switch (c->parser.FullToken.Token.Type) {
1727 case TGSI_TOKEN_TYPE_DECLARATION:
1728 emit_tgsi_declaration(c,
1729 &c->parser.FullToken.FullDeclaration);
1730 break;
1731
1732 case TGSI_TOKEN_TYPE_INSTRUCTION:
1733 emit_tgsi_instruction(c,
1734 &c->parser.FullToken.FullInstruction);
1735 break;
1736
1737 case TGSI_TOKEN_TYPE_IMMEDIATE:
1738 parse_tgsi_immediate(c,
1739 &c->parser.FullToken.FullImmediate);
1740 break;
1741 }
1742 }
1743
1744 switch (stage) {
1745 case QSTAGE_FRAG:
1746 emit_frag_end(c);
1747 break;
1748 case QSTAGE_VERT:
1749 emit_vert_end(c,
1750 vc4->prog.fs->input_semantics,
1751 vc4->prog.fs->num_inputs);
1752 break;
1753 case QSTAGE_COORD:
1754 emit_coord_end(c);
1755 break;
1756 }
1757
1758 tgsi_parse_free(&c->parser);
1759
1760 qir_optimize(c);
1761
1762 if (vc4_debug & VC4_DEBUG_QIR) {
1763 fprintf(stderr, "QIR:\n");
1764 qir_dump(c);
1765 }
1766 qir_reorder_uniforms(c);
1767 vc4_generate_code(vc4, c);
1768
1769 if (vc4_debug & VC4_DEBUG_SHADERDB) {
1770 fprintf(stderr, "SHADER-DB: %s: %d instructions\n",
1771 qir_get_stage_name(c->stage), c->qpu_inst_count);
1772 fprintf(stderr, "SHADER-DB: %s: %d uniforms\n",
1773 qir_get_stage_name(c->stage), c->num_uniforms);
1774 }
1775
1776 return c;
1777 }
1778
1779 static void *
1780 vc4_shader_state_create(struct pipe_context *pctx,
1781 const struct pipe_shader_state *cso)
1782 {
1783 struct vc4_uncompiled_shader *so = CALLOC_STRUCT(vc4_uncompiled_shader);
1784 if (!so)
1785 return NULL;
1786
1787 const struct tgsi_lowering_config lowering_config = {
1788 .lower_DST = true,
1789 .lower_XPD = true,
1790 .lower_SCS = true,
1791 .lower_POW = true,
1792 .lower_LIT = true,
1793 .lower_EXP = true,
1794 .lower_LOG = true,
1795 .lower_DP4 = true,
1796 .lower_DP3 = true,
1797 .lower_DPH = true,
1798 .lower_DP2 = true,
1799 .lower_DP2A = true,
1800 };
1801
1802 struct tgsi_shader_info info;
1803 so->base.tokens = tgsi_transform_lowering(&lowering_config, cso->tokens, &info);
1804 if (!so->base.tokens)
1805 so->base.tokens = tgsi_dup_tokens(cso->tokens);
1806
1807 return so;
1808 }
1809
1810 static void
1811 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
1812 struct vc4_compile *c)
1813 {
1814 int count = c->num_uniforms;
1815 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
1816
1817 uinfo->count = count;
1818 uinfo->data = ralloc_array(shader, uint32_t, count);
1819 memcpy(uinfo->data, c->uniform_data,
1820 count * sizeof(*uinfo->data));
1821 uinfo->contents = ralloc_array(shader, enum quniform_contents, count);
1822 memcpy(uinfo->contents, c->uniform_contents,
1823 count * sizeof(*uinfo->contents));
1824 uinfo->num_texture_samples = c->num_texture_samples;
1825 }
1826
1827 static struct vc4_compiled_shader *
1828 vc4_get_compiled_shader(struct vc4_context *vc4, enum qstage stage,
1829 struct vc4_key *key)
1830 {
1831 struct util_hash_table *ht;
1832 uint32_t key_size;
1833 if (stage == QSTAGE_FRAG) {
1834 ht = vc4->fs_cache;
1835 key_size = sizeof(struct vc4_fs_key);
1836 } else {
1837 ht = vc4->vs_cache;
1838 key_size = sizeof(struct vc4_vs_key);
1839 }
1840
1841 struct vc4_compiled_shader *shader;
1842 shader = util_hash_table_get(ht, key);
1843 if (shader)
1844 return shader;
1845
1846 struct vc4_compile *c = vc4_shader_tgsi_to_qir(vc4, stage, key);
1847 shader = rzalloc(NULL, struct vc4_compiled_shader);
1848
1849 shader->program_id = vc4->next_compiled_program_id++;
1850 if (stage == QSTAGE_FRAG) {
1851 shader->input_semantics = ralloc_array(shader,
1852 struct vc4_varying_semantic,
1853 c->num_input_semantics);
1854
1855 for (int i = 0; i < c->num_input_semantics; i++) {
1856 struct vc4_varying_semantic *sem = &c->input_semantics[i];
1857
1858 /* Skip non-VS-output inputs. */
1859 if (sem->semantic == (uint8_t)~0)
1860 continue;
1861
1862 if (sem->semantic == TGSI_SEMANTIC_COLOR)
1863 shader->color_inputs |= (1 << shader->num_inputs);
1864 shader->input_semantics[shader->num_inputs] = *sem;
1865 shader->num_inputs++;
1866 }
1867 } else {
1868 shader->num_inputs = c->num_inputs;
1869 }
1870
1871 copy_uniform_state_to_shader(shader, c);
1872 shader->bo = vc4_bo_alloc_mem(vc4->screen, c->qpu_insts,
1873 c->qpu_inst_count * sizeof(uint64_t),
1874 "code");
1875
1876 qir_compile_destroy(c);
1877
1878 struct vc4_key *dup_key;
1879 dup_key = malloc(key_size);
1880 memcpy(dup_key, key, key_size);
1881 util_hash_table_set(ht, dup_key, shader);
1882
1883 return shader;
1884 }
1885
1886 static void
1887 vc4_setup_shared_key(struct vc4_key *key, struct vc4_texture_stateobj *texstate)
1888 {
1889 for (int i = 0; i < texstate->num_textures; i++) {
1890 struct pipe_sampler_view *sampler = texstate->textures[i];
1891 struct pipe_sampler_state *sampler_state =
1892 texstate->samplers[i];
1893
1894 if (sampler) {
1895 key->tex[i].format = sampler->format;
1896 key->tex[i].swizzle[0] = sampler->swizzle_r;
1897 key->tex[i].swizzle[1] = sampler->swizzle_g;
1898 key->tex[i].swizzle[2] = sampler->swizzle_b;
1899 key->tex[i].swizzle[3] = sampler->swizzle_a;
1900 key->tex[i].compare_mode = sampler_state->compare_mode;
1901 key->tex[i].compare_func = sampler_state->compare_func;
1902 key->tex[i].wrap_s = sampler_state->wrap_s;
1903 key->tex[i].wrap_t = sampler_state->wrap_t;
1904 }
1905 }
1906 }
1907
1908 static void
1909 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
1910 {
1911 struct vc4_fs_key local_key;
1912 struct vc4_fs_key *key = &local_key;
1913
1914 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
1915 VC4_DIRTY_BLEND |
1916 VC4_DIRTY_FRAMEBUFFER |
1917 VC4_DIRTY_ZSA |
1918 VC4_DIRTY_RASTERIZER |
1919 VC4_DIRTY_FRAGTEX |
1920 VC4_DIRTY_TEXSTATE |
1921 VC4_DIRTY_PROG))) {
1922 return;
1923 }
1924
1925 memset(key, 0, sizeof(*key));
1926 vc4_setup_shared_key(&key->base, &vc4->fragtex);
1927 key->base.shader_state = vc4->prog.bind_fs;
1928 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
1929 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
1930 prim_mode <= PIPE_PRIM_LINE_STRIP);
1931 key->blend = vc4->blend->rt[0];
1932
1933 if (vc4->framebuffer.cbufs[0])
1934 key->color_format = vc4->framebuffer.cbufs[0]->format;
1935
1936 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
1937 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
1938 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
1939 key->depth_enabled = (vc4->zsa->base.depth.enabled ||
1940 key->stencil_enabled);
1941 if (vc4->zsa->base.alpha.enabled) {
1942 key->alpha_test = true;
1943 key->alpha_test_func = vc4->zsa->base.alpha.func;
1944 }
1945
1946 if (key->is_points) {
1947 key->point_sprite_mask =
1948 vc4->rasterizer->base.sprite_coord_enable;
1949 key->point_coord_upper_left =
1950 (vc4->rasterizer->base.sprite_coord_mode ==
1951 PIPE_SPRITE_COORD_UPPER_LEFT);
1952 }
1953
1954 key->light_twoside = vc4->rasterizer->base.light_twoside;
1955
1956 struct vc4_compiled_shader *old_fs = vc4->prog.fs;
1957 vc4->prog.fs = vc4_get_compiled_shader(vc4, QSTAGE_FRAG, &key->base);
1958 if (vc4->prog.fs == old_fs)
1959 return;
1960
1961 if (vc4->rasterizer->base.flatshade &&
1962 old_fs && vc4->prog.fs->color_inputs != old_fs->color_inputs) {
1963 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
1964 }
1965 }
1966
1967 static void
1968 vc4_update_compiled_vs(struct vc4_context *vc4, uint8_t prim_mode)
1969 {
1970 struct vc4_vs_key local_key;
1971 struct vc4_vs_key *key = &local_key;
1972
1973 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
1974 VC4_DIRTY_RASTERIZER |
1975 VC4_DIRTY_VERTTEX |
1976 VC4_DIRTY_TEXSTATE |
1977 VC4_DIRTY_VTXSTATE |
1978 VC4_DIRTY_PROG))) {
1979 return;
1980 }
1981
1982 memset(key, 0, sizeof(*key));
1983 vc4_setup_shared_key(&key->base, &vc4->verttex);
1984 key->base.shader_state = vc4->prog.bind_vs;
1985 key->compiled_fs_id = vc4->prog.fs->program_id;
1986
1987 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
1988 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
1989
1990 key->per_vertex_point_size =
1991 (prim_mode == PIPE_PRIM_POINTS &&
1992 vc4->rasterizer->base.point_size_per_vertex);
1993
1994 vc4->prog.vs = vc4_get_compiled_shader(vc4, QSTAGE_VERT, &key->base);
1995 key->is_coord = true;
1996 vc4->prog.cs = vc4_get_compiled_shader(vc4, QSTAGE_COORD, &key->base);
1997 }
1998
1999 void
2000 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
2001 {
2002 vc4_update_compiled_fs(vc4, prim_mode);
2003 vc4_update_compiled_vs(vc4, prim_mode);
2004 }
2005
2006 static unsigned
2007 fs_cache_hash(void *key)
2008 {
2009 return _mesa_hash_data(key, sizeof(struct vc4_fs_key));
2010 }
2011
2012 static unsigned
2013 vs_cache_hash(void *key)
2014 {
2015 return _mesa_hash_data(key, sizeof(struct vc4_vs_key));
2016 }
2017
2018 static int
2019 fs_cache_compare(void *key1, void *key2)
2020 {
2021 return memcmp(key1, key2, sizeof(struct vc4_fs_key));
2022 }
2023
2024 static int
2025 vs_cache_compare(void *key1, void *key2)
2026 {
2027 return memcmp(key1, key2, sizeof(struct vc4_vs_key));
2028 }
2029
2030 struct delete_state {
2031 struct vc4_context *vc4;
2032 struct vc4_uncompiled_shader *shader_state;
2033 };
2034
2035 static enum pipe_error
2036 fs_delete_from_cache(void *in_key, void *in_value, void *data)
2037 {
2038 struct delete_state *del = data;
2039 struct vc4_fs_key *key = in_key;
2040 struct vc4_compiled_shader *shader = in_value;
2041
2042 if (key->base.shader_state == data) {
2043 util_hash_table_remove(del->vc4->fs_cache, key);
2044 vc4_bo_unreference(&shader->bo);
2045 ralloc_free(shader);
2046 }
2047
2048 return 0;
2049 }
2050
2051 static enum pipe_error
2052 vs_delete_from_cache(void *in_key, void *in_value, void *data)
2053 {
2054 struct delete_state *del = data;
2055 struct vc4_vs_key *key = in_key;
2056 struct vc4_compiled_shader *shader = in_value;
2057
2058 if (key->base.shader_state == data) {
2059 util_hash_table_remove(del->vc4->vs_cache, key);
2060 vc4_bo_unreference(&shader->bo);
2061 ralloc_free(shader);
2062 }
2063
2064 return 0;
2065 }
2066
2067 static void
2068 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
2069 {
2070 struct vc4_context *vc4 = vc4_context(pctx);
2071 struct vc4_uncompiled_shader *so = hwcso;
2072 struct delete_state del;
2073
2074 del.vc4 = vc4;
2075 del.shader_state = so;
2076 util_hash_table_foreach(vc4->fs_cache, fs_delete_from_cache, &del);
2077 util_hash_table_foreach(vc4->vs_cache, vs_delete_from_cache, &del);
2078
2079 if (so->twoside_tokens != so->base.tokens)
2080 free((void *)so->twoside_tokens);
2081 free((void *)so->base.tokens);
2082 free(so);
2083 }
2084
2085 static uint32_t translate_wrap(uint32_t p_wrap, bool using_nearest)
2086 {
2087 switch (p_wrap) {
2088 case PIPE_TEX_WRAP_REPEAT:
2089 return 0;
2090 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
2091 return 1;
2092 case PIPE_TEX_WRAP_MIRROR_REPEAT:
2093 return 2;
2094 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
2095 return 3;
2096 case PIPE_TEX_WRAP_CLAMP:
2097 return (using_nearest ? 1 : 3);
2098 default:
2099 fprintf(stderr, "Unknown wrap mode %d\n", p_wrap);
2100 assert(!"not reached");
2101 return 0;
2102 }
2103 }
2104
2105 static void
2106 write_texture_p0(struct vc4_context *vc4,
2107 struct vc4_texture_stateobj *texstate,
2108 uint32_t unit)
2109 {
2110 struct pipe_sampler_view *texture = texstate->textures[unit];
2111 struct vc4_resource *rsc = vc4_resource(texture->texture);
2112
2113 cl_reloc(vc4, &vc4->uniforms, rsc->bo,
2114 VC4_SET_FIELD(rsc->slices[0].offset >> 12, VC4_TEX_P0_OFFSET) |
2115 VC4_SET_FIELD(texture->u.tex.last_level, VC4_TEX_P0_MIPLVLS) |
2116 VC4_SET_FIELD(texture->target == PIPE_TEXTURE_CUBE,
2117 VC4_TEX_P0_CMMODE) |
2118 VC4_SET_FIELD(rsc->vc4_format & 7, VC4_TEX_P0_TYPE));
2119 }
2120
2121 static void
2122 write_texture_p1(struct vc4_context *vc4,
2123 struct vc4_texture_stateobj *texstate,
2124 uint32_t unit)
2125 {
2126 struct pipe_sampler_view *texture = texstate->textures[unit];
2127 struct vc4_resource *rsc = vc4_resource(texture->texture);
2128 struct pipe_sampler_state *sampler = texstate->samplers[unit];
2129 static const uint8_t minfilter_map[6] = {
2130 VC4_TEX_P1_MINFILT_NEAR_MIP_NEAR,
2131 VC4_TEX_P1_MINFILT_LIN_MIP_NEAR,
2132 VC4_TEX_P1_MINFILT_NEAR_MIP_LIN,
2133 VC4_TEX_P1_MINFILT_LIN_MIP_LIN,
2134 VC4_TEX_P1_MINFILT_NEAREST,
2135 VC4_TEX_P1_MINFILT_LINEAR,
2136 };
2137 static const uint32_t magfilter_map[] = {
2138 [PIPE_TEX_FILTER_NEAREST] = VC4_TEX_P1_MAGFILT_NEAREST,
2139 [PIPE_TEX_FILTER_LINEAR] = VC4_TEX_P1_MAGFILT_LINEAR,
2140 };
2141
2142 bool either_nearest =
2143 (sampler->mag_img_filter == PIPE_TEX_MIPFILTER_NEAREST ||
2144 sampler->min_img_filter == PIPE_TEX_MIPFILTER_NEAREST);
2145
2146 cl_u32(&vc4->uniforms,
2147 VC4_SET_FIELD(rsc->vc4_format >> 4, VC4_TEX_P1_TYPE4) |
2148 VC4_SET_FIELD(texture->texture->height0 & 2047,
2149 VC4_TEX_P1_HEIGHT) |
2150 VC4_SET_FIELD(texture->texture->width0 & 2047,
2151 VC4_TEX_P1_WIDTH) |
2152 VC4_SET_FIELD(magfilter_map[sampler->mag_img_filter],
2153 VC4_TEX_P1_MAGFILT) |
2154 VC4_SET_FIELD(minfilter_map[sampler->min_mip_filter * 2 +
2155 sampler->min_img_filter],
2156 VC4_TEX_P1_MINFILT) |
2157 VC4_SET_FIELD(translate_wrap(sampler->wrap_s, either_nearest),
2158 VC4_TEX_P1_WRAP_S) |
2159 VC4_SET_FIELD(translate_wrap(sampler->wrap_t, either_nearest),
2160 VC4_TEX_P1_WRAP_T));
2161 }
2162
2163 static void
2164 write_texture_p2(struct vc4_context *vc4,
2165 struct vc4_texture_stateobj *texstate,
2166 uint32_t unit)
2167 {
2168 struct pipe_sampler_view *texture = texstate->textures[unit];
2169 struct vc4_resource *rsc = vc4_resource(texture->texture);
2170
2171 cl_u32(&vc4->uniforms,
2172 VC4_SET_FIELD(VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE,
2173 VC4_TEX_P2_PTYPE) |
2174 VC4_SET_FIELD(rsc->cube_map_stride >> 12, VC4_TEX_P2_CMST));
2175 }
2176
2177
2178 #define SWIZ(x,y,z,w) { \
2179 UTIL_FORMAT_SWIZZLE_##x, \
2180 UTIL_FORMAT_SWIZZLE_##y, \
2181 UTIL_FORMAT_SWIZZLE_##z, \
2182 UTIL_FORMAT_SWIZZLE_##w \
2183 }
2184
2185 static void
2186 write_texture_border_color(struct vc4_context *vc4,
2187 struct vc4_texture_stateobj *texstate,
2188 uint32_t unit)
2189 {
2190 struct pipe_sampler_state *sampler = texstate->samplers[unit];
2191 struct pipe_sampler_view *texture = texstate->textures[unit];
2192 struct vc4_resource *rsc = vc4_resource(texture->texture);
2193 union util_color uc;
2194
2195 const struct util_format_description *tex_format_desc =
2196 util_format_description(texture->format);
2197
2198 float border_color[4];
2199 for (int i = 0; i < 4; i++)
2200 border_color[i] = sampler->border_color.f[i];
2201 if (util_format_is_srgb(texture->format)) {
2202 for (int i = 0; i < 3; i++)
2203 border_color[i] =
2204 util_format_linear_to_srgb_float(border_color[i]);
2205 }
2206
2207 /* Turn the border color into the layout of channels that it would
2208 * have when stored as texture contents.
2209 */
2210 float storage_color[4];
2211 util_format_unswizzle_4f(storage_color,
2212 border_color,
2213 tex_format_desc->swizzle);
2214
2215 /* Now, pack so that when the vc4_format-sampled texture contents are
2216 * replaced with our border color, the vc4_get_format_swizzle()
2217 * swizzling will get the right channels.
2218 */
2219 if (util_format_is_depth_or_stencil(texture->format)) {
2220 uc.ui[0] = util_pack_z(PIPE_FORMAT_Z24X8_UNORM,
2221 sampler->border_color.f[0]) << 8;
2222 } else {
2223 switch (rsc->vc4_format) {
2224 default:
2225 case VC4_TEXTURE_TYPE_RGBA8888:
2226 util_pack_color(storage_color,
2227 PIPE_FORMAT_R8G8B8A8_UNORM, &uc);
2228 break;
2229 case VC4_TEXTURE_TYPE_RGBA4444:
2230 util_pack_color(storage_color,
2231 PIPE_FORMAT_A8B8G8R8_UNORM, &uc);
2232 break;
2233 case VC4_TEXTURE_TYPE_RGB565:
2234 util_pack_color(storage_color,
2235 PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
2236 break;
2237 case VC4_TEXTURE_TYPE_ALPHA:
2238 uc.ui[0] = float_to_ubyte(storage_color[0]) << 24;
2239 break;
2240 case VC4_TEXTURE_TYPE_LUMALPHA:
2241 uc.ui[0] = ((float_to_ubyte(storage_color[1]) << 24) |
2242 (float_to_ubyte(storage_color[0]) << 0));
2243 break;
2244 }
2245 }
2246
2247 cl_u32(&vc4->uniforms, uc.ui[0]);
2248 }
2249
2250 static uint32_t
2251 get_texrect_scale(struct vc4_texture_stateobj *texstate,
2252 enum quniform_contents contents,
2253 uint32_t data)
2254 {
2255 struct pipe_sampler_view *texture = texstate->textures[data];
2256 uint32_t dim;
2257
2258 if (contents == QUNIFORM_TEXRECT_SCALE_X)
2259 dim = texture->texture->width0;
2260 else
2261 dim = texture->texture->height0;
2262
2263 return fui(1.0f / dim);
2264 }
2265
2266 void
2267 vc4_write_uniforms(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
2268 struct vc4_constbuf_stateobj *cb,
2269 struct vc4_texture_stateobj *texstate)
2270 {
2271 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
2272 const uint32_t *gallium_uniforms = cb->cb[0].user_buffer;
2273
2274 cl_start_shader_reloc(&vc4->uniforms, uinfo->num_texture_samples);
2275
2276 for (int i = 0; i < uinfo->count; i++) {
2277
2278 switch (uinfo->contents[i]) {
2279 case QUNIFORM_CONSTANT:
2280 cl_u32(&vc4->uniforms, uinfo->data[i]);
2281 break;
2282 case QUNIFORM_UNIFORM:
2283 cl_u32(&vc4->uniforms,
2284 gallium_uniforms[uinfo->data[i]]);
2285 break;
2286 case QUNIFORM_VIEWPORT_X_SCALE:
2287 cl_f(&vc4->uniforms, vc4->viewport.scale[0] * 16.0f);
2288 break;
2289 case QUNIFORM_VIEWPORT_Y_SCALE:
2290 cl_f(&vc4->uniforms, vc4->viewport.scale[1] * 16.0f);
2291 break;
2292
2293 case QUNIFORM_VIEWPORT_Z_OFFSET:
2294 cl_f(&vc4->uniforms, vc4->viewport.translate[2]);
2295 break;
2296 case QUNIFORM_VIEWPORT_Z_SCALE:
2297 cl_f(&vc4->uniforms, vc4->viewport.scale[2]);
2298 break;
2299
2300 case QUNIFORM_TEXTURE_CONFIG_P0:
2301 write_texture_p0(vc4, texstate, uinfo->data[i]);
2302 break;
2303
2304 case QUNIFORM_TEXTURE_CONFIG_P1:
2305 write_texture_p1(vc4, texstate, uinfo->data[i]);
2306 break;
2307
2308 case QUNIFORM_TEXTURE_CONFIG_P2:
2309 write_texture_p2(vc4, texstate, uinfo->data[i]);
2310 break;
2311
2312 case QUNIFORM_TEXTURE_BORDER_COLOR:
2313 write_texture_border_color(vc4, texstate, uinfo->data[i]);
2314 break;
2315
2316 case QUNIFORM_TEXRECT_SCALE_X:
2317 case QUNIFORM_TEXRECT_SCALE_Y:
2318 cl_u32(&vc4->uniforms,
2319 get_texrect_scale(texstate,
2320 uinfo->contents[i],
2321 uinfo->data[i]));
2322 break;
2323
2324 case QUNIFORM_BLEND_CONST_COLOR:
2325 cl_f(&vc4->uniforms,
2326 vc4->blend_color.color[uinfo->data[i]]);
2327 break;
2328
2329 case QUNIFORM_STENCIL:
2330 cl_u32(&vc4->uniforms,
2331 vc4->zsa->stencil_uniforms[uinfo->data[i]] |
2332 (uinfo->data[i] <= 1 ?
2333 (vc4->stencil_ref.ref_value[uinfo->data[i]] << 8) :
2334 0));
2335 break;
2336
2337 case QUNIFORM_ALPHA_REF:
2338 cl_f(&vc4->uniforms, vc4->zsa->base.alpha.ref_value);
2339 break;
2340 }
2341 #if 0
2342 uint32_t written_val = *(uint32_t *)(vc4->uniforms.next - 4);
2343 fprintf(stderr, "%p/%d: %d: 0x%08x (%f)\n",
2344 shader, i, written_val, uif(written_val));
2345 #endif
2346 }
2347 }
2348
2349 static void
2350 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
2351 {
2352 struct vc4_context *vc4 = vc4_context(pctx);
2353 vc4->prog.bind_fs = hwcso;
2354 vc4->prog.dirty |= VC4_SHADER_DIRTY_FP;
2355 vc4->dirty |= VC4_DIRTY_PROG;
2356 }
2357
2358 static void
2359 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
2360 {
2361 struct vc4_context *vc4 = vc4_context(pctx);
2362 vc4->prog.bind_vs = hwcso;
2363 vc4->prog.dirty |= VC4_SHADER_DIRTY_VP;
2364 vc4->dirty |= VC4_DIRTY_PROG;
2365 }
2366
2367 void
2368 vc4_program_init(struct pipe_context *pctx)
2369 {
2370 struct vc4_context *vc4 = vc4_context(pctx);
2371
2372 pctx->create_vs_state = vc4_shader_state_create;
2373 pctx->delete_vs_state = vc4_shader_state_delete;
2374
2375 pctx->create_fs_state = vc4_shader_state_create;
2376 pctx->delete_fs_state = vc4_shader_state_delete;
2377
2378 pctx->bind_fs_state = vc4_fp_state_bind;
2379 pctx->bind_vs_state = vc4_vp_state_bind;
2380
2381 vc4->fs_cache = util_hash_table_create(fs_cache_hash, fs_cache_compare);
2382 vc4->vs_cache = util_hash_table_create(vs_cache_hash, vs_cache_compare);
2383 }