2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "pipe/p_state.h"
27 #include "util/u_format.h"
28 #include "util/u_hash_table.h"
29 #include "util/u_hash.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include "util/format_srgb.h"
33 #include "util/ralloc.h"
34 #include "tgsi/tgsi_dump.h"
35 #include "tgsi/tgsi_info.h"
36 #include "tgsi/tgsi_lowering.h"
38 #include "vc4_context.h"
41 #ifdef USE_VC4_SIMULATOR
42 #include "simpenrose/simpenrose.h"
46 struct vc4_uncompiled_shader
*shader_state
;
48 enum pipe_format format
;
49 unsigned compare_mode
:1;
50 unsigned compare_func
:3;
54 } tex
[VC4_MAX_TEXTURE_SAMPLERS
];
59 enum pipe_format color_format
;
63 bool stencil_full_writemasks
;
67 bool point_coord_upper_left
;
69 uint8_t alpha_test_func
;
70 uint32_t point_sprite_mask
;
72 struct pipe_rt_blend_state blend
;
77 enum pipe_format attr_formats
[8];
78 bool per_vertex_point_size
;
82 resize_qreg_array(struct vc4_compile
*c
,
87 if (*size
>= decl_size
)
90 uint32_t old_size
= *size
;
91 *size
= MAX2(*size
* 2, decl_size
);
92 *regs
= reralloc(c
, *regs
, struct qreg
, *size
);
94 fprintf(stderr
, "Malloc failure\n");
98 for (uint32_t i
= old_size
; i
< *size
; i
++)
99 (*regs
)[i
] = c
->undef
;
103 add_uniform(struct vc4_compile
*c
,
104 enum quniform_contents contents
,
107 uint32_t uniform
= c
->num_uniforms
++;
108 struct qreg u
= { QFILE_UNIF
, uniform
};
110 if (uniform
>= c
->uniform_array_size
) {
111 c
->uniform_array_size
= MAX2(MAX2(16, uniform
+ 1),
112 c
->uniform_array_size
* 2);
114 c
->uniform_data
= reralloc(c
, c
->uniform_data
,
116 c
->uniform_array_size
);
117 c
->uniform_contents
= reralloc(c
, c
->uniform_contents
,
118 enum quniform_contents
,
119 c
->uniform_array_size
);
122 c
->uniform_contents
[uniform
] = contents
;
123 c
->uniform_data
[uniform
] = data
;
129 get_temp_for_uniform(struct vc4_compile
*c
, enum quniform_contents contents
,
132 struct qreg u
= add_uniform(c
, contents
, data
);
133 struct qreg t
= qir_MOV(c
, u
);
138 qir_uniform_ui(struct vc4_compile
*c
, uint32_t ui
)
140 return get_temp_for_uniform(c
, QUNIFORM_CONSTANT
, ui
);
144 qir_uniform_f(struct vc4_compile
*c
, float f
)
146 return qir_uniform_ui(c
, fui(f
));
150 get_src(struct vc4_compile
*c
, unsigned tgsi_op
,
151 struct tgsi_src_register
*src
, int i
)
153 struct qreg r
= c
->undef
;
173 assert(!src
->Indirect
);
178 case TGSI_FILE_TEMPORARY
:
179 r
= c
->temps
[src
->Index
* 4 + s
];
181 case TGSI_FILE_IMMEDIATE
:
182 r
= c
->consts
[src
->Index
* 4 + s
];
184 case TGSI_FILE_CONSTANT
:
185 r
= get_temp_for_uniform(c
, QUNIFORM_UNIFORM
,
188 case TGSI_FILE_INPUT
:
189 r
= c
->inputs
[src
->Index
* 4 + s
];
191 case TGSI_FILE_SAMPLER
:
192 case TGSI_FILE_SAMPLER_VIEW
:
196 fprintf(stderr
, "unknown src file %d\n", src
->File
);
201 r
= qir_FMAXABS(c
, r
, r
);
204 switch (tgsi_opcode_infer_src_type(tgsi_op
)) {
205 case TGSI_TYPE_SIGNED
:
206 case TGSI_TYPE_UNSIGNED
:
207 r
= qir_SUB(c
, qir_uniform_ui(c
, 0), r
);
210 r
= qir_FSUB(c
, qir_uniform_f(c
, 0.0), r
);
220 update_dst(struct vc4_compile
*c
, struct tgsi_full_instruction
*tgsi_inst
,
221 int i
, struct qreg val
)
223 struct tgsi_dst_register
*tgsi_dst
= &tgsi_inst
->Dst
[0].Register
;
225 assert(!tgsi_dst
->Indirect
);
227 switch (tgsi_dst
->File
) {
228 case TGSI_FILE_TEMPORARY
:
229 c
->temps
[tgsi_dst
->Index
* 4 + i
] = val
;
231 case TGSI_FILE_OUTPUT
:
232 c
->outputs
[tgsi_dst
->Index
* 4 + i
] = val
;
233 c
->num_outputs
= MAX2(c
->num_outputs
,
234 tgsi_dst
->Index
* 4 + i
+ 1);
237 fprintf(stderr
, "unknown dst file %d\n", tgsi_dst
->File
);
243 get_swizzled_channel(struct vc4_compile
*c
,
244 struct qreg
*srcs
, int swiz
)
248 case UTIL_FORMAT_SWIZZLE_NONE
:
249 fprintf(stderr
, "warning: unknown swizzle\n");
251 case UTIL_FORMAT_SWIZZLE_0
:
252 return qir_uniform_f(c
, 0.0);
253 case UTIL_FORMAT_SWIZZLE_1
:
254 return qir_uniform_f(c
, 1.0);
255 case UTIL_FORMAT_SWIZZLE_X
:
256 case UTIL_FORMAT_SWIZZLE_Y
:
257 case UTIL_FORMAT_SWIZZLE_Z
:
258 case UTIL_FORMAT_SWIZZLE_W
:
264 tgsi_to_qir_alu(struct vc4_compile
*c
,
265 struct tgsi_full_instruction
*tgsi_inst
,
266 enum qop op
, struct qreg
*src
, int i
)
268 struct qreg dst
= qir_get_temp(c
);
269 qir_emit(c
, qir_inst4(op
, dst
,
278 tgsi_to_qir_scalar(struct vc4_compile
*c
,
279 struct tgsi_full_instruction
*tgsi_inst
,
280 enum qop op
, struct qreg
*src
, int i
)
282 struct qreg dst
= qir_get_temp(c
);
283 qir_emit(c
, qir_inst(op
, dst
,
290 qir_srgb_decode(struct vc4_compile
*c
, struct qreg srgb
)
292 struct qreg low
= qir_FMUL(c
, srgb
, qir_uniform_f(c
, 1.0 / 12.92));
293 struct qreg high
= qir_POW(c
,
297 qir_uniform_f(c
, 0.055)),
298 qir_uniform_f(c
, 1.0 / 1.055)),
299 qir_uniform_f(c
, 2.4));
301 qir_SF(c
, qir_FSUB(c
, srgb
, qir_uniform_f(c
, 0.04045)));
302 return qir_SEL_X_Y_NS(c
, low
, high
);
306 qir_srgb_encode(struct vc4_compile
*c
, struct qreg linear
)
308 struct qreg low
= qir_FMUL(c
, linear
, qir_uniform_f(c
, 12.92));
309 struct qreg high
= qir_FSUB(c
,
311 qir_uniform_f(c
, 1.055),
314 qir_uniform_f(c
, 0.41666))),
315 qir_uniform_f(c
, 0.055));
317 qir_SF(c
, qir_FSUB(c
, linear
, qir_uniform_f(c
, 0.0031308)));
318 return qir_SEL_X_Y_NS(c
, low
, high
);
322 tgsi_to_qir_umul(struct vc4_compile
*c
,
323 struct tgsi_full_instruction
*tgsi_inst
,
324 enum qop op
, struct qreg
*src
, int i
)
326 struct qreg src0_hi
= qir_SHR(c
, src
[0 * 4 + i
],
327 qir_uniform_ui(c
, 16));
328 struct qreg src0_lo
= qir_AND(c
, src
[0 * 4 + i
],
329 qir_uniform_ui(c
, 0xffff));
330 struct qreg src1_hi
= qir_SHR(c
, src
[1 * 4 + i
],
331 qir_uniform_ui(c
, 16));
332 struct qreg src1_lo
= qir_AND(c
, src
[1 * 4 + i
],
333 qir_uniform_ui(c
, 0xffff));
335 struct qreg hilo
= qir_MUL24(c
, src0_hi
, src1_lo
);
336 struct qreg lohi
= qir_MUL24(c
, src0_lo
, src1_hi
);
337 struct qreg lolo
= qir_MUL24(c
, src0_lo
, src1_lo
);
339 return qir_ADD(c
, lolo
, qir_SHL(c
,
340 qir_ADD(c
, hilo
, lohi
),
341 qir_uniform_ui(c
, 16)));
345 tgsi_to_qir_idiv(struct vc4_compile
*c
,
346 struct tgsi_full_instruction
*tgsi_inst
,
347 enum qop op
, struct qreg
*src
, int i
)
349 return qir_FTOI(c
, qir_FMUL(c
,
350 qir_ITOF(c
, src
[0 * 4 + i
]),
351 qir_RCP(c
, qir_ITOF(c
, src
[1 * 4 + i
]))));
355 tgsi_to_qir_ineg(struct vc4_compile
*c
,
356 struct tgsi_full_instruction
*tgsi_inst
,
357 enum qop op
, struct qreg
*src
, int i
)
359 return qir_SUB(c
, qir_uniform_ui(c
, 0), src
[0 * 4 + i
]);
363 tgsi_to_qir_seq(struct vc4_compile
*c
,
364 struct tgsi_full_instruction
*tgsi_inst
,
365 enum qop op
, struct qreg
*src
, int i
)
367 qir_SF(c
, qir_FSUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
368 return qir_SEL_X_0_ZS(c
, qir_uniform_f(c
, 1.0));
372 tgsi_to_qir_sne(struct vc4_compile
*c
,
373 struct tgsi_full_instruction
*tgsi_inst
,
374 enum qop op
, struct qreg
*src
, int i
)
376 qir_SF(c
, qir_FSUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
377 return qir_SEL_X_0_ZC(c
, qir_uniform_f(c
, 1.0));
381 tgsi_to_qir_slt(struct vc4_compile
*c
,
382 struct tgsi_full_instruction
*tgsi_inst
,
383 enum qop op
, struct qreg
*src
, int i
)
385 qir_SF(c
, qir_FSUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
386 return qir_SEL_X_0_NS(c
, qir_uniform_f(c
, 1.0));
390 tgsi_to_qir_sge(struct vc4_compile
*c
,
391 struct tgsi_full_instruction
*tgsi_inst
,
392 enum qop op
, struct qreg
*src
, int i
)
394 qir_SF(c
, qir_FSUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
395 return qir_SEL_X_0_NC(c
, qir_uniform_f(c
, 1.0));
399 tgsi_to_qir_fseq(struct vc4_compile
*c
,
400 struct tgsi_full_instruction
*tgsi_inst
,
401 enum qop op
, struct qreg
*src
, int i
)
403 qir_SF(c
, qir_FSUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
404 return qir_SEL_X_0_ZS(c
, qir_uniform_ui(c
, ~0));
408 tgsi_to_qir_fsne(struct vc4_compile
*c
,
409 struct tgsi_full_instruction
*tgsi_inst
,
410 enum qop op
, struct qreg
*src
, int i
)
412 qir_SF(c
, qir_FSUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
413 return qir_SEL_X_0_ZC(c
, qir_uniform_ui(c
, ~0));
417 tgsi_to_qir_fslt(struct vc4_compile
*c
,
418 struct tgsi_full_instruction
*tgsi_inst
,
419 enum qop op
, struct qreg
*src
, int i
)
421 qir_SF(c
, qir_FSUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
422 return qir_SEL_X_0_NS(c
, qir_uniform_ui(c
, ~0));
426 tgsi_to_qir_fsge(struct vc4_compile
*c
,
427 struct tgsi_full_instruction
*tgsi_inst
,
428 enum qop op
, struct qreg
*src
, int i
)
430 qir_SF(c
, qir_FSUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
431 return qir_SEL_X_0_NC(c
, qir_uniform_ui(c
, ~0));
435 tgsi_to_qir_useq(struct vc4_compile
*c
,
436 struct tgsi_full_instruction
*tgsi_inst
,
437 enum qop op
, struct qreg
*src
, int i
)
439 qir_SF(c
, qir_SUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
440 return qir_SEL_X_0_ZS(c
, qir_uniform_ui(c
, ~0));
444 tgsi_to_qir_usne(struct vc4_compile
*c
,
445 struct tgsi_full_instruction
*tgsi_inst
,
446 enum qop op
, struct qreg
*src
, int i
)
448 qir_SF(c
, qir_SUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
449 return qir_SEL_X_0_ZC(c
, qir_uniform_ui(c
, ~0));
453 tgsi_to_qir_islt(struct vc4_compile
*c
,
454 struct tgsi_full_instruction
*tgsi_inst
,
455 enum qop op
, struct qreg
*src
, int i
)
457 qir_SF(c
, qir_SUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
458 return qir_SEL_X_0_NS(c
, qir_uniform_ui(c
, ~0));
462 tgsi_to_qir_isge(struct vc4_compile
*c
,
463 struct tgsi_full_instruction
*tgsi_inst
,
464 enum qop op
, struct qreg
*src
, int i
)
466 qir_SF(c
, qir_SUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
467 return qir_SEL_X_0_NC(c
, qir_uniform_ui(c
, ~0));
471 tgsi_to_qir_cmp(struct vc4_compile
*c
,
472 struct tgsi_full_instruction
*tgsi_inst
,
473 enum qop op
, struct qreg
*src
, int i
)
475 qir_SF(c
, src
[0 * 4 + i
]);
476 return qir_SEL_X_Y_NS(c
,
482 tgsi_to_qir_mad(struct vc4_compile
*c
,
483 struct tgsi_full_instruction
*tgsi_inst
,
484 enum qop op
, struct qreg
*src
, int i
)
494 tgsi_to_qir_lrp(struct vc4_compile
*c
,
495 struct tgsi_full_instruction
*tgsi_inst
,
496 enum qop op
, struct qreg
*src
, int i
)
498 struct qreg src0
= src
[0 * 4 + i
];
499 struct qreg src1
= src
[1 * 4 + i
];
500 struct qreg src2
= src
[2 * 4 + i
];
503 * src0 * src1 + (1 - src0) * src2.
504 * -> src0 * src1 + src2 - src0 * src2
505 * -> src2 + src0 * (src1 - src2)
507 return qir_FADD(c
, src2
, qir_FMUL(c
, src0
, qir_FSUB(c
, src1
, src2
)));
512 tgsi_to_qir_tex(struct vc4_compile
*c
,
513 struct tgsi_full_instruction
*tgsi_inst
,
514 enum qop op
, struct qreg
*src
)
516 assert(!tgsi_inst
->Instruction
.Saturate
);
518 struct qreg s
= src
[0 * 4 + 0];
519 struct qreg t
= src
[0 * 4 + 1];
520 struct qreg r
= src
[0 * 4 + 2];
521 uint32_t unit
= tgsi_inst
->Src
[1].Register
.Index
;
523 struct qreg proj
= c
->undef
;
524 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXP
) {
525 proj
= qir_RCP(c
, src
[0 * 4 + 3]);
526 s
= qir_FMUL(c
, s
, proj
);
527 t
= qir_FMUL(c
, t
, proj
);
530 struct qreg texture_u
[] = {
531 add_uniform(c
, QUNIFORM_TEXTURE_CONFIG_P0
, unit
),
532 add_uniform(c
, QUNIFORM_TEXTURE_CONFIG_P1
, unit
),
533 add_uniform(c
, QUNIFORM_CONSTANT
, 0),
534 add_uniform(c
, QUNIFORM_CONSTANT
, 0),
536 uint32_t next_texture_u
= 0;
538 /* There is no native support for GL texture rectangle coordinates, so
539 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
542 if (tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_RECT
||
543 tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWRECT
) {
545 get_temp_for_uniform(c
,
546 QUNIFORM_TEXRECT_SCALE_X
,
549 get_temp_for_uniform(c
,
550 QUNIFORM_TEXRECT_SCALE_Y
,
554 if (tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE
||
555 tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
) {
556 struct qreg ma
= qir_FMAXABS(c
, qir_FMAXABS(c
, s
, t
), r
);
557 struct qreg rcp_ma
= qir_RCP(c
, ma
);
558 s
= qir_FMUL(c
, s
, rcp_ma
);
559 t
= qir_FMUL(c
, t
, rcp_ma
);
560 r
= qir_FMUL(c
, r
, rcp_ma
);
562 texture_u
[2] = add_uniform(c
, QUNIFORM_TEXTURE_CONFIG_P2
, unit
);
564 qir_TEX_R(c
, r
, texture_u
[next_texture_u
++]);
565 } else if (c
->key
->tex
[unit
].wrap_s
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
566 c
->key
->tex
[unit
].wrap_s
== PIPE_TEX_WRAP_CLAMP
||
567 c
->key
->tex
[unit
].wrap_t
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
568 c
->key
->tex
[unit
].wrap_t
== PIPE_TEX_WRAP_CLAMP
) {
569 qir_TEX_R(c
, get_temp_for_uniform(c
, QUNIFORM_TEXTURE_BORDER_COLOR
, unit
),
570 texture_u
[next_texture_u
++]);
573 if (c
->key
->tex
[unit
].wrap_s
== PIPE_TEX_WRAP_CLAMP
) {
574 s
= qir_FMIN(c
, qir_FMAX(c
, s
, qir_uniform_f(c
, 0.0)),
575 qir_uniform_f(c
, 1.0));
578 if (c
->key
->tex
[unit
].wrap_t
== PIPE_TEX_WRAP_CLAMP
) {
579 t
= qir_FMIN(c
, qir_FMAX(c
, t
, qir_uniform_f(c
, 0.0)),
580 qir_uniform_f(c
, 1.0));
583 qir_TEX_T(c
, t
, texture_u
[next_texture_u
++]);
585 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB
)
586 qir_TEX_B(c
, src
[0 * 4 + 3], texture_u
[next_texture_u
++]);
588 qir_TEX_S(c
, s
, texture_u
[next_texture_u
++]);
590 c
->num_texture_samples
++;
591 struct qreg r4
= qir_TEX_RESULT(c
);
593 enum pipe_format format
= c
->key
->tex
[unit
].format
;
595 struct qreg unpacked
[4];
596 if (util_format_is_depth_or_stencil(format
)) {
597 struct qreg depthf
= qir_ITOF(c
, qir_SHR(c
, r4
,
598 qir_uniform_ui(c
, 8)));
599 struct qreg normalized
= qir_FMUL(c
, depthf
,
600 qir_uniform_f(c
, 1.0f
/0xffffff));
602 struct qreg depth_output
;
604 struct qreg one
= qir_uniform_f(c
, 1.0f
);
605 if (c
->key
->tex
[unit
].compare_mode
) {
606 struct qreg compare
= src
[0 * 4 + 2];
608 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXP
)
609 compare
= qir_FMUL(c
, compare
, proj
);
611 switch (c
->key
->tex
[unit
].compare_func
) {
612 case PIPE_FUNC_NEVER
:
613 depth_output
= qir_uniform_f(c
, 0.0f
);
615 case PIPE_FUNC_ALWAYS
:
618 case PIPE_FUNC_EQUAL
:
619 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
620 depth_output
= qir_SEL_X_0_ZS(c
, one
);
622 case PIPE_FUNC_NOTEQUAL
:
623 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
624 depth_output
= qir_SEL_X_0_ZC(c
, one
);
626 case PIPE_FUNC_GREATER
:
627 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
628 depth_output
= qir_SEL_X_0_NC(c
, one
);
630 case PIPE_FUNC_GEQUAL
:
631 qir_SF(c
, qir_FSUB(c
, normalized
, compare
));
632 depth_output
= qir_SEL_X_0_NS(c
, one
);
635 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
636 depth_output
= qir_SEL_X_0_NS(c
, one
);
638 case PIPE_FUNC_LEQUAL
:
639 qir_SF(c
, qir_FSUB(c
, normalized
, compare
));
640 depth_output
= qir_SEL_X_0_NC(c
, one
);
644 depth_output
= normalized
;
647 for (int i
= 0; i
< 4; i
++)
648 unpacked
[i
] = depth_output
;
650 for (int i
= 0; i
< 4; i
++)
651 unpacked
[i
] = qir_R4_UNPACK(c
, r4
, i
);
654 const uint8_t *format_swiz
= vc4_get_format_swizzle(format
);
655 struct qreg texture_output
[4];
656 for (int i
= 0; i
< 4; i
++) {
657 texture_output
[i
] = get_swizzled_channel(c
, unpacked
,
661 if (util_format_is_srgb(format
)) {
662 for (int i
= 0; i
< 3; i
++)
663 texture_output
[i
] = qir_srgb_decode(c
,
667 for (int i
= 0; i
< 4; i
++) {
668 if (!(tgsi_inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
671 update_dst(c
, tgsi_inst
, i
,
672 get_swizzled_channel(c
, texture_output
,
673 c
->key
->tex
[unit
].swizzle
[i
]));
678 tgsi_to_qir_trunc(struct vc4_compile
*c
,
679 struct tgsi_full_instruction
*tgsi_inst
,
680 enum qop op
, struct qreg
*src
, int i
)
682 return qir_ITOF(c
, qir_FTOI(c
, src
[0 * 4 + i
]));
686 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
690 tgsi_to_qir_frc(struct vc4_compile
*c
,
691 struct tgsi_full_instruction
*tgsi_inst
,
692 enum qop op
, struct qreg
*src
, int i
)
694 struct qreg trunc
= qir_ITOF(c
, qir_FTOI(c
, src
[0 * 4 + i
]));
695 struct qreg diff
= qir_FSUB(c
, src
[0 * 4 + i
], trunc
);
697 return qir_SEL_X_Y_NS(c
,
698 qir_FADD(c
, diff
, qir_uniform_f(c
, 1.0)),
703 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
707 tgsi_to_qir_flr(struct vc4_compile
*c
,
708 struct tgsi_full_instruction
*tgsi_inst
,
709 enum qop op
, struct qreg
*src
, int i
)
711 struct qreg trunc
= qir_ITOF(c
, qir_FTOI(c
, src
[0 * 4 + i
]));
713 /* This will be < 0 if we truncated and the truncation was of a value
714 * that was < 0 in the first place.
716 qir_SF(c
, qir_FSUB(c
, src
[0 * 4 + i
], trunc
));
718 return qir_SEL_X_Y_NS(c
,
719 qir_FSUB(c
, trunc
, qir_uniform_f(c
, 1.0)),
724 tgsi_to_qir_abs(struct vc4_compile
*c
,
725 struct tgsi_full_instruction
*tgsi_inst
,
726 enum qop op
, struct qreg
*src
, int i
)
728 struct qreg arg
= src
[0 * 4 + i
];
729 return qir_FMAXABS(c
, arg
, arg
);
732 /* Note that this instruction replicates its result from the x channel */
734 tgsi_to_qir_sin(struct vc4_compile
*c
,
735 struct tgsi_full_instruction
*tgsi_inst
,
736 enum qop op
, struct qreg
*src
, int i
)
740 -pow(2.0 * M_PI
, 3) / (3 * 2 * 1),
741 pow(2.0 * M_PI
, 5) / (5 * 4 * 3 * 2 * 1),
742 -pow(2.0 * M_PI
, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
745 struct qreg scaled_x
=
748 qir_uniform_f(c
, 1.0f
/ (M_PI
* 2.0f
)));
751 struct qreg x
= tgsi_to_qir_frc(c
, NULL
, 0, &scaled_x
, 0);
752 struct qreg x2
= qir_FMUL(c
, x
, x
);
753 struct qreg sum
= qir_FMUL(c
, x
, qir_uniform_f(c
, coeff
[0]));
754 for (int i
= 1; i
< ARRAY_SIZE(coeff
); i
++) {
755 x
= qir_FMUL(c
, x
, x2
);
760 qir_uniform_f(c
, coeff
[i
])));
765 /* Note that this instruction replicates its result from the x channel */
767 tgsi_to_qir_cos(struct vc4_compile
*c
,
768 struct tgsi_full_instruction
*tgsi_inst
,
769 enum qop op
, struct qreg
*src
, int i
)
773 -pow(2.0 * M_PI
, 2) / (2 * 1),
774 pow(2.0 * M_PI
, 4) / (4 * 3 * 2 * 1),
775 -pow(2.0 * M_PI
, 6) / (6 * 5 * 4 * 3 * 2 * 1),
778 struct qreg scaled_x
=
779 qir_FMUL(c
, src
[0 * 4 + 0],
780 qir_uniform_f(c
, 1.0f
/ (M_PI
* 2.0f
)));
781 struct qreg x_frac
= tgsi_to_qir_frc(c
, NULL
, 0, &scaled_x
, 0);
783 struct qreg sum
= qir_uniform_f(c
, coeff
[0]);
784 struct qreg x2
= qir_FMUL(c
, x_frac
, x_frac
);
785 struct qreg x
= x2
; /* Current x^2, x^4, or x^6 */
786 for (int i
= 1; i
< ARRAY_SIZE(coeff
); i
++) {
788 x
= qir_FMUL(c
, x
, x2
);
790 struct qreg mul
= qir_FMUL(c
,
792 qir_uniform_f(c
, coeff
[i
]));
796 sum
= qir_FADD(c
, sum
, mul
);
802 tgsi_to_qir_clamp(struct vc4_compile
*c
,
803 struct tgsi_full_instruction
*tgsi_inst
,
804 enum qop op
, struct qreg
*src
, int i
)
806 return qir_FMAX(c
, qir_FMIN(c
,
813 emit_vertex_input(struct vc4_compile
*c
, int attr
)
815 enum pipe_format format
= c
->vs_key
->attr_formats
[attr
];
816 struct qreg vpm_reads
[4];
818 /* Right now, we're setting the VPM offsets to be 16 bytes wide every
819 * time, so we always read 4 32-bit VPM entries.
821 for (int i
= 0; i
< 4; i
++) {
822 vpm_reads
[i
] = qir_get_temp(c
);
823 qir_emit(c
, qir_inst(QOP_VPM_READ
,
830 bool format_warned
= false;
831 const struct util_format_description
*desc
=
832 util_format_description(format
);
834 for (int i
= 0; i
< 4; i
++) {
835 uint8_t swiz
= desc
->swizzle
[i
];
838 if (swiz
> UTIL_FORMAT_SWIZZLE_W
)
839 result
= get_swizzled_channel(c
, vpm_reads
, swiz
);
840 else if (desc
->channel
[swiz
].size
== 32 &&
841 desc
->channel
[swiz
].type
== UTIL_FORMAT_TYPE_FLOAT
) {
842 result
= get_swizzled_channel(c
, vpm_reads
, swiz
);
843 } else if (desc
->channel
[swiz
].size
== 8 &&
844 (desc
->channel
[swiz
].type
== UTIL_FORMAT_TYPE_UNSIGNED
||
845 desc
->channel
[swiz
].type
== UTIL_FORMAT_TYPE_SIGNED
) &&
846 desc
->channel
[swiz
].normalized
) {
847 struct qreg vpm
= vpm_reads
[0];
848 if (desc
->channel
[swiz
].type
== UTIL_FORMAT_TYPE_SIGNED
)
849 vpm
= qir_XOR(c
, vpm
, qir_uniform_ui(c
, 0x80808080));
850 result
= qir_UNPACK_8(c
, vpm
, swiz
);
852 if (!format_warned
) {
854 "vtx element %d unsupported type: %s\n",
855 attr
, util_format_name(format
));
856 format_warned
= true;
858 result
= qir_uniform_f(c
, 0.0);
861 if (desc
->channel
[swiz
].normalized
&&
862 desc
->channel
[swiz
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
866 qir_uniform_f(c
, 2.0)),
867 qir_uniform_f(c
, 1.0));
870 c
->inputs
[attr
* 4 + i
] = result
;
875 tgsi_to_qir_kill_if(struct vc4_compile
*c
, struct qreg
*src
, int i
)
877 if (c
->discard
.file
== QFILE_NULL
)
878 c
->discard
= qir_uniform_f(c
, 0.0);
879 qir_SF(c
, src
[0 * 4 + i
]);
880 c
->discard
= qir_SEL_X_Y_NS(c
, qir_uniform_f(c
, 1.0),
885 emit_fragcoord_input(struct vc4_compile
*c
, int attr
)
887 c
->inputs
[attr
* 4 + 0] = qir_FRAG_X(c
);
888 c
->inputs
[attr
* 4 + 1] = qir_FRAG_Y(c
);
889 c
->inputs
[attr
* 4 + 2] =
891 qir_ITOF(c
, qir_FRAG_Z(c
)),
892 qir_uniform_f(c
, 1.0 / 0xffffff));
893 c
->inputs
[attr
* 4 + 3] = qir_RCP(c
, qir_FRAG_W(c
));
897 emit_point_coord_input(struct vc4_compile
*c
, int attr
)
899 if (c
->point_x
.file
== QFILE_NULL
) {
900 c
->point_x
= qir_uniform_f(c
, 0.0);
901 c
->point_y
= qir_uniform_f(c
, 0.0);
904 c
->inputs
[attr
* 4 + 0] = c
->point_x
;
905 if (c
->fs_key
->point_coord_upper_left
) {
906 c
->inputs
[attr
* 4 + 1] = qir_FSUB(c
,
907 qir_uniform_f(c
, 1.0),
910 c
->inputs
[attr
* 4 + 1] = c
->point_y
;
912 c
->inputs
[attr
* 4 + 2] = qir_uniform_f(c
, 0.0);
913 c
->inputs
[attr
* 4 + 3] = qir_uniform_f(c
, 1.0);
917 emit_fragment_varying(struct vc4_compile
*c
, int index
)
924 return qir_VARY_ADD_C(c
, qir_FMUL(c
, vary
, qir_FRAG_W(c
)));
928 emit_fragment_input(struct vc4_compile
*c
, int attr
,
929 struct tgsi_full_declaration
*decl
)
931 for (int i
= 0; i
< 4; i
++) {
932 c
->inputs
[attr
* 4 + i
] =
933 emit_fragment_varying(c
, attr
* 4 + i
);
936 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_COLOR
||
937 decl
->Semantic
.Name
== TGSI_SEMANTIC_BCOLOR
)
938 c
->color_inputs
|= 1 << i
;
943 emit_face_input(struct vc4_compile
*c
, int attr
)
945 c
->inputs
[attr
* 4 + 0] = qir_FSUB(c
,
946 qir_uniform_f(c
, 1.0),
948 qir_ITOF(c
, qir_FRAG_REV_FLAG(c
)),
949 qir_uniform_f(c
, 2.0)));
950 c
->inputs
[attr
* 4 + 1] = qir_uniform_f(c
, 0.0);
951 c
->inputs
[attr
* 4 + 2] = qir_uniform_f(c
, 0.0);
952 c
->inputs
[attr
* 4 + 3] = qir_uniform_f(c
, 1.0);
956 emit_tgsi_declaration(struct vc4_compile
*c
,
957 struct tgsi_full_declaration
*decl
)
959 switch (decl
->Declaration
.File
) {
960 case TGSI_FILE_TEMPORARY
: {
961 uint32_t old_size
= c
->temps_array_size
;
962 resize_qreg_array(c
, &c
->temps
, &c
->temps_array_size
,
963 (decl
->Range
.Last
+ 1) * 4);
965 for (int i
= old_size
; i
< c
->temps_array_size
; i
++)
966 c
->temps
[i
] = qir_uniform_ui(c
, 0);
970 case TGSI_FILE_INPUT
:
971 resize_qreg_array(c
, &c
->inputs
, &c
->inputs_array_size
,
972 (decl
->Range
.Last
+ 1) * 4);
974 for (int i
= decl
->Range
.First
;
975 i
<= decl
->Range
.Last
;
977 if (c
->stage
== QSTAGE_FRAG
) {
978 if (decl
->Semantic
.Name
==
979 TGSI_SEMANTIC_POSITION
) {
980 emit_fragcoord_input(c
, i
);
981 } else if (decl
->Semantic
.Name
== TGSI_SEMANTIC_FACE
) {
982 emit_face_input(c
, i
);
983 } else if (decl
->Semantic
.Name
== TGSI_SEMANTIC_GENERIC
&&
984 (c
->fs_key
->point_sprite_mask
&
985 (1 << decl
->Semantic
.Index
))) {
986 emit_point_coord_input(c
, i
);
988 emit_fragment_input(c
, i
, decl
);
991 emit_vertex_input(c
, i
);
996 case TGSI_FILE_OUTPUT
:
997 resize_qreg_array(c
, &c
->outputs
, &c
->outputs_array_size
,
998 (decl
->Range
.Last
+ 1) * 4);
1000 switch (decl
->Semantic
.Name
) {
1001 case TGSI_SEMANTIC_POSITION
:
1002 c
->output_position_index
= decl
->Range
.First
* 4;
1004 case TGSI_SEMANTIC_COLOR
:
1005 c
->output_color_index
= decl
->Range
.First
* 4;
1007 case TGSI_SEMANTIC_PSIZE
:
1008 c
->output_point_size_index
= decl
->Range
.First
* 4;
1017 emit_tgsi_instruction(struct vc4_compile
*c
,
1018 struct tgsi_full_instruction
*tgsi_inst
)
1022 struct qreg (*func
)(struct vc4_compile
*c
,
1023 struct tgsi_full_instruction
*tgsi_inst
,
1025 struct qreg
*src
, int i
);
1027 [TGSI_OPCODE_MOV
] = { QOP_MOV
, tgsi_to_qir_alu
},
1028 [TGSI_OPCODE_ABS
] = { 0, tgsi_to_qir_abs
},
1029 [TGSI_OPCODE_MUL
] = { QOP_FMUL
, tgsi_to_qir_alu
},
1030 [TGSI_OPCODE_ADD
] = { QOP_FADD
, tgsi_to_qir_alu
},
1031 [TGSI_OPCODE_SUB
] = { QOP_FSUB
, tgsi_to_qir_alu
},
1032 [TGSI_OPCODE_MIN
] = { QOP_FMIN
, tgsi_to_qir_alu
},
1033 [TGSI_OPCODE_MAX
] = { QOP_FMAX
, tgsi_to_qir_alu
},
1034 [TGSI_OPCODE_F2I
] = { QOP_FTOI
, tgsi_to_qir_alu
},
1035 [TGSI_OPCODE_I2F
] = { QOP_ITOF
, tgsi_to_qir_alu
},
1036 [TGSI_OPCODE_UADD
] = { QOP_ADD
, tgsi_to_qir_alu
},
1037 [TGSI_OPCODE_USHR
] = { QOP_SHR
, tgsi_to_qir_alu
},
1038 [TGSI_OPCODE_ISHR
] = { QOP_ASR
, tgsi_to_qir_alu
},
1039 [TGSI_OPCODE_SHL
] = { QOP_SHL
, tgsi_to_qir_alu
},
1040 [TGSI_OPCODE_IMIN
] = { QOP_MIN
, tgsi_to_qir_alu
},
1041 [TGSI_OPCODE_IMAX
] = { QOP_MAX
, tgsi_to_qir_alu
},
1042 [TGSI_OPCODE_AND
] = { QOP_AND
, tgsi_to_qir_alu
},
1043 [TGSI_OPCODE_OR
] = { QOP_OR
, tgsi_to_qir_alu
},
1044 [TGSI_OPCODE_XOR
] = { QOP_XOR
, tgsi_to_qir_alu
},
1045 [TGSI_OPCODE_NOT
] = { QOP_NOT
, tgsi_to_qir_alu
},
1047 [TGSI_OPCODE_UMUL
] = { 0, tgsi_to_qir_umul
},
1048 [TGSI_OPCODE_IDIV
] = { 0, tgsi_to_qir_idiv
},
1049 [TGSI_OPCODE_INEG
] = { 0, tgsi_to_qir_ineg
},
1051 [TGSI_OPCODE_RSQ
] = { QOP_RSQ
, tgsi_to_qir_alu
},
1052 [TGSI_OPCODE_SEQ
] = { 0, tgsi_to_qir_seq
},
1053 [TGSI_OPCODE_SNE
] = { 0, tgsi_to_qir_sne
},
1054 [TGSI_OPCODE_SGE
] = { 0, tgsi_to_qir_sge
},
1055 [TGSI_OPCODE_SLT
] = { 0, tgsi_to_qir_slt
},
1056 [TGSI_OPCODE_FSEQ
] = { 0, tgsi_to_qir_fseq
},
1057 [TGSI_OPCODE_FSNE
] = { 0, tgsi_to_qir_fsne
},
1058 [TGSI_OPCODE_FSGE
] = { 0, tgsi_to_qir_fsge
},
1059 [TGSI_OPCODE_FSLT
] = { 0, tgsi_to_qir_fslt
},
1060 [TGSI_OPCODE_USEQ
] = { 0, tgsi_to_qir_useq
},
1061 [TGSI_OPCODE_USNE
] = { 0, tgsi_to_qir_usne
},
1062 [TGSI_OPCODE_ISGE
] = { 0, tgsi_to_qir_isge
},
1063 [TGSI_OPCODE_ISLT
] = { 0, tgsi_to_qir_islt
},
1065 [TGSI_OPCODE_CMP
] = { 0, tgsi_to_qir_cmp
},
1066 [TGSI_OPCODE_MAD
] = { 0, tgsi_to_qir_mad
},
1067 [TGSI_OPCODE_RCP
] = { QOP_RCP
, tgsi_to_qir_scalar
},
1068 [TGSI_OPCODE_RSQ
] = { QOP_RSQ
, tgsi_to_qir_scalar
},
1069 [TGSI_OPCODE_EX2
] = { QOP_EXP2
, tgsi_to_qir_scalar
},
1070 [TGSI_OPCODE_LG2
] = { QOP_LOG2
, tgsi_to_qir_scalar
},
1071 [TGSI_OPCODE_LRP
] = { 0, tgsi_to_qir_lrp
},
1072 [TGSI_OPCODE_TRUNC
] = { 0, tgsi_to_qir_trunc
},
1073 [TGSI_OPCODE_FRC
] = { 0, tgsi_to_qir_frc
},
1074 [TGSI_OPCODE_FLR
] = { 0, tgsi_to_qir_flr
},
1075 [TGSI_OPCODE_SIN
] = { 0, tgsi_to_qir_sin
},
1076 [TGSI_OPCODE_COS
] = { 0, tgsi_to_qir_cos
},
1077 [TGSI_OPCODE_CLAMP
] = { 0, tgsi_to_qir_clamp
},
1079 static int asdf
= 0;
1080 uint32_t tgsi_op
= tgsi_inst
->Instruction
.Opcode
;
1082 if (tgsi_op
== TGSI_OPCODE_END
)
1085 struct qreg src_regs
[12];
1086 for (int s
= 0; s
< 3; s
++) {
1087 for (int i
= 0; i
< 4; i
++) {
1088 src_regs
[4 * s
+ i
] =
1089 get_src(c
, tgsi_inst
->Instruction
.Opcode
,
1090 &tgsi_inst
->Src
[s
].Register
, i
);
1095 case TGSI_OPCODE_TEX
:
1096 case TGSI_OPCODE_TXP
:
1097 case TGSI_OPCODE_TXB
:
1098 tgsi_to_qir_tex(c
, tgsi_inst
,
1099 op_trans
[tgsi_op
].op
, src_regs
);
1101 case TGSI_OPCODE_KILL
:
1102 c
->discard
= qir_uniform_f(c
, 1.0);
1104 case TGSI_OPCODE_KILL_IF
:
1105 for (int i
= 0; i
< 4; i
++)
1106 tgsi_to_qir_kill_if(c
, src_regs
, i
);
1112 if (tgsi_op
> ARRAY_SIZE(op_trans
) || !(op_trans
[tgsi_op
].func
)) {
1113 fprintf(stderr
, "unknown tgsi inst: ");
1114 tgsi_dump_instruction(tgsi_inst
, asdf
++);
1115 fprintf(stderr
, "\n");
1119 for (int i
= 0; i
< 4; i
++) {
1120 if (!(tgsi_inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
1125 result
= op_trans
[tgsi_op
].func(c
, tgsi_inst
,
1126 op_trans
[tgsi_op
].op
,
1129 if (tgsi_inst
->Instruction
.Saturate
) {
1130 float low
= (tgsi_inst
->Instruction
.Saturate
==
1131 TGSI_SAT_MINUS_PLUS_ONE
? -1.0 : 0.0);
1132 result
= qir_FMAX(c
,
1135 qir_uniform_f(c
, 1.0)),
1136 qir_uniform_f(c
, low
));
1139 update_dst(c
, tgsi_inst
, i
, result
);
1144 parse_tgsi_immediate(struct vc4_compile
*c
, struct tgsi_full_immediate
*imm
)
1146 for (int i
= 0; i
< 4; i
++) {
1147 unsigned n
= c
->num_consts
++;
1148 resize_qreg_array(c
, &c
->consts
, &c
->consts_array_size
, n
+ 1);
1149 c
->consts
[n
] = qir_uniform_ui(c
, imm
->u
[i
].Uint
);
1154 vc4_blend_channel(struct vc4_compile
*c
,
1162 case PIPE_BLENDFACTOR_ONE
:
1164 case PIPE_BLENDFACTOR_SRC_COLOR
:
1165 return qir_FMUL(c
, val
, src
[channel
]);
1166 case PIPE_BLENDFACTOR_SRC_ALPHA
:
1167 return qir_FMUL(c
, val
, src
[3]);
1168 case PIPE_BLENDFACTOR_DST_ALPHA
:
1169 return qir_FMUL(c
, val
, dst
[3]);
1170 case PIPE_BLENDFACTOR_DST_COLOR
:
1171 return qir_FMUL(c
, val
, dst
[channel
]);
1172 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
1173 return qir_FMIN(c
, src
[3], qir_FSUB(c
,
1174 qir_uniform_f(c
, 1.0),
1176 case PIPE_BLENDFACTOR_CONST_COLOR
:
1177 return qir_FMUL(c
, val
,
1178 get_temp_for_uniform(c
,
1179 QUNIFORM_BLEND_CONST_COLOR
,
1181 case PIPE_BLENDFACTOR_CONST_ALPHA
:
1182 return qir_FMUL(c
, val
,
1183 get_temp_for_uniform(c
,
1184 QUNIFORM_BLEND_CONST_COLOR
,
1186 case PIPE_BLENDFACTOR_ZERO
:
1187 return qir_uniform_f(c
, 0.0);
1188 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
1189 return qir_FMUL(c
, val
, qir_FSUB(c
, qir_uniform_f(c
, 1.0),
1191 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
1192 return qir_FMUL(c
, val
, qir_FSUB(c
, qir_uniform_f(c
, 1.0),
1194 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
1195 return qir_FMUL(c
, val
, qir_FSUB(c
, qir_uniform_f(c
, 1.0),
1197 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
1198 return qir_FMUL(c
, val
, qir_FSUB(c
, qir_uniform_f(c
, 1.0),
1200 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
1201 return qir_FMUL(c
, val
,
1202 qir_FSUB(c
, qir_uniform_f(c
, 1.0),
1203 get_temp_for_uniform(c
,
1204 QUNIFORM_BLEND_CONST_COLOR
,
1206 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
1207 return qir_FMUL(c
, val
,
1208 qir_FSUB(c
, qir_uniform_f(c
, 1.0),
1209 get_temp_for_uniform(c
,
1210 QUNIFORM_BLEND_CONST_COLOR
,
1214 case PIPE_BLENDFACTOR_SRC1_COLOR
:
1215 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
1216 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
1217 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
1219 fprintf(stderr
, "Unknown blend factor %d\n", factor
);
1225 vc4_blend_func(struct vc4_compile
*c
,
1226 struct qreg src
, struct qreg dst
,
1230 case PIPE_BLEND_ADD
:
1231 return qir_FADD(c
, src
, dst
);
1232 case PIPE_BLEND_SUBTRACT
:
1233 return qir_FSUB(c
, src
, dst
);
1234 case PIPE_BLEND_REVERSE_SUBTRACT
:
1235 return qir_FSUB(c
, dst
, src
);
1236 case PIPE_BLEND_MIN
:
1237 return qir_FMIN(c
, src
, dst
);
1238 case PIPE_BLEND_MAX
:
1239 return qir_FMAX(c
, src
, dst
);
1243 fprintf(stderr
, "Unknown blend func %d\n", func
);
1250 * Implements fixed function blending in shader code.
1252 * VC4 doesn't have any hardware support for blending. Instead, you read the
1253 * current contents of the destination from the tile buffer after having
1254 * waited for the scoreboard (which is handled by vc4_qpu_emit.c), then do
1255 * math using your output color and that destination value, and update the
1256 * output color appropriately.
1259 vc4_blend(struct vc4_compile
*c
, struct qreg
*result
,
1260 struct qreg
*dst_color
, struct qreg
*src_color
)
1262 struct pipe_rt_blend_state
*blend
= &c
->fs_key
->blend
;
1264 if (!blend
->blend_enable
) {
1265 for (int i
= 0; i
< 4; i
++)
1266 result
[i
] = src_color
[i
];
1270 struct qreg src_blend
[4], dst_blend
[4];
1271 for (int i
= 0; i
< 3; i
++) {
1272 src_blend
[i
] = vc4_blend_channel(c
,
1273 dst_color
, src_color
,
1275 blend
->rgb_src_factor
, i
);
1276 dst_blend
[i
] = vc4_blend_channel(c
,
1277 dst_color
, src_color
,
1279 blend
->rgb_dst_factor
, i
);
1281 src_blend
[3] = vc4_blend_channel(c
,
1282 dst_color
, src_color
,
1284 blend
->alpha_src_factor
, 3);
1285 dst_blend
[3] = vc4_blend_channel(c
,
1286 dst_color
, src_color
,
1288 blend
->alpha_dst_factor
, 3);
1290 for (int i
= 0; i
< 3; i
++) {
1291 result
[i
] = vc4_blend_func(c
,
1292 src_blend
[i
], dst_blend
[i
],
1295 result
[3] = vc4_blend_func(c
,
1296 src_blend
[3], dst_blend
[3],
1301 alpha_test_discard(struct vc4_compile
*c
)
1303 struct qreg src_alpha
;
1304 struct qreg alpha_ref
= get_temp_for_uniform(c
, QUNIFORM_ALPHA_REF
, 0);
1306 if (!c
->fs_key
->alpha_test
)
1309 if (c
->output_color_index
!= -1)
1310 src_alpha
= c
->outputs
[c
->output_color_index
+ 3];
1312 src_alpha
= qir_uniform_f(c
, 1.0);
1314 if (c
->discard
.file
== QFILE_NULL
)
1315 c
->discard
= qir_uniform_f(c
, 0.0);
1317 switch (c
->fs_key
->alpha_test_func
) {
1318 case PIPE_FUNC_NEVER
:
1319 c
->discard
= qir_uniform_f(c
, 1.0);
1321 case PIPE_FUNC_ALWAYS
:
1323 case PIPE_FUNC_EQUAL
:
1324 qir_SF(c
, qir_FSUB(c
, src_alpha
, alpha_ref
));
1325 c
->discard
= qir_SEL_X_Y_ZS(c
, c
->discard
,
1326 qir_uniform_f(c
, 1.0));
1328 case PIPE_FUNC_NOTEQUAL
:
1329 qir_SF(c
, qir_FSUB(c
, src_alpha
, alpha_ref
));
1330 c
->discard
= qir_SEL_X_Y_ZC(c
, c
->discard
,
1331 qir_uniform_f(c
, 1.0));
1333 case PIPE_FUNC_GREATER
:
1334 qir_SF(c
, qir_FSUB(c
, src_alpha
, alpha_ref
));
1335 c
->discard
= qir_SEL_X_Y_NC(c
, c
->discard
,
1336 qir_uniform_f(c
, 1.0));
1338 case PIPE_FUNC_GEQUAL
:
1339 qir_SF(c
, qir_FSUB(c
, alpha_ref
, src_alpha
));
1340 c
->discard
= qir_SEL_X_Y_NS(c
, c
->discard
,
1341 qir_uniform_f(c
, 1.0));
1343 case PIPE_FUNC_LESS
:
1344 qir_SF(c
, qir_FSUB(c
, src_alpha
, alpha_ref
));
1345 c
->discard
= qir_SEL_X_Y_NS(c
, c
->discard
,
1346 qir_uniform_f(c
, 1.0));
1348 case PIPE_FUNC_LEQUAL
:
1349 qir_SF(c
, qir_FSUB(c
, alpha_ref
, src_alpha
));
1350 c
->discard
= qir_SEL_X_Y_NC(c
, c
->discard
,
1351 qir_uniform_f(c
, 1.0));
1357 emit_frag_end(struct vc4_compile
*c
)
1359 alpha_test_discard(c
);
1361 enum pipe_format color_format
= c
->fs_key
->color_format
;
1362 const uint8_t *format_swiz
= vc4_get_format_swizzle(color_format
);
1363 struct qreg tlb_read_color
[4] = { c
->undef
, c
->undef
, c
->undef
, c
->undef
};
1364 struct qreg dst_color
[4] = { c
->undef
, c
->undef
, c
->undef
, c
->undef
};
1365 struct qreg linear_dst_color
[4] = { c
->undef
, c
->undef
, c
->undef
, c
->undef
};
1366 if (c
->fs_key
->blend
.blend_enable
||
1367 c
->fs_key
->blend
.colormask
!= 0xf) {
1368 struct qreg r4
= qir_TLB_COLOR_READ(c
);
1369 for (int i
= 0; i
< 4; i
++)
1370 tlb_read_color
[i
] = qir_R4_UNPACK(c
, r4
, i
);
1371 for (int i
= 0; i
< 4; i
++) {
1372 dst_color
[i
] = get_swizzled_channel(c
,
1375 if (util_format_is_srgb(color_format
) && i
!= 3) {
1376 linear_dst_color
[i
] =
1377 qir_srgb_decode(c
, dst_color
[i
]);
1379 linear_dst_color
[i
] = dst_color
[i
];
1384 struct qreg blend_color
[4];
1385 struct qreg undef_array
[4] = {
1386 c
->undef
, c
->undef
, c
->undef
, c
->undef
1388 vc4_blend(c
, blend_color
, linear_dst_color
,
1389 (c
->output_color_index
!= -1 ?
1390 c
->outputs
+ c
->output_color_index
:
1393 if (util_format_is_srgb(color_format
)) {
1394 for (int i
= 0; i
< 3; i
++)
1395 blend_color
[i
] = qir_srgb_encode(c
, blend_color
[i
]);
1398 /* If the bit isn't set in the color mask, then just return the
1399 * original dst color, instead.
1401 for (int i
= 0; i
< 4; i
++) {
1402 if (!(c
->fs_key
->blend
.colormask
& (1 << i
))) {
1403 blend_color
[i
] = dst_color
[i
];
1407 /* Debug: Sometimes you're getting a black output and just want to see
1408 * if the FS is getting executed at all. Spam magenta into the color
1412 blend_color
[0] = qir_uniform_f(c
, 1.0);
1413 blend_color
[1] = qir_uniform_f(c
, 0.0);
1414 blend_color
[2] = qir_uniform_f(c
, 1.0);
1415 blend_color
[3] = qir_uniform_f(c
, 0.5);
1418 struct qreg swizzled_outputs
[4];
1419 for (int i
= 0; i
< 4; i
++) {
1420 swizzled_outputs
[i
] = get_swizzled_channel(c
, blend_color
,
1424 if (c
->discard
.file
!= QFILE_NULL
)
1425 qir_TLB_DISCARD_SETUP(c
, c
->discard
);
1427 if (c
->fs_key
->stencil_enabled
) {
1428 qir_TLB_STENCIL_SETUP(c
, add_uniform(c
, QUNIFORM_STENCIL
, 0));
1429 if (c
->fs_key
->stencil_twoside
) {
1430 qir_TLB_STENCIL_SETUP(c
, add_uniform(c
, QUNIFORM_STENCIL
, 1));
1432 if (c
->fs_key
->stencil_full_writemasks
) {
1433 qir_TLB_STENCIL_SETUP(c
, add_uniform(c
, QUNIFORM_STENCIL
, 2));
1437 if (c
->fs_key
->depth_enabled
) {
1439 if (c
->output_position_index
!= -1) {
1440 z
= qir_FTOI(c
, qir_FMUL(c
, c
->outputs
[c
->output_position_index
+ 2],
1441 qir_uniform_f(c
, 0xffffff)));
1445 qir_TLB_Z_WRITE(c
, z
);
1448 bool color_written
= false;
1449 for (int i
= 0; i
< 4; i
++) {
1450 if (swizzled_outputs
[i
].file
!= QFILE_NULL
)
1451 color_written
= true;
1454 struct qreg packed_color
;
1455 if (color_written
) {
1456 /* Fill in any undefined colors. The simulator will assertion
1457 * fail if we read something that wasn't written, and I don't
1458 * know what hardware does.
1460 for (int i
= 0; i
< 4; i
++) {
1461 if (swizzled_outputs
[i
].file
== QFILE_NULL
)
1462 swizzled_outputs
[i
] = qir_uniform_f(c
, 0.0);
1464 packed_color
= qir_get_temp(c
);
1465 qir_emit(c
, qir_inst4(QOP_PACK_COLORS
, packed_color
,
1466 swizzled_outputs
[0],
1467 swizzled_outputs
[1],
1468 swizzled_outputs
[2],
1469 swizzled_outputs
[3]));
1471 packed_color
= qir_uniform_ui(c
, 0);
1474 qir_emit(c
, qir_inst(QOP_TLB_COLOR_WRITE
, c
->undef
,
1475 packed_color
, c
->undef
));
1479 emit_scaled_viewport_write(struct vc4_compile
*c
, struct qreg rcp_w
)
1483 for (int i
= 0; i
< 2; i
++) {
1485 add_uniform(c
, QUNIFORM_VIEWPORT_X_SCALE
+ i
, 0);
1487 xyi
[i
] = qir_FTOI(c
, qir_FMUL(c
,
1494 qir_VPM_WRITE(c
, qir_PACK_SCALED(c
, xyi
[0], xyi
[1]));
1498 emit_zs_write(struct vc4_compile
*c
, struct qreg rcp_w
)
1500 struct qreg zscale
= add_uniform(c
, QUNIFORM_VIEWPORT_Z_SCALE
, 0);
1501 struct qreg zoffset
= add_uniform(c
, QUNIFORM_VIEWPORT_Z_OFFSET
, 0);
1503 qir_VPM_WRITE(c
, qir_FMUL(c
, qir_FADD(c
, qir_FMUL(c
,
1511 emit_rcp_wc_write(struct vc4_compile
*c
, struct qreg rcp_w
)
1513 qir_VPM_WRITE(c
, rcp_w
);
1517 emit_point_size_write(struct vc4_compile
*c
)
1519 struct qreg point_size
;
1521 if (c
->output_point_size_index
)
1522 point_size
= c
->outputs
[c
->output_point_size_index
+ 3];
1524 point_size
= qir_uniform_f(c
, 1.0);
1526 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1529 point_size
= qir_FMAX(c
, point_size
, qir_uniform_f(c
, .125));
1531 qir_VPM_WRITE(c
, point_size
);
1535 emit_vert_end(struct vc4_compile
*c
)
1537 struct qreg rcp_w
= qir_RCP(c
, c
->outputs
[3]);
1539 emit_scaled_viewport_write(c
, rcp_w
);
1540 emit_zs_write(c
, rcp_w
);
1541 emit_rcp_wc_write(c
, rcp_w
);
1542 if (c
->vs_key
->per_vertex_point_size
)
1543 emit_point_size_write(c
);
1545 for (int i
= 4; i
< c
->num_outputs
; i
++) {
1546 qir_VPM_WRITE(c
, c
->outputs
[i
]);
1551 emit_coord_end(struct vc4_compile
*c
)
1553 struct qreg rcp_w
= qir_RCP(c
, c
->outputs
[3]);
1555 for (int i
= 0; i
< 4; i
++)
1556 qir_VPM_WRITE(c
, c
->outputs
[i
]);
1558 emit_scaled_viewport_write(c
, rcp_w
);
1559 emit_zs_write(c
, rcp_w
);
1560 emit_rcp_wc_write(c
, rcp_w
);
1561 if (c
->vs_key
->per_vertex_point_size
)
1562 emit_point_size_write(c
);
1565 static struct vc4_compile
*
1566 vc4_shader_tgsi_to_qir(struct vc4_context
*vc4
,
1567 struct vc4_compiled_shader
*shader
, enum qstage stage
,
1568 struct vc4_key
*key
)
1570 struct vc4_compile
*c
= qir_compile_init();
1574 c
->shader_state
= &key
->shader_state
->base
;
1579 c
->fs_key
= (struct vc4_fs_key
*)key
;
1580 if (c
->fs_key
->is_points
) {
1581 c
->point_x
= emit_fragment_varying(c
, 0);
1582 c
->point_y
= emit_fragment_varying(c
, 0);
1583 } else if (c
->fs_key
->is_lines
) {
1584 c
->line_x
= emit_fragment_varying(c
, 0);
1588 c
->vs_key
= (struct vc4_vs_key
*)key
;
1591 c
->vs_key
= (struct vc4_vs_key
*)key
;
1595 const struct tgsi_token
*tokens
= key
->shader_state
->base
.tokens
;
1596 if (c
->fs_key
&& c
->fs_key
->light_twoside
) {
1597 if (!key
->shader_state
->twoside_tokens
) {
1598 const struct tgsi_lowering_config lowering_config
= {
1599 .color_two_side
= true,
1601 struct tgsi_shader_info info
;
1602 key
->shader_state
->twoside_tokens
=
1603 tgsi_transform_lowering(&lowering_config
,
1604 key
->shader_state
->base
.tokens
,
1607 /* If no transformation occurred, then NULL is
1608 * returned and we just use our original tokens.
1610 if (!key
->shader_state
->twoside_tokens
) {
1611 key
->shader_state
->twoside_tokens
=
1612 key
->shader_state
->base
.tokens
;
1615 tokens
= key
->shader_state
->twoside_tokens
;
1618 ret
= tgsi_parse_init(&c
->parser
, tokens
);
1619 assert(ret
== TGSI_PARSE_OK
);
1621 if (vc4_debug
& VC4_DEBUG_TGSI
) {
1622 fprintf(stderr
, "TGSI:\n");
1623 tgsi_dump(tokens
, 0);
1626 while (!tgsi_parse_end_of_tokens(&c
->parser
)) {
1627 tgsi_parse_token(&c
->parser
);
1629 switch (c
->parser
.FullToken
.Token
.Type
) {
1630 case TGSI_TOKEN_TYPE_DECLARATION
:
1631 emit_tgsi_declaration(c
,
1632 &c
->parser
.FullToken
.FullDeclaration
);
1635 case TGSI_TOKEN_TYPE_INSTRUCTION
:
1636 emit_tgsi_instruction(c
,
1637 &c
->parser
.FullToken
.FullInstruction
);
1640 case TGSI_TOKEN_TYPE_IMMEDIATE
:
1641 parse_tgsi_immediate(c
,
1642 &c
->parser
.FullToken
.FullImmediate
);
1659 tgsi_parse_free(&c
->parser
);
1663 if (vc4_debug
& VC4_DEBUG_QIR
) {
1664 fprintf(stderr
, "QIR:\n");
1667 qir_reorder_uniforms(c
);
1668 vc4_generate_code(vc4
, c
);
1670 if (vc4_debug
& VC4_DEBUG_SHADERDB
) {
1671 fprintf(stderr
, "SHADER-DB: %s: %d instructions\n",
1672 qir_get_stage_name(c
->stage
), c
->qpu_inst_count
);
1673 fprintf(stderr
, "SHADER-DB: %s: %d uniforms\n",
1674 qir_get_stage_name(c
->stage
), c
->num_uniforms
);
1681 vc4_shader_state_create(struct pipe_context
*pctx
,
1682 const struct pipe_shader_state
*cso
)
1684 struct vc4_uncompiled_shader
*so
= CALLOC_STRUCT(vc4_uncompiled_shader
);
1688 const struct tgsi_lowering_config lowering_config
= {
1703 struct tgsi_shader_info info
;
1704 so
->base
.tokens
= tgsi_transform_lowering(&lowering_config
, cso
->tokens
, &info
);
1705 if (!so
->base
.tokens
)
1706 so
->base
.tokens
= tgsi_dup_tokens(cso
->tokens
);
1712 copy_uniform_state_to_shader(struct vc4_compiled_shader
*shader
,
1714 struct vc4_compile
*c
)
1716 int count
= c
->num_uniforms
;
1717 struct vc4_shader_uniform_info
*uinfo
= &shader
->uniforms
[shader_index
];
1719 uinfo
->count
= count
;
1720 uinfo
->data
= malloc(count
* sizeof(*uinfo
->data
));
1721 memcpy(uinfo
->data
, c
->uniform_data
,
1722 count
* sizeof(*uinfo
->data
));
1723 uinfo
->contents
= malloc(count
* sizeof(*uinfo
->contents
));
1724 memcpy(uinfo
->contents
, c
->uniform_contents
,
1725 count
* sizeof(*uinfo
->contents
));
1726 uinfo
->num_texture_samples
= c
->num_texture_samples
;
1730 vc4_fs_compile(struct vc4_context
*vc4
, struct vc4_compiled_shader
*shader
,
1731 struct vc4_fs_key
*key
)
1733 struct vc4_compile
*c
= vc4_shader_tgsi_to_qir(vc4
, shader
,
1736 shader
->num_inputs
= c
->num_inputs
;
1737 shader
->color_inputs
= c
->color_inputs
;
1738 copy_uniform_state_to_shader(shader
, 0, c
);
1739 shader
->bo
= vc4_bo_alloc_mem(vc4
->screen
, c
->qpu_insts
,
1740 c
->qpu_inst_count
* sizeof(uint64_t),
1743 qir_compile_destroy(c
);
1747 vc4_vs_compile(struct vc4_context
*vc4
, struct vc4_compiled_shader
*shader
,
1748 struct vc4_vs_key
*key
)
1750 struct vc4_compile
*vs_c
= vc4_shader_tgsi_to_qir(vc4
, shader
,
1753 copy_uniform_state_to_shader(shader
, 0, vs_c
);
1755 struct vc4_compile
*cs_c
= vc4_shader_tgsi_to_qir(vc4
, shader
,
1758 copy_uniform_state_to_shader(shader
, 1, cs_c
);
1760 uint32_t vs_size
= vs_c
->qpu_inst_count
* sizeof(uint64_t);
1761 uint32_t cs_size
= cs_c
->qpu_inst_count
* sizeof(uint64_t);
1762 shader
->coord_shader_offset
= vs_size
; /* XXX: alignment? */
1763 shader
->bo
= vc4_bo_alloc(vc4
->screen
,
1764 shader
->coord_shader_offset
+ cs_size
,
1767 void *map
= vc4_bo_map(shader
->bo
);
1768 memcpy(map
, vs_c
->qpu_insts
, vs_size
);
1769 memcpy(map
+ shader
->coord_shader_offset
,
1770 cs_c
->qpu_insts
, cs_size
);
1772 qir_compile_destroy(vs_c
);
1773 qir_compile_destroy(cs_c
);
1777 vc4_setup_shared_key(struct vc4_key
*key
, struct vc4_texture_stateobj
*texstate
)
1779 for (int i
= 0; i
< texstate
->num_textures
; i
++) {
1780 struct pipe_sampler_view
*sampler
= texstate
->textures
[i
];
1781 struct pipe_sampler_state
*sampler_state
=
1782 texstate
->samplers
[i
];
1785 key
->tex
[i
].format
= sampler
->format
;
1786 key
->tex
[i
].swizzle
[0] = sampler
->swizzle_r
;
1787 key
->tex
[i
].swizzle
[1] = sampler
->swizzle_g
;
1788 key
->tex
[i
].swizzle
[2] = sampler
->swizzle_b
;
1789 key
->tex
[i
].swizzle
[3] = sampler
->swizzle_a
;
1790 key
->tex
[i
].compare_mode
= sampler_state
->compare_mode
;
1791 key
->tex
[i
].compare_func
= sampler_state
->compare_func
;
1792 key
->tex
[i
].wrap_s
= sampler_state
->wrap_s
;
1793 key
->tex
[i
].wrap_t
= sampler_state
->wrap_t
;
1799 vc4_update_compiled_fs(struct vc4_context
*vc4
, uint8_t prim_mode
)
1801 struct vc4_fs_key local_key
;
1802 struct vc4_fs_key
*key
= &local_key
;
1804 memset(key
, 0, sizeof(*key
));
1805 vc4_setup_shared_key(&key
->base
, &vc4
->fragtex
);
1806 key
->base
.shader_state
= vc4
->prog
.bind_fs
;
1807 key
->is_points
= (prim_mode
== PIPE_PRIM_POINTS
);
1808 key
->is_lines
= (prim_mode
>= PIPE_PRIM_LINES
&&
1809 prim_mode
<= PIPE_PRIM_LINE_STRIP
);
1810 key
->blend
= vc4
->blend
->rt
[0];
1812 if (vc4
->framebuffer
.cbufs
[0])
1813 key
->color_format
= vc4
->framebuffer
.cbufs
[0]->format
;
1815 key
->stencil_enabled
= vc4
->zsa
->stencil_uniforms
[0] != 0;
1816 key
->stencil_twoside
= vc4
->zsa
->stencil_uniforms
[1] != 0;
1817 key
->stencil_full_writemasks
= vc4
->zsa
->stencil_uniforms
[2] != 0;
1818 key
->depth_enabled
= (vc4
->zsa
->base
.depth
.enabled
||
1819 key
->stencil_enabled
);
1820 if (vc4
->zsa
->base
.alpha
.enabled
) {
1821 key
->alpha_test
= true;
1822 key
->alpha_test_func
= vc4
->zsa
->base
.alpha
.func
;
1825 if (key
->is_points
) {
1826 key
->point_sprite_mask
=
1827 vc4
->rasterizer
->base
.sprite_coord_enable
;
1828 key
->point_coord_upper_left
=
1829 (vc4
->rasterizer
->base
.sprite_coord_mode
==
1830 PIPE_SPRITE_COORD_UPPER_LEFT
);
1833 key
->light_twoside
= vc4
->rasterizer
->base
.light_twoside
;
1835 vc4
->prog
.fs
= util_hash_table_get(vc4
->fs_cache
, key
);
1839 key
= malloc(sizeof(*key
));
1840 memcpy(key
, &local_key
, sizeof(*key
));
1842 struct vc4_compiled_shader
*shader
= CALLOC_STRUCT(vc4_compiled_shader
);
1843 vc4_fs_compile(vc4
, shader
, key
);
1844 util_hash_table_set(vc4
->fs_cache
, key
, shader
);
1846 if (vc4
->rasterizer
->base
.flatshade
&&
1848 vc4
->prog
.fs
->color_inputs
!= shader
->color_inputs
) {
1849 vc4
->dirty
|= VC4_DIRTY_FLAT_SHADE_FLAGS
;
1852 vc4
->prog
.fs
= shader
;
1856 vc4_update_compiled_vs(struct vc4_context
*vc4
, uint8_t prim_mode
)
1858 struct vc4_vs_key local_key
;
1859 struct vc4_vs_key
*key
= &local_key
;
1861 memset(key
, 0, sizeof(*key
));
1862 vc4_setup_shared_key(&key
->base
, &vc4
->verttex
);
1863 key
->base
.shader_state
= vc4
->prog
.bind_vs
;
1865 for (int i
= 0; i
< ARRAY_SIZE(key
->attr_formats
); i
++)
1866 key
->attr_formats
[i
] = vc4
->vtx
->pipe
[i
].src_format
;
1868 key
->per_vertex_point_size
=
1869 (prim_mode
== PIPE_PRIM_POINTS
&&
1870 vc4
->rasterizer
->base
.point_size_per_vertex
);
1872 vc4
->prog
.vs
= util_hash_table_get(vc4
->vs_cache
, key
);
1876 key
= malloc(sizeof(*key
));
1877 memcpy(key
, &local_key
, sizeof(*key
));
1879 struct vc4_compiled_shader
*shader
= CALLOC_STRUCT(vc4_compiled_shader
);
1880 vc4_vs_compile(vc4
, shader
, key
);
1881 util_hash_table_set(vc4
->vs_cache
, key
, shader
);
1883 vc4
->prog
.vs
= shader
;
1887 vc4_update_compiled_shaders(struct vc4_context
*vc4
, uint8_t prim_mode
)
1889 vc4_update_compiled_fs(vc4
, prim_mode
);
1890 vc4_update_compiled_vs(vc4
, prim_mode
);
1894 fs_cache_hash(void *key
)
1896 return util_hash_crc32(key
, sizeof(struct vc4_fs_key
));
1900 vs_cache_hash(void *key
)
1902 return util_hash_crc32(key
, sizeof(struct vc4_vs_key
));
1906 fs_cache_compare(void *key1
, void *key2
)
1908 return memcmp(key1
, key2
, sizeof(struct vc4_fs_key
));
1912 vs_cache_compare(void *key1
, void *key2
)
1914 return memcmp(key1
, key2
, sizeof(struct vc4_vs_key
));
1917 struct delete_state
{
1918 struct vc4_context
*vc4
;
1919 struct vc4_uncompiled_shader
*shader_state
;
1922 static enum pipe_error
1923 fs_delete_from_cache(void *in_key
, void *in_value
, void *data
)
1925 struct delete_state
*del
= data
;
1926 struct vc4_fs_key
*key
= in_key
;
1927 struct vc4_compiled_shader
*shader
= in_value
;
1929 if (key
->base
.shader_state
== data
) {
1930 util_hash_table_remove(del
->vc4
->fs_cache
, key
);
1931 vc4_bo_unreference(&shader
->bo
);
1938 static enum pipe_error
1939 vs_delete_from_cache(void *in_key
, void *in_value
, void *data
)
1941 struct delete_state
*del
= data
;
1942 struct vc4_vs_key
*key
= in_key
;
1943 struct vc4_compiled_shader
*shader
= in_value
;
1945 if (key
->base
.shader_state
== data
) {
1946 util_hash_table_remove(del
->vc4
->vs_cache
, key
);
1947 vc4_bo_unreference(&shader
->bo
);
1955 vc4_shader_state_delete(struct pipe_context
*pctx
, void *hwcso
)
1957 struct vc4_context
*vc4
= vc4_context(pctx
);
1958 struct vc4_uncompiled_shader
*so
= hwcso
;
1959 struct delete_state del
;
1962 del
.shader_state
= so
;
1963 util_hash_table_foreach(vc4
->fs_cache
, fs_delete_from_cache
, &del
);
1964 util_hash_table_foreach(vc4
->vs_cache
, vs_delete_from_cache
, &del
);
1966 if (so
->twoside_tokens
!= so
->base
.tokens
)
1967 free((void *)so
->twoside_tokens
);
1968 free((void *)so
->base
.tokens
);
1972 static uint32_t translate_wrap(uint32_t p_wrap
, bool using_nearest
)
1975 case PIPE_TEX_WRAP_REPEAT
:
1977 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1979 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1981 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1983 case PIPE_TEX_WRAP_CLAMP
:
1984 return (using_nearest
? 1 : 3);
1986 fprintf(stderr
, "Unknown wrap mode %d\n", p_wrap
);
1987 assert(!"not reached");
1993 write_texture_p0(struct vc4_context
*vc4
,
1994 struct vc4_texture_stateobj
*texstate
,
1997 struct pipe_sampler_view
*texture
= texstate
->textures
[unit
];
1998 struct vc4_resource
*rsc
= vc4_resource(texture
->texture
);
2000 bool is_cube
= texture
->target
== PIPE_TEXTURE_CUBE
;
2002 cl_reloc(vc4
, &vc4
->uniforms
, rsc
->bo
,
2003 rsc
->slices
[0].offset
| texture
->u
.tex
.last_level
|
2005 ((rsc
->vc4_format
& 7) << 4));
2009 write_texture_p1(struct vc4_context
*vc4
,
2010 struct vc4_texture_stateobj
*texstate
,
2013 struct pipe_sampler_view
*texture
= texstate
->textures
[unit
];
2014 struct vc4_resource
*rsc
= vc4_resource(texture
->texture
);
2015 struct pipe_sampler_state
*sampler
= texstate
->samplers
[unit
];
2016 static const uint8_t minfilter_map
[6] = {
2017 2, 4, /* mipfilter nearest */
2018 3, 5, /* mipfilter linear */
2019 1, 0, /* mipfilter none */
2021 static const uint32_t magfilter_map
[] = {
2022 [PIPE_TEX_FILTER_NEAREST
] = 1,
2023 [PIPE_TEX_FILTER_LINEAR
] = 0,
2026 bool either_nearest
=
2027 (sampler
->mag_img_filter
== PIPE_TEX_MIPFILTER_NEAREST
||
2028 sampler
->min_img_filter
== PIPE_TEX_MIPFILTER_NEAREST
);
2030 cl_u32(&vc4
->uniforms
,
2031 ((rsc
->vc4_format
>> 4) << 31) |
2032 (texture
->texture
->height0
<< 20) |
2033 (texture
->texture
->width0
<< 8) |
2034 (magfilter_map
[sampler
->mag_img_filter
] << 7) |
2035 (minfilter_map
[sampler
->min_mip_filter
* 2 +
2036 sampler
->min_img_filter
] << 4) |
2037 (translate_wrap(sampler
->wrap_t
, either_nearest
) << 2) |
2038 (translate_wrap(sampler
->wrap_s
, either_nearest
) << 0));
2042 write_texture_p2(struct vc4_context
*vc4
,
2043 struct vc4_texture_stateobj
*texstate
,
2046 struct pipe_sampler_view
*texture
= texstate
->textures
[unit
];
2047 struct vc4_resource
*rsc
= vc4_resource(texture
->texture
);
2049 cl_u32(&vc4
->uniforms
, (1 << 30) | rsc
->cube_map_stride
);
2053 #define SWIZ(x,y,z,w) { \
2054 UTIL_FORMAT_SWIZZLE_##x, \
2055 UTIL_FORMAT_SWIZZLE_##y, \
2056 UTIL_FORMAT_SWIZZLE_##z, \
2057 UTIL_FORMAT_SWIZZLE_##w \
2061 write_texture_border_color(struct vc4_context
*vc4
,
2062 struct vc4_texture_stateobj
*texstate
,
2065 struct pipe_sampler_state
*sampler
= texstate
->samplers
[unit
];
2066 struct pipe_sampler_view
*texture
= texstate
->textures
[unit
];
2067 struct vc4_resource
*rsc
= vc4_resource(texture
->texture
);
2068 union util_color uc
;
2070 const struct util_format_description
*tex_format_desc
=
2071 util_format_description(texture
->format
);
2073 float border_color
[4];
2074 for (int i
= 0; i
< 4; i
++)
2075 border_color
[i
] = sampler
->border_color
.f
[i
];
2076 if (util_format_is_srgb(texture
->format
)) {
2077 for (int i
= 0; i
< 3; i
++)
2079 util_format_linear_to_srgb_float(border_color
[i
]);
2082 /* Turn the border color into the layout of channels that it would
2083 * have when stored as texture contents.
2085 float storage_color
[4];
2086 util_format_unswizzle_4f(storage_color
,
2088 tex_format_desc
->swizzle
);
2090 /* Now, pack so that when the vc4_format-sampled texture contents are
2091 * replaced with our border color, the vc4_get_format_swizzle()
2092 * swizzling will get the right channels.
2094 if (util_format_is_depth_or_stencil(texture
->format
)) {
2095 uc
.ui
[0] = util_pack_z(PIPE_FORMAT_Z24X8_UNORM
,
2096 sampler
->border_color
.f
[0]) << 8;
2098 switch (rsc
->vc4_format
) {
2100 case VC4_TEXTURE_TYPE_RGBA8888
:
2101 util_pack_color(storage_color
,
2102 PIPE_FORMAT_R8G8B8A8_UNORM
, &uc
);
2104 case VC4_TEXTURE_TYPE_RGBA4444
:
2105 util_pack_color(storage_color
,
2106 PIPE_FORMAT_A8B8G8R8_UNORM
, &uc
);
2108 case VC4_TEXTURE_TYPE_RGB565
:
2109 util_pack_color(storage_color
,
2110 PIPE_FORMAT_B8G8R8A8_UNORM
, &uc
);
2112 case VC4_TEXTURE_TYPE_ALPHA
:
2113 uc
.ui
[0] = float_to_ubyte(storage_color
[0]) << 24;
2115 case VC4_TEXTURE_TYPE_LUMALPHA
:
2116 uc
.ui
[0] = ((float_to_ubyte(storage_color
[1]) << 24) |
2117 (float_to_ubyte(storage_color
[0]) << 0));
2122 cl_u32(&vc4
->uniforms
, uc
.ui
[0]);
2126 get_texrect_scale(struct vc4_texture_stateobj
*texstate
,
2127 enum quniform_contents contents
,
2130 struct pipe_sampler_view
*texture
= texstate
->textures
[data
];
2133 if (contents
== QUNIFORM_TEXRECT_SCALE_X
)
2134 dim
= texture
->texture
->width0
;
2136 dim
= texture
->texture
->height0
;
2138 return fui(1.0f
/ dim
);
2142 vc4_write_uniforms(struct vc4_context
*vc4
, struct vc4_compiled_shader
*shader
,
2143 struct vc4_constbuf_stateobj
*cb
,
2144 struct vc4_texture_stateobj
*texstate
,
2147 struct vc4_shader_uniform_info
*uinfo
= &shader
->uniforms
[shader_index
];
2148 const uint32_t *gallium_uniforms
= cb
->cb
[0].user_buffer
;
2150 cl_start_shader_reloc(&vc4
->uniforms
, uinfo
->num_texture_samples
);
2152 for (int i
= 0; i
< uinfo
->count
; i
++) {
2154 switch (uinfo
->contents
[i
]) {
2155 case QUNIFORM_CONSTANT
:
2156 cl_u32(&vc4
->uniforms
, uinfo
->data
[i
]);
2158 case QUNIFORM_UNIFORM
:
2159 cl_u32(&vc4
->uniforms
,
2160 gallium_uniforms
[uinfo
->data
[i
]]);
2162 case QUNIFORM_VIEWPORT_X_SCALE
:
2163 cl_f(&vc4
->uniforms
, vc4
->viewport
.scale
[0] * 16.0f
);
2165 case QUNIFORM_VIEWPORT_Y_SCALE
:
2166 cl_f(&vc4
->uniforms
, vc4
->viewport
.scale
[1] * 16.0f
);
2169 case QUNIFORM_VIEWPORT_Z_OFFSET
:
2170 cl_f(&vc4
->uniforms
, vc4
->viewport
.translate
[2]);
2172 case QUNIFORM_VIEWPORT_Z_SCALE
:
2173 cl_f(&vc4
->uniforms
, vc4
->viewport
.scale
[2]);
2176 case QUNIFORM_TEXTURE_CONFIG_P0
:
2177 write_texture_p0(vc4
, texstate
, uinfo
->data
[i
]);
2180 case QUNIFORM_TEXTURE_CONFIG_P1
:
2181 write_texture_p1(vc4
, texstate
, uinfo
->data
[i
]);
2184 case QUNIFORM_TEXTURE_CONFIG_P2
:
2185 write_texture_p2(vc4
, texstate
, uinfo
->data
[i
]);
2188 case QUNIFORM_TEXTURE_BORDER_COLOR
:
2189 write_texture_border_color(vc4
, texstate
, uinfo
->data
[i
]);
2192 case QUNIFORM_TEXRECT_SCALE_X
:
2193 case QUNIFORM_TEXRECT_SCALE_Y
:
2194 cl_u32(&vc4
->uniforms
,
2195 get_texrect_scale(texstate
,
2200 case QUNIFORM_BLEND_CONST_COLOR
:
2201 cl_f(&vc4
->uniforms
,
2202 vc4
->blend_color
.color
[uinfo
->data
[i
]]);
2205 case QUNIFORM_STENCIL
:
2206 cl_u32(&vc4
->uniforms
,
2207 vc4
->zsa
->stencil_uniforms
[uinfo
->data
[i
]] |
2208 (uinfo
->data
[i
] <= 1 ?
2209 (vc4
->stencil_ref
.ref_value
[uinfo
->data
[i
]] << 8) :
2213 case QUNIFORM_ALPHA_REF
:
2214 cl_f(&vc4
->uniforms
, vc4
->zsa
->base
.alpha
.ref_value
);
2218 uint32_t written_val
= *(uint32_t *)(vc4
->uniforms
.next
- 4);
2219 fprintf(stderr
, "%p/%d: %d: 0x%08x (%f)\n",
2220 shader
, shader_index
, i
, written_val
, uif(written_val
));
2226 vc4_fp_state_bind(struct pipe_context
*pctx
, void *hwcso
)
2228 struct vc4_context
*vc4
= vc4_context(pctx
);
2229 vc4
->prog
.bind_fs
= hwcso
;
2230 vc4
->prog
.dirty
|= VC4_SHADER_DIRTY_FP
;
2231 vc4
->dirty
|= VC4_DIRTY_PROG
;
2235 vc4_vp_state_bind(struct pipe_context
*pctx
, void *hwcso
)
2237 struct vc4_context
*vc4
= vc4_context(pctx
);
2238 vc4
->prog
.bind_vs
= hwcso
;
2239 vc4
->prog
.dirty
|= VC4_SHADER_DIRTY_VP
;
2240 vc4
->dirty
|= VC4_DIRTY_PROG
;
2244 vc4_program_init(struct pipe_context
*pctx
)
2246 struct vc4_context
*vc4
= vc4_context(pctx
);
2248 pctx
->create_vs_state
= vc4_shader_state_create
;
2249 pctx
->delete_vs_state
= vc4_shader_state_delete
;
2251 pctx
->create_fs_state
= vc4_shader_state_create
;
2252 pctx
->delete_fs_state
= vc4_shader_state_delete
;
2254 pctx
->bind_fs_state
= vc4_fp_state_bind
;
2255 pctx
->bind_vs_state
= vc4_vp_state_bind
;
2257 vc4
->fs_cache
= util_hash_table_create(fs_cache_hash
, fs_cache_compare
);
2258 vc4
->vs_cache
= util_hash_table_create(vs_cache_hash
, vs_cache_compare
);