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vc4: Make sure that vertex shader texture2D() calls use LOD 0.
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "util/u_format.h"
27 #include "util/u_hash.h"
28 #include "util/u_math.h"
29 #include "util/u_memory.h"
30 #include "util/ralloc.h"
31 #include "util/hash_table.h"
32 #include "tgsi/tgsi_dump.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "compiler/nir/nir.h"
35 #include "compiler/nir/nir_builder.h"
36 #include "nir/tgsi_to_nir.h"
37 #include "vc4_context.h"
38 #include "vc4_qpu.h"
39 #include "vc4_qir.h"
40 #include "mesa/state_tracker/st_glsl_types.h"
41
42 static struct qreg
43 ntq_get_src(struct vc4_compile *c, nir_src src, int i);
44 static void
45 ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list);
46
47 static void
48 resize_qreg_array(struct vc4_compile *c,
49 struct qreg **regs,
50 uint32_t *size,
51 uint32_t decl_size)
52 {
53 if (*size >= decl_size)
54 return;
55
56 uint32_t old_size = *size;
57 *size = MAX2(*size * 2, decl_size);
58 *regs = reralloc(c, *regs, struct qreg, *size);
59 if (!*regs) {
60 fprintf(stderr, "Malloc failure\n");
61 abort();
62 }
63
64 for (uint32_t i = old_size; i < *size; i++)
65 (*regs)[i] = c->undef;
66 }
67
68 static struct qreg
69 indirect_uniform_load(struct vc4_compile *c, nir_intrinsic_instr *intr)
70 {
71 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0);
72 uint32_t offset = nir_intrinsic_base(intr);
73 struct vc4_compiler_ubo_range *range = NULL;
74 unsigned i;
75 for (i = 0; i < c->num_uniform_ranges; i++) {
76 range = &c->ubo_ranges[i];
77 if (offset >= range->src_offset &&
78 offset < range->src_offset + range->size) {
79 break;
80 }
81 }
82 /* The driver-location-based offset always has to be within a declared
83 * uniform range.
84 */
85 assert(range);
86 if (!range->used) {
87 range->used = true;
88 range->dst_offset = c->next_ubo_dst_offset;
89 c->next_ubo_dst_offset += range->size;
90 c->num_ubo_ranges++;
91 }
92
93 offset -= range->src_offset;
94
95 /* Adjust for where we stored the TGSI register base. */
96 indirect_offset = qir_ADD(c, indirect_offset,
97 qir_uniform_ui(c, (range->dst_offset +
98 offset)));
99
100 /* Clamp to [0, array size). Note that MIN/MAX are signed. */
101 indirect_offset = qir_MAX(c, indirect_offset, qir_uniform_ui(c, 0));
102 indirect_offset = qir_MIN(c, indirect_offset,
103 qir_uniform_ui(c, (range->dst_offset +
104 range->size - 4)));
105
106 qir_TEX_DIRECT(c, indirect_offset, qir_uniform(c, QUNIFORM_UBO_ADDR, 0));
107 c->num_texture_samples++;
108 return qir_TEX_RESULT(c);
109 }
110
111 nir_ssa_def *
112 vc4_nir_get_swizzled_channel(nir_builder *b, nir_ssa_def **srcs, int swiz)
113 {
114 switch (swiz) {
115 default:
116 case PIPE_SWIZZLE_NONE:
117 fprintf(stderr, "warning: unknown swizzle\n");
118 /* FALLTHROUGH */
119 case PIPE_SWIZZLE_0:
120 return nir_imm_float(b, 0.0);
121 case PIPE_SWIZZLE_1:
122 return nir_imm_float(b, 1.0);
123 case PIPE_SWIZZLE_X:
124 case PIPE_SWIZZLE_Y:
125 case PIPE_SWIZZLE_Z:
126 case PIPE_SWIZZLE_W:
127 return srcs[swiz];
128 }
129 }
130
131 static struct qreg *
132 ntq_init_ssa_def(struct vc4_compile *c, nir_ssa_def *def)
133 {
134 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
135 def->num_components);
136 _mesa_hash_table_insert(c->def_ht, def, qregs);
137 return qregs;
138 }
139
140 /**
141 * This function is responsible for getting QIR results into the associated
142 * storage for a NIR instruction.
143 *
144 * If it's a NIR SSA def, then we just set the associated hash table entry to
145 * the new result.
146 *
147 * If it's a NIR reg, then we need to update the existing qreg assigned to the
148 * NIR destination with the incoming value. To do that without introducing
149 * new MOVs, we require that the incoming qreg either be a uniform, or be
150 * SSA-defined by the previous QIR instruction in the block and rewritable by
151 * this function. That lets us sneak ahead and insert the SF flag beforehand
152 * (knowing that the previous instruction doesn't depend on flags) and rewrite
153 * its destination to be the NIR reg's destination
154 */
155 static void
156 ntq_store_dest(struct vc4_compile *c, nir_dest *dest, int chan,
157 struct qreg result)
158 {
159 struct qinst *last_inst = NULL;
160 if (!list_empty(&c->cur_block->instructions))
161 last_inst = (struct qinst *)c->cur_block->instructions.prev;
162
163 assert(result.file == QFILE_UNIF ||
164 (result.file == QFILE_TEMP &&
165 last_inst && last_inst == c->defs[result.index]));
166
167 if (dest->is_ssa) {
168 assert(chan < dest->ssa.num_components);
169
170 struct qreg *qregs;
171 struct hash_entry *entry =
172 _mesa_hash_table_search(c->def_ht, &dest->ssa);
173
174 if (entry)
175 qregs = entry->data;
176 else
177 qregs = ntq_init_ssa_def(c, &dest->ssa);
178
179 qregs[chan] = result;
180 } else {
181 nir_register *reg = dest->reg.reg;
182 assert(dest->reg.base_offset == 0);
183 assert(reg->num_array_elems == 0);
184 struct hash_entry *entry =
185 _mesa_hash_table_search(c->def_ht, reg);
186 struct qreg *qregs = entry->data;
187
188 /* Insert a MOV if the source wasn't an SSA def in the
189 * previous instruction.
190 */
191 if (result.file == QFILE_UNIF) {
192 result = qir_MOV(c, result);
193 last_inst = c->defs[result.index];
194 }
195
196 /* We know they're both temps, so just rewrite index. */
197 c->defs[last_inst->dst.index] = NULL;
198 last_inst->dst.index = qregs[chan].index;
199
200 /* If we're in control flow, then make this update of the reg
201 * conditional on the execution mask.
202 */
203 if (c->execute.file != QFILE_NULL) {
204 last_inst->dst.index = qregs[chan].index;
205
206 /* Set the flags to the current exec mask. To insert
207 * the SF, we temporarily remove our SSA instruction.
208 */
209 list_del(&last_inst->link);
210 qir_SF(c, c->execute);
211 list_addtail(&last_inst->link,
212 &c->cur_block->instructions);
213
214 last_inst->cond = QPU_COND_ZS;
215 last_inst->cond_is_exec_mask = true;
216 }
217 }
218 }
219
220 static struct qreg *
221 ntq_get_dest(struct vc4_compile *c, nir_dest *dest)
222 {
223 if (dest->is_ssa) {
224 struct qreg *qregs = ntq_init_ssa_def(c, &dest->ssa);
225 for (int i = 0; i < dest->ssa.num_components; i++)
226 qregs[i] = c->undef;
227 return qregs;
228 } else {
229 nir_register *reg = dest->reg.reg;
230 assert(dest->reg.base_offset == 0);
231 assert(reg->num_array_elems == 0);
232 struct hash_entry *entry =
233 _mesa_hash_table_search(c->def_ht, reg);
234 return entry->data;
235 }
236 }
237
238 static struct qreg
239 ntq_get_src(struct vc4_compile *c, nir_src src, int i)
240 {
241 struct hash_entry *entry;
242 if (src.is_ssa) {
243 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
244 assert(i < src.ssa->num_components);
245 } else {
246 nir_register *reg = src.reg.reg;
247 entry = _mesa_hash_table_search(c->def_ht, reg);
248 assert(reg->num_array_elems == 0);
249 assert(src.reg.base_offset == 0);
250 assert(i < reg->num_components);
251 }
252
253 struct qreg *qregs = entry->data;
254 return qregs[i];
255 }
256
257 static struct qreg
258 ntq_get_alu_src(struct vc4_compile *c, nir_alu_instr *instr,
259 unsigned src)
260 {
261 assert(util_is_power_of_two(instr->dest.write_mask));
262 unsigned chan = ffs(instr->dest.write_mask) - 1;
263 struct qreg r = ntq_get_src(c, instr->src[src].src,
264 instr->src[src].swizzle[chan]);
265
266 assert(!instr->src[src].abs);
267 assert(!instr->src[src].negate);
268
269 return r;
270 };
271
272 static inline struct qreg
273 qir_SAT(struct vc4_compile *c, struct qreg val)
274 {
275 return qir_FMAX(c,
276 qir_FMIN(c, val, qir_uniform_f(c, 1.0)),
277 qir_uniform_f(c, 0.0));
278 }
279
280 static struct qreg
281 ntq_rcp(struct vc4_compile *c, struct qreg x)
282 {
283 struct qreg r = qir_RCP(c, x);
284
285 /* Apply a Newton-Raphson step to improve the accuracy. */
286 r = qir_FMUL(c, r, qir_FSUB(c,
287 qir_uniform_f(c, 2.0),
288 qir_FMUL(c, x, r)));
289
290 return r;
291 }
292
293 static struct qreg
294 ntq_rsq(struct vc4_compile *c, struct qreg x)
295 {
296 struct qreg r = qir_RSQ(c, x);
297
298 /* Apply a Newton-Raphson step to improve the accuracy. */
299 r = qir_FMUL(c, r, qir_FSUB(c,
300 qir_uniform_f(c, 1.5),
301 qir_FMUL(c,
302 qir_uniform_f(c, 0.5),
303 qir_FMUL(c, x,
304 qir_FMUL(c, r, r)))));
305
306 return r;
307 }
308
309 static struct qreg
310 ntq_umul(struct vc4_compile *c, struct qreg src0, struct qreg src1)
311 {
312 struct qreg src0_hi = qir_SHR(c, src0,
313 qir_uniform_ui(c, 24));
314 struct qreg src1_hi = qir_SHR(c, src1,
315 qir_uniform_ui(c, 24));
316
317 struct qreg hilo = qir_MUL24(c, src0_hi, src1);
318 struct qreg lohi = qir_MUL24(c, src0, src1_hi);
319 struct qreg lolo = qir_MUL24(c, src0, src1);
320
321 return qir_ADD(c, lolo, qir_SHL(c,
322 qir_ADD(c, hilo, lohi),
323 qir_uniform_ui(c, 24)));
324 }
325
326 static struct qreg
327 ntq_scale_depth_texture(struct vc4_compile *c, struct qreg src)
328 {
329 struct qreg depthf = qir_ITOF(c, qir_SHR(c, src,
330 qir_uniform_ui(c, 8)));
331 return qir_FMUL(c, depthf, qir_uniform_f(c, 1.0f/0xffffff));
332 }
333
334 /**
335 * Emits a lowered TXF_MS from an MSAA texture.
336 *
337 * The addressing math has been lowered in NIR, and now we just need to read
338 * it like a UBO.
339 */
340 static void
341 ntq_emit_txf(struct vc4_compile *c, nir_tex_instr *instr)
342 {
343 uint32_t tile_width = 32;
344 uint32_t tile_height = 32;
345 uint32_t tile_size = (tile_height * tile_width *
346 VC4_MAX_SAMPLES * sizeof(uint32_t));
347
348 unsigned unit = instr->texture_index;
349 uint32_t w = align(c->key->tex[unit].msaa_width, tile_width);
350 uint32_t w_tiles = w / tile_width;
351 uint32_t h = align(c->key->tex[unit].msaa_height, tile_height);
352 uint32_t h_tiles = h / tile_height;
353 uint32_t size = w_tiles * h_tiles * tile_size;
354
355 struct qreg addr;
356 assert(instr->num_srcs == 1);
357 assert(instr->src[0].src_type == nir_tex_src_coord);
358 addr = ntq_get_src(c, instr->src[0].src, 0);
359
360 /* Perform the clamping required by kernel validation. */
361 addr = qir_MAX(c, addr, qir_uniform_ui(c, 0));
362 addr = qir_MIN(c, addr, qir_uniform_ui(c, size - 4));
363
364 qir_TEX_DIRECT(c, addr, qir_uniform(c, QUNIFORM_TEXTURE_MSAA_ADDR, unit));
365
366 struct qreg tex = qir_TEX_RESULT(c);
367 c->num_texture_samples++;
368
369 enum pipe_format format = c->key->tex[unit].format;
370 if (util_format_is_depth_or_stencil(format)) {
371 struct qreg scaled = ntq_scale_depth_texture(c, tex);
372 for (int i = 0; i < 4; i++)
373 ntq_store_dest(c, &instr->dest, i, qir_MOV(c, scaled));
374 } else {
375 for (int i = 0; i < 4; i++)
376 ntq_store_dest(c, &instr->dest, i,
377 qir_UNPACK_8_F(c, tex, i));
378 }
379 }
380
381 static void
382 ntq_emit_tex(struct vc4_compile *c, nir_tex_instr *instr)
383 {
384 struct qreg s, t, r, lod, compare;
385 bool is_txb = false, is_txl = false;
386 unsigned unit = instr->texture_index;
387
388 if (instr->op == nir_texop_txf) {
389 ntq_emit_txf(c, instr);
390 return;
391 }
392
393 for (unsigned i = 0; i < instr->num_srcs; i++) {
394 switch (instr->src[i].src_type) {
395 case nir_tex_src_coord:
396 s = ntq_get_src(c, instr->src[i].src, 0);
397 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D)
398 t = qir_uniform_f(c, 0.5);
399 else
400 t = ntq_get_src(c, instr->src[i].src, 1);
401 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
402 r = ntq_get_src(c, instr->src[i].src, 2);
403 break;
404 case nir_tex_src_bias:
405 lod = ntq_get_src(c, instr->src[i].src, 0);
406 is_txb = true;
407 break;
408 case nir_tex_src_lod:
409 lod = ntq_get_src(c, instr->src[i].src, 0);
410 is_txl = true;
411 break;
412 case nir_tex_src_comparitor:
413 compare = ntq_get_src(c, instr->src[i].src, 0);
414 break;
415 default:
416 unreachable("unknown texture source");
417 }
418 }
419
420 if (c->stage != QSTAGE_FRAG && !is_txl) {
421 /* From the GLSL 1.20 spec:
422 *
423 * "If it is mip-mapped and running on the vertex shader,
424 * then the base texture is used."
425 */
426 is_txl = true;
427 lod = qir_uniform_ui(c, 0);
428 }
429
430 if (c->key->tex[unit].force_first_level) {
431 lod = qir_uniform(c, QUNIFORM_TEXTURE_FIRST_LEVEL, unit);
432 is_txl = true;
433 is_txb = false;
434 }
435
436 struct qreg texture_u[] = {
437 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit),
438 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
439 qir_uniform(c, QUNIFORM_CONSTANT, 0),
440 qir_uniform(c, QUNIFORM_CONSTANT, 0),
441 };
442 uint32_t next_texture_u = 0;
443
444 /* There is no native support for GL texture rectangle coordinates, so
445 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
446 * 1]).
447 */
448 if (instr->sampler_dim == GLSL_SAMPLER_DIM_RECT) {
449 s = qir_FMUL(c, s,
450 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_X, unit));
451 t = qir_FMUL(c, t,
452 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_Y, unit));
453 }
454
455 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE || is_txl) {
456 texture_u[2] = qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P2,
457 unit | (is_txl << 16));
458 }
459
460 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
461 qir_TEX_R(c, r, texture_u[next_texture_u++]);
462 } else if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
463 c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP ||
464 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
465 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
466 qir_TEX_R(c, qir_uniform(c, QUNIFORM_TEXTURE_BORDER_COLOR, unit),
467 texture_u[next_texture_u++]);
468 }
469
470 if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP) {
471 s = qir_SAT(c, s);
472 }
473
474 if (c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
475 t = qir_SAT(c, t);
476 }
477
478 qir_TEX_T(c, t, texture_u[next_texture_u++]);
479
480 if (is_txl || is_txb)
481 qir_TEX_B(c, lod, texture_u[next_texture_u++]);
482
483 qir_TEX_S(c, s, texture_u[next_texture_u++]);
484
485 c->num_texture_samples++;
486 struct qreg tex = qir_TEX_RESULT(c);
487
488 enum pipe_format format = c->key->tex[unit].format;
489
490 struct qreg *dest = ntq_get_dest(c, &instr->dest);
491 if (util_format_is_depth_or_stencil(format)) {
492 struct qreg normalized = ntq_scale_depth_texture(c, tex);
493 struct qreg depth_output;
494
495 struct qreg u0 = qir_uniform_f(c, 0.0f);
496 struct qreg u1 = qir_uniform_f(c, 1.0f);
497 if (c->key->tex[unit].compare_mode) {
498 switch (c->key->tex[unit].compare_func) {
499 case PIPE_FUNC_NEVER:
500 depth_output = qir_uniform_f(c, 0.0f);
501 break;
502 case PIPE_FUNC_ALWAYS:
503 depth_output = u1;
504 break;
505 case PIPE_FUNC_EQUAL:
506 qir_SF(c, qir_FSUB(c, compare, normalized));
507 depth_output = qir_SEL(c, QPU_COND_ZS, u1, u0);
508 break;
509 case PIPE_FUNC_NOTEQUAL:
510 qir_SF(c, qir_FSUB(c, compare, normalized));
511 depth_output = qir_SEL(c, QPU_COND_ZC, u1, u0);
512 break;
513 case PIPE_FUNC_GREATER:
514 qir_SF(c, qir_FSUB(c, compare, normalized));
515 depth_output = qir_SEL(c, QPU_COND_NC, u1, u0);
516 break;
517 case PIPE_FUNC_GEQUAL:
518 qir_SF(c, qir_FSUB(c, normalized, compare));
519 depth_output = qir_SEL(c, QPU_COND_NS, u1, u0);
520 break;
521 case PIPE_FUNC_LESS:
522 qir_SF(c, qir_FSUB(c, compare, normalized));
523 depth_output = qir_SEL(c, QPU_COND_NS, u1, u0);
524 break;
525 case PIPE_FUNC_LEQUAL:
526 qir_SF(c, qir_FSUB(c, normalized, compare));
527 depth_output = qir_SEL(c, QPU_COND_NC, u1, u0);
528 break;
529 }
530 } else {
531 depth_output = normalized;
532 }
533
534 for (int i = 0; i < 4; i++)
535 dest[i] = depth_output;
536 } else {
537 for (int i = 0; i < 4; i++)
538 dest[i] = qir_UNPACK_8_F(c, tex, i);
539 }
540 }
541
542 /**
543 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
544 * to zero).
545 */
546 static struct qreg
547 ntq_ffract(struct vc4_compile *c, struct qreg src)
548 {
549 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
550 struct qreg diff = qir_FSUB(c, src, trunc);
551 qir_SF(c, diff);
552 return qir_MOV(c, qir_SEL(c, QPU_COND_NS,
553 qir_FADD(c, diff, qir_uniform_f(c, 1.0)),
554 diff));
555 }
556
557 /**
558 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
559 * zero).
560 */
561 static struct qreg
562 ntq_ffloor(struct vc4_compile *c, struct qreg src)
563 {
564 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
565
566 /* This will be < 0 if we truncated and the truncation was of a value
567 * that was < 0 in the first place.
568 */
569 qir_SF(c, qir_FSUB(c, src, trunc));
570
571 return qir_MOV(c, qir_SEL(c, QPU_COND_NS,
572 qir_FSUB(c, trunc, qir_uniform_f(c, 1.0)),
573 trunc));
574 }
575
576 /**
577 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
578 * zero).
579 */
580 static struct qreg
581 ntq_fceil(struct vc4_compile *c, struct qreg src)
582 {
583 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
584
585 /* This will be < 0 if we truncated and the truncation was of a value
586 * that was > 0 in the first place.
587 */
588 qir_SF(c, qir_FSUB(c, trunc, src));
589
590 return qir_MOV(c, qir_SEL(c, QPU_COND_NS,
591 qir_FADD(c, trunc, qir_uniform_f(c, 1.0)),
592 trunc));
593 }
594
595 static struct qreg
596 ntq_fsin(struct vc4_compile *c, struct qreg src)
597 {
598 float coeff[] = {
599 -2.0 * M_PI,
600 pow(2.0 * M_PI, 3) / (3 * 2 * 1),
601 -pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
602 pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
603 -pow(2.0 * M_PI, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
604 };
605
606 struct qreg scaled_x =
607 qir_FMUL(c,
608 src,
609 qir_uniform_f(c, 1.0 / (M_PI * 2.0)));
610
611 struct qreg x = qir_FADD(c,
612 ntq_ffract(c, scaled_x),
613 qir_uniform_f(c, -0.5));
614 struct qreg x2 = qir_FMUL(c, x, x);
615 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
616 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
617 x = qir_FMUL(c, x, x2);
618 sum = qir_FADD(c,
619 sum,
620 qir_FMUL(c,
621 x,
622 qir_uniform_f(c, coeff[i])));
623 }
624 return sum;
625 }
626
627 static struct qreg
628 ntq_fcos(struct vc4_compile *c, struct qreg src)
629 {
630 float coeff[] = {
631 -1.0f,
632 pow(2.0 * M_PI, 2) / (2 * 1),
633 -pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
634 pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
635 -pow(2.0 * M_PI, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
636 pow(2.0 * M_PI, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
637 };
638
639 struct qreg scaled_x =
640 qir_FMUL(c, src,
641 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
642 struct qreg x_frac = qir_FADD(c,
643 ntq_ffract(c, scaled_x),
644 qir_uniform_f(c, -0.5));
645
646 struct qreg sum = qir_uniform_f(c, coeff[0]);
647 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
648 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
649 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
650 if (i != 1)
651 x = qir_FMUL(c, x, x2);
652
653 struct qreg mul = qir_FMUL(c,
654 x,
655 qir_uniform_f(c, coeff[i]));
656 if (i == 0)
657 sum = mul;
658 else
659 sum = qir_FADD(c, sum, mul);
660 }
661 return sum;
662 }
663
664 static struct qreg
665 ntq_fsign(struct vc4_compile *c, struct qreg src)
666 {
667 struct qreg t = qir_get_temp(c);
668
669 qir_SF(c, src);
670 qir_MOV_dest(c, t, qir_uniform_f(c, 0.0));
671 qir_MOV_dest(c, t, qir_uniform_f(c, 1.0))->cond = QPU_COND_ZC;
672 qir_MOV_dest(c, t, qir_uniform_f(c, -1.0))->cond = QPU_COND_NS;
673 return qir_MOV(c, t);
674 }
675
676 static void
677 emit_vertex_input(struct vc4_compile *c, int attr)
678 {
679 enum pipe_format format = c->vs_key->attr_formats[attr];
680 uint32_t attr_size = util_format_get_blocksize(format);
681
682 c->vattr_sizes[attr] = align(attr_size, 4);
683 for (int i = 0; i < align(attr_size, 4) / 4; i++) {
684 c->inputs[attr * 4 + i] =
685 qir_MOV(c, qir_reg(QFILE_VPM, attr * 4 + i));
686 c->num_inputs++;
687 }
688 }
689
690 static void
691 emit_fragcoord_input(struct vc4_compile *c, int attr)
692 {
693 c->inputs[attr * 4 + 0] = qir_ITOF(c, qir_reg(QFILE_FRAG_X, 0));
694 c->inputs[attr * 4 + 1] = qir_ITOF(c, qir_reg(QFILE_FRAG_Y, 0));
695 c->inputs[attr * 4 + 2] =
696 qir_FMUL(c,
697 qir_ITOF(c, qir_FRAG_Z(c)),
698 qir_uniform_f(c, 1.0 / 0xffffff));
699 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
700 }
701
702 static struct qreg
703 emit_fragment_varying(struct vc4_compile *c, gl_varying_slot slot,
704 uint8_t swizzle)
705 {
706 uint32_t i = c->num_input_slots++;
707 struct qreg vary = {
708 QFILE_VARY,
709 i
710 };
711
712 if (c->num_input_slots >= c->input_slots_array_size) {
713 c->input_slots_array_size =
714 MAX2(4, c->input_slots_array_size * 2);
715
716 c->input_slots = reralloc(c, c->input_slots,
717 struct vc4_varying_slot,
718 c->input_slots_array_size);
719 }
720
721 c->input_slots[i].slot = slot;
722 c->input_slots[i].swizzle = swizzle;
723
724 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
725 }
726
727 static void
728 emit_fragment_input(struct vc4_compile *c, int attr, gl_varying_slot slot)
729 {
730 for (int i = 0; i < 4; i++) {
731 c->inputs[attr * 4 + i] =
732 emit_fragment_varying(c, slot, i);
733 c->num_inputs++;
734 }
735 }
736
737 static void
738 add_output(struct vc4_compile *c,
739 uint32_t decl_offset,
740 uint8_t slot,
741 uint8_t swizzle)
742 {
743 uint32_t old_array_size = c->outputs_array_size;
744 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
745 decl_offset + 1);
746
747 if (old_array_size != c->outputs_array_size) {
748 c->output_slots = reralloc(c,
749 c->output_slots,
750 struct vc4_varying_slot,
751 c->outputs_array_size);
752 }
753
754 c->output_slots[decl_offset].slot = slot;
755 c->output_slots[decl_offset].swizzle = swizzle;
756 }
757
758 static void
759 declare_uniform_range(struct vc4_compile *c, uint32_t start, uint32_t size)
760 {
761 unsigned array_id = c->num_uniform_ranges++;
762 if (array_id >= c->ubo_ranges_array_size) {
763 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
764 array_id + 1);
765 c->ubo_ranges = reralloc(c, c->ubo_ranges,
766 struct vc4_compiler_ubo_range,
767 c->ubo_ranges_array_size);
768 }
769
770 c->ubo_ranges[array_id].dst_offset = 0;
771 c->ubo_ranges[array_id].src_offset = start;
772 c->ubo_ranges[array_id].size = size;
773 c->ubo_ranges[array_id].used = false;
774 }
775
776 static bool
777 ntq_src_is_only_ssa_def_user(nir_src *src)
778 {
779 if (!src->is_ssa)
780 return false;
781
782 if (!list_empty(&src->ssa->if_uses))
783 return false;
784
785 return (src->ssa->uses.next == &src->use_link &&
786 src->ssa->uses.next->next == &src->ssa->uses);
787 }
788
789 /**
790 * In general, emits a nir_pack_unorm_4x8 as a series of MOVs with the pack
791 * bit set.
792 *
793 * However, as an optimization, it tries to find the instructions generating
794 * the sources to be packed and just emit the pack flag there, if possible.
795 */
796 static void
797 ntq_emit_pack_unorm_4x8(struct vc4_compile *c, nir_alu_instr *instr)
798 {
799 struct qreg result = qir_get_temp(c);
800 struct nir_alu_instr *vec4 = NULL;
801
802 /* If packing from a vec4 op (as expected), identify it so that we can
803 * peek back at what generated its sources.
804 */
805 if (instr->src[0].src.is_ssa &&
806 instr->src[0].src.ssa->parent_instr->type == nir_instr_type_alu &&
807 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr)->op ==
808 nir_op_vec4) {
809 vec4 = nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
810 }
811
812 /* If the pack is replicating the same channel 4 times, use the 8888
813 * pack flag. This is common for blending using the alpha
814 * channel.
815 */
816 if (instr->src[0].swizzle[0] == instr->src[0].swizzle[1] &&
817 instr->src[0].swizzle[0] == instr->src[0].swizzle[2] &&
818 instr->src[0].swizzle[0] == instr->src[0].swizzle[3]) {
819 struct qreg rep = ntq_get_src(c,
820 instr->src[0].src,
821 instr->src[0].swizzle[0]);
822 ntq_store_dest(c, &instr->dest.dest, 0, qir_PACK_8888_F(c, rep));
823 return;
824 }
825
826 for (int i = 0; i < 4; i++) {
827 int swiz = instr->src[0].swizzle[i];
828 struct qreg src;
829 if (vec4) {
830 src = ntq_get_src(c, vec4->src[swiz].src,
831 vec4->src[swiz].swizzle[0]);
832 } else {
833 src = ntq_get_src(c, instr->src[0].src, swiz);
834 }
835
836 if (vec4 &&
837 ntq_src_is_only_ssa_def_user(&vec4->src[swiz].src) &&
838 src.file == QFILE_TEMP &&
839 c->defs[src.index] &&
840 qir_is_mul(c->defs[src.index]) &&
841 !c->defs[src.index]->dst.pack) {
842 struct qinst *rewrite = c->defs[src.index];
843 c->defs[src.index] = NULL;
844 rewrite->dst = result;
845 rewrite->dst.pack = QPU_PACK_MUL_8A + i;
846 continue;
847 }
848
849 qir_PACK_8_F(c, result, src, i);
850 }
851
852 ntq_store_dest(c, &instr->dest.dest, 0, qir_MOV(c, result));
853 }
854
855 /** Handles sign-extended bitfield extracts for 16 bits. */
856 static struct qreg
857 ntq_emit_ibfe(struct vc4_compile *c, struct qreg base, struct qreg offset,
858 struct qreg bits)
859 {
860 assert(bits.file == QFILE_UNIF &&
861 c->uniform_contents[bits.index] == QUNIFORM_CONSTANT &&
862 c->uniform_data[bits.index] == 16);
863
864 assert(offset.file == QFILE_UNIF &&
865 c->uniform_contents[offset.index] == QUNIFORM_CONSTANT);
866 int offset_bit = c->uniform_data[offset.index];
867 assert(offset_bit % 16 == 0);
868
869 return qir_UNPACK_16_I(c, base, offset_bit / 16);
870 }
871
872 /** Handles unsigned bitfield extracts for 8 bits. */
873 static struct qreg
874 ntq_emit_ubfe(struct vc4_compile *c, struct qreg base, struct qreg offset,
875 struct qreg bits)
876 {
877 assert(bits.file == QFILE_UNIF &&
878 c->uniform_contents[bits.index] == QUNIFORM_CONSTANT &&
879 c->uniform_data[bits.index] == 8);
880
881 assert(offset.file == QFILE_UNIF &&
882 c->uniform_contents[offset.index] == QUNIFORM_CONSTANT);
883 int offset_bit = c->uniform_data[offset.index];
884 assert(offset_bit % 8 == 0);
885
886 return qir_UNPACK_8_I(c, base, offset_bit / 8);
887 }
888
889 /**
890 * If compare_instr is a valid comparison instruction, emits the
891 * compare_instr's comparison and returns the sel_instr's return value based
892 * on the compare_instr's result.
893 */
894 static bool
895 ntq_emit_comparison(struct vc4_compile *c, struct qreg *dest,
896 nir_alu_instr *compare_instr,
897 nir_alu_instr *sel_instr)
898 {
899 enum qpu_cond cond;
900
901 switch (compare_instr->op) {
902 case nir_op_feq:
903 case nir_op_ieq:
904 case nir_op_seq:
905 cond = QPU_COND_ZS;
906 break;
907 case nir_op_fne:
908 case nir_op_ine:
909 case nir_op_sne:
910 cond = QPU_COND_ZC;
911 break;
912 case nir_op_fge:
913 case nir_op_ige:
914 case nir_op_uge:
915 case nir_op_sge:
916 cond = QPU_COND_NC;
917 break;
918 case nir_op_flt:
919 case nir_op_ilt:
920 case nir_op_slt:
921 cond = QPU_COND_NS;
922 break;
923 default:
924 return false;
925 }
926
927 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
928 struct qreg src1 = ntq_get_alu_src(c, compare_instr, 1);
929
930 unsigned unsized_type =
931 nir_alu_type_get_base_type(nir_op_infos[compare_instr->op].input_types[0]);
932 if (unsized_type == nir_type_float)
933 qir_SF(c, qir_FSUB(c, src0, src1));
934 else
935 qir_SF(c, qir_SUB(c, src0, src1));
936
937 switch (sel_instr->op) {
938 case nir_op_seq:
939 case nir_op_sne:
940 case nir_op_sge:
941 case nir_op_slt:
942 *dest = qir_SEL(c, cond,
943 qir_uniform_f(c, 1.0), qir_uniform_f(c, 0.0));
944 break;
945
946 case nir_op_bcsel:
947 *dest = qir_SEL(c, cond,
948 ntq_get_alu_src(c, sel_instr, 1),
949 ntq_get_alu_src(c, sel_instr, 2));
950 break;
951
952 default:
953 *dest = qir_SEL(c, cond,
954 qir_uniform_ui(c, ~0), qir_uniform_ui(c, 0));
955 break;
956 }
957
958 /* Make the temporary for nir_store_dest(). */
959 *dest = qir_MOV(c, *dest);
960
961 return true;
962 }
963
964 /**
965 * Attempts to fold a comparison generating a boolean result into the
966 * condition code for selecting between two values, instead of comparing the
967 * boolean result against 0 to generate the condition code.
968 */
969 static struct qreg ntq_emit_bcsel(struct vc4_compile *c, nir_alu_instr *instr,
970 struct qreg *src)
971 {
972 if (!instr->src[0].src.is_ssa)
973 goto out;
974 if (instr->src[0].src.ssa->parent_instr->type != nir_instr_type_alu)
975 goto out;
976 nir_alu_instr *compare =
977 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
978 if (!compare)
979 goto out;
980
981 struct qreg dest;
982 if (ntq_emit_comparison(c, &dest, compare, instr))
983 return dest;
984
985 out:
986 qir_SF(c, src[0]);
987 return qir_MOV(c, qir_SEL(c, QPU_COND_NS, src[1], src[2]));
988 }
989
990 static struct qreg
991 ntq_fddx(struct vc4_compile *c, struct qreg src)
992 {
993 /* Make sure that we have a bare temp to use for MUL rotation, so it
994 * can be allocated to an accumulator.
995 */
996 if (src.pack || src.file != QFILE_TEMP)
997 src = qir_MOV(c, src);
998
999 struct qreg from_left = qir_ROT_MUL(c, src, 1);
1000 struct qreg from_right = qir_ROT_MUL(c, src, 15);
1001
1002 /* Distinguish left/right pixels of the quad. */
1003 qir_SF(c, qir_AND(c, qir_reg(QFILE_QPU_ELEMENT, 0),
1004 qir_uniform_ui(c, 1)));
1005
1006 return qir_MOV(c, qir_SEL(c, QPU_COND_ZS,
1007 qir_FSUB(c, from_right, src),
1008 qir_FSUB(c, src, from_left)));
1009 }
1010
1011 static struct qreg
1012 ntq_fddy(struct vc4_compile *c, struct qreg src)
1013 {
1014 if (src.pack || src.file != QFILE_TEMP)
1015 src = qir_MOV(c, src);
1016
1017 struct qreg from_bottom = qir_ROT_MUL(c, src, 2);
1018 struct qreg from_top = qir_ROT_MUL(c, src, 14);
1019
1020 /* Distinguish top/bottom pixels of the quad. */
1021 qir_SF(c, qir_AND(c,
1022 qir_reg(QFILE_QPU_ELEMENT, 0),
1023 qir_uniform_ui(c, 2)));
1024
1025 return qir_MOV(c, qir_SEL(c, QPU_COND_ZS,
1026 qir_FSUB(c, from_top, src),
1027 qir_FSUB(c, src, from_bottom)));
1028 }
1029
1030 static void
1031 ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr)
1032 {
1033 /* This should always be lowered to ALU operations for VC4. */
1034 assert(!instr->dest.saturate);
1035
1036 /* Vectors are special in that they have non-scalarized writemasks,
1037 * and just take the first swizzle channel for each argument in order
1038 * into each writemask channel.
1039 */
1040 if (instr->op == nir_op_vec2 ||
1041 instr->op == nir_op_vec3 ||
1042 instr->op == nir_op_vec4) {
1043 struct qreg srcs[4];
1044 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1045 srcs[i] = ntq_get_src(c, instr->src[i].src,
1046 instr->src[i].swizzle[0]);
1047 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1048 ntq_store_dest(c, &instr->dest.dest, i,
1049 qir_MOV(c, srcs[i]));
1050 return;
1051 }
1052
1053 if (instr->op == nir_op_pack_unorm_4x8) {
1054 ntq_emit_pack_unorm_4x8(c, instr);
1055 return;
1056 }
1057
1058 if (instr->op == nir_op_unpack_unorm_4x8) {
1059 struct qreg src = ntq_get_src(c, instr->src[0].src,
1060 instr->src[0].swizzle[0]);
1061 for (int i = 0; i < 4; i++) {
1062 if (instr->dest.write_mask & (1 << i))
1063 ntq_store_dest(c, &instr->dest.dest, i,
1064 qir_UNPACK_8_F(c, src, i));
1065 }
1066 return;
1067 }
1068
1069 /* General case: We can just grab the one used channel per src. */
1070 struct qreg src[nir_op_infos[instr->op].num_inputs];
1071 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
1072 src[i] = ntq_get_alu_src(c, instr, i);
1073 }
1074
1075 struct qreg result;
1076
1077 switch (instr->op) {
1078 case nir_op_fmov:
1079 case nir_op_imov:
1080 result = qir_MOV(c, src[0]);
1081 break;
1082 case nir_op_fmul:
1083 result = qir_FMUL(c, src[0], src[1]);
1084 break;
1085 case nir_op_fadd:
1086 result = qir_FADD(c, src[0], src[1]);
1087 break;
1088 case nir_op_fsub:
1089 result = qir_FSUB(c, src[0], src[1]);
1090 break;
1091 case nir_op_fmin:
1092 result = qir_FMIN(c, src[0], src[1]);
1093 break;
1094 case nir_op_fmax:
1095 result = qir_FMAX(c, src[0], src[1]);
1096 break;
1097
1098 case nir_op_f2i:
1099 case nir_op_f2u:
1100 result = qir_FTOI(c, src[0]);
1101 break;
1102 case nir_op_i2f:
1103 case nir_op_u2f:
1104 result = qir_ITOF(c, src[0]);
1105 break;
1106 case nir_op_b2f:
1107 result = qir_AND(c, src[0], qir_uniform_f(c, 1.0));
1108 break;
1109 case nir_op_b2i:
1110 result = qir_AND(c, src[0], qir_uniform_ui(c, 1));
1111 break;
1112 case nir_op_i2b:
1113 case nir_op_f2b:
1114 qir_SF(c, src[0]);
1115 result = qir_MOV(c, qir_SEL(c, QPU_COND_ZC,
1116 qir_uniform_ui(c, ~0),
1117 qir_uniform_ui(c, 0)));
1118 break;
1119
1120 case nir_op_iadd:
1121 result = qir_ADD(c, src[0], src[1]);
1122 break;
1123 case nir_op_ushr:
1124 result = qir_SHR(c, src[0], src[1]);
1125 break;
1126 case nir_op_isub:
1127 result = qir_SUB(c, src[0], src[1]);
1128 break;
1129 case nir_op_ishr:
1130 result = qir_ASR(c, src[0], src[1]);
1131 break;
1132 case nir_op_ishl:
1133 result = qir_SHL(c, src[0], src[1]);
1134 break;
1135 case nir_op_imin:
1136 result = qir_MIN(c, src[0], src[1]);
1137 break;
1138 case nir_op_imax:
1139 result = qir_MAX(c, src[0], src[1]);
1140 break;
1141 case nir_op_iand:
1142 result = qir_AND(c, src[0], src[1]);
1143 break;
1144 case nir_op_ior:
1145 result = qir_OR(c, src[0], src[1]);
1146 break;
1147 case nir_op_ixor:
1148 result = qir_XOR(c, src[0], src[1]);
1149 break;
1150 case nir_op_inot:
1151 result = qir_NOT(c, src[0]);
1152 break;
1153
1154 case nir_op_imul:
1155 result = ntq_umul(c, src[0], src[1]);
1156 break;
1157
1158 case nir_op_seq:
1159 case nir_op_sne:
1160 case nir_op_sge:
1161 case nir_op_slt:
1162 case nir_op_feq:
1163 case nir_op_fne:
1164 case nir_op_fge:
1165 case nir_op_flt:
1166 case nir_op_ieq:
1167 case nir_op_ine:
1168 case nir_op_ige:
1169 case nir_op_uge:
1170 case nir_op_ilt:
1171 if (!ntq_emit_comparison(c, &result, instr, instr)) {
1172 fprintf(stderr, "Bad comparison instruction\n");
1173 }
1174 break;
1175
1176 case nir_op_bcsel:
1177 result = ntq_emit_bcsel(c, instr, src);
1178 break;
1179 case nir_op_fcsel:
1180 qir_SF(c, src[0]);
1181 result = qir_MOV(c, qir_SEL(c, QPU_COND_ZC, src[1], src[2]));
1182 break;
1183
1184 case nir_op_frcp:
1185 result = ntq_rcp(c, src[0]);
1186 break;
1187 case nir_op_frsq:
1188 result = ntq_rsq(c, src[0]);
1189 break;
1190 case nir_op_fexp2:
1191 result = qir_EXP2(c, src[0]);
1192 break;
1193 case nir_op_flog2:
1194 result = qir_LOG2(c, src[0]);
1195 break;
1196
1197 case nir_op_ftrunc:
1198 result = qir_ITOF(c, qir_FTOI(c, src[0]));
1199 break;
1200 case nir_op_fceil:
1201 result = ntq_fceil(c, src[0]);
1202 break;
1203 case nir_op_ffract:
1204 result = ntq_ffract(c, src[0]);
1205 break;
1206 case nir_op_ffloor:
1207 result = ntq_ffloor(c, src[0]);
1208 break;
1209
1210 case nir_op_fsin:
1211 result = ntq_fsin(c, src[0]);
1212 break;
1213 case nir_op_fcos:
1214 result = ntq_fcos(c, src[0]);
1215 break;
1216
1217 case nir_op_fsign:
1218 result = ntq_fsign(c, src[0]);
1219 break;
1220
1221 case nir_op_fabs:
1222 result = qir_FMAXABS(c, src[0], src[0]);
1223 break;
1224 case nir_op_iabs:
1225 result = qir_MAX(c, src[0],
1226 qir_SUB(c, qir_uniform_ui(c, 0), src[0]));
1227 break;
1228
1229 case nir_op_ibitfield_extract:
1230 result = ntq_emit_ibfe(c, src[0], src[1], src[2]);
1231 break;
1232
1233 case nir_op_ubitfield_extract:
1234 result = ntq_emit_ubfe(c, src[0], src[1], src[2]);
1235 break;
1236
1237 case nir_op_usadd_4x8:
1238 result = qir_V8ADDS(c, src[0], src[1]);
1239 break;
1240
1241 case nir_op_ussub_4x8:
1242 result = qir_V8SUBS(c, src[0], src[1]);
1243 break;
1244
1245 case nir_op_umin_4x8:
1246 result = qir_V8MIN(c, src[0], src[1]);
1247 break;
1248
1249 case nir_op_umax_4x8:
1250 result = qir_V8MAX(c, src[0], src[1]);
1251 break;
1252
1253 case nir_op_umul_unorm_4x8:
1254 result = qir_V8MULD(c, src[0], src[1]);
1255 break;
1256
1257 case nir_op_fddx:
1258 case nir_op_fddx_coarse:
1259 case nir_op_fddx_fine:
1260 result = ntq_fddx(c, src[0]);
1261 break;
1262
1263 case nir_op_fddy:
1264 case nir_op_fddy_coarse:
1265 case nir_op_fddy_fine:
1266 result = ntq_fddy(c, src[0]);
1267 break;
1268
1269 default:
1270 fprintf(stderr, "unknown NIR ALU inst: ");
1271 nir_print_instr(&instr->instr, stderr);
1272 fprintf(stderr, "\n");
1273 abort();
1274 }
1275
1276 /* We have a scalar result, so the instruction should only have a
1277 * single channel written to.
1278 */
1279 assert(util_is_power_of_two(instr->dest.write_mask));
1280 ntq_store_dest(c, &instr->dest.dest,
1281 ffs(instr->dest.write_mask) - 1, result);
1282 }
1283
1284 static void
1285 emit_frag_end(struct vc4_compile *c)
1286 {
1287 struct qreg color;
1288 if (c->output_color_index != -1) {
1289 color = c->outputs[c->output_color_index];
1290 } else {
1291 color = qir_uniform_ui(c, 0);
1292 }
1293
1294 uint32_t discard_cond = QPU_COND_ALWAYS;
1295 if (c->s->info->fs.uses_discard) {
1296 qir_SF(c, c->discard);
1297 discard_cond = QPU_COND_ZS;
1298 }
1299
1300 if (c->fs_key->stencil_enabled) {
1301 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1302 qir_uniform(c, QUNIFORM_STENCIL, 0));
1303 if (c->fs_key->stencil_twoside) {
1304 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1305 qir_uniform(c, QUNIFORM_STENCIL, 1));
1306 }
1307 if (c->fs_key->stencil_full_writemasks) {
1308 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1309 qir_uniform(c, QUNIFORM_STENCIL, 2));
1310 }
1311 }
1312
1313 if (c->output_sample_mask_index != -1) {
1314 qir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1315 }
1316
1317 if (c->fs_key->depth_enabled) {
1318 if (c->output_position_index != -1) {
1319 qir_FTOI_dest(c, qir_reg(QFILE_TLB_Z_WRITE, 0),
1320 qir_FMUL(c,
1321 c->outputs[c->output_position_index],
1322 qir_uniform_f(c, 0xffffff)))->cond = discard_cond;
1323 } else {
1324 qir_MOV_dest(c, qir_reg(QFILE_TLB_Z_WRITE, 0),
1325 qir_FRAG_Z(c))->cond = discard_cond;
1326 }
1327 }
1328
1329 if (!c->msaa_per_sample_output) {
1330 qir_MOV_dest(c, qir_reg(QFILE_TLB_COLOR_WRITE, 0),
1331 color)->cond = discard_cond;
1332 } else {
1333 for (int i = 0; i < VC4_MAX_SAMPLES; i++) {
1334 qir_MOV_dest(c, qir_reg(QFILE_TLB_COLOR_WRITE_MS, 0),
1335 c->sample_colors[i])->cond = discard_cond;
1336 }
1337 }
1338 }
1339
1340 static void
1341 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1342 {
1343 struct qreg packed = qir_get_temp(c);
1344
1345 for (int i = 0; i < 2; i++) {
1346 struct qreg scale =
1347 qir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1348
1349 struct qreg packed_chan = packed;
1350 packed_chan.pack = QPU_PACK_A_16A + i;
1351
1352 qir_FTOI_dest(c, packed_chan,
1353 qir_FMUL(c,
1354 qir_FMUL(c,
1355 c->outputs[c->output_position_index + i],
1356 scale),
1357 rcp_w));
1358 }
1359
1360 qir_VPM_WRITE(c, packed);
1361 }
1362
1363 static void
1364 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1365 {
1366 struct qreg zscale = qir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1367 struct qreg zoffset = qir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1368
1369 qir_VPM_WRITE(c, qir_FADD(c, qir_FMUL(c, qir_FMUL(c,
1370 c->outputs[c->output_position_index + 2],
1371 zscale),
1372 rcp_w),
1373 zoffset));
1374 }
1375
1376 static void
1377 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1378 {
1379 qir_VPM_WRITE(c, rcp_w);
1380 }
1381
1382 static void
1383 emit_point_size_write(struct vc4_compile *c)
1384 {
1385 struct qreg point_size;
1386
1387 if (c->output_point_size_index != -1)
1388 point_size = c->outputs[c->output_point_size_index];
1389 else
1390 point_size = qir_uniform_f(c, 1.0);
1391
1392 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1393 * BCM21553).
1394 */
1395 point_size = qir_FMAX(c, point_size, qir_uniform_f(c, .125));
1396
1397 qir_VPM_WRITE(c, point_size);
1398 }
1399
1400 /**
1401 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1402 *
1403 * The simulator insists that there be at least one vertex attribute, so
1404 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also
1405 * insists that all vertex attributes loaded get read by the VS/CS, so we have
1406 * to consume it here.
1407 */
1408 static void
1409 emit_stub_vpm_read(struct vc4_compile *c)
1410 {
1411 if (c->num_inputs)
1412 return;
1413
1414 c->vattr_sizes[0] = 4;
1415 (void)qir_MOV(c, qir_reg(QFILE_VPM, 0));
1416 c->num_inputs++;
1417 }
1418
1419 static void
1420 emit_vert_end(struct vc4_compile *c,
1421 struct vc4_varying_slot *fs_inputs,
1422 uint32_t num_fs_inputs)
1423 {
1424 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1425
1426 emit_stub_vpm_read(c);
1427
1428 emit_scaled_viewport_write(c, rcp_w);
1429 emit_zs_write(c, rcp_w);
1430 emit_rcp_wc_write(c, rcp_w);
1431 if (c->vs_key->per_vertex_point_size)
1432 emit_point_size_write(c);
1433
1434 for (int i = 0; i < num_fs_inputs; i++) {
1435 struct vc4_varying_slot *input = &fs_inputs[i];
1436 int j;
1437
1438 for (j = 0; j < c->num_outputs; j++) {
1439 struct vc4_varying_slot *output =
1440 &c->output_slots[j];
1441
1442 if (input->slot == output->slot &&
1443 input->swizzle == output->swizzle) {
1444 qir_VPM_WRITE(c, c->outputs[j]);
1445 break;
1446 }
1447 }
1448 /* Emit padding if we didn't find a declared VS output for
1449 * this FS input.
1450 */
1451 if (j == c->num_outputs)
1452 qir_VPM_WRITE(c, qir_uniform_f(c, 0.0));
1453 }
1454 }
1455
1456 static void
1457 emit_coord_end(struct vc4_compile *c)
1458 {
1459 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1460
1461 emit_stub_vpm_read(c);
1462
1463 for (int i = 0; i < 4; i++)
1464 qir_VPM_WRITE(c, c->outputs[c->output_position_index + i]);
1465
1466 emit_scaled_viewport_write(c, rcp_w);
1467 emit_zs_write(c, rcp_w);
1468 emit_rcp_wc_write(c, rcp_w);
1469 if (c->vs_key->per_vertex_point_size)
1470 emit_point_size_write(c);
1471 }
1472
1473 static void
1474 vc4_optimize_nir(struct nir_shader *s)
1475 {
1476 bool progress;
1477
1478 do {
1479 progress = false;
1480
1481 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1482 NIR_PASS(progress, s, nir_lower_alu_to_scalar);
1483 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1484 NIR_PASS(progress, s, nir_copy_prop);
1485 NIR_PASS(progress, s, nir_opt_remove_phis);
1486 NIR_PASS(progress, s, nir_opt_dce);
1487 NIR_PASS(progress, s, nir_opt_dead_cf);
1488 NIR_PASS(progress, s, nir_opt_cse);
1489 NIR_PASS(progress, s, nir_opt_peephole_select, 8);
1490 NIR_PASS(progress, s, nir_opt_algebraic);
1491 NIR_PASS(progress, s, nir_opt_constant_folding);
1492 NIR_PASS(progress, s, nir_opt_undef);
1493 } while (progress);
1494 }
1495
1496 static int
1497 driver_location_compare(const void *in_a, const void *in_b)
1498 {
1499 const nir_variable *const *a = in_a;
1500 const nir_variable *const *b = in_b;
1501
1502 return (*a)->data.driver_location - (*b)->data.driver_location;
1503 }
1504
1505 static void
1506 ntq_setup_inputs(struct vc4_compile *c)
1507 {
1508 unsigned num_entries = 0;
1509 nir_foreach_variable(var, &c->s->inputs)
1510 num_entries++;
1511
1512 nir_variable *vars[num_entries];
1513
1514 unsigned i = 0;
1515 nir_foreach_variable(var, &c->s->inputs)
1516 vars[i++] = var;
1517
1518 /* Sort the variables so that we emit the input setup in
1519 * driver_location order. This is required for VPM reads, whose data
1520 * is fetched into the VPM in driver_location (TGSI register index)
1521 * order.
1522 */
1523 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1524
1525 for (unsigned i = 0; i < num_entries; i++) {
1526 nir_variable *var = vars[i];
1527 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1528 unsigned loc = var->data.driver_location;
1529
1530 assert(array_len == 1);
1531 (void)array_len;
1532 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1533 (loc + 1) * 4);
1534
1535 if (c->stage == QSTAGE_FRAG) {
1536 if (var->data.location == VARYING_SLOT_POS) {
1537 emit_fragcoord_input(c, loc);
1538 } else if (var->data.location == VARYING_SLOT_PNTC ||
1539 (var->data.location >= VARYING_SLOT_VAR0 &&
1540 (c->fs_key->point_sprite_mask &
1541 (1 << (var->data.location -
1542 VARYING_SLOT_VAR0))))) {
1543 c->inputs[loc * 4 + 0] = c->point_x;
1544 c->inputs[loc * 4 + 1] = c->point_y;
1545 } else {
1546 emit_fragment_input(c, loc, var->data.location);
1547 }
1548 } else {
1549 emit_vertex_input(c, loc);
1550 }
1551 }
1552 }
1553
1554 static void
1555 ntq_setup_outputs(struct vc4_compile *c)
1556 {
1557 nir_foreach_variable(var, &c->s->outputs) {
1558 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1559 unsigned loc = var->data.driver_location * 4;
1560
1561 assert(array_len == 1);
1562 (void)array_len;
1563
1564 for (int i = 0; i < 4; i++)
1565 add_output(c, loc + i, var->data.location, i);
1566
1567 if (c->stage == QSTAGE_FRAG) {
1568 switch (var->data.location) {
1569 case FRAG_RESULT_COLOR:
1570 case FRAG_RESULT_DATA0:
1571 c->output_color_index = loc;
1572 break;
1573 case FRAG_RESULT_DEPTH:
1574 c->output_position_index = loc;
1575 break;
1576 case FRAG_RESULT_SAMPLE_MASK:
1577 c->output_sample_mask_index = loc;
1578 break;
1579 }
1580 } else {
1581 switch (var->data.location) {
1582 case VARYING_SLOT_POS:
1583 c->output_position_index = loc;
1584 break;
1585 case VARYING_SLOT_PSIZ:
1586 c->output_point_size_index = loc;
1587 break;
1588 }
1589 }
1590 }
1591 }
1592
1593 static void
1594 ntq_setup_uniforms(struct vc4_compile *c)
1595 {
1596 nir_foreach_variable(var, &c->s->uniforms) {
1597 uint32_t vec4_count = st_glsl_type_size(var->type);
1598 unsigned vec4_size = 4 * sizeof(float);
1599
1600 declare_uniform_range(c, var->data.driver_location * vec4_size,
1601 vec4_count * vec4_size);
1602
1603 }
1604 }
1605
1606 /**
1607 * Sets up the mapping from nir_register to struct qreg *.
1608 *
1609 * Each nir_register gets a struct qreg per 32-bit component being stored.
1610 */
1611 static void
1612 ntq_setup_registers(struct vc4_compile *c, struct exec_list *list)
1613 {
1614 foreach_list_typed(nir_register, nir_reg, node, list) {
1615 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1616 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1617 array_len *
1618 nir_reg->num_components);
1619
1620 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1621
1622 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1623 qregs[i] = qir_get_temp(c);
1624 }
1625 }
1626
1627 static void
1628 ntq_emit_load_const(struct vc4_compile *c, nir_load_const_instr *instr)
1629 {
1630 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1631 for (int i = 0; i < instr->def.num_components; i++)
1632 qregs[i] = qir_uniform_ui(c, instr->value.u32[i]);
1633
1634 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1635 }
1636
1637 static void
1638 ntq_emit_ssa_undef(struct vc4_compile *c, nir_ssa_undef_instr *instr)
1639 {
1640 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1641
1642 /* QIR needs there to be *some* value, so pick 0 (same as for
1643 * ntq_setup_registers().
1644 */
1645 for (int i = 0; i < instr->def.num_components; i++)
1646 qregs[i] = qir_uniform_ui(c, 0);
1647 }
1648
1649 static void
1650 ntq_emit_intrinsic(struct vc4_compile *c, nir_intrinsic_instr *instr)
1651 {
1652 nir_const_value *const_offset;
1653 unsigned offset;
1654
1655 switch (instr->intrinsic) {
1656 case nir_intrinsic_load_uniform:
1657 assert(instr->num_components == 1);
1658 const_offset = nir_src_as_const_value(instr->src[0]);
1659 if (const_offset) {
1660 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1661 assert(offset % 4 == 0);
1662 /* We need dwords */
1663 offset = offset / 4;
1664 ntq_store_dest(c, &instr->dest, 0,
1665 qir_uniform(c, QUNIFORM_UNIFORM,
1666 offset));
1667 } else {
1668 ntq_store_dest(c, &instr->dest, 0,
1669 indirect_uniform_load(c, instr));
1670 }
1671 break;
1672
1673 case nir_intrinsic_load_user_clip_plane:
1674 for (int i = 0; i < instr->num_components; i++) {
1675 ntq_store_dest(c, &instr->dest, i,
1676 qir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1677 nir_intrinsic_ucp_id(instr) *
1678 4 + i));
1679 }
1680 break;
1681
1682 case nir_intrinsic_load_blend_const_color_r_float:
1683 case nir_intrinsic_load_blend_const_color_g_float:
1684 case nir_intrinsic_load_blend_const_color_b_float:
1685 case nir_intrinsic_load_blend_const_color_a_float:
1686 ntq_store_dest(c, &instr->dest, 0,
1687 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_X +
1688 (instr->intrinsic -
1689 nir_intrinsic_load_blend_const_color_r_float),
1690 0));
1691 break;
1692
1693 case nir_intrinsic_load_blend_const_color_rgba8888_unorm:
1694 ntq_store_dest(c, &instr->dest, 0,
1695 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_RGBA,
1696 0));
1697 break;
1698
1699 case nir_intrinsic_load_blend_const_color_aaaa8888_unorm:
1700 ntq_store_dest(c, &instr->dest, 0,
1701 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_AAAA,
1702 0));
1703 break;
1704
1705 case nir_intrinsic_load_alpha_ref_float:
1706 ntq_store_dest(c, &instr->dest, 0,
1707 qir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1708 break;
1709
1710 case nir_intrinsic_load_sample_mask_in:
1711 ntq_store_dest(c, &instr->dest, 0,
1712 qir_uniform(c, QUNIFORM_SAMPLE_MASK, 0));
1713 break;
1714
1715 case nir_intrinsic_load_front_face:
1716 /* The register contains 0 (front) or 1 (back), and we need to
1717 * turn it into a NIR bool where true means front.
1718 */
1719 ntq_store_dest(c, &instr->dest, 0,
1720 qir_ADD(c,
1721 qir_uniform_ui(c, -1),
1722 qir_reg(QFILE_FRAG_REV_FLAG, 0)));
1723 break;
1724
1725 case nir_intrinsic_load_input:
1726 assert(instr->num_components == 1);
1727 const_offset = nir_src_as_const_value(instr->src[0]);
1728 assert(const_offset && "vc4 doesn't support indirect inputs");
1729 if (c->stage == QSTAGE_FRAG &&
1730 nir_intrinsic_base(instr) >= VC4_NIR_TLB_COLOR_READ_INPUT) {
1731 assert(const_offset->u32[0] == 0);
1732 /* Reads of the per-sample color need to be done in
1733 * order.
1734 */
1735 int sample_index = (nir_intrinsic_base(instr) -
1736 VC4_NIR_TLB_COLOR_READ_INPUT);
1737 for (int i = 0; i <= sample_index; i++) {
1738 if (c->color_reads[i].file == QFILE_NULL) {
1739 c->color_reads[i] =
1740 qir_TLB_COLOR_READ(c);
1741 }
1742 }
1743 ntq_store_dest(c, &instr->dest, 0,
1744 qir_MOV(c, c->color_reads[sample_index]));
1745 } else {
1746 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1747 int comp = nir_intrinsic_component(instr);
1748 ntq_store_dest(c, &instr->dest, 0,
1749 qir_MOV(c, c->inputs[offset * 4 + comp]));
1750 }
1751 break;
1752
1753 case nir_intrinsic_store_output:
1754 const_offset = nir_src_as_const_value(instr->src[1]);
1755 assert(const_offset && "vc4 doesn't support indirect outputs");
1756 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1757
1758 /* MSAA color outputs are the only case where we have an
1759 * output that's not lowered to being a store of a single 32
1760 * bit value.
1761 */
1762 if (c->stage == QSTAGE_FRAG && instr->num_components == 4) {
1763 assert(offset == c->output_color_index);
1764 for (int i = 0; i < 4; i++) {
1765 c->sample_colors[i] =
1766 qir_MOV(c, ntq_get_src(c, instr->src[0],
1767 i));
1768 }
1769 } else {
1770 offset = offset * 4 + nir_intrinsic_component(instr);
1771 assert(instr->num_components == 1);
1772 c->outputs[offset] =
1773 qir_MOV(c, ntq_get_src(c, instr->src[0], 0));
1774 c->num_outputs = MAX2(c->num_outputs, offset + 1);
1775 }
1776 break;
1777
1778 case nir_intrinsic_discard:
1779 if (c->execute.file != QFILE_NULL) {
1780 qir_SF(c, c->execute);
1781 qir_MOV_cond(c, QPU_COND_ZS, c->discard,
1782 qir_uniform_ui(c, ~0));
1783 } else {
1784 qir_MOV_dest(c, c->discard, qir_uniform_ui(c, ~0));
1785 }
1786 break;
1787
1788 case nir_intrinsic_discard_if: {
1789 /* true (~0) if we're discarding */
1790 struct qreg cond = ntq_get_src(c, instr->src[0], 0);
1791
1792 if (c->execute.file != QFILE_NULL) {
1793 /* execute == 0 means the channel is active. Invert
1794 * the condition so that we can use zero as "executing
1795 * and discarding."
1796 */
1797 qir_SF(c, qir_AND(c, c->execute, qir_NOT(c, cond)));
1798 qir_MOV_cond(c, QPU_COND_ZS, c->discard, cond);
1799 } else {
1800 qir_OR_dest(c, c->discard, c->discard,
1801 ntq_get_src(c, instr->src[0], 0));
1802 }
1803
1804 break;
1805 }
1806
1807 default:
1808 fprintf(stderr, "Unknown intrinsic: ");
1809 nir_print_instr(&instr->instr, stderr);
1810 fprintf(stderr, "\n");
1811 break;
1812 }
1813 }
1814
1815 /* Clears (activates) the execute flags for any channels whose jump target
1816 * matches this block.
1817 */
1818 static void
1819 ntq_activate_execute_for_block(struct vc4_compile *c)
1820 {
1821 qir_SF(c, qir_SUB(c,
1822 c->execute,
1823 qir_uniform_ui(c, c->cur_block->index)));
1824 qir_MOV_cond(c, QPU_COND_ZS, c->execute, qir_uniform_ui(c, 0));
1825 }
1826
1827 static void
1828 ntq_emit_if(struct vc4_compile *c, nir_if *if_stmt)
1829 {
1830 if (!c->vc4->screen->has_control_flow) {
1831 fprintf(stderr,
1832 "IF statement support requires updated kernel.\n");
1833 return;
1834 }
1835
1836 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
1837 bool empty_else_block =
1838 (nir_else_block == nir_if_last_else_block(if_stmt) &&
1839 exec_list_is_empty(&nir_else_block->instr_list));
1840
1841 struct qblock *then_block = qir_new_block(c);
1842 struct qblock *after_block = qir_new_block(c);
1843 struct qblock *else_block;
1844 if (empty_else_block)
1845 else_block = after_block;
1846 else
1847 else_block = qir_new_block(c);
1848
1849 bool was_top_level = false;
1850 if (c->execute.file == QFILE_NULL) {
1851 c->execute = qir_MOV(c, qir_uniform_ui(c, 0));
1852 was_top_level = true;
1853 }
1854
1855 /* Set ZS for executing (execute == 0) and jumping (if->condition ==
1856 * 0) channels, and then update execute flags for those to point to
1857 * the ELSE block.
1858 */
1859 qir_SF(c, qir_OR(c,
1860 c->execute,
1861 ntq_get_src(c, if_stmt->condition, 0)));
1862 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
1863 qir_uniform_ui(c, else_block->index));
1864
1865 /* Jump to ELSE if nothing is active for THEN, otherwise fall
1866 * through.
1867 */
1868 qir_SF(c, c->execute);
1869 qir_BRANCH(c, QPU_COND_BRANCH_ALL_ZC);
1870 qir_link_blocks(c->cur_block, else_block);
1871 qir_link_blocks(c->cur_block, then_block);
1872
1873 /* Process the THEN block. */
1874 qir_set_emit_block(c, then_block);
1875 ntq_emit_cf_list(c, &if_stmt->then_list);
1876
1877 if (!empty_else_block) {
1878 /* Handle the end of the THEN block. First, all currently
1879 * active channels update their execute flags to point to
1880 * ENDIF
1881 */
1882 qir_SF(c, c->execute);
1883 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
1884 qir_uniform_ui(c, after_block->index));
1885
1886 /* If everything points at ENDIF, then jump there immediately. */
1887 qir_SF(c, qir_SUB(c, c->execute, qir_uniform_ui(c, after_block->index)));
1888 qir_BRANCH(c, QPU_COND_BRANCH_ALL_ZS);
1889 qir_link_blocks(c->cur_block, after_block);
1890 qir_link_blocks(c->cur_block, else_block);
1891
1892 qir_set_emit_block(c, else_block);
1893 ntq_activate_execute_for_block(c);
1894 ntq_emit_cf_list(c, &if_stmt->else_list);
1895 }
1896
1897 qir_link_blocks(c->cur_block, after_block);
1898
1899 qir_set_emit_block(c, after_block);
1900 if (was_top_level)
1901 c->execute = c->undef;
1902 else
1903 ntq_activate_execute_for_block(c);
1904
1905 }
1906
1907 static void
1908 ntq_emit_jump(struct vc4_compile *c, nir_jump_instr *jump)
1909 {
1910 switch (jump->type) {
1911 case nir_jump_break:
1912 qir_SF(c, c->execute);
1913 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
1914 qir_uniform_ui(c, c->loop_break_block->index));
1915 break;
1916
1917 case nir_jump_continue:
1918 qir_SF(c, c->execute);
1919 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
1920 qir_uniform_ui(c, c->loop_cont_block->index));
1921 break;
1922
1923 case nir_jump_return:
1924 unreachable("All returns shouold be lowered\n");
1925 }
1926 }
1927
1928 static void
1929 ntq_emit_instr(struct vc4_compile *c, nir_instr *instr)
1930 {
1931 switch (instr->type) {
1932 case nir_instr_type_alu:
1933 ntq_emit_alu(c, nir_instr_as_alu(instr));
1934 break;
1935
1936 case nir_instr_type_intrinsic:
1937 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
1938 break;
1939
1940 case nir_instr_type_load_const:
1941 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
1942 break;
1943
1944 case nir_instr_type_ssa_undef:
1945 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
1946 break;
1947
1948 case nir_instr_type_tex:
1949 ntq_emit_tex(c, nir_instr_as_tex(instr));
1950 break;
1951
1952 case nir_instr_type_jump:
1953 ntq_emit_jump(c, nir_instr_as_jump(instr));
1954 break;
1955
1956 default:
1957 fprintf(stderr, "Unknown NIR instr type: ");
1958 nir_print_instr(instr, stderr);
1959 fprintf(stderr, "\n");
1960 abort();
1961 }
1962 }
1963
1964 static void
1965 ntq_emit_block(struct vc4_compile *c, nir_block *block)
1966 {
1967 nir_foreach_instr(instr, block) {
1968 ntq_emit_instr(c, instr);
1969 }
1970 }
1971
1972 static void ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list);
1973
1974 static void
1975 ntq_emit_loop(struct vc4_compile *c, nir_loop *loop)
1976 {
1977 if (!c->vc4->screen->has_control_flow) {
1978 fprintf(stderr,
1979 "loop support requires updated kernel.\n");
1980 ntq_emit_cf_list(c, &loop->body);
1981 return;
1982 }
1983
1984 bool was_top_level = false;
1985 if (c->execute.file == QFILE_NULL) {
1986 c->execute = qir_MOV(c, qir_uniform_ui(c, 0));
1987 was_top_level = true;
1988 }
1989
1990 struct qblock *save_loop_cont_block = c->loop_cont_block;
1991 struct qblock *save_loop_break_block = c->loop_break_block;
1992
1993 c->loop_cont_block = qir_new_block(c);
1994 c->loop_break_block = qir_new_block(c);
1995
1996 qir_link_blocks(c->cur_block, c->loop_cont_block);
1997 qir_set_emit_block(c, c->loop_cont_block);
1998 ntq_activate_execute_for_block(c);
1999
2000 ntq_emit_cf_list(c, &loop->body);
2001
2002 /* If anything had explicitly continued, or is here at the end of the
2003 * loop, then we need to loop again. SF updates are masked by the
2004 * instruction's condition, so we can do the OR of the two conditions
2005 * within SF.
2006 */
2007 qir_SF(c, c->execute);
2008 struct qinst *cont_check =
2009 qir_SUB_dest(c,
2010 c->undef,
2011 c->execute,
2012 qir_uniform_ui(c, c->loop_cont_block->index));
2013 cont_check->cond = QPU_COND_ZC;
2014 cont_check->sf = true;
2015
2016 qir_BRANCH(c, QPU_COND_BRANCH_ANY_ZS);
2017 qir_link_blocks(c->cur_block, c->loop_cont_block);
2018 qir_link_blocks(c->cur_block, c->loop_break_block);
2019
2020 qir_set_emit_block(c, c->loop_break_block);
2021 if (was_top_level)
2022 c->execute = c->undef;
2023 else
2024 ntq_activate_execute_for_block(c);
2025
2026 c->loop_break_block = save_loop_break_block;
2027 c->loop_cont_block = save_loop_cont_block;
2028 }
2029
2030 static void
2031 ntq_emit_function(struct vc4_compile *c, nir_function_impl *func)
2032 {
2033 fprintf(stderr, "FUNCTIONS not handled.\n");
2034 abort();
2035 }
2036
2037 static void
2038 ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list)
2039 {
2040 foreach_list_typed(nir_cf_node, node, node, list) {
2041 switch (node->type) {
2042 case nir_cf_node_block:
2043 ntq_emit_block(c, nir_cf_node_as_block(node));
2044 break;
2045
2046 case nir_cf_node_if:
2047 ntq_emit_if(c, nir_cf_node_as_if(node));
2048 break;
2049
2050 case nir_cf_node_loop:
2051 ntq_emit_loop(c, nir_cf_node_as_loop(node));
2052 break;
2053
2054 case nir_cf_node_function:
2055 ntq_emit_function(c, nir_cf_node_as_function(node));
2056 break;
2057
2058 default:
2059 fprintf(stderr, "Unknown NIR node type\n");
2060 abort();
2061 }
2062 }
2063 }
2064
2065 static void
2066 ntq_emit_impl(struct vc4_compile *c, nir_function_impl *impl)
2067 {
2068 ntq_setup_registers(c, &impl->registers);
2069 ntq_emit_cf_list(c, &impl->body);
2070 }
2071
2072 static void
2073 nir_to_qir(struct vc4_compile *c)
2074 {
2075 if (c->stage == QSTAGE_FRAG && c->s->info->fs.uses_discard)
2076 c->discard = qir_MOV(c, qir_uniform_ui(c, 0));
2077
2078 ntq_setup_inputs(c);
2079 ntq_setup_outputs(c);
2080 ntq_setup_uniforms(c);
2081 ntq_setup_registers(c, &c->s->registers);
2082
2083 /* Find the main function and emit the body. */
2084 nir_foreach_function(function, c->s) {
2085 assert(strcmp(function->name, "main") == 0);
2086 assert(function->impl);
2087 ntq_emit_impl(c, function->impl);
2088 }
2089 }
2090
2091 static const nir_shader_compiler_options nir_options = {
2092 .lower_extract_byte = true,
2093 .lower_extract_word = true,
2094 .lower_ffma = true,
2095 .lower_flrp32 = true,
2096 .lower_fpow = true,
2097 .lower_fsat = true,
2098 .lower_fsqrt = true,
2099 .lower_negate = true,
2100 .native_integers = true,
2101 };
2102
2103 const void *
2104 vc4_screen_get_compiler_options(struct pipe_screen *pscreen,
2105 enum pipe_shader_ir ir, unsigned shader)
2106 {
2107 return &nir_options;
2108 }
2109
2110 static int
2111 count_nir_instrs(nir_shader *nir)
2112 {
2113 int count = 0;
2114 nir_foreach_function(function, nir) {
2115 if (!function->impl)
2116 continue;
2117 nir_foreach_block(block, function->impl) {
2118 nir_foreach_instr(instr, block)
2119 count++;
2120 }
2121 }
2122 return count;
2123 }
2124
2125 static struct vc4_compile *
2126 vc4_shader_ntq(struct vc4_context *vc4, enum qstage stage,
2127 struct vc4_key *key)
2128 {
2129 struct vc4_compile *c = qir_compile_init();
2130
2131 c->vc4 = vc4;
2132 c->stage = stage;
2133 c->shader_state = &key->shader_state->base;
2134 c->program_id = key->shader_state->program_id;
2135 c->variant_id =
2136 p_atomic_inc_return(&key->shader_state->compiled_variant_count);
2137
2138 c->key = key;
2139 switch (stage) {
2140 case QSTAGE_FRAG:
2141 c->fs_key = (struct vc4_fs_key *)key;
2142 if (c->fs_key->is_points) {
2143 c->point_x = emit_fragment_varying(c, ~0, 0);
2144 c->point_y = emit_fragment_varying(c, ~0, 0);
2145 } else if (c->fs_key->is_lines) {
2146 c->line_x = emit_fragment_varying(c, ~0, 0);
2147 }
2148 break;
2149 case QSTAGE_VERT:
2150 c->vs_key = (struct vc4_vs_key *)key;
2151 break;
2152 case QSTAGE_COORD:
2153 c->vs_key = (struct vc4_vs_key *)key;
2154 break;
2155 }
2156
2157 c->s = nir_shader_clone(c, key->shader_state->base.ir.nir);
2158
2159 if (stage == QSTAGE_FRAG)
2160 NIR_PASS_V(c->s, vc4_nir_lower_blend, c);
2161
2162 struct nir_lower_tex_options tex_options = {
2163 /* We would need to implement txs, but we don't want the
2164 * int/float conversions
2165 */
2166 .lower_rect = false,
2167
2168 .lower_txp = ~0,
2169
2170 /* Apply swizzles to all samplers. */
2171 .swizzle_result = ~0,
2172 };
2173
2174 /* Lower the format swizzle and ARB_texture_swizzle-style swizzle.
2175 * The format swizzling applies before sRGB decode, and
2176 * ARB_texture_swizzle is the last thing before returning the sample.
2177 */
2178 for (int i = 0; i < ARRAY_SIZE(key->tex); i++) {
2179 enum pipe_format format = c->key->tex[i].format;
2180
2181 if (!format)
2182 continue;
2183
2184 const uint8_t *format_swizzle = vc4_get_format_swizzle(format);
2185
2186 for (int j = 0; j < 4; j++) {
2187 uint8_t arb_swiz = c->key->tex[i].swizzle[j];
2188
2189 if (arb_swiz <= 3) {
2190 tex_options.swizzles[i][j] =
2191 format_swizzle[arb_swiz];
2192 } else {
2193 tex_options.swizzles[i][j] = arb_swiz;
2194 }
2195 }
2196
2197 if (util_format_is_srgb(format))
2198 tex_options.lower_srgb |= (1 << i);
2199 }
2200
2201 NIR_PASS_V(c->s, nir_lower_tex, &tex_options);
2202
2203 if (c->fs_key && c->fs_key->light_twoside)
2204 NIR_PASS_V(c->s, nir_lower_two_sided_color);
2205
2206 if (c->vs_key && c->vs_key->clamp_color)
2207 NIR_PASS_V(c->s, nir_lower_clamp_color_outputs);
2208
2209 if (c->key->ucp_enables) {
2210 if (stage == QSTAGE_FRAG) {
2211 NIR_PASS_V(c->s, nir_lower_clip_fs, c->key->ucp_enables);
2212 } else {
2213 NIR_PASS_V(c->s, nir_lower_clip_vs, c->key->ucp_enables);
2214 NIR_PASS_V(c->s, nir_lower_io_to_scalar,
2215 nir_var_shader_out);
2216 }
2217 }
2218
2219 /* FS input scalarizing must happen after nir_lower_two_sided_color,
2220 * which only handles a vec4 at a time. Similarly, VS output
2221 * scalarizing must happen after nir_lower_clip_vs.
2222 */
2223 if (c->stage == QSTAGE_FRAG)
2224 NIR_PASS_V(c->s, nir_lower_io_to_scalar, nir_var_shader_in);
2225 else
2226 NIR_PASS_V(c->s, nir_lower_io_to_scalar, nir_var_shader_out);
2227
2228 NIR_PASS_V(c->s, vc4_nir_lower_io, c);
2229 NIR_PASS_V(c->s, vc4_nir_lower_txf_ms, c);
2230 NIR_PASS_V(c->s, nir_lower_idiv);
2231
2232 vc4_optimize_nir(c->s);
2233
2234 NIR_PASS_V(c->s, nir_convert_from_ssa, true);
2235
2236 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2237 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d NIR instructions\n",
2238 qir_get_stage_name(c->stage),
2239 c->program_id, c->variant_id,
2240 count_nir_instrs(c->s));
2241 }
2242
2243 if (vc4_debug & VC4_DEBUG_NIR) {
2244 fprintf(stderr, "%s prog %d/%d NIR:\n",
2245 qir_get_stage_name(c->stage),
2246 c->program_id, c->variant_id);
2247 nir_print_shader(c->s, stderr);
2248 }
2249
2250 nir_to_qir(c);
2251
2252 switch (stage) {
2253 case QSTAGE_FRAG:
2254 emit_frag_end(c);
2255 break;
2256 case QSTAGE_VERT:
2257 emit_vert_end(c,
2258 c->vs_key->fs_inputs->input_slots,
2259 c->vs_key->fs_inputs->num_inputs);
2260 break;
2261 case QSTAGE_COORD:
2262 emit_coord_end(c);
2263 break;
2264 }
2265
2266 if (vc4_debug & VC4_DEBUG_QIR) {
2267 fprintf(stderr, "%s prog %d/%d pre-opt QIR:\n",
2268 qir_get_stage_name(c->stage),
2269 c->program_id, c->variant_id);
2270 qir_dump(c);
2271 fprintf(stderr, "\n");
2272 }
2273
2274 qir_optimize(c);
2275 qir_lower_uniforms(c);
2276
2277 qir_schedule_instructions(c);
2278 qir_emit_uniform_stream_resets(c);
2279
2280 if (vc4_debug & VC4_DEBUG_QIR) {
2281 fprintf(stderr, "%s prog %d/%d QIR:\n",
2282 qir_get_stage_name(c->stage),
2283 c->program_id, c->variant_id);
2284 qir_dump(c);
2285 fprintf(stderr, "\n");
2286 }
2287
2288 qir_reorder_uniforms(c);
2289 vc4_generate_code(vc4, c);
2290
2291 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2292 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d instructions\n",
2293 qir_get_stage_name(c->stage),
2294 c->program_id, c->variant_id,
2295 c->qpu_inst_count);
2296 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d uniforms\n",
2297 qir_get_stage_name(c->stage),
2298 c->program_id, c->variant_id,
2299 c->num_uniforms);
2300 }
2301
2302 ralloc_free(c->s);
2303
2304 return c;
2305 }
2306
2307 static void *
2308 vc4_shader_state_create(struct pipe_context *pctx,
2309 const struct pipe_shader_state *cso)
2310 {
2311 struct vc4_context *vc4 = vc4_context(pctx);
2312 struct vc4_uncompiled_shader *so = CALLOC_STRUCT(vc4_uncompiled_shader);
2313 if (!so)
2314 return NULL;
2315
2316 so->program_id = vc4->next_uncompiled_program_id++;
2317
2318 nir_shader *s;
2319
2320 if (cso->type == PIPE_SHADER_IR_NIR) {
2321 /* The backend takes ownership of the NIR shader on state
2322 * creation.
2323 */
2324 s = cso->ir.nir;
2325 } else {
2326 assert(cso->type == PIPE_SHADER_IR_TGSI);
2327
2328 if (vc4_debug & VC4_DEBUG_TGSI) {
2329 fprintf(stderr, "prog %d TGSI:\n",
2330 so->program_id);
2331 tgsi_dump(cso->tokens, 0);
2332 fprintf(stderr, "\n");
2333 }
2334 s = tgsi_to_nir(cso->tokens, &nir_options);
2335 }
2336
2337 NIR_PASS_V(s, nir_opt_global_to_local);
2338 NIR_PASS_V(s, nir_convert_to_ssa);
2339 NIR_PASS_V(s, nir_normalize_cubemap_coords);
2340
2341 NIR_PASS_V(s, nir_lower_load_const_to_scalar);
2342
2343 vc4_optimize_nir(s);
2344
2345 NIR_PASS_V(s, nir_remove_dead_variables, nir_var_local);
2346
2347 /* Garbage collect dead instructions */
2348 nir_sweep(s);
2349
2350 so->base.type = PIPE_SHADER_IR_NIR;
2351 so->base.ir.nir = s;
2352
2353 if (vc4_debug & VC4_DEBUG_NIR) {
2354 fprintf(stderr, "%s prog %d NIR:\n",
2355 gl_shader_stage_name(s->stage),
2356 so->program_id);
2357 nir_print_shader(s, stderr);
2358 fprintf(stderr, "\n");
2359 }
2360
2361 return so;
2362 }
2363
2364 static void
2365 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
2366 struct vc4_compile *c)
2367 {
2368 int count = c->num_uniforms;
2369 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
2370
2371 uinfo->count = count;
2372 uinfo->data = ralloc_array(shader, uint32_t, count);
2373 memcpy(uinfo->data, c->uniform_data,
2374 count * sizeof(*uinfo->data));
2375 uinfo->contents = ralloc_array(shader, enum quniform_contents, count);
2376 memcpy(uinfo->contents, c->uniform_contents,
2377 count * sizeof(*uinfo->contents));
2378 uinfo->num_texture_samples = c->num_texture_samples;
2379
2380 vc4_set_shader_uniform_dirty_flags(shader);
2381 }
2382
2383 static void
2384 vc4_setup_compiled_fs_inputs(struct vc4_context *vc4, struct vc4_compile *c,
2385 struct vc4_compiled_shader *shader)
2386 {
2387 struct vc4_fs_inputs inputs;
2388
2389 memset(&inputs, 0, sizeof(inputs));
2390 inputs.input_slots = ralloc_array(shader,
2391 struct vc4_varying_slot,
2392 c->num_input_slots);
2393
2394 bool input_live[c->num_input_slots];
2395
2396 memset(input_live, 0, sizeof(input_live));
2397 qir_for_each_inst_inorder(inst, c) {
2398 for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) {
2399 if (inst->src[i].file == QFILE_VARY)
2400 input_live[inst->src[i].index] = true;
2401 }
2402 }
2403
2404 for (int i = 0; i < c->num_input_slots; i++) {
2405 struct vc4_varying_slot *slot = &c->input_slots[i];
2406
2407 if (!input_live[i])
2408 continue;
2409
2410 /* Skip non-VS-output inputs. */
2411 if (slot->slot == (uint8_t)~0)
2412 continue;
2413
2414 if (slot->slot == VARYING_SLOT_COL0 ||
2415 slot->slot == VARYING_SLOT_COL1 ||
2416 slot->slot == VARYING_SLOT_BFC0 ||
2417 slot->slot == VARYING_SLOT_BFC1) {
2418 shader->color_inputs |= (1 << inputs.num_inputs);
2419 }
2420
2421 inputs.input_slots[inputs.num_inputs] = *slot;
2422 inputs.num_inputs++;
2423 }
2424 shader->num_inputs = inputs.num_inputs;
2425
2426 /* Add our set of inputs to the set of all inputs seen. This way, we
2427 * can have a single pointer that identifies an FS inputs set,
2428 * allowing VS to avoid recompiling when the FS is recompiled (or a
2429 * new one is bound using separate shader objects) but the inputs
2430 * don't change.
2431 */
2432 struct set_entry *entry = _mesa_set_search(vc4->fs_inputs_set, &inputs);
2433 if (entry) {
2434 shader->fs_inputs = entry->key;
2435 ralloc_free(inputs.input_slots);
2436 } else {
2437 struct vc4_fs_inputs *alloc_inputs;
2438
2439 alloc_inputs = rzalloc(vc4->fs_inputs_set, struct vc4_fs_inputs);
2440 memcpy(alloc_inputs, &inputs, sizeof(inputs));
2441 ralloc_steal(alloc_inputs, inputs.input_slots);
2442 _mesa_set_add(vc4->fs_inputs_set, alloc_inputs);
2443
2444 shader->fs_inputs = alloc_inputs;
2445 }
2446 }
2447
2448 static struct vc4_compiled_shader *
2449 vc4_get_compiled_shader(struct vc4_context *vc4, enum qstage stage,
2450 struct vc4_key *key)
2451 {
2452 struct hash_table *ht;
2453 uint32_t key_size;
2454 if (stage == QSTAGE_FRAG) {
2455 ht = vc4->fs_cache;
2456 key_size = sizeof(struct vc4_fs_key);
2457 } else {
2458 ht = vc4->vs_cache;
2459 key_size = sizeof(struct vc4_vs_key);
2460 }
2461
2462 struct vc4_compiled_shader *shader;
2463 struct hash_entry *entry = _mesa_hash_table_search(ht, key);
2464 if (entry)
2465 return entry->data;
2466
2467 struct vc4_compile *c = vc4_shader_ntq(vc4, stage, key);
2468 shader = rzalloc(NULL, struct vc4_compiled_shader);
2469
2470 shader->program_id = vc4->next_compiled_program_id++;
2471 if (stage == QSTAGE_FRAG) {
2472 vc4_setup_compiled_fs_inputs(vc4, c, shader);
2473
2474 /* Note: the temporary clone in c->s has been freed. */
2475 nir_shader *orig_shader = key->shader_state->base.ir.nir;
2476 if (orig_shader->info->outputs_written & (1 << FRAG_RESULT_DEPTH))
2477 shader->disable_early_z = true;
2478 } else {
2479 shader->num_inputs = c->num_inputs;
2480
2481 shader->vattr_offsets[0] = 0;
2482 for (int i = 0; i < 8; i++) {
2483 shader->vattr_offsets[i + 1] =
2484 shader->vattr_offsets[i] + c->vattr_sizes[i];
2485
2486 if (c->vattr_sizes[i])
2487 shader->vattrs_live |= (1 << i);
2488 }
2489 }
2490
2491 copy_uniform_state_to_shader(shader, c);
2492 shader->bo = vc4_bo_alloc_shader(vc4->screen, c->qpu_insts,
2493 c->qpu_inst_count * sizeof(uint64_t));
2494
2495 /* Copy the compiler UBO range state to the compiled shader, dropping
2496 * out arrays that were never referenced by an indirect load.
2497 *
2498 * (Note that QIR dead code elimination of an array access still
2499 * leaves that array alive, though)
2500 */
2501 if (c->num_ubo_ranges) {
2502 shader->num_ubo_ranges = c->num_ubo_ranges;
2503 shader->ubo_ranges = ralloc_array(shader, struct vc4_ubo_range,
2504 c->num_ubo_ranges);
2505 uint32_t j = 0;
2506 for (int i = 0; i < c->num_uniform_ranges; i++) {
2507 struct vc4_compiler_ubo_range *range =
2508 &c->ubo_ranges[i];
2509 if (!range->used)
2510 continue;
2511
2512 shader->ubo_ranges[j].dst_offset = range->dst_offset;
2513 shader->ubo_ranges[j].src_offset = range->src_offset;
2514 shader->ubo_ranges[j].size = range->size;
2515 shader->ubo_size += c->ubo_ranges[i].size;
2516 j++;
2517 }
2518 }
2519 if (shader->ubo_size) {
2520 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2521 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d UBO uniforms\n",
2522 qir_get_stage_name(c->stage),
2523 c->program_id, c->variant_id,
2524 shader->ubo_size / 4);
2525 }
2526 }
2527
2528 qir_compile_destroy(c);
2529
2530 struct vc4_key *dup_key;
2531 dup_key = rzalloc_size(shader, key_size); /* TODO: don't use rzalloc */
2532 memcpy(dup_key, key, key_size);
2533 _mesa_hash_table_insert(ht, dup_key, shader);
2534
2535 return shader;
2536 }
2537
2538 static void
2539 vc4_setup_shared_key(struct vc4_context *vc4, struct vc4_key *key,
2540 struct vc4_texture_stateobj *texstate)
2541 {
2542 for (int i = 0; i < texstate->num_textures; i++) {
2543 struct pipe_sampler_view *sampler = texstate->textures[i];
2544 struct vc4_sampler_view *vc4_sampler = vc4_sampler_view(sampler);
2545 struct pipe_sampler_state *sampler_state =
2546 texstate->samplers[i];
2547
2548 if (!sampler)
2549 continue;
2550
2551 key->tex[i].format = sampler->format;
2552 key->tex[i].swizzle[0] = sampler->swizzle_r;
2553 key->tex[i].swizzle[1] = sampler->swizzle_g;
2554 key->tex[i].swizzle[2] = sampler->swizzle_b;
2555 key->tex[i].swizzle[3] = sampler->swizzle_a;
2556
2557 if (sampler->texture->nr_samples > 1) {
2558 key->tex[i].msaa_width = sampler->texture->width0;
2559 key->tex[i].msaa_height = sampler->texture->height0;
2560 } else if (sampler){
2561 key->tex[i].compare_mode = sampler_state->compare_mode;
2562 key->tex[i].compare_func = sampler_state->compare_func;
2563 key->tex[i].wrap_s = sampler_state->wrap_s;
2564 key->tex[i].wrap_t = sampler_state->wrap_t;
2565 key->tex[i].force_first_level =
2566 vc4_sampler->force_first_level;
2567 }
2568 }
2569
2570 key->ucp_enables = vc4->rasterizer->base.clip_plane_enable;
2571 }
2572
2573 static void
2574 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
2575 {
2576 struct vc4_job *job = vc4->job;
2577 struct vc4_fs_key local_key;
2578 struct vc4_fs_key *key = &local_key;
2579
2580 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2581 VC4_DIRTY_BLEND |
2582 VC4_DIRTY_FRAMEBUFFER |
2583 VC4_DIRTY_ZSA |
2584 VC4_DIRTY_RASTERIZER |
2585 VC4_DIRTY_SAMPLE_MASK |
2586 VC4_DIRTY_FRAGTEX |
2587 VC4_DIRTY_UNCOMPILED_FS))) {
2588 return;
2589 }
2590
2591 memset(key, 0, sizeof(*key));
2592 vc4_setup_shared_key(vc4, &key->base, &vc4->fragtex);
2593 key->base.shader_state = vc4->prog.bind_fs;
2594 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
2595 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
2596 prim_mode <= PIPE_PRIM_LINE_STRIP);
2597 key->blend = vc4->blend->rt[0];
2598 if (vc4->blend->logicop_enable) {
2599 key->logicop_func = vc4->blend->logicop_func;
2600 } else {
2601 key->logicop_func = PIPE_LOGICOP_COPY;
2602 }
2603 if (job->msaa) {
2604 key->msaa = vc4->rasterizer->base.multisample;
2605 key->sample_coverage = (vc4->rasterizer->base.multisample &&
2606 vc4->sample_mask != (1 << VC4_MAX_SAMPLES) - 1);
2607 key->sample_alpha_to_coverage = vc4->blend->alpha_to_coverage;
2608 key->sample_alpha_to_one = vc4->blend->alpha_to_one;
2609 }
2610
2611 if (vc4->framebuffer.cbufs[0])
2612 key->color_format = vc4->framebuffer.cbufs[0]->format;
2613
2614 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
2615 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
2616 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
2617 key->depth_enabled = (vc4->zsa->base.depth.enabled ||
2618 key->stencil_enabled);
2619 if (vc4->zsa->base.alpha.enabled) {
2620 key->alpha_test = true;
2621 key->alpha_test_func = vc4->zsa->base.alpha.func;
2622 }
2623
2624 if (key->is_points) {
2625 key->point_sprite_mask =
2626 vc4->rasterizer->base.sprite_coord_enable;
2627 key->point_coord_upper_left =
2628 (vc4->rasterizer->base.sprite_coord_mode ==
2629 PIPE_SPRITE_COORD_UPPER_LEFT);
2630 }
2631
2632 key->light_twoside = vc4->rasterizer->base.light_twoside;
2633
2634 struct vc4_compiled_shader *old_fs = vc4->prog.fs;
2635 vc4->prog.fs = vc4_get_compiled_shader(vc4, QSTAGE_FRAG, &key->base);
2636 if (vc4->prog.fs == old_fs)
2637 return;
2638
2639 vc4->dirty |= VC4_DIRTY_COMPILED_FS;
2640
2641 if (vc4->rasterizer->base.flatshade &&
2642 old_fs && vc4->prog.fs->color_inputs != old_fs->color_inputs) {
2643 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
2644 }
2645
2646 if (old_fs && vc4->prog.fs->fs_inputs != old_fs->fs_inputs)
2647 vc4->dirty |= VC4_DIRTY_FS_INPUTS;
2648 }
2649
2650 static void
2651 vc4_update_compiled_vs(struct vc4_context *vc4, uint8_t prim_mode)
2652 {
2653 struct vc4_vs_key local_key;
2654 struct vc4_vs_key *key = &local_key;
2655
2656 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2657 VC4_DIRTY_RASTERIZER |
2658 VC4_DIRTY_VERTTEX |
2659 VC4_DIRTY_VTXSTATE |
2660 VC4_DIRTY_UNCOMPILED_VS |
2661 VC4_DIRTY_FS_INPUTS))) {
2662 return;
2663 }
2664
2665 memset(key, 0, sizeof(*key));
2666 vc4_setup_shared_key(vc4, &key->base, &vc4->verttex);
2667 key->base.shader_state = vc4->prog.bind_vs;
2668 key->fs_inputs = vc4->prog.fs->fs_inputs;
2669 key->clamp_color = vc4->rasterizer->base.clamp_vertex_color;
2670
2671 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
2672 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
2673
2674 key->per_vertex_point_size =
2675 (prim_mode == PIPE_PRIM_POINTS &&
2676 vc4->rasterizer->base.point_size_per_vertex);
2677
2678 struct vc4_compiled_shader *vs =
2679 vc4_get_compiled_shader(vc4, QSTAGE_VERT, &key->base);
2680 if (vs != vc4->prog.vs) {
2681 vc4->prog.vs = vs;
2682 vc4->dirty |= VC4_DIRTY_COMPILED_VS;
2683 }
2684
2685 key->is_coord = true;
2686 /* Coord shaders don't care what the FS inputs are. */
2687 key->fs_inputs = NULL;
2688 struct vc4_compiled_shader *cs =
2689 vc4_get_compiled_shader(vc4, QSTAGE_COORD, &key->base);
2690 if (cs != vc4->prog.cs) {
2691 vc4->prog.cs = cs;
2692 vc4->dirty |= VC4_DIRTY_COMPILED_CS;
2693 }
2694 }
2695
2696 void
2697 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
2698 {
2699 vc4_update_compiled_fs(vc4, prim_mode);
2700 vc4_update_compiled_vs(vc4, prim_mode);
2701 }
2702
2703 static uint32_t
2704 fs_cache_hash(const void *key)
2705 {
2706 return _mesa_hash_data(key, sizeof(struct vc4_fs_key));
2707 }
2708
2709 static uint32_t
2710 vs_cache_hash(const void *key)
2711 {
2712 return _mesa_hash_data(key, sizeof(struct vc4_vs_key));
2713 }
2714
2715 static bool
2716 fs_cache_compare(const void *key1, const void *key2)
2717 {
2718 return memcmp(key1, key2, sizeof(struct vc4_fs_key)) == 0;
2719 }
2720
2721 static bool
2722 vs_cache_compare(const void *key1, const void *key2)
2723 {
2724 return memcmp(key1, key2, sizeof(struct vc4_vs_key)) == 0;
2725 }
2726
2727 static uint32_t
2728 fs_inputs_hash(const void *key)
2729 {
2730 const struct vc4_fs_inputs *inputs = key;
2731
2732 return _mesa_hash_data(inputs->input_slots,
2733 sizeof(*inputs->input_slots) *
2734 inputs->num_inputs);
2735 }
2736
2737 static bool
2738 fs_inputs_compare(const void *key1, const void *key2)
2739 {
2740 const struct vc4_fs_inputs *inputs1 = key1;
2741 const struct vc4_fs_inputs *inputs2 = key2;
2742
2743 return (inputs1->num_inputs == inputs2->num_inputs &&
2744 memcmp(inputs1->input_slots,
2745 inputs2->input_slots,
2746 sizeof(*inputs1->input_slots) *
2747 inputs1->num_inputs) == 0);
2748 }
2749
2750 static void
2751 delete_from_cache_if_matches(struct hash_table *ht,
2752 struct hash_entry *entry,
2753 struct vc4_uncompiled_shader *so)
2754 {
2755 const struct vc4_key *key = entry->key;
2756
2757 if (key->shader_state == so) {
2758 struct vc4_compiled_shader *shader = entry->data;
2759 _mesa_hash_table_remove(ht, entry);
2760 vc4_bo_unreference(&shader->bo);
2761 ralloc_free(shader);
2762 }
2763 }
2764
2765 static void
2766 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
2767 {
2768 struct vc4_context *vc4 = vc4_context(pctx);
2769 struct vc4_uncompiled_shader *so = hwcso;
2770
2771 struct hash_entry *entry;
2772 hash_table_foreach(vc4->fs_cache, entry)
2773 delete_from_cache_if_matches(vc4->fs_cache, entry, so);
2774 hash_table_foreach(vc4->vs_cache, entry)
2775 delete_from_cache_if_matches(vc4->vs_cache, entry, so);
2776
2777 ralloc_free(so->base.ir.nir);
2778 free(so);
2779 }
2780
2781 static void
2782 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
2783 {
2784 struct vc4_context *vc4 = vc4_context(pctx);
2785 vc4->prog.bind_fs = hwcso;
2786 vc4->dirty |= VC4_DIRTY_UNCOMPILED_FS;
2787 }
2788
2789 static void
2790 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
2791 {
2792 struct vc4_context *vc4 = vc4_context(pctx);
2793 vc4->prog.bind_vs = hwcso;
2794 vc4->dirty |= VC4_DIRTY_UNCOMPILED_VS;
2795 }
2796
2797 void
2798 vc4_program_init(struct pipe_context *pctx)
2799 {
2800 struct vc4_context *vc4 = vc4_context(pctx);
2801
2802 pctx->create_vs_state = vc4_shader_state_create;
2803 pctx->delete_vs_state = vc4_shader_state_delete;
2804
2805 pctx->create_fs_state = vc4_shader_state_create;
2806 pctx->delete_fs_state = vc4_shader_state_delete;
2807
2808 pctx->bind_fs_state = vc4_fp_state_bind;
2809 pctx->bind_vs_state = vc4_vp_state_bind;
2810
2811 vc4->fs_cache = _mesa_hash_table_create(pctx, fs_cache_hash,
2812 fs_cache_compare);
2813 vc4->vs_cache = _mesa_hash_table_create(pctx, vs_cache_hash,
2814 vs_cache_compare);
2815 vc4->fs_inputs_set = _mesa_set_create(pctx, fs_inputs_hash,
2816 fs_inputs_compare);
2817 }
2818
2819 void
2820 vc4_program_fini(struct pipe_context *pctx)
2821 {
2822 struct vc4_context *vc4 = vc4_context(pctx);
2823
2824 struct hash_entry *entry;
2825 hash_table_foreach(vc4->fs_cache, entry) {
2826 struct vc4_compiled_shader *shader = entry->data;
2827 vc4_bo_unreference(&shader->bo);
2828 ralloc_free(shader);
2829 _mesa_hash_table_remove(vc4->fs_cache, entry);
2830 }
2831
2832 hash_table_foreach(vc4->vs_cache, entry) {
2833 struct vc4_compiled_shader *shader = entry->data;
2834 vc4_bo_unreference(&shader->bo);
2835 ralloc_free(shader);
2836 _mesa_hash_table_remove(vc4->vs_cache, entry);
2837 }
2838 }