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vc4: Stop trying to reuse temporaries that store uniform values.
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "pipe/p_state.h"
27 #include "util/u_format.h"
28 #include "util/u_hash_table.h"
29 #include "util/u_hash.h"
30 #include "util/u_memory.h"
31 #include "util/ralloc.h"
32 #include "tgsi/tgsi_dump.h"
33 #include "tgsi/tgsi_info.h"
34
35 #include "vc4_context.h"
36 #include "vc4_qpu.h"
37 #include "vc4_qir.h"
38 #ifdef USE_VC4_SIMULATOR
39 #include "simpenrose/simpenrose.h"
40 #endif
41
42 struct vc4_key {
43 struct pipe_shader_state *shader_state;
44 struct {
45 enum pipe_format format;
46 unsigned compare_mode:1;
47 unsigned compare_func:3;
48 uint8_t swizzle[4];
49 } tex[VC4_MAX_TEXTURE_SAMPLERS];
50 };
51
52 struct vc4_fs_key {
53 struct vc4_key base;
54 enum pipe_format color_format;
55 bool depth_enabled;
56 bool stencil_enabled;
57 bool stencil_twoside;
58 bool stencil_full_writemasks;
59 bool is_points;
60 bool is_lines;
61 bool alpha_test;
62 bool point_coord_upper_left;
63 uint8_t alpha_test_func;
64 uint32_t point_sprite_mask;
65
66 struct pipe_rt_blend_state blend;
67 };
68
69 struct vc4_vs_key {
70 struct vc4_key base;
71 enum pipe_format attr_formats[8];
72 bool per_vertex_point_size;
73 };
74
75 static void
76 resize_qreg_array(struct vc4_compile *c,
77 struct qreg **regs,
78 uint32_t *size,
79 uint32_t decl_size)
80 {
81 if (*size >= decl_size)
82 return;
83
84 uint32_t old_size = *size;
85 *size = MAX2(*size * 2, decl_size);
86 *regs = reralloc(c, *regs, struct qreg, *size);
87 if (!*regs) {
88 fprintf(stderr, "Malloc failure\n");
89 abort();
90 }
91
92 for (uint32_t i = old_size; i < *size; i++)
93 (*regs)[i] = c->undef;
94 }
95
96 static struct qreg
97 add_uniform(struct vc4_compile *c,
98 enum quniform_contents contents,
99 uint32_t data)
100 {
101 uint32_t uniform = c->num_uniforms++;
102 struct qreg u = { QFILE_UNIF, uniform };
103
104 c->uniform_contents[uniform] = contents;
105 c->uniform_data[uniform] = data;
106
107 return u;
108 }
109
110 static struct qreg
111 get_temp_for_uniform(struct vc4_compile *c, enum quniform_contents contents,
112 uint32_t data)
113 {
114 struct qreg u = add_uniform(c, contents, data);
115 struct qreg t = qir_MOV(c, u);
116 return t;
117 }
118
119 static struct qreg
120 qir_uniform_ui(struct vc4_compile *c, uint32_t ui)
121 {
122 return get_temp_for_uniform(c, QUNIFORM_CONSTANT, ui);
123 }
124
125 static struct qreg
126 qir_uniform_f(struct vc4_compile *c, float f)
127 {
128 return qir_uniform_ui(c, fui(f));
129 }
130
131 static struct qreg
132 get_src(struct vc4_compile *c, unsigned tgsi_op,
133 struct tgsi_src_register *src, int i)
134 {
135 struct qreg r = c->undef;
136
137 uint32_t s = i;
138 switch (i) {
139 case TGSI_SWIZZLE_X:
140 s = src->SwizzleX;
141 break;
142 case TGSI_SWIZZLE_Y:
143 s = src->SwizzleY;
144 break;
145 case TGSI_SWIZZLE_Z:
146 s = src->SwizzleZ;
147 break;
148 case TGSI_SWIZZLE_W:
149 s = src->SwizzleW;
150 break;
151 default:
152 abort();
153 }
154
155 assert(!src->Indirect);
156
157 switch (src->File) {
158 case TGSI_FILE_NULL:
159 return r;
160 case TGSI_FILE_TEMPORARY:
161 r = c->temps[src->Index * 4 + s];
162 break;
163 case TGSI_FILE_IMMEDIATE:
164 r = c->consts[src->Index * 4 + s];
165 break;
166 case TGSI_FILE_CONSTANT:
167 r = get_temp_for_uniform(c, QUNIFORM_UNIFORM,
168 src->Index * 4 + s);
169 break;
170 case TGSI_FILE_INPUT:
171 r = c->inputs[src->Index * 4 + s];
172 break;
173 case TGSI_FILE_SAMPLER:
174 case TGSI_FILE_SAMPLER_VIEW:
175 r = c->undef;
176 break;
177 default:
178 fprintf(stderr, "unknown src file %d\n", src->File);
179 abort();
180 }
181
182 if (src->Absolute)
183 r = qir_FMAXABS(c, r, r);
184
185 if (src->Negate) {
186 switch (tgsi_opcode_infer_src_type(tgsi_op)) {
187 case TGSI_TYPE_SIGNED:
188 case TGSI_TYPE_UNSIGNED:
189 r = qir_SUB(c, qir_uniform_ui(c, 0), r);
190 break;
191 default:
192 r = qir_FSUB(c, qir_uniform_f(c, 0.0), r);
193 break;
194 }
195 }
196
197 return r;
198 };
199
200
201 static void
202 update_dst(struct vc4_compile *c, struct tgsi_full_instruction *tgsi_inst,
203 int i, struct qreg val)
204 {
205 struct tgsi_dst_register *tgsi_dst = &tgsi_inst->Dst[0].Register;
206
207 assert(!tgsi_dst->Indirect);
208
209 switch (tgsi_dst->File) {
210 case TGSI_FILE_TEMPORARY:
211 c->temps[tgsi_dst->Index * 4 + i] = val;
212 break;
213 case TGSI_FILE_OUTPUT:
214 c->outputs[tgsi_dst->Index * 4 + i] = val;
215 c->num_outputs = MAX2(c->num_outputs,
216 tgsi_dst->Index * 4 + i + 1);
217 break;
218 default:
219 fprintf(stderr, "unknown dst file %d\n", tgsi_dst->File);
220 abort();
221 }
222 };
223
224 static struct qreg
225 get_swizzled_channel(struct vc4_compile *c,
226 struct qreg *srcs, int swiz)
227 {
228 switch (swiz) {
229 default:
230 case UTIL_FORMAT_SWIZZLE_NONE:
231 fprintf(stderr, "warning: unknown swizzle\n");
232 /* FALLTHROUGH */
233 case UTIL_FORMAT_SWIZZLE_0:
234 return qir_uniform_f(c, 0.0);
235 case UTIL_FORMAT_SWIZZLE_1:
236 return qir_uniform_f(c, 1.0);
237 case UTIL_FORMAT_SWIZZLE_X:
238 case UTIL_FORMAT_SWIZZLE_Y:
239 case UTIL_FORMAT_SWIZZLE_Z:
240 case UTIL_FORMAT_SWIZZLE_W:
241 return srcs[swiz];
242 }
243 }
244
245 static struct qreg
246 tgsi_to_qir_alu(struct vc4_compile *c,
247 struct tgsi_full_instruction *tgsi_inst,
248 enum qop op, struct qreg *src, int i)
249 {
250 struct qreg dst = qir_get_temp(c);
251 qir_emit(c, qir_inst4(op, dst,
252 src[0 * 4 + i],
253 src[1 * 4 + i],
254 src[2 * 4 + i],
255 c->undef));
256 return dst;
257 }
258
259 static struct qreg
260 tgsi_to_qir_umul(struct vc4_compile *c,
261 struct tgsi_full_instruction *tgsi_inst,
262 enum qop op, struct qreg *src, int i)
263 {
264 struct qreg src0_hi = qir_SHR(c, src[0 * 4 + i],
265 qir_uniform_ui(c, 16));
266 struct qreg src0_lo = qir_AND(c, src[0 * 4 + i],
267 qir_uniform_ui(c, 0xffff));
268 struct qreg src1_hi = qir_SHR(c, src[1 * 4 + i],
269 qir_uniform_ui(c, 16));
270 struct qreg src1_lo = qir_AND(c, src[1 * 4 + i],
271 qir_uniform_ui(c, 0xffff));
272
273 struct qreg hilo = qir_MUL24(c, src0_hi, src1_lo);
274 struct qreg lohi = qir_MUL24(c, src0_lo, src1_hi);
275 struct qreg lolo = qir_MUL24(c, src0_lo, src1_lo);
276
277 return qir_ADD(c, lolo, qir_SHL(c,
278 qir_ADD(c, hilo, lohi),
279 qir_uniform_ui(c, 16)));
280 }
281
282 static struct qreg
283 tgsi_to_qir_idiv(struct vc4_compile *c,
284 struct tgsi_full_instruction *tgsi_inst,
285 enum qop op, struct qreg *src, int i)
286 {
287 return qir_FTOI(c, qir_FMUL(c,
288 qir_ITOF(c, src[0 * 4 + i]),
289 qir_RCP(c, qir_ITOF(c, src[1 * 4 + i]))));
290 }
291
292 static struct qreg
293 tgsi_to_qir_ineg(struct vc4_compile *c,
294 struct tgsi_full_instruction *tgsi_inst,
295 enum qop op, struct qreg *src, int i)
296 {
297 return qir_SUB(c, qir_uniform_ui(c, 0), src[0 * 4 + i]);
298 }
299
300 static struct qreg
301 tgsi_to_qir_seq(struct vc4_compile *c,
302 struct tgsi_full_instruction *tgsi_inst,
303 enum qop op, struct qreg *src, int i)
304 {
305 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
306 return qir_SEL_X_0_ZS(c, qir_uniform_f(c, 1.0));
307 }
308
309 static struct qreg
310 tgsi_to_qir_sne(struct vc4_compile *c,
311 struct tgsi_full_instruction *tgsi_inst,
312 enum qop op, struct qreg *src, int i)
313 {
314 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
315 return qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0));
316 }
317
318 static struct qreg
319 tgsi_to_qir_slt(struct vc4_compile *c,
320 struct tgsi_full_instruction *tgsi_inst,
321 enum qop op, struct qreg *src, int i)
322 {
323 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
324 return qir_SEL_X_0_NS(c, qir_uniform_f(c, 1.0));
325 }
326
327 static struct qreg
328 tgsi_to_qir_sge(struct vc4_compile *c,
329 struct tgsi_full_instruction *tgsi_inst,
330 enum qop op, struct qreg *src, int i)
331 {
332 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
333 return qir_SEL_X_0_NC(c, qir_uniform_f(c, 1.0));
334 }
335
336 static struct qreg
337 tgsi_to_qir_fseq(struct vc4_compile *c,
338 struct tgsi_full_instruction *tgsi_inst,
339 enum qop op, struct qreg *src, int i)
340 {
341 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
342 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
343 }
344
345 static struct qreg
346 tgsi_to_qir_fsne(struct vc4_compile *c,
347 struct tgsi_full_instruction *tgsi_inst,
348 enum qop op, struct qreg *src, int i)
349 {
350 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
351 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
352 }
353
354 static struct qreg
355 tgsi_to_qir_fslt(struct vc4_compile *c,
356 struct tgsi_full_instruction *tgsi_inst,
357 enum qop op, struct qreg *src, int i)
358 {
359 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
360 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
361 }
362
363 static struct qreg
364 tgsi_to_qir_fsge(struct vc4_compile *c,
365 struct tgsi_full_instruction *tgsi_inst,
366 enum qop op, struct qreg *src, int i)
367 {
368 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
369 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
370 }
371
372 static struct qreg
373 tgsi_to_qir_useq(struct vc4_compile *c,
374 struct tgsi_full_instruction *tgsi_inst,
375 enum qop op, struct qreg *src, int i)
376 {
377 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
378 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
379 }
380
381 static struct qreg
382 tgsi_to_qir_usne(struct vc4_compile *c,
383 struct tgsi_full_instruction *tgsi_inst,
384 enum qop op, struct qreg *src, int i)
385 {
386 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
387 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
388 }
389
390 static struct qreg
391 tgsi_to_qir_islt(struct vc4_compile *c,
392 struct tgsi_full_instruction *tgsi_inst,
393 enum qop op, struct qreg *src, int i)
394 {
395 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
396 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
397 }
398
399 static struct qreg
400 tgsi_to_qir_isge(struct vc4_compile *c,
401 struct tgsi_full_instruction *tgsi_inst,
402 enum qop op, struct qreg *src, int i)
403 {
404 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
405 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
406 }
407
408 static struct qreg
409 tgsi_to_qir_cmp(struct vc4_compile *c,
410 struct tgsi_full_instruction *tgsi_inst,
411 enum qop op, struct qreg *src, int i)
412 {
413 qir_SF(c, src[0 * 4 + i]);
414 return qir_SEL_X_Y_NS(c,
415 src[1 * 4 + i],
416 src[2 * 4 + i]);
417 }
418
419 static struct qreg
420 tgsi_to_qir_mad(struct vc4_compile *c,
421 struct tgsi_full_instruction *tgsi_inst,
422 enum qop op, struct qreg *src, int i)
423 {
424 return qir_FADD(c,
425 qir_FMUL(c,
426 src[0 * 4 + i],
427 src[1 * 4 + i]),
428 src[2 * 4 + i]);
429 }
430
431 static struct qreg
432 tgsi_to_qir_lit(struct vc4_compile *c,
433 struct tgsi_full_instruction *tgsi_inst,
434 enum qop op, struct qreg *src, int i)
435 {
436 struct qreg x = src[0 * 4 + 0];
437 struct qreg y = src[0 * 4 + 1];
438 struct qreg w = src[0 * 4 + 3];
439
440 switch (i) {
441 case 0:
442 case 3:
443 return qir_uniform_f(c, 1.0);
444 case 1:
445 return qir_FMAX(c, src[0 * 4 + 0], qir_uniform_f(c, 0.0));
446 case 2: {
447 struct qreg zero = qir_uniform_f(c, 0.0);
448
449 qir_SF(c, x);
450 /* XXX: Clamp w to -128..128 */
451 return qir_SEL_X_0_NC(c,
452 qir_EXP2(c, qir_FMUL(c,
453 w,
454 qir_LOG2(c,
455 qir_FMAX(c,
456 y,
457 zero)))));
458 }
459 default:
460 assert(!"not reached");
461 return c->undef;
462 }
463 }
464
465 static struct qreg
466 tgsi_to_qir_lrp(struct vc4_compile *c,
467 struct tgsi_full_instruction *tgsi_inst,
468 enum qop op, struct qreg *src, int i)
469 {
470 struct qreg src0 = src[0 * 4 + i];
471 struct qreg src1 = src[1 * 4 + i];
472 struct qreg src2 = src[2 * 4 + i];
473
474 /* LRP is:
475 * src0 * src1 + (1 - src0) * src2.
476 * -> src0 * src1 + src2 - src0 * src2
477 * -> src2 + src0 * (src1 - src2)
478 */
479 return qir_FADD(c, src2, qir_FMUL(c, src0, qir_FSUB(c, src1, src2)));
480
481 }
482
483 static void
484 tgsi_to_qir_tex(struct vc4_compile *c,
485 struct tgsi_full_instruction *tgsi_inst,
486 enum qop op, struct qreg *src)
487 {
488 assert(!tgsi_inst->Instruction.Saturate);
489
490 struct qreg s = src[0 * 4 + 0];
491 struct qreg t = src[0 * 4 + 1];
492 uint32_t unit = tgsi_inst->Src[1].Register.Index;
493
494 struct qreg proj = c->undef;
495 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
496 proj = qir_RCP(c, src[0 * 4 + 3]);
497 s = qir_FMUL(c, s, proj);
498 t = qir_FMUL(c, t, proj);
499 }
500
501 /* There is no native support for GL texture rectangle coordinates, so
502 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
503 * 1]).
504 */
505 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_RECT ||
506 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT) {
507 s = qir_FMUL(c, s,
508 get_temp_for_uniform(c,
509 QUNIFORM_TEXRECT_SCALE_X,
510 unit));
511 t = qir_FMUL(c, t,
512 get_temp_for_uniform(c,
513 QUNIFORM_TEXRECT_SCALE_Y,
514 unit));
515 }
516
517 qir_TEX_T(c, t, add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit));
518
519 struct qreg sampler_p1 = add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1,
520 unit);
521 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB) {
522 qir_TEX_B(c, src[0 * 4 + 3], sampler_p1);
523 qir_TEX_S(c, s, add_uniform(c, QUNIFORM_CONSTANT, 0));
524 } else {
525 qir_TEX_S(c, s, sampler_p1);
526 }
527
528 c->num_texture_samples++;
529 struct qreg r4 = qir_TEX_RESULT(c);
530
531 enum pipe_format format = c->key->tex[unit].format;
532
533 struct qreg unpacked[4];
534 if (util_format_is_depth_or_stencil(format)) {
535 struct qreg depthf = qir_ITOF(c, qir_SHR(c, r4,
536 qir_uniform_ui(c, 8)));
537 struct qreg normalized = qir_FMUL(c, depthf,
538 qir_uniform_f(c, 1.0f/0xffffff));
539
540 struct qreg depth_output;
541
542 struct qreg compare = src[0 * 4 + 2];
543
544 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP)
545 compare = qir_FMUL(c, compare, proj);
546
547 struct qreg one = qir_uniform_f(c, 1.0f);
548 if (c->key->tex[unit].compare_mode) {
549 switch (c->key->tex[unit].compare_func) {
550 case PIPE_FUNC_NEVER:
551 depth_output = qir_uniform_f(c, 0.0f);
552 break;
553 case PIPE_FUNC_ALWAYS:
554 depth_output = one;
555 break;
556 case PIPE_FUNC_EQUAL:
557 qir_SF(c, qir_FSUB(c, compare, normalized));
558 depth_output = qir_SEL_X_0_ZS(c, one);
559 break;
560 case PIPE_FUNC_NOTEQUAL:
561 qir_SF(c, qir_FSUB(c, compare, normalized));
562 depth_output = qir_SEL_X_0_ZC(c, one);
563 break;
564 case PIPE_FUNC_GREATER:
565 qir_SF(c, qir_FSUB(c, compare, normalized));
566 depth_output = qir_SEL_X_0_NC(c, one);
567 break;
568 case PIPE_FUNC_GEQUAL:
569 qir_SF(c, qir_FSUB(c, normalized, compare));
570 depth_output = qir_SEL_X_0_NS(c, one);
571 break;
572 case PIPE_FUNC_LESS:
573 qir_SF(c, qir_FSUB(c, compare, normalized));
574 depth_output = qir_SEL_X_0_NS(c, one);
575 break;
576 case PIPE_FUNC_LEQUAL:
577 qir_SF(c, qir_FSUB(c, normalized, compare));
578 depth_output = qir_SEL_X_0_NC(c, one);
579 break;
580 }
581 } else {
582 depth_output = normalized;
583 }
584
585 for (int i = 0; i < 4; i++)
586 unpacked[i] = depth_output;
587 } else {
588 for (int i = 0; i < 4; i++)
589 unpacked[i] = qir_R4_UNPACK(c, r4, i);
590 }
591
592 const uint8_t *format_swiz = vc4_get_format_swizzle(format);
593 uint8_t swiz[4];
594 util_format_compose_swizzles(format_swiz, c->key->tex[unit].swizzle, swiz);
595 for (int i = 0; i < 4; i++) {
596 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
597 continue;
598
599 update_dst(c, tgsi_inst, i,
600 get_swizzled_channel(c, unpacked, swiz[i]));
601 }
602 }
603
604 static struct qreg
605 tgsi_to_qir_pow(struct vc4_compile *c,
606 struct tgsi_full_instruction *tgsi_inst,
607 enum qop op, struct qreg *src, int i)
608 {
609 /* Note that this instruction replicates its result from the x channel
610 */
611 return qir_EXP2(c, qir_FMUL(c,
612 src[1 * 4 + 0],
613 qir_LOG2(c, src[0 * 4 + 0])));
614 }
615
616 static struct qreg
617 tgsi_to_qir_trunc(struct vc4_compile *c,
618 struct tgsi_full_instruction *tgsi_inst,
619 enum qop op, struct qreg *src, int i)
620 {
621 return qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
622 }
623
624 /**
625 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
626 * to zero).
627 */
628 static struct qreg
629 tgsi_to_qir_frc(struct vc4_compile *c,
630 struct tgsi_full_instruction *tgsi_inst,
631 enum qop op, struct qreg *src, int i)
632 {
633 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
634 struct qreg diff = qir_FSUB(c, src[0 * 4 + i], trunc);
635 qir_SF(c, diff);
636 return qir_SEL_X_Y_NS(c,
637 qir_FADD(c, diff, qir_uniform_f(c, 1.0)),
638 diff);
639 }
640
641 /**
642 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
643 * zero).
644 */
645 static struct qreg
646 tgsi_to_qir_flr(struct vc4_compile *c,
647 struct tgsi_full_instruction *tgsi_inst,
648 enum qop op, struct qreg *src, int i)
649 {
650 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
651
652 /* This will be < 0 if we truncated and the truncation was of a value
653 * that was < 0 in the first place.
654 */
655 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], trunc));
656
657 return qir_SEL_X_Y_NS(c,
658 qir_FSUB(c, trunc, qir_uniform_f(c, 1.0)),
659 trunc);
660 }
661
662 static struct qreg
663 tgsi_to_qir_dp(struct vc4_compile *c,
664 struct tgsi_full_instruction *tgsi_inst,
665 int num, struct qreg *src, int i)
666 {
667 struct qreg sum = qir_FMUL(c, src[0 * 4 + 0], src[1 * 4 + 0]);
668 for (int j = 1; j < num; j++) {
669 sum = qir_FADD(c, sum, qir_FMUL(c,
670 src[0 * 4 + j],
671 src[1 * 4 + j]));
672 }
673 return sum;
674 }
675
676 static struct qreg
677 tgsi_to_qir_dp2(struct vc4_compile *c,
678 struct tgsi_full_instruction *tgsi_inst,
679 enum qop op, struct qreg *src, int i)
680 {
681 return tgsi_to_qir_dp(c, tgsi_inst, 2, src, i);
682 }
683
684 static struct qreg
685 tgsi_to_qir_dp3(struct vc4_compile *c,
686 struct tgsi_full_instruction *tgsi_inst,
687 enum qop op, struct qreg *src, int i)
688 {
689 return tgsi_to_qir_dp(c, tgsi_inst, 3, src, i);
690 }
691
692 static struct qreg
693 tgsi_to_qir_dp4(struct vc4_compile *c,
694 struct tgsi_full_instruction *tgsi_inst,
695 enum qop op, struct qreg *src, int i)
696 {
697 return tgsi_to_qir_dp(c, tgsi_inst, 4, src, i);
698 }
699
700 static struct qreg
701 tgsi_to_qir_abs(struct vc4_compile *c,
702 struct tgsi_full_instruction *tgsi_inst,
703 enum qop op, struct qreg *src, int i)
704 {
705 struct qreg arg = src[0 * 4 + i];
706 return qir_FMAXABS(c, arg, arg);
707 }
708
709 /* Note that this instruction replicates its result from the x channel */
710 static struct qreg
711 tgsi_to_qir_sin(struct vc4_compile *c,
712 struct tgsi_full_instruction *tgsi_inst,
713 enum qop op, struct qreg *src, int i)
714 {
715 float coeff[] = {
716 2.0 * M_PI,
717 -pow(2.0 * M_PI, 3) / (3 * 2 * 1),
718 pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
719 -pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
720 };
721
722 struct qreg scaled_x =
723 qir_FMUL(c,
724 src[0 * 4 + 0],
725 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
726
727
728 struct qreg x = tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0);
729 struct qreg x2 = qir_FMUL(c, x, x);
730 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
731 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
732 x = qir_FMUL(c, x, x2);
733 sum = qir_FADD(c,
734 sum,
735 qir_FMUL(c,
736 x,
737 qir_uniform_f(c, coeff[i])));
738 }
739 return sum;
740 }
741
742 /* Note that this instruction replicates its result from the x channel */
743 static struct qreg
744 tgsi_to_qir_cos(struct vc4_compile *c,
745 struct tgsi_full_instruction *tgsi_inst,
746 enum qop op, struct qreg *src, int i)
747 {
748 float coeff[] = {
749 1.0f,
750 -pow(2.0 * M_PI, 2) / (2 * 1),
751 pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
752 -pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
753 };
754
755 struct qreg scaled_x =
756 qir_FMUL(c, src[0 * 4 + 0],
757 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
758 struct qreg x_frac = tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0);
759
760 struct qreg sum = qir_uniform_f(c, coeff[0]);
761 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
762 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
763 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
764 if (i != 1)
765 x = qir_FMUL(c, x, x2);
766
767 struct qreg mul = qir_FMUL(c,
768 x,
769 qir_uniform_f(c, coeff[i]));
770 if (i == 0)
771 sum = mul;
772 else
773 sum = qir_FADD(c, sum, mul);
774 }
775 return sum;
776 }
777
778 static void
779 emit_vertex_input(struct vc4_compile *c, int attr)
780 {
781 enum pipe_format format = c->vs_key->attr_formats[attr];
782 struct qreg vpm_reads[4];
783
784 /* Right now, we're setting the VPM offsets to be 16 bytes wide every
785 * time, so we always read 4 32-bit VPM entries.
786 */
787 for (int i = 0; i < 4; i++) {
788 vpm_reads[i] = qir_get_temp(c);
789 qir_emit(c, qir_inst(QOP_VPM_READ,
790 vpm_reads[i],
791 c->undef,
792 c->undef));
793 c->num_inputs++;
794 }
795
796 bool format_warned = false;
797 const struct util_format_description *desc =
798 util_format_description(format);
799
800 for (int i = 0; i < 4; i++) {
801 uint8_t swiz = desc->swizzle[i];
802 struct qreg result;
803
804 if (swiz > UTIL_FORMAT_SWIZZLE_W)
805 result = get_swizzled_channel(c, vpm_reads, swiz);
806 else if (desc->channel[swiz].size == 32 &&
807 desc->channel[swiz].type == UTIL_FORMAT_TYPE_FLOAT) {
808 result = get_swizzled_channel(c, vpm_reads, swiz);
809 } else if (desc->channel[swiz].size == 8 &&
810 (desc->channel[swiz].type == UTIL_FORMAT_TYPE_UNSIGNED ||
811 desc->channel[swiz].type == UTIL_FORMAT_TYPE_SIGNED) &&
812 desc->channel[swiz].normalized) {
813 struct qreg vpm = vpm_reads[0];
814 if (desc->channel[swiz].type == UTIL_FORMAT_TYPE_SIGNED)
815 vpm = qir_XOR(c, vpm, qir_uniform_ui(c, 0x80808080));
816 result = qir_UNPACK_8(c, vpm, swiz);
817 } else {
818 if (!format_warned) {
819 fprintf(stderr,
820 "vtx element %d unsupported type: %s\n",
821 attr, util_format_name(format));
822 format_warned = true;
823 }
824 result = qir_uniform_f(c, 0.0);
825 }
826
827 if (desc->channel[swiz].normalized &&
828 desc->channel[swiz].type == UTIL_FORMAT_TYPE_SIGNED) {
829 result = qir_FSUB(c,
830 qir_FMUL(c,
831 result,
832 qir_uniform_f(c, 2.0)),
833 qir_uniform_f(c, 1.0));
834 }
835
836 c->inputs[attr * 4 + i] = result;
837 }
838 }
839
840 static void
841 tgsi_to_qir_kill_if(struct vc4_compile *c, struct qreg *src, int i)
842 {
843 if (c->discard.file == QFILE_NULL)
844 c->discard = qir_uniform_f(c, 0.0);
845 qir_SF(c, src[0 * 4 + i]);
846 c->discard = qir_SEL_X_Y_NS(c, qir_uniform_f(c, 1.0),
847 c->discard);
848 }
849
850 static void
851 emit_fragcoord_input(struct vc4_compile *c, int attr)
852 {
853 c->inputs[attr * 4 + 0] = qir_FRAG_X(c);
854 c->inputs[attr * 4 + 1] = qir_FRAG_Y(c);
855 c->inputs[attr * 4 + 2] =
856 qir_FMUL(c,
857 qir_ITOF(c, qir_FRAG_Z(c)),
858 qir_uniform_f(c, 1.0 / 0xffffff));
859 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
860 }
861
862 static void
863 emit_point_coord_input(struct vc4_compile *c, int attr)
864 {
865 if (c->point_x.file == QFILE_NULL) {
866 c->point_x = qir_uniform_f(c, 0.0);
867 c->point_y = qir_uniform_f(c, 0.0);
868 }
869
870 c->inputs[attr * 4 + 0] = c->point_x;
871 if (c->fs_key->point_coord_upper_left) {
872 c->inputs[attr * 4 + 1] = qir_FSUB(c,
873 qir_uniform_f(c, 1.0),
874 c->point_y);
875 } else {
876 c->inputs[attr * 4 + 1] = c->point_y;
877 }
878 c->inputs[attr * 4 + 2] = qir_uniform_f(c, 0.0);
879 c->inputs[attr * 4 + 3] = qir_uniform_f(c, 1.0);
880 }
881
882 static struct qreg
883 emit_fragment_varying(struct vc4_compile *c, int index)
884 {
885 struct qreg vary = {
886 QFILE_VARY,
887 index
888 };
889
890 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
891 }
892
893 static void
894 emit_fragment_input(struct vc4_compile *c, int attr,
895 struct tgsi_full_declaration *decl)
896 {
897 for (int i = 0; i < 4; i++) {
898 c->inputs[attr * 4 + i] =
899 emit_fragment_varying(c, attr * 4 + i);
900 c->num_inputs++;
901
902 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR ||
903 decl->Semantic.Name == TGSI_SEMANTIC_BCOLOR)
904 c->color_inputs |= 1 << i;
905 }
906 }
907
908 static void
909 emit_tgsi_declaration(struct vc4_compile *c,
910 struct tgsi_full_declaration *decl)
911 {
912 switch (decl->Declaration.File) {
913 case TGSI_FILE_TEMPORARY:
914 resize_qreg_array(c, &c->temps, &c->temps_array_size,
915 (decl->Range.Last + 1) * 4);
916 break;
917
918 case TGSI_FILE_INPUT:
919 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
920 (decl->Range.Last + 1) * 4);
921
922 for (int i = decl->Range.First;
923 i <= decl->Range.Last;
924 i++) {
925 if (c->stage == QSTAGE_FRAG) {
926 if (decl->Semantic.Name ==
927 TGSI_SEMANTIC_POSITION) {
928 emit_fragcoord_input(c, i);
929 } else if (decl->Semantic.Name == TGSI_SEMANTIC_GENERIC &&
930 (c->fs_key->point_sprite_mask &
931 (1 << decl->Semantic.Index))) {
932 emit_point_coord_input(c, i);
933 } else {
934 emit_fragment_input(c, i, decl);
935 }
936 } else {
937 emit_vertex_input(c, i);
938 }
939 }
940 break;
941
942 case TGSI_FILE_OUTPUT:
943 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
944 (decl->Range.Last + 1) * 4);
945
946 switch (decl->Semantic.Name) {
947 case TGSI_SEMANTIC_POSITION:
948 c->output_position_index = decl->Range.First * 4;
949 break;
950 case TGSI_SEMANTIC_COLOR:
951 c->output_color_index = decl->Range.First * 4;
952 break;
953 case TGSI_SEMANTIC_PSIZE:
954 c->output_point_size_index = decl->Range.First * 4;
955 break;
956 }
957
958 break;
959 }
960 }
961
962 static void
963 emit_tgsi_instruction(struct vc4_compile *c,
964 struct tgsi_full_instruction *tgsi_inst)
965 {
966 struct {
967 enum qop op;
968 struct qreg (*func)(struct vc4_compile *c,
969 struct tgsi_full_instruction *tgsi_inst,
970 enum qop op,
971 struct qreg *src, int i);
972 } op_trans[] = {
973 [TGSI_OPCODE_MOV] = { QOP_MOV, tgsi_to_qir_alu },
974 [TGSI_OPCODE_ABS] = { 0, tgsi_to_qir_abs },
975 [TGSI_OPCODE_MUL] = { QOP_FMUL, tgsi_to_qir_alu },
976 [TGSI_OPCODE_ADD] = { QOP_FADD, tgsi_to_qir_alu },
977 [TGSI_OPCODE_SUB] = { QOP_FSUB, tgsi_to_qir_alu },
978 [TGSI_OPCODE_MIN] = { QOP_FMIN, tgsi_to_qir_alu },
979 [TGSI_OPCODE_MAX] = { QOP_FMAX, tgsi_to_qir_alu },
980 [TGSI_OPCODE_F2I] = { QOP_FTOI, tgsi_to_qir_alu },
981 [TGSI_OPCODE_I2F] = { QOP_ITOF, tgsi_to_qir_alu },
982 [TGSI_OPCODE_UADD] = { QOP_ADD, tgsi_to_qir_alu },
983 [TGSI_OPCODE_USHR] = { QOP_SHR, tgsi_to_qir_alu },
984 [TGSI_OPCODE_ISHR] = { QOP_ASR, tgsi_to_qir_alu },
985 [TGSI_OPCODE_SHL] = { QOP_SHL, tgsi_to_qir_alu },
986 [TGSI_OPCODE_IMIN] = { QOP_MIN, tgsi_to_qir_alu },
987 [TGSI_OPCODE_IMAX] = { QOP_MAX, tgsi_to_qir_alu },
988 [TGSI_OPCODE_AND] = { QOP_AND, tgsi_to_qir_alu },
989 [TGSI_OPCODE_OR] = { QOP_OR, tgsi_to_qir_alu },
990 [TGSI_OPCODE_XOR] = { QOP_XOR, tgsi_to_qir_alu },
991 [TGSI_OPCODE_NOT] = { QOP_NOT, tgsi_to_qir_alu },
992
993 [TGSI_OPCODE_UMUL] = { 0, tgsi_to_qir_umul },
994 [TGSI_OPCODE_IDIV] = { 0, tgsi_to_qir_idiv },
995 [TGSI_OPCODE_INEG] = { 0, tgsi_to_qir_ineg },
996
997 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_alu },
998 [TGSI_OPCODE_SEQ] = { 0, tgsi_to_qir_seq },
999 [TGSI_OPCODE_SNE] = { 0, tgsi_to_qir_sne },
1000 [TGSI_OPCODE_SGE] = { 0, tgsi_to_qir_sge },
1001 [TGSI_OPCODE_SLT] = { 0, tgsi_to_qir_slt },
1002 [TGSI_OPCODE_FSEQ] = { 0, tgsi_to_qir_fseq },
1003 [TGSI_OPCODE_FSNE] = { 0, tgsi_to_qir_fsne },
1004 [TGSI_OPCODE_FSGE] = { 0, tgsi_to_qir_fsge },
1005 [TGSI_OPCODE_FSLT] = { 0, tgsi_to_qir_fslt },
1006 [TGSI_OPCODE_USEQ] = { 0, tgsi_to_qir_useq },
1007 [TGSI_OPCODE_USNE] = { 0, tgsi_to_qir_usne },
1008 [TGSI_OPCODE_ISGE] = { 0, tgsi_to_qir_isge },
1009 [TGSI_OPCODE_ISLT] = { 0, tgsi_to_qir_islt },
1010
1011 [TGSI_OPCODE_CMP] = { 0, tgsi_to_qir_cmp },
1012 [TGSI_OPCODE_MAD] = { 0, tgsi_to_qir_mad },
1013 [TGSI_OPCODE_DP2] = { 0, tgsi_to_qir_dp2 },
1014 [TGSI_OPCODE_DP3] = { 0, tgsi_to_qir_dp3 },
1015 [TGSI_OPCODE_DP4] = { 0, tgsi_to_qir_dp4 },
1016 [TGSI_OPCODE_RCP] = { QOP_RCP, tgsi_to_qir_alu },
1017 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_alu },
1018 [TGSI_OPCODE_EX2] = { QOP_EXP2, tgsi_to_qir_alu },
1019 [TGSI_OPCODE_LG2] = { QOP_LOG2, tgsi_to_qir_alu },
1020 [TGSI_OPCODE_LIT] = { 0, tgsi_to_qir_lit },
1021 [TGSI_OPCODE_LRP] = { 0, tgsi_to_qir_lrp },
1022 [TGSI_OPCODE_POW] = { 0, tgsi_to_qir_pow },
1023 [TGSI_OPCODE_TRUNC] = { 0, tgsi_to_qir_trunc },
1024 [TGSI_OPCODE_FRC] = { 0, tgsi_to_qir_frc },
1025 [TGSI_OPCODE_FLR] = { 0, tgsi_to_qir_flr },
1026 [TGSI_OPCODE_SIN] = { 0, tgsi_to_qir_sin },
1027 [TGSI_OPCODE_COS] = { 0, tgsi_to_qir_cos },
1028 };
1029 static int asdf = 0;
1030 uint32_t tgsi_op = tgsi_inst->Instruction.Opcode;
1031
1032 if (tgsi_op == TGSI_OPCODE_END)
1033 return;
1034
1035 struct qreg src_regs[12];
1036 for (int s = 0; s < 3; s++) {
1037 for (int i = 0; i < 4; i++) {
1038 src_regs[4 * s + i] =
1039 get_src(c, tgsi_inst->Instruction.Opcode,
1040 &tgsi_inst->Src[s].Register, i);
1041 }
1042 }
1043
1044 switch (tgsi_op) {
1045 case TGSI_OPCODE_TEX:
1046 case TGSI_OPCODE_TXP:
1047 case TGSI_OPCODE_TXB:
1048 tgsi_to_qir_tex(c, tgsi_inst,
1049 op_trans[tgsi_op].op, src_regs);
1050 return;
1051 case TGSI_OPCODE_KILL:
1052 c->discard = qir_uniform_f(c, 1.0);
1053 return;
1054 case TGSI_OPCODE_KILL_IF:
1055 for (int i = 0; i < 4; i++)
1056 tgsi_to_qir_kill_if(c, src_regs, i);
1057 return;
1058 default:
1059 break;
1060 }
1061
1062 if (tgsi_op > ARRAY_SIZE(op_trans) || !(op_trans[tgsi_op].func)) {
1063 fprintf(stderr, "unknown tgsi inst: ");
1064 tgsi_dump_instruction(tgsi_inst, asdf++);
1065 fprintf(stderr, "\n");
1066 abort();
1067 }
1068
1069 for (int i = 0; i < 4; i++) {
1070 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
1071 continue;
1072
1073 struct qreg result;
1074
1075 result = op_trans[tgsi_op].func(c, tgsi_inst,
1076 op_trans[tgsi_op].op,
1077 src_regs, i);
1078
1079 if (tgsi_inst->Instruction.Saturate) {
1080 float low = (tgsi_inst->Instruction.Saturate ==
1081 TGSI_SAT_MINUS_PLUS_ONE ? -1.0 : 0.0);
1082 result = qir_FMAX(c,
1083 qir_FMIN(c,
1084 result,
1085 qir_uniform_f(c, 1.0)),
1086 qir_uniform_f(c, low));
1087 }
1088
1089 update_dst(c, tgsi_inst, i, result);
1090 }
1091 }
1092
1093 static void
1094 parse_tgsi_immediate(struct vc4_compile *c, struct tgsi_full_immediate *imm)
1095 {
1096 for (int i = 0; i < 4; i++) {
1097 unsigned n = c->num_consts++;
1098 resize_qreg_array(c, &c->consts, &c->consts_array_size, n + 1);
1099 c->consts[n] = qir_uniform_ui(c, imm->u[i].Uint);
1100 }
1101 }
1102
1103 static struct qreg
1104 vc4_blend_channel(struct vc4_compile *c,
1105 struct qreg *dst,
1106 struct qreg *src,
1107 struct qreg val,
1108 unsigned factor,
1109 int channel)
1110 {
1111 switch(factor) {
1112 case PIPE_BLENDFACTOR_ONE:
1113 return val;
1114 case PIPE_BLENDFACTOR_SRC_COLOR:
1115 return qir_FMUL(c, val, src[channel]);
1116 case PIPE_BLENDFACTOR_SRC_ALPHA:
1117 return qir_FMUL(c, val, src[3]);
1118 case PIPE_BLENDFACTOR_DST_ALPHA:
1119 return qir_FMUL(c, val, dst[3]);
1120 case PIPE_BLENDFACTOR_DST_COLOR:
1121 return qir_FMUL(c, val, dst[channel]);
1122 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
1123 return qir_FMIN(c, src[3], qir_FSUB(c,
1124 qir_uniform_f(c, 1.0),
1125 dst[3]));
1126 case PIPE_BLENDFACTOR_CONST_COLOR:
1127 return qir_FMUL(c, val,
1128 get_temp_for_uniform(c,
1129 QUNIFORM_BLEND_CONST_COLOR,
1130 channel));
1131 case PIPE_BLENDFACTOR_CONST_ALPHA:
1132 return qir_FMUL(c, val,
1133 get_temp_for_uniform(c,
1134 QUNIFORM_BLEND_CONST_COLOR,
1135 3));
1136 case PIPE_BLENDFACTOR_ZERO:
1137 return qir_uniform_f(c, 0.0);
1138 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
1139 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1140 src[channel]));
1141 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
1142 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1143 src[3]));
1144 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
1145 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1146 dst[3]));
1147 case PIPE_BLENDFACTOR_INV_DST_COLOR:
1148 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1149 dst[channel]));
1150 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
1151 return qir_FMUL(c, val,
1152 qir_FSUB(c, qir_uniform_f(c, 1.0),
1153 get_temp_for_uniform(c,
1154 QUNIFORM_BLEND_CONST_COLOR,
1155 channel)));
1156 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
1157 return qir_FMUL(c, val,
1158 qir_FSUB(c, qir_uniform_f(c, 1.0),
1159 get_temp_for_uniform(c,
1160 QUNIFORM_BLEND_CONST_COLOR,
1161 3)));
1162
1163 default:
1164 case PIPE_BLENDFACTOR_SRC1_COLOR:
1165 case PIPE_BLENDFACTOR_SRC1_ALPHA:
1166 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
1167 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
1168 /* Unsupported. */
1169 fprintf(stderr, "Unknown blend factor %d\n", factor);
1170 return val;
1171 }
1172 }
1173
1174 static struct qreg
1175 vc4_blend_func(struct vc4_compile *c,
1176 struct qreg src, struct qreg dst,
1177 unsigned func)
1178 {
1179 switch (func) {
1180 case PIPE_BLEND_ADD:
1181 return qir_FADD(c, src, dst);
1182 case PIPE_BLEND_SUBTRACT:
1183 return qir_FSUB(c, src, dst);
1184 case PIPE_BLEND_REVERSE_SUBTRACT:
1185 return qir_FSUB(c, dst, src);
1186 case PIPE_BLEND_MIN:
1187 return qir_FMIN(c, src, dst);
1188 case PIPE_BLEND_MAX:
1189 return qir_FMAX(c, src, dst);
1190
1191 default:
1192 /* Unsupported. */
1193 fprintf(stderr, "Unknown blend func %d\n", func);
1194 return src;
1195
1196 }
1197 }
1198
1199 /**
1200 * Implements fixed function blending in shader code.
1201 *
1202 * VC4 doesn't have any hardware support for blending. Instead, you read the
1203 * current contents of the destination from the tile buffer after having
1204 * waited for the scoreboard (which is handled by vc4_qpu_emit.c), then do
1205 * math using your output color and that destination value, and update the
1206 * output color appropriately.
1207 */
1208 static void
1209 vc4_blend(struct vc4_compile *c, struct qreg *result,
1210 struct qreg *dst_color, struct qreg *src_color)
1211 {
1212 struct pipe_rt_blend_state *blend = &c->fs_key->blend;
1213
1214 if (!blend->blend_enable) {
1215 for (int i = 0; i < 4; i++)
1216 result[i] = src_color[i];
1217 return;
1218 }
1219
1220 struct qreg src_blend[4], dst_blend[4];
1221 for (int i = 0; i < 3; i++) {
1222 src_blend[i] = vc4_blend_channel(c,
1223 dst_color, src_color,
1224 src_color[i],
1225 blend->rgb_src_factor, i);
1226 dst_blend[i] = vc4_blend_channel(c,
1227 dst_color, src_color,
1228 dst_color[i],
1229 blend->rgb_dst_factor, i);
1230 }
1231 src_blend[3] = vc4_blend_channel(c,
1232 dst_color, src_color,
1233 src_color[3],
1234 blend->alpha_src_factor, 3);
1235 dst_blend[3] = vc4_blend_channel(c,
1236 dst_color, src_color,
1237 dst_color[3],
1238 blend->alpha_dst_factor, 3);
1239
1240 for (int i = 0; i < 3; i++) {
1241 result[i] = vc4_blend_func(c,
1242 src_blend[i], dst_blend[i],
1243 blend->rgb_func);
1244 }
1245 result[3] = vc4_blend_func(c,
1246 src_blend[3], dst_blend[3],
1247 blend->alpha_func);
1248 }
1249
1250 static void
1251 alpha_test_discard(struct vc4_compile *c)
1252 {
1253 struct qreg src_alpha;
1254 struct qreg alpha_ref = get_temp_for_uniform(c, QUNIFORM_ALPHA_REF, 0);
1255
1256 if (!c->fs_key->alpha_test)
1257 return;
1258
1259 if (c->output_color_index != -1)
1260 src_alpha = c->outputs[c->output_color_index + 3];
1261 else
1262 src_alpha = qir_uniform_f(c, 1.0);
1263
1264 if (c->discard.file == QFILE_NULL)
1265 c->discard = qir_uniform_f(c, 0.0);
1266
1267 switch (c->fs_key->alpha_test_func) {
1268 case PIPE_FUNC_NEVER:
1269 c->discard = qir_uniform_f(c, 1.0);
1270 break;
1271 case PIPE_FUNC_ALWAYS:
1272 break;
1273 case PIPE_FUNC_EQUAL:
1274 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1275 c->discard = qir_SEL_X_Y_ZS(c, c->discard,
1276 qir_uniform_f(c, 1.0));
1277 break;
1278 case PIPE_FUNC_NOTEQUAL:
1279 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1280 c->discard = qir_SEL_X_Y_ZC(c, c->discard,
1281 qir_uniform_f(c, 1.0));
1282 break;
1283 case PIPE_FUNC_GREATER:
1284 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1285 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1286 qir_uniform_f(c, 1.0));
1287 break;
1288 case PIPE_FUNC_GEQUAL:
1289 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1290 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1291 qir_uniform_f(c, 1.0));
1292 break;
1293 case PIPE_FUNC_LESS:
1294 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1295 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1296 qir_uniform_f(c, 1.0));
1297 break;
1298 case PIPE_FUNC_LEQUAL:
1299 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1300 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1301 qir_uniform_f(c, 1.0));
1302 break;
1303 }
1304 }
1305
1306 static void
1307 emit_frag_end(struct vc4_compile *c)
1308 {
1309 alpha_test_discard(c);
1310
1311 enum pipe_format color_format = c->fs_key->color_format;
1312 const uint8_t *format_swiz = vc4_get_format_swizzle(color_format);
1313 struct qreg tlb_read_color[4] = { c->undef, c->undef, c->undef, c->undef };
1314 struct qreg dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1315 if (c->fs_key->blend.blend_enable ||
1316 c->fs_key->blend.colormask != 0xf) {
1317 struct qreg r4 = qir_TLB_COLOR_READ(c);
1318 for (int i = 0; i < 4; i++)
1319 tlb_read_color[i] = qir_R4_UNPACK(c, r4, i);
1320 for (int i = 0; i < 4; i++)
1321 dst_color[i] = get_swizzled_channel(c,
1322 tlb_read_color,
1323 format_swiz[i]);
1324 }
1325
1326 struct qreg blend_color[4];
1327 struct qreg undef_array[4] = {
1328 c->undef, c->undef, c->undef, c->undef
1329 };
1330 vc4_blend(c, blend_color, dst_color,
1331 (c->output_color_index != -1 ?
1332 c->outputs + c->output_color_index :
1333 undef_array));
1334
1335 /* If the bit isn't set in the color mask, then just return the
1336 * original dst color, instead.
1337 */
1338 for (int i = 0; i < 4; i++) {
1339 if (!(c->fs_key->blend.colormask & (1 << i))) {
1340 blend_color[i] = dst_color[i];
1341 }
1342 }
1343
1344 /* Debug: Sometimes you're getting a black output and just want to see
1345 * if the FS is getting executed at all. Spam magenta into the color
1346 * output.
1347 */
1348 if (0) {
1349 blend_color[0] = qir_uniform_f(c, 1.0);
1350 blend_color[1] = qir_uniform_f(c, 0.0);
1351 blend_color[2] = qir_uniform_f(c, 1.0);
1352 blend_color[3] = qir_uniform_f(c, 0.5);
1353 }
1354
1355 struct qreg swizzled_outputs[4];
1356 for (int i = 0; i < 4; i++) {
1357 swizzled_outputs[i] = get_swizzled_channel(c, blend_color,
1358 format_swiz[i]);
1359 }
1360
1361 if (c->discard.file != QFILE_NULL)
1362 qir_TLB_DISCARD_SETUP(c, c->discard);
1363
1364 if (c->fs_key->stencil_enabled) {
1365 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 0));
1366 if (c->fs_key->stencil_twoside) {
1367 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 1));
1368 }
1369 if (c->fs_key->stencil_full_writemasks) {
1370 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 2));
1371 }
1372 }
1373
1374 if (c->fs_key->depth_enabled) {
1375 struct qreg z;
1376 if (c->output_position_index != -1) {
1377 z = qir_FTOI(c, qir_FMUL(c, c->outputs[c->output_position_index + 2],
1378 qir_uniform_f(c, 0xffffff)));
1379 } else {
1380 z = qir_FRAG_Z(c);
1381 }
1382 qir_TLB_Z_WRITE(c, z);
1383 }
1384
1385 bool color_written = false;
1386 for (int i = 0; i < 4; i++) {
1387 if (swizzled_outputs[i].file != QFILE_NULL)
1388 color_written = true;
1389 }
1390
1391 struct qreg packed_color;
1392 if (color_written) {
1393 /* Fill in any undefined colors. The simulator will assertion
1394 * fail if we read something that wasn't written, and I don't
1395 * know what hardware does.
1396 */
1397 for (int i = 0; i < 4; i++) {
1398 if (swizzled_outputs[i].file == QFILE_NULL)
1399 swizzled_outputs[i] = qir_uniform_f(c, 0.0);
1400 }
1401 packed_color = qir_get_temp(c);
1402 qir_emit(c, qir_inst4(QOP_PACK_COLORS, packed_color,
1403 swizzled_outputs[0],
1404 swizzled_outputs[1],
1405 swizzled_outputs[2],
1406 swizzled_outputs[3]));
1407 } else {
1408 packed_color = qir_uniform_ui(c, 0);
1409 }
1410
1411 qir_emit(c, qir_inst(QOP_TLB_COLOR_WRITE, c->undef,
1412 packed_color, c->undef));
1413 }
1414
1415 static void
1416 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1417 {
1418 struct qreg xyi[2];
1419
1420 for (int i = 0; i < 2; i++) {
1421 struct qreg scale =
1422 add_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1423
1424 xyi[i] = qir_FTOI(c, qir_FMUL(c,
1425 qir_FMUL(c,
1426 c->outputs[i],
1427 scale),
1428 rcp_w));
1429 }
1430
1431 qir_VPM_WRITE(c, qir_PACK_SCALED(c, xyi[0], xyi[1]));
1432 }
1433
1434 static void
1435 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1436 {
1437 struct qreg zscale = add_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1438 struct qreg zoffset = add_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1439
1440 qir_VPM_WRITE(c, qir_FMUL(c, qir_FADD(c, qir_FMUL(c,
1441 c->outputs[2],
1442 zscale),
1443 zoffset),
1444 rcp_w));
1445 }
1446
1447 static void
1448 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1449 {
1450 qir_VPM_WRITE(c, rcp_w);
1451 }
1452
1453 static void
1454 emit_point_size_write(struct vc4_compile *c)
1455 {
1456 struct qreg point_size;
1457
1458 if (c->output_point_size_index)
1459 point_size = c->outputs[c->output_point_size_index + 3];
1460 else
1461 point_size = qir_uniform_f(c, 1.0);
1462
1463 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1464 * BCM21553).
1465 */
1466 point_size = qir_FMAX(c, point_size, qir_uniform_f(c, .125));
1467
1468 qir_VPM_WRITE(c, point_size);
1469 }
1470
1471 static void
1472 emit_vert_end(struct vc4_compile *c)
1473 {
1474 struct qreg rcp_w = qir_RCP(c, c->outputs[3]);
1475
1476 emit_scaled_viewport_write(c, rcp_w);
1477 emit_zs_write(c, rcp_w);
1478 emit_rcp_wc_write(c, rcp_w);
1479 if (c->vs_key->per_vertex_point_size)
1480 emit_point_size_write(c);
1481
1482 for (int i = 4; i < c->num_outputs; i++) {
1483 qir_VPM_WRITE(c, c->outputs[i]);
1484 }
1485 }
1486
1487 static void
1488 emit_coord_end(struct vc4_compile *c)
1489 {
1490 struct qreg rcp_w = qir_RCP(c, c->outputs[3]);
1491
1492 for (int i = 0; i < 4; i++)
1493 qir_VPM_WRITE(c, c->outputs[i]);
1494
1495 emit_scaled_viewport_write(c, rcp_w);
1496 emit_zs_write(c, rcp_w);
1497 emit_rcp_wc_write(c, rcp_w);
1498 if (c->vs_key->per_vertex_point_size)
1499 emit_point_size_write(c);
1500 }
1501
1502 static struct vc4_compile *
1503 vc4_shader_tgsi_to_qir(struct vc4_context *vc4,
1504 struct vc4_compiled_shader *shader, enum qstage stage,
1505 struct vc4_key *key)
1506 {
1507 struct vc4_compile *c = qir_compile_init();
1508 int ret;
1509
1510 c->stage = stage;
1511
1512 c->uniform_data = ralloc_array(c, uint32_t, 1024);
1513 c->uniform_contents = ralloc_array(c, enum quniform_contents, 1024);
1514
1515 c->shader_state = key->shader_state;
1516 ret = tgsi_parse_init(&c->parser, c->shader_state->tokens);
1517 assert(ret == TGSI_PARSE_OK);
1518
1519 if (vc4_debug & VC4_DEBUG_TGSI) {
1520 fprintf(stderr, "TGSI:\n");
1521 tgsi_dump(c->shader_state->tokens, 0);
1522 }
1523
1524 c->key = key;
1525 switch (stage) {
1526 case QSTAGE_FRAG:
1527 c->fs_key = (struct vc4_fs_key *)key;
1528 if (c->fs_key->is_points) {
1529 c->point_x = emit_fragment_varying(c, 0);
1530 c->point_y = emit_fragment_varying(c, 0);
1531 } else if (c->fs_key->is_lines) {
1532 c->line_x = emit_fragment_varying(c, 0);
1533 }
1534 break;
1535 case QSTAGE_VERT:
1536 c->vs_key = (struct vc4_vs_key *)key;
1537 break;
1538 case QSTAGE_COORD:
1539 c->vs_key = (struct vc4_vs_key *)key;
1540 break;
1541 }
1542
1543 while (!tgsi_parse_end_of_tokens(&c->parser)) {
1544 tgsi_parse_token(&c->parser);
1545
1546 switch (c->parser.FullToken.Token.Type) {
1547 case TGSI_TOKEN_TYPE_DECLARATION:
1548 emit_tgsi_declaration(c,
1549 &c->parser.FullToken.FullDeclaration);
1550 break;
1551
1552 case TGSI_TOKEN_TYPE_INSTRUCTION:
1553 emit_tgsi_instruction(c,
1554 &c->parser.FullToken.FullInstruction);
1555 break;
1556
1557 case TGSI_TOKEN_TYPE_IMMEDIATE:
1558 parse_tgsi_immediate(c,
1559 &c->parser.FullToken.FullImmediate);
1560 break;
1561 }
1562 }
1563
1564 switch (stage) {
1565 case QSTAGE_FRAG:
1566 emit_frag_end(c);
1567 break;
1568 case QSTAGE_VERT:
1569 emit_vert_end(c);
1570 break;
1571 case QSTAGE_COORD:
1572 emit_coord_end(c);
1573 break;
1574 }
1575
1576 tgsi_parse_free(&c->parser);
1577
1578 qir_optimize(c);
1579
1580 if (vc4_debug & VC4_DEBUG_QIR) {
1581 fprintf(stderr, "QIR:\n");
1582 qir_dump(c);
1583 }
1584 qir_reorder_uniforms(c);
1585 vc4_generate_code(vc4, c);
1586
1587 if (vc4_debug & VC4_DEBUG_SHADERDB) {
1588 fprintf(stderr, "SHADER-DB: %s: %d instructions\n",
1589 qir_get_stage_name(c->stage), c->qpu_inst_count);
1590 fprintf(stderr, "SHADER-DB: %s: %d uniforms\n",
1591 qir_get_stage_name(c->stage), c->num_uniforms);
1592 }
1593
1594 return c;
1595 }
1596
1597 static void *
1598 vc4_shader_state_create(struct pipe_context *pctx,
1599 const struct pipe_shader_state *cso)
1600 {
1601 struct pipe_shader_state *so = CALLOC_STRUCT(pipe_shader_state);
1602 if (!so)
1603 return NULL;
1604
1605 so->tokens = tgsi_dup_tokens(cso->tokens);
1606
1607 return so;
1608 }
1609
1610 static void
1611 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
1612 int shader_index,
1613 struct vc4_compile *c)
1614 {
1615 int count = c->num_uniforms;
1616 struct vc4_shader_uniform_info *uinfo = &shader->uniforms[shader_index];
1617
1618 uinfo->count = count;
1619 uinfo->data = malloc(count * sizeof(*uinfo->data));
1620 memcpy(uinfo->data, c->uniform_data,
1621 count * sizeof(*uinfo->data));
1622 uinfo->contents = malloc(count * sizeof(*uinfo->contents));
1623 memcpy(uinfo->contents, c->uniform_contents,
1624 count * sizeof(*uinfo->contents));
1625 uinfo->num_texture_samples = c->num_texture_samples;
1626 }
1627
1628 static void
1629 vc4_fs_compile(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1630 struct vc4_fs_key *key)
1631 {
1632 struct vc4_compile *c = vc4_shader_tgsi_to_qir(vc4, shader,
1633 QSTAGE_FRAG,
1634 &key->base);
1635 shader->num_inputs = c->num_inputs;
1636 shader->color_inputs = c->color_inputs;
1637 copy_uniform_state_to_shader(shader, 0, c);
1638 shader->bo = vc4_bo_alloc_mem(vc4->screen, c->qpu_insts,
1639 c->qpu_inst_count * sizeof(uint64_t),
1640 "fs_code");
1641
1642 qir_compile_destroy(c);
1643 }
1644
1645 static void
1646 vc4_vs_compile(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1647 struct vc4_vs_key *key)
1648 {
1649 struct vc4_compile *vs_c = vc4_shader_tgsi_to_qir(vc4, shader,
1650 QSTAGE_VERT,
1651 &key->base);
1652 copy_uniform_state_to_shader(shader, 0, vs_c);
1653
1654 struct vc4_compile *cs_c = vc4_shader_tgsi_to_qir(vc4, shader,
1655 QSTAGE_COORD,
1656 &key->base);
1657 copy_uniform_state_to_shader(shader, 1, cs_c);
1658
1659 uint32_t vs_size = vs_c->qpu_inst_count * sizeof(uint64_t);
1660 uint32_t cs_size = cs_c->qpu_inst_count * sizeof(uint64_t);
1661 shader->coord_shader_offset = vs_size; /* XXX: alignment? */
1662 shader->bo = vc4_bo_alloc(vc4->screen,
1663 shader->coord_shader_offset + cs_size,
1664 "vs_code");
1665
1666 void *map = vc4_bo_map(shader->bo);
1667 memcpy(map, vs_c->qpu_insts, vs_size);
1668 memcpy(map + shader->coord_shader_offset,
1669 cs_c->qpu_insts, cs_size);
1670
1671 qir_compile_destroy(vs_c);
1672 qir_compile_destroy(cs_c);
1673 }
1674
1675 static void
1676 vc4_setup_shared_key(struct vc4_key *key, struct vc4_texture_stateobj *texstate)
1677 {
1678 for (int i = 0; i < texstate->num_textures; i++) {
1679 struct pipe_sampler_view *sampler = texstate->textures[i];
1680 struct pipe_sampler_state *sampler_state =
1681 texstate->samplers[i];
1682
1683 if (sampler) {
1684 struct pipe_resource *prsc = sampler->texture;
1685 key->tex[i].format = prsc->format;
1686 key->tex[i].swizzle[0] = sampler->swizzle_r;
1687 key->tex[i].swizzle[1] = sampler->swizzle_g;
1688 key->tex[i].swizzle[2] = sampler->swizzle_b;
1689 key->tex[i].swizzle[3] = sampler->swizzle_a;
1690 key->tex[i].compare_mode = sampler_state->compare_mode;
1691 key->tex[i].compare_func = sampler_state->compare_func;
1692 }
1693 }
1694 }
1695
1696 static void
1697 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
1698 {
1699 struct vc4_fs_key local_key;
1700 struct vc4_fs_key *key = &local_key;
1701
1702 memset(key, 0, sizeof(*key));
1703 vc4_setup_shared_key(&key->base, &vc4->fragtex);
1704 key->base.shader_state = vc4->prog.bind_fs;
1705 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
1706 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
1707 prim_mode <= PIPE_PRIM_LINE_STRIP);
1708 key->blend = vc4->blend->rt[0];
1709
1710 if (vc4->framebuffer.cbufs[0])
1711 key->color_format = vc4->framebuffer.cbufs[0]->format;
1712
1713 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
1714 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
1715 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
1716 key->depth_enabled = (vc4->zsa->base.depth.enabled ||
1717 key->stencil_enabled);
1718 if (vc4->zsa->base.alpha.enabled) {
1719 key->alpha_test = true;
1720 key->alpha_test_func = vc4->zsa->base.alpha.func;
1721 }
1722
1723 if (key->is_points) {
1724 key->point_sprite_mask =
1725 vc4->rasterizer->base.sprite_coord_enable;
1726 key->point_coord_upper_left =
1727 (vc4->rasterizer->base.sprite_coord_mode ==
1728 PIPE_SPRITE_COORD_UPPER_LEFT);
1729 }
1730
1731 vc4->prog.fs = util_hash_table_get(vc4->fs_cache, key);
1732 if (vc4->prog.fs)
1733 return;
1734
1735 key = malloc(sizeof(*key));
1736 memcpy(key, &local_key, sizeof(*key));
1737
1738 struct vc4_compiled_shader *shader = CALLOC_STRUCT(vc4_compiled_shader);
1739 vc4_fs_compile(vc4, shader, key);
1740 util_hash_table_set(vc4->fs_cache, key, shader);
1741
1742 if (vc4->rasterizer->base.flatshade &&
1743 vc4->prog.fs &&
1744 vc4->prog.fs->color_inputs != shader->color_inputs) {
1745 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
1746 }
1747
1748 vc4->prog.fs = shader;
1749 }
1750
1751 static void
1752 vc4_update_compiled_vs(struct vc4_context *vc4, uint8_t prim_mode)
1753 {
1754 struct vc4_vs_key local_key;
1755 struct vc4_vs_key *key = &local_key;
1756
1757 memset(key, 0, sizeof(*key));
1758 vc4_setup_shared_key(&key->base, &vc4->verttex);
1759 key->base.shader_state = vc4->prog.bind_vs;
1760
1761 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
1762 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
1763
1764 key->per_vertex_point_size =
1765 (prim_mode == PIPE_PRIM_POINTS &&
1766 vc4->rasterizer->base.point_size_per_vertex);
1767
1768 vc4->prog.vs = util_hash_table_get(vc4->vs_cache, key);
1769 if (vc4->prog.vs)
1770 return;
1771
1772 key = malloc(sizeof(*key));
1773 memcpy(key, &local_key, sizeof(*key));
1774
1775 struct vc4_compiled_shader *shader = CALLOC_STRUCT(vc4_compiled_shader);
1776 vc4_vs_compile(vc4, shader, key);
1777 util_hash_table_set(vc4->vs_cache, key, shader);
1778
1779 vc4->prog.vs = shader;
1780 }
1781
1782 void
1783 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
1784 {
1785 vc4_update_compiled_fs(vc4, prim_mode);
1786 vc4_update_compiled_vs(vc4, prim_mode);
1787 }
1788
1789 static unsigned
1790 fs_cache_hash(void *key)
1791 {
1792 return util_hash_crc32(key, sizeof(struct vc4_fs_key));
1793 }
1794
1795 static unsigned
1796 vs_cache_hash(void *key)
1797 {
1798 return util_hash_crc32(key, sizeof(struct vc4_vs_key));
1799 }
1800
1801 static int
1802 fs_cache_compare(void *key1, void *key2)
1803 {
1804 return memcmp(key1, key2, sizeof(struct vc4_fs_key));
1805 }
1806
1807 static int
1808 vs_cache_compare(void *key1, void *key2)
1809 {
1810 return memcmp(key1, key2, sizeof(struct vc4_vs_key));
1811 }
1812
1813 struct delete_state {
1814 struct vc4_context *vc4;
1815 struct pipe_shader_state *shader_state;
1816 };
1817
1818 static enum pipe_error
1819 fs_delete_from_cache(void *in_key, void *in_value, void *data)
1820 {
1821 struct delete_state *del = data;
1822 struct vc4_fs_key *key = in_key;
1823 struct vc4_compiled_shader *shader = in_value;
1824
1825 if (key->base.shader_state == data) {
1826 util_hash_table_remove(del->vc4->fs_cache, key);
1827 vc4_bo_unreference(&shader->bo);
1828 free(shader);
1829 }
1830
1831 return 0;
1832 }
1833
1834 static enum pipe_error
1835 vs_delete_from_cache(void *in_key, void *in_value, void *data)
1836 {
1837 struct delete_state *del = data;
1838 struct vc4_vs_key *key = in_key;
1839 struct vc4_compiled_shader *shader = in_value;
1840
1841 if (key->base.shader_state == data) {
1842 util_hash_table_remove(del->vc4->vs_cache, key);
1843 vc4_bo_unreference(&shader->bo);
1844 free(shader);
1845 }
1846
1847 return 0;
1848 }
1849
1850 static void
1851 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
1852 {
1853 struct vc4_context *vc4 = vc4_context(pctx);
1854 struct pipe_shader_state *so = hwcso;
1855 struct delete_state del;
1856
1857 del.vc4 = vc4;
1858 del.shader_state = so;
1859 util_hash_table_foreach(vc4->fs_cache, fs_delete_from_cache, &del);
1860 util_hash_table_foreach(vc4->vs_cache, vs_delete_from_cache, &del);
1861
1862 free((void *)so->tokens);
1863 free(so);
1864 }
1865
1866 static uint32_t translate_wrap(uint32_t p_wrap)
1867 {
1868 switch (p_wrap) {
1869 case PIPE_TEX_WRAP_REPEAT:
1870 return 0;
1871 case PIPE_TEX_WRAP_CLAMP:
1872 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1873 return 1;
1874 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1875 return 2;
1876 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1877 return 3;
1878 default:
1879 fprintf(stderr, "Unknown wrap mode %d\n", p_wrap);
1880 assert(!"not reached");
1881 return 0;
1882 }
1883 }
1884
1885 static void
1886 write_texture_p0(struct vc4_context *vc4,
1887 struct vc4_texture_stateobj *texstate,
1888 uint32_t unit)
1889 {
1890 struct pipe_sampler_view *texture = texstate->textures[unit];
1891 struct vc4_resource *rsc = vc4_resource(texture->texture);
1892
1893 cl_reloc(vc4, &vc4->uniforms, rsc->bo,
1894 rsc->slices[0].offset | texture->u.tex.last_level |
1895 ((rsc->vc4_format & 7) << 4));
1896 }
1897
1898 static void
1899 write_texture_p1(struct vc4_context *vc4,
1900 struct vc4_texture_stateobj *texstate,
1901 uint32_t unit)
1902 {
1903 struct pipe_sampler_view *texture = texstate->textures[unit];
1904 struct vc4_resource *rsc = vc4_resource(texture->texture);
1905 struct pipe_sampler_state *sampler = texstate->samplers[unit];
1906 static const uint32_t mipfilter_map[] = {
1907 [PIPE_TEX_MIPFILTER_NEAREST] = 2,
1908 [PIPE_TEX_MIPFILTER_LINEAR] = 4,
1909 [PIPE_TEX_MIPFILTER_NONE] = 0
1910 };
1911 static const uint32_t imgfilter_map[] = {
1912 [PIPE_TEX_FILTER_NEAREST] = 1,
1913 [PIPE_TEX_FILTER_LINEAR] = 0,
1914 };
1915
1916 cl_u32(&vc4->uniforms,
1917 ((rsc->vc4_format >> 4) << 31) |
1918 (texture->texture->height0 << 20) |
1919 (texture->texture->width0 << 8) |
1920 (imgfilter_map[sampler->mag_img_filter] << 7) |
1921 ((imgfilter_map[sampler->min_img_filter] +
1922 mipfilter_map[sampler->min_mip_filter]) << 4) |
1923 (translate_wrap(sampler->wrap_t) << 2) |
1924 (translate_wrap(sampler->wrap_s) << 0));
1925 }
1926
1927 static uint32_t
1928 get_texrect_scale(struct vc4_texture_stateobj *texstate,
1929 enum quniform_contents contents,
1930 uint32_t data)
1931 {
1932 struct pipe_sampler_view *texture = texstate->textures[data];
1933 uint32_t dim;
1934
1935 if (contents == QUNIFORM_TEXRECT_SCALE_X)
1936 dim = texture->texture->width0;
1937 else
1938 dim = texture->texture->height0;
1939
1940 return fui(1.0f / dim);
1941 }
1942
1943 void
1944 vc4_write_uniforms(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1945 struct vc4_constbuf_stateobj *cb,
1946 struct vc4_texture_stateobj *texstate,
1947 int shader_index)
1948 {
1949 struct vc4_shader_uniform_info *uinfo = &shader->uniforms[shader_index];
1950 const uint32_t *gallium_uniforms = cb->cb[0].user_buffer;
1951
1952 cl_start_shader_reloc(&vc4->uniforms, uinfo->num_texture_samples);
1953
1954 for (int i = 0; i < uinfo->count; i++) {
1955
1956 switch (uinfo->contents[i]) {
1957 case QUNIFORM_CONSTANT:
1958 cl_u32(&vc4->uniforms, uinfo->data[i]);
1959 break;
1960 case QUNIFORM_UNIFORM:
1961 cl_u32(&vc4->uniforms,
1962 gallium_uniforms[uinfo->data[i]]);
1963 break;
1964 case QUNIFORM_VIEWPORT_X_SCALE:
1965 cl_f(&vc4->uniforms, vc4->viewport.scale[0] * 16.0f);
1966 break;
1967 case QUNIFORM_VIEWPORT_Y_SCALE:
1968 cl_f(&vc4->uniforms, vc4->viewport.scale[1] * 16.0f);
1969 break;
1970
1971 case QUNIFORM_VIEWPORT_Z_OFFSET:
1972 cl_f(&vc4->uniforms, vc4->viewport.translate[2]);
1973 break;
1974 case QUNIFORM_VIEWPORT_Z_SCALE:
1975 cl_f(&vc4->uniforms, vc4->viewport.scale[2]);
1976 break;
1977
1978 case QUNIFORM_TEXTURE_CONFIG_P0:
1979 write_texture_p0(vc4, texstate, uinfo->data[i]);
1980 break;
1981
1982 case QUNIFORM_TEXTURE_CONFIG_P1:
1983 write_texture_p1(vc4, texstate, uinfo->data[i]);
1984 break;
1985
1986 case QUNIFORM_TEXRECT_SCALE_X:
1987 case QUNIFORM_TEXRECT_SCALE_Y:
1988 cl_u32(&vc4->uniforms,
1989 get_texrect_scale(texstate,
1990 uinfo->contents[i],
1991 uinfo->data[i]));
1992 break;
1993
1994 case QUNIFORM_BLEND_CONST_COLOR:
1995 cl_f(&vc4->uniforms,
1996 vc4->blend_color.color[uinfo->data[i]]);
1997 break;
1998
1999 case QUNIFORM_STENCIL:
2000 cl_u32(&vc4->uniforms,
2001 vc4->zsa->stencil_uniforms[uinfo->data[i]] |
2002 (uinfo->data[i] <= 1 ?
2003 (vc4->stencil_ref.ref_value[uinfo->data[i]] << 8) :
2004 0));
2005 break;
2006
2007 case QUNIFORM_ALPHA_REF:
2008 cl_f(&vc4->uniforms, vc4->zsa->base.alpha.ref_value);
2009 break;
2010 }
2011 #if 0
2012 uint32_t written_val = *(uint32_t *)(vc4->uniforms.next - 4);
2013 fprintf(stderr, "%p/%d: %d: 0x%08x (%f)\n",
2014 shader, shader_index, i, written_val, uif(written_val));
2015 #endif
2016 }
2017 }
2018
2019 static void
2020 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
2021 {
2022 struct vc4_context *vc4 = vc4_context(pctx);
2023 vc4->prog.bind_fs = hwcso;
2024 vc4->prog.dirty |= VC4_SHADER_DIRTY_FP;
2025 vc4->dirty |= VC4_DIRTY_PROG;
2026 }
2027
2028 static void
2029 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
2030 {
2031 struct vc4_context *vc4 = vc4_context(pctx);
2032 vc4->prog.bind_vs = hwcso;
2033 vc4->prog.dirty |= VC4_SHADER_DIRTY_VP;
2034 vc4->dirty |= VC4_DIRTY_PROG;
2035 }
2036
2037 void
2038 vc4_program_init(struct pipe_context *pctx)
2039 {
2040 struct vc4_context *vc4 = vc4_context(pctx);
2041
2042 pctx->create_vs_state = vc4_shader_state_create;
2043 pctx->delete_vs_state = vc4_shader_state_delete;
2044
2045 pctx->create_fs_state = vc4_shader_state_create;
2046 pctx->delete_fs_state = vc4_shader_state_delete;
2047
2048 pctx->bind_fs_state = vc4_fp_state_bind;
2049 pctx->bind_vs_state = vc4_vp_state_bind;
2050
2051 vc4->fs_cache = util_hash_table_create(fs_cache_hash, fs_cache_compare);
2052 vc4->vs_cache = util_hash_table_create(vs_cache_hash, vs_cache_compare);
2053 }