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vc4: Switch to using native integers.
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "pipe/p_state.h"
27 #include "util/u_format.h"
28 #include "util/u_hash_table.h"
29 #include "util/u_hash.h"
30 #include "util/u_memory.h"
31 #include "tgsi/tgsi_parse.h"
32 #include "tgsi/tgsi_dump.h"
33 #include "tgsi/tgsi_info.h"
34
35 #include "vc4_context.h"
36 #include "vc4_qpu.h"
37 #include "vc4_qir.h"
38 #ifdef USE_VC4_SIMULATOR
39 #include "simpenrose/simpenrose.h"
40 #endif
41
42 struct tgsi_to_qir {
43 struct tgsi_parse_context parser;
44 struct qcompile *c;
45 struct qreg *temps;
46 struct qreg *inputs;
47 struct qreg *outputs;
48 struct qreg *uniforms;
49 struct qreg *consts;
50 struct qreg line_x, point_x, point_y;
51 struct qreg discard;
52
53 uint32_t num_consts;
54
55 struct pipe_shader_state *shader_state;
56 struct vc4_key *key;
57 struct vc4_fs_key *fs_key;
58 struct vc4_vs_key *vs_key;
59
60 uint32_t *uniform_data;
61 enum quniform_contents *uniform_contents;
62 uint32_t num_uniforms;
63 uint32_t num_outputs;
64 uint32_t num_texture_samples;
65 };
66
67 struct vc4_key {
68 struct pipe_shader_state *shader_state;
69 enum pipe_format tex_format[VC4_MAX_TEXTURE_SAMPLERS];
70 };
71
72 struct vc4_fs_key {
73 struct vc4_key base;
74 enum pipe_format color_format;
75 bool depth_enabled;
76 bool is_points;
77 bool is_lines;
78
79 struct pipe_rt_blend_state blend;
80 };
81
82 struct vc4_vs_key {
83 struct vc4_key base;
84 enum pipe_format attr_formats[8];
85 };
86
87 static struct qreg
88 add_uniform(struct tgsi_to_qir *trans,
89 enum quniform_contents contents,
90 uint32_t data)
91 {
92 uint32_t uniform = trans->num_uniforms++;
93 struct qreg u = { QFILE_UNIF, uniform };
94
95 trans->uniform_contents[uniform] = contents;
96 trans->uniform_data[uniform] = data;
97
98 return u;
99 }
100
101 static struct qreg
102 get_temp_for_uniform(struct tgsi_to_qir *trans, enum quniform_contents contents,
103 uint32_t data)
104 {
105 struct qcompile *c = trans->c;
106
107 for (int i = 0; i < trans->num_uniforms; i++) {
108 if (trans->uniform_contents[i] == contents &&
109 trans->uniform_data[i] == data)
110 return trans->uniforms[i];
111 }
112
113 struct qreg u = add_uniform(trans, contents, data);
114 struct qreg t = qir_MOV(c, u);
115
116 trans->uniforms[u.index] = t;
117 return t;
118 }
119
120 static struct qreg
121 qir_uniform_ui(struct tgsi_to_qir *trans, uint32_t ui)
122 {
123 return get_temp_for_uniform(trans, QUNIFORM_CONSTANT, ui);
124 }
125
126 static struct qreg
127 qir_uniform_f(struct tgsi_to_qir *trans, float f)
128 {
129 return qir_uniform_ui(trans, fui(f));
130 }
131
132 static struct qreg
133 get_src(struct tgsi_to_qir *trans, unsigned tgsi_op,
134 struct tgsi_src_register *src, int i)
135 {
136 struct qcompile *c = trans->c;
137 struct qreg r = c->undef;
138
139 uint32_t s = i;
140 switch (i) {
141 case TGSI_SWIZZLE_X:
142 s = src->SwizzleX;
143 break;
144 case TGSI_SWIZZLE_Y:
145 s = src->SwizzleY;
146 break;
147 case TGSI_SWIZZLE_Z:
148 s = src->SwizzleZ;
149 break;
150 case TGSI_SWIZZLE_W:
151 s = src->SwizzleW;
152 break;
153 default:
154 abort();
155 }
156
157 assert(!src->Indirect);
158
159 switch (src->File) {
160 case TGSI_FILE_NULL:
161 return r;
162 case TGSI_FILE_TEMPORARY:
163 r = trans->temps[src->Index * 4 + s];
164 break;
165 case TGSI_FILE_IMMEDIATE:
166 r = trans->consts[src->Index * 4 + s];
167 break;
168 case TGSI_FILE_CONSTANT:
169 r = get_temp_for_uniform(trans, QUNIFORM_UNIFORM,
170 src->Index * 4 + s);
171 break;
172 case TGSI_FILE_INPUT:
173 r = trans->inputs[src->Index * 4 + s];
174 break;
175 case TGSI_FILE_SAMPLER:
176 case TGSI_FILE_SAMPLER_VIEW:
177 r = c->undef;
178 break;
179 default:
180 fprintf(stderr, "unknown src file %d\n", src->File);
181 abort();
182 }
183
184 if (src->Absolute)
185 r = qir_FMAXABS(c, r, r);
186
187 if (src->Negate) {
188 switch (tgsi_opcode_infer_src_type(tgsi_op)) {
189 case TGSI_TYPE_SIGNED:
190 case TGSI_TYPE_UNSIGNED:
191 r = qir_SUB(c, qir_uniform_ui(trans, 0), r);
192 break;
193 default:
194 r = qir_FSUB(c, qir_uniform_f(trans, 0.0), r);
195 break;
196 }
197 }
198
199 return r;
200 };
201
202
203 static void
204 update_dst(struct tgsi_to_qir *trans, struct tgsi_full_instruction *tgsi_inst,
205 int i, struct qreg val)
206 {
207 struct tgsi_dst_register *tgsi_dst = &tgsi_inst->Dst[0].Register;
208
209 assert(!tgsi_dst->Indirect);
210
211 switch (tgsi_dst->File) {
212 case TGSI_FILE_TEMPORARY:
213 trans->temps[tgsi_dst->Index * 4 + i] = val;
214 break;
215 case TGSI_FILE_OUTPUT:
216 trans->outputs[tgsi_dst->Index * 4 + i] = val;
217 trans->num_outputs = MAX2(trans->num_outputs,
218 tgsi_dst->Index * 4 + i + 1);
219 break;
220 default:
221 fprintf(stderr, "unknown dst file %d\n", tgsi_dst->File);
222 abort();
223 }
224 };
225
226 static struct qreg
227 get_swizzled_channel(struct tgsi_to_qir *trans,
228 struct qreg *srcs, int swiz)
229 {
230 switch (swiz) {
231 default:
232 case UTIL_FORMAT_SWIZZLE_NONE:
233 fprintf(stderr, "warning: unknown swizzle\n");
234 /* FALLTHROUGH */
235 case UTIL_FORMAT_SWIZZLE_0:
236 return qir_uniform_f(trans, 0.0);
237 case UTIL_FORMAT_SWIZZLE_1:
238 return qir_uniform_f(trans, 1.0);
239 case UTIL_FORMAT_SWIZZLE_X:
240 case UTIL_FORMAT_SWIZZLE_Y:
241 case UTIL_FORMAT_SWIZZLE_Z:
242 case UTIL_FORMAT_SWIZZLE_W:
243 return srcs[swiz];
244 }
245 }
246
247 static struct qreg
248 tgsi_to_qir_alu(struct tgsi_to_qir *trans,
249 struct tgsi_full_instruction *tgsi_inst,
250 enum qop op, struct qreg *src, int i)
251 {
252 struct qcompile *c = trans->c;
253 struct qreg dst = qir_get_temp(c);
254 qir_emit(c, qir_inst4(op, dst,
255 src[0 * 4 + i],
256 src[1 * 4 + i],
257 src[2 * 4 + i],
258 c->undef));
259 return dst;
260 }
261
262 static struct qreg
263 tgsi_to_qir_umul(struct tgsi_to_qir *trans,
264 struct tgsi_full_instruction *tgsi_inst,
265 enum qop op, struct qreg *src, int i)
266 {
267 struct qcompile *c = trans->c;
268
269 struct qreg src0_hi = qir_SHR(c, src[0 * 4 + i],
270 qir_uniform_ui(trans, 16));
271 struct qreg src0_lo = qir_AND(c, src[0 * 4 + i],
272 qir_uniform_ui(trans, 0xffff));
273 struct qreg src1_hi = qir_SHR(c, src[1 * 4 + i],
274 qir_uniform_ui(trans, 16));
275 struct qreg src1_lo = qir_AND(c, src[1 * 4 + i],
276 qir_uniform_ui(trans, 0xffff));
277
278 struct qreg hilo = qir_MUL24(c, src0_hi, src1_lo);
279 struct qreg lohi = qir_MUL24(c, src0_lo, src1_hi);
280 struct qreg lolo = qir_MUL24(c, src0_lo, src1_lo);
281
282 return qir_ADD(c, lolo, qir_SHL(c,
283 qir_ADD(c, hilo, lohi),
284 qir_uniform_ui(trans, 16)));
285 }
286
287 static struct qreg
288 tgsi_to_qir_idiv(struct tgsi_to_qir *trans,
289 struct tgsi_full_instruction *tgsi_inst,
290 enum qop op, struct qreg *src, int i)
291 {
292 struct qcompile *c = trans->c;
293 return qir_FTOI(c, qir_FMUL(c,
294 qir_ITOF(c, src[0 * 4 + i]),
295 qir_RCP(c, qir_ITOF(c, src[1 * 4 + i]))));
296 }
297
298 static struct qreg
299 tgsi_to_qir_ineg(struct tgsi_to_qir *trans,
300 struct tgsi_full_instruction *tgsi_inst,
301 enum qop op, struct qreg *src, int i)
302 {
303 struct qcompile *c = trans->c;
304 return qir_SUB(c, qir_uniform_ui(trans, 0), src[0 * 4 + i]);
305 }
306
307 static struct qreg
308 tgsi_to_qir_seq(struct tgsi_to_qir *trans,
309 struct tgsi_full_instruction *tgsi_inst,
310 enum qop op, struct qreg *src, int i)
311 {
312 struct qcompile *c = trans->c;
313 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
314 return qir_SEL_X_0_ZS(c, qir_uniform_f(trans, 1.0));
315 }
316
317 static struct qreg
318 tgsi_to_qir_sne(struct tgsi_to_qir *trans,
319 struct tgsi_full_instruction *tgsi_inst,
320 enum qop op, struct qreg *src, int i)
321 {
322 struct qcompile *c = trans->c;
323 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
324 return qir_SEL_X_0_ZC(c, qir_uniform_f(trans, 1.0));
325 }
326
327 static struct qreg
328 tgsi_to_qir_slt(struct tgsi_to_qir *trans,
329 struct tgsi_full_instruction *tgsi_inst,
330 enum qop op, struct qreg *src, int i)
331 {
332 struct qcompile *c = trans->c;
333 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
334 return qir_SEL_X_0_NS(c, qir_uniform_f(trans, 1.0));
335 }
336
337 static struct qreg
338 tgsi_to_qir_sge(struct tgsi_to_qir *trans,
339 struct tgsi_full_instruction *tgsi_inst,
340 enum qop op, struct qreg *src, int i)
341 {
342 struct qcompile *c = trans->c;
343 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
344 return qir_SEL_X_0_NC(c, qir_uniform_f(trans, 1.0));
345 }
346
347 static struct qreg
348 tgsi_to_qir_fseq(struct tgsi_to_qir *trans,
349 struct tgsi_full_instruction *tgsi_inst,
350 enum qop op, struct qreg *src, int i)
351 {
352 struct qcompile *c = trans->c;
353 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
354 return qir_SEL_X_0_ZS(c, qir_uniform_ui(trans, ~0));
355 }
356
357 static struct qreg
358 tgsi_to_qir_fsne(struct tgsi_to_qir *trans,
359 struct tgsi_full_instruction *tgsi_inst,
360 enum qop op, struct qreg *src, int i)
361 {
362 struct qcompile *c = trans->c;
363 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
364 return qir_SEL_X_0_ZC(c, qir_uniform_ui(trans, ~0));
365 }
366
367 static struct qreg
368 tgsi_to_qir_fslt(struct tgsi_to_qir *trans,
369 struct tgsi_full_instruction *tgsi_inst,
370 enum qop op, struct qreg *src, int i)
371 {
372 struct qcompile *c = trans->c;
373 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
374 return qir_SEL_X_0_NS(c, qir_uniform_ui(trans, ~0));
375 }
376
377 static struct qreg
378 tgsi_to_qir_fsge(struct tgsi_to_qir *trans,
379 struct tgsi_full_instruction *tgsi_inst,
380 enum qop op, struct qreg *src, int i)
381 {
382 struct qcompile *c = trans->c;
383 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
384 return qir_SEL_X_0_NC(c, qir_uniform_ui(trans, ~0));
385 }
386
387 static struct qreg
388 tgsi_to_qir_useq(struct tgsi_to_qir *trans,
389 struct tgsi_full_instruction *tgsi_inst,
390 enum qop op, struct qreg *src, int i)
391 {
392 struct qcompile *c = trans->c;
393 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
394 return qir_SEL_X_0_ZS(c, qir_uniform_ui(trans, ~0));
395 }
396
397 static struct qreg
398 tgsi_to_qir_usne(struct tgsi_to_qir *trans,
399 struct tgsi_full_instruction *tgsi_inst,
400 enum qop op, struct qreg *src, int i)
401 {
402 struct qcompile *c = trans->c;
403 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
404 return qir_SEL_X_0_ZC(c, qir_uniform_ui(trans, ~0));
405 }
406
407 static struct qreg
408 tgsi_to_qir_islt(struct tgsi_to_qir *trans,
409 struct tgsi_full_instruction *tgsi_inst,
410 enum qop op, struct qreg *src, int i)
411 {
412 struct qcompile *c = trans->c;
413 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
414 return qir_SEL_X_0_NS(c, qir_uniform_ui(trans, ~0));
415 }
416
417 static struct qreg
418 tgsi_to_qir_isge(struct tgsi_to_qir *trans,
419 struct tgsi_full_instruction *tgsi_inst,
420 enum qop op, struct qreg *src, int i)
421 {
422 struct qcompile *c = trans->c;
423 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
424 return qir_SEL_X_0_NC(c, qir_uniform_ui(trans, ~0));
425 }
426
427 static struct qreg
428 tgsi_to_qir_cmp(struct tgsi_to_qir *trans,
429 struct tgsi_full_instruction *tgsi_inst,
430 enum qop op, struct qreg *src, int i)
431 {
432 struct qcompile *c = trans->c;
433 qir_SF(c, src[0 * 4 + i]);
434 return qir_SEL_X_Y_NS(c,
435 src[1 * 4 + i],
436 src[2 * 4 + i]);
437 }
438
439 static struct qreg
440 tgsi_to_qir_mad(struct tgsi_to_qir *trans,
441 struct tgsi_full_instruction *tgsi_inst,
442 enum qop op, struct qreg *src, int i)
443 {
444 struct qcompile *c = trans->c;
445 return qir_FADD(c,
446 qir_FMUL(c,
447 src[0 * 4 + i],
448 src[1 * 4 + i]),
449 src[2 * 4 + i]);
450 }
451
452 static struct qreg
453 tgsi_to_qir_lit(struct tgsi_to_qir *trans,
454 struct tgsi_full_instruction *tgsi_inst,
455 enum qop op, struct qreg *src, int i)
456 {
457 struct qcompile *c = trans->c;
458 struct qreg x = src[0 * 4 + 0];
459 struct qreg y = src[0 * 4 + 1];
460 struct qreg w = src[0 * 4 + 3];
461
462 switch (i) {
463 case 0:
464 case 3:
465 return qir_uniform_f(trans, 1.0);
466 case 1:
467 return qir_FMAX(c, src[0 * 4 + 0], qir_uniform_f(trans, 0.0));
468 case 2: {
469 struct qreg zero = qir_uniform_f(trans, 0.0);
470
471 qir_SF(c, x);
472 /* XXX: Clamp w to -128..128 */
473 return qir_SEL_X_0_NC(c,
474 qir_EXP2(c, qir_FMUL(c,
475 w,
476 qir_LOG2(c,
477 qir_FMAX(c,
478 y,
479 zero)))));
480 }
481 default:
482 assert(!"not reached");
483 return c->undef;
484 }
485 }
486
487 static struct qreg
488 tgsi_to_qir_lrp(struct tgsi_to_qir *trans,
489 struct tgsi_full_instruction *tgsi_inst,
490 enum qop op, struct qreg *src, int i)
491 {
492 struct qcompile *c = trans->c;
493 struct qreg src0 = src[0 * 4 + i];
494 struct qreg src1 = src[1 * 4 + i];
495 struct qreg src2 = src[2 * 4 + i];
496
497 /* LRP is:
498 * src0 * src1 + (1 - src0) * src2.
499 * -> src0 * src1 + src2 - src0 * src2
500 * -> src2 + src0 * (src1 - src2)
501 */
502 return qir_FADD(c, src2, qir_FMUL(c, src0, qir_FSUB(c, src1, src2)));
503
504 }
505
506 static void
507 tgsi_to_qir_tex(struct tgsi_to_qir *trans,
508 struct tgsi_full_instruction *tgsi_inst,
509 enum qop op, struct qreg *src)
510 {
511 struct qcompile *c = trans->c;
512
513 assert(!tgsi_inst->Instruction.Saturate);
514
515 struct qreg s = src[0 * 4 + 0];
516 struct qreg t = src[0 * 4 + 1];
517 uint32_t unit = tgsi_inst->Src[1].Register.Index;
518
519 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
520 struct qreg proj = qir_RCP(c, src[0 * 4 + 3]);
521 s = qir_FMUL(c, s, proj);
522 t = qir_FMUL(c, t, proj);
523 }
524
525 /* There is no native support for GL texture rectangle coordinates, so
526 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
527 * 1]).
528 */
529 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_RECT) {
530 s = qir_FMUL(c, s,
531 get_temp_for_uniform(trans,
532 QUNIFORM_TEXRECT_SCALE_X,
533 unit));
534 t = qir_FMUL(c, t,
535 get_temp_for_uniform(trans,
536 QUNIFORM_TEXRECT_SCALE_Y,
537 unit));
538 }
539
540 qir_TEX_T(c, t, add_uniform(trans, QUNIFORM_TEXTURE_CONFIG_P0,
541 unit));
542
543 struct qreg sampler_p1 = add_uniform(trans, QUNIFORM_TEXTURE_CONFIG_P1,
544 unit);
545 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB) {
546 qir_TEX_B(c, src[0 * 4 + 3], sampler_p1);
547 qir_TEX_S(c, s, add_uniform(trans, QUNIFORM_CONSTANT, 0));
548 } else {
549 qir_TEX_S(c, s, sampler_p1);
550 }
551
552 trans->num_texture_samples++;
553 qir_emit(c, qir_inst(QOP_TEX_RESULT, c->undef, c->undef, c->undef));
554
555 struct qreg unpacked[4];
556 for (int i = 0; i < 4; i++)
557 unpacked[i] = qir_R4_UNPACK(c, i);
558
559 enum pipe_format format = trans->key->tex_format[unit];
560 const uint8_t *swiz = vc4_get_format_swizzle(format);
561 for (int i = 0; i < 4; i++) {
562 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
563 continue;
564
565 update_dst(trans, tgsi_inst, i,
566 get_swizzled_channel(trans, unpacked, swiz[i]));
567 }
568 }
569
570 static struct qreg
571 tgsi_to_qir_pow(struct tgsi_to_qir *trans,
572 struct tgsi_full_instruction *tgsi_inst,
573 enum qop op, struct qreg *src, int i)
574 {
575 struct qcompile *c = trans->c;
576
577 /* Note that this instruction replicates its result from the x channel
578 */
579 return qir_EXP2(c, qir_FMUL(c,
580 src[1 * 4 + 0],
581 qir_LOG2(c, src[0 * 4 + 0])));
582 }
583
584 static struct qreg
585 tgsi_to_qir_trunc(struct tgsi_to_qir *trans,
586 struct tgsi_full_instruction *tgsi_inst,
587 enum qop op, struct qreg *src, int i)
588 {
589 struct qcompile *c = trans->c;
590 return qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
591 }
592
593 /**
594 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
595 * to zero).
596 */
597 static struct qreg
598 tgsi_to_qir_frc(struct tgsi_to_qir *trans,
599 struct tgsi_full_instruction *tgsi_inst,
600 enum qop op, struct qreg *src, int i)
601 {
602 struct qcompile *c = trans->c;
603 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
604 struct qreg diff = qir_FSUB(c, src[0 * 4 + i], trunc);
605 qir_SF(c, diff);
606 return qir_SEL_X_Y_NS(c,
607 qir_FADD(c, diff, qir_uniform_f(trans, 1.0)),
608 diff);
609 }
610
611 /**
612 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
613 * zero).
614 */
615 static struct qreg
616 tgsi_to_qir_flr(struct tgsi_to_qir *trans,
617 struct tgsi_full_instruction *tgsi_inst,
618 enum qop op, struct qreg *src, int i)
619 {
620 struct qcompile *c = trans->c;
621 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
622
623 /* This will be < 0 if we truncated and the truncation was of a value
624 * that was < 0 in the first place.
625 */
626 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], trunc));
627
628 return qir_SEL_X_Y_NS(c,
629 qir_FSUB(c, trunc, qir_uniform_f(trans, 1.0)),
630 trunc);
631 }
632
633 static struct qreg
634 tgsi_to_qir_dp(struct tgsi_to_qir *trans,
635 struct tgsi_full_instruction *tgsi_inst,
636 int num, struct qreg *src, int i)
637 {
638 struct qcompile *c = trans->c;
639
640 struct qreg sum = qir_FMUL(c, src[0 * 4 + 0], src[1 * 4 + 0]);
641 for (int j = 1; j < num; j++) {
642 sum = qir_FADD(c, sum, qir_FMUL(c,
643 src[0 * 4 + j],
644 src[1 * 4 + j]));
645 }
646 return sum;
647 }
648
649 static struct qreg
650 tgsi_to_qir_dp2(struct tgsi_to_qir *trans,
651 struct tgsi_full_instruction *tgsi_inst,
652 enum qop op, struct qreg *src, int i)
653 {
654 return tgsi_to_qir_dp(trans, tgsi_inst, 2, src, i);
655 }
656
657 static struct qreg
658 tgsi_to_qir_dp3(struct tgsi_to_qir *trans,
659 struct tgsi_full_instruction *tgsi_inst,
660 enum qop op, struct qreg *src, int i)
661 {
662 return tgsi_to_qir_dp(trans, tgsi_inst, 3, src, i);
663 }
664
665 static struct qreg
666 tgsi_to_qir_dp4(struct tgsi_to_qir *trans,
667 struct tgsi_full_instruction *tgsi_inst,
668 enum qop op, struct qreg *src, int i)
669 {
670 return tgsi_to_qir_dp(trans, tgsi_inst, 4, src, i);
671 }
672
673 static struct qreg
674 tgsi_to_qir_abs(struct tgsi_to_qir *trans,
675 struct tgsi_full_instruction *tgsi_inst,
676 enum qop op, struct qreg *src, int i)
677 {
678 struct qcompile *c = trans->c;
679 struct qreg arg = src[0 * 4 + i];
680 return qir_FMAXABS(c, arg, arg);
681 }
682
683 /* Note that this instruction replicates its result from the x channel */
684 static struct qreg
685 tgsi_to_qir_sin(struct tgsi_to_qir *trans,
686 struct tgsi_full_instruction *tgsi_inst,
687 enum qop op, struct qreg *src, int i)
688 {
689 struct qcompile *c = trans->c;
690 float coeff[] = {
691 2.0 * M_PI,
692 -pow(2.0 * M_PI, 3) / (3 * 2 * 1),
693 pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
694 -pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
695 };
696
697 struct qreg scaled_x =
698 qir_FMUL(c,
699 src[0 * 4 + 0],
700 qir_uniform_f(trans, 1.0f / (M_PI * 2.0f)));
701
702
703 struct qreg x = tgsi_to_qir_frc(trans, NULL, 0, &scaled_x, 0);
704 struct qreg x2 = qir_FMUL(c, x, x);
705 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(trans, coeff[0]));
706 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
707 x = qir_FMUL(c, x, x2);
708 sum = qir_FADD(c,
709 sum,
710 qir_FMUL(c,
711 x,
712 qir_uniform_f(trans, coeff[i])));
713 }
714 return sum;
715 }
716
717 /* Note that this instruction replicates its result from the x channel */
718 static struct qreg
719 tgsi_to_qir_cos(struct tgsi_to_qir *trans,
720 struct tgsi_full_instruction *tgsi_inst,
721 enum qop op, struct qreg *src, int i)
722 {
723 struct qcompile *c = trans->c;
724 float coeff[] = {
725 1.0f,
726 -pow(2.0 * M_PI, 2) / (2 * 1),
727 pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
728 -pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
729 };
730
731 struct qreg scaled_x =
732 qir_FMUL(c, src[0 * 4 + 0],
733 qir_uniform_f(trans, 1.0f / (M_PI * 2.0f)));
734 struct qreg x_frac = tgsi_to_qir_frc(trans, NULL, 0, &scaled_x, 0);
735
736 struct qreg sum = qir_uniform_f(trans, coeff[0]);
737 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
738 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
739 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
740 if (i != 1)
741 x = qir_FMUL(c, x, x2);
742
743 struct qreg mul = qir_FMUL(c,
744 x,
745 qir_uniform_f(trans, coeff[i]));
746 if (i == 0)
747 sum = mul;
748 else
749 sum = qir_FADD(c, sum, mul);
750 }
751 return sum;
752 }
753
754 static void
755 emit_vertex_input(struct tgsi_to_qir *trans, int attr)
756 {
757 enum pipe_format format = trans->vs_key->attr_formats[attr];
758 struct qcompile *c = trans->c;
759 struct qreg vpm_reads[4];
760
761 /* Right now, we're setting the VPM offsets to be 16 bytes wide every
762 * time, so we always read 4 32-bit VPM entries.
763 */
764 for (int i = 0; i < 4; i++) {
765 vpm_reads[i] = qir_get_temp(c);
766 qir_emit(c, qir_inst(QOP_VPM_READ,
767 vpm_reads[i],
768 c->undef,
769 c->undef));
770 c->num_inputs++;
771 }
772
773 bool format_warned = false;
774 const struct util_format_description *desc =
775 util_format_description(format);
776
777 for (int i = 0; i < 4; i++) {
778 uint8_t swiz = desc->swizzle[i];
779
780 if (swiz <= UTIL_FORMAT_SWIZZLE_W &&
781 !format_warned &&
782 (desc->channel[swiz].type != UTIL_FORMAT_TYPE_FLOAT ||
783 desc->channel[swiz].size != 32)) {
784 fprintf(stderr,
785 "vtx element %d unsupported type: %s\n",
786 attr, util_format_name(format));
787 format_warned = true;
788 }
789
790 trans->inputs[attr * 4 + i] =
791 get_swizzled_channel(trans, vpm_reads, swiz);
792 }
793 }
794
795 static void
796 tgsi_to_qir_kill_if(struct tgsi_to_qir *trans, struct qreg *src, int i)
797 {
798 struct qcompile *c = trans->c;
799
800 if (trans->discard.file == QFILE_NULL)
801 trans->discard = qir_uniform_f(trans, 0.0);
802 qir_SF(c, src[0 * 4 + i]);
803 trans->discard = qir_SEL_X_Y_NS(c,
804 qir_uniform_f(trans, 1.0),
805 trans->discard);
806 }
807
808 static void
809 emit_fragcoord_input(struct tgsi_to_qir *trans, int attr)
810 {
811 struct qcompile *c = trans->c;
812
813 trans->inputs[attr * 4 + 0] = qir_FRAG_X(c);
814 trans->inputs[attr * 4 + 1] = qir_FRAG_Y(c);
815 trans->inputs[attr * 4 + 2] =
816 qir_FMUL(c,
817 qir_FRAG_Z(c),
818 qir_uniform_f(trans, 1.0 / 0xffffff));
819 trans->inputs[attr * 4 + 3] = qir_FRAG_RCP_W(c);
820 }
821
822 static struct qreg
823 emit_fragment_varying(struct tgsi_to_qir *trans, int index)
824 {
825 struct qcompile *c = trans->c;
826
827 struct qreg vary = {
828 QFILE_VARY,
829 index
830 };
831
832 /* XXX: multiply by W */
833 return qir_VARY_ADD_C(c, qir_MOV(c, vary));
834 }
835
836 static void
837 emit_fragment_input(struct tgsi_to_qir *trans, int attr)
838 {
839 struct qcompile *c = trans->c;
840
841 for (int i = 0; i < 4; i++) {
842 trans->inputs[attr * 4 + i] =
843 emit_fragment_varying(trans, attr * 4 + i);
844 c->num_inputs++;
845 }
846 }
847
848 static void
849 emit_tgsi_declaration(struct tgsi_to_qir *trans,
850 struct tgsi_full_declaration *decl)
851 {
852 struct qcompile *c = trans->c;
853
854 switch (decl->Declaration.File) {
855 case TGSI_FILE_INPUT:
856 for (int i = decl->Range.First;
857 i <= decl->Range.Last;
858 i++) {
859 if (c->stage == QSTAGE_FRAG) {
860 if (decl->Semantic.Name ==
861 TGSI_SEMANTIC_POSITION) {
862 emit_fragcoord_input(trans, i);
863 } else {
864 emit_fragment_input(trans, i);
865 }
866 } else {
867 emit_vertex_input(trans, i);
868 }
869 }
870 break;
871 }
872 }
873
874 static void
875 emit_tgsi_instruction(struct tgsi_to_qir *trans,
876 struct tgsi_full_instruction *tgsi_inst)
877 {
878 struct qcompile *c = trans->c;
879 struct {
880 enum qop op;
881 struct qreg (*func)(struct tgsi_to_qir *trans,
882 struct tgsi_full_instruction *tgsi_inst,
883 enum qop op,
884 struct qreg *src, int i);
885 } op_trans[] = {
886 [TGSI_OPCODE_MOV] = { QOP_MOV, tgsi_to_qir_alu },
887 [TGSI_OPCODE_ABS] = { 0, tgsi_to_qir_abs },
888 [TGSI_OPCODE_MUL] = { QOP_FMUL, tgsi_to_qir_alu },
889 [TGSI_OPCODE_ADD] = { QOP_FADD, tgsi_to_qir_alu },
890 [TGSI_OPCODE_SUB] = { QOP_FSUB, tgsi_to_qir_alu },
891 [TGSI_OPCODE_MIN] = { QOP_FMIN, tgsi_to_qir_alu },
892 [TGSI_OPCODE_MAX] = { QOP_FMAX, tgsi_to_qir_alu },
893 [TGSI_OPCODE_F2I] = { QOP_FTOI, tgsi_to_qir_alu },
894 [TGSI_OPCODE_I2F] = { QOP_ITOF, tgsi_to_qir_alu },
895 [TGSI_OPCODE_UADD] = { QOP_ADD, tgsi_to_qir_alu },
896 [TGSI_OPCODE_USHR] = { QOP_SHR, tgsi_to_qir_alu },
897 [TGSI_OPCODE_ISHR] = { QOP_ASR, tgsi_to_qir_alu },
898 [TGSI_OPCODE_SHL] = { QOP_SHL, tgsi_to_qir_alu },
899 [TGSI_OPCODE_IMIN] = { QOP_MIN, tgsi_to_qir_alu },
900 [TGSI_OPCODE_IMAX] = { QOP_MAX, tgsi_to_qir_alu },
901 [TGSI_OPCODE_AND] = { QOP_AND, tgsi_to_qir_alu },
902 [TGSI_OPCODE_OR] = { QOP_OR, tgsi_to_qir_alu },
903 [TGSI_OPCODE_XOR] = { QOP_XOR, tgsi_to_qir_alu },
904 [TGSI_OPCODE_NOT] = { QOP_NOT, tgsi_to_qir_alu },
905
906 [TGSI_OPCODE_UMUL] = { 0, tgsi_to_qir_umul },
907 [TGSI_OPCODE_IDIV] = { 0, tgsi_to_qir_idiv },
908 [TGSI_OPCODE_INEG] = { 0, tgsi_to_qir_ineg },
909
910 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_alu },
911 [TGSI_OPCODE_SEQ] = { 0, tgsi_to_qir_seq },
912 [TGSI_OPCODE_SNE] = { 0, tgsi_to_qir_sne },
913 [TGSI_OPCODE_SGE] = { 0, tgsi_to_qir_sge },
914 [TGSI_OPCODE_SLT] = { 0, tgsi_to_qir_slt },
915 [TGSI_OPCODE_FSEQ] = { 0, tgsi_to_qir_fseq },
916 [TGSI_OPCODE_FSNE] = { 0, tgsi_to_qir_fsne },
917 [TGSI_OPCODE_FSGE] = { 0, tgsi_to_qir_fsge },
918 [TGSI_OPCODE_FSLT] = { 0, tgsi_to_qir_fslt },
919 [TGSI_OPCODE_USEQ] = { 0, tgsi_to_qir_useq },
920 [TGSI_OPCODE_USNE] = { 0, tgsi_to_qir_usne },
921 [TGSI_OPCODE_ISGE] = { 0, tgsi_to_qir_isge },
922 [TGSI_OPCODE_ISLT] = { 0, tgsi_to_qir_islt },
923
924 [TGSI_OPCODE_CMP] = { 0, tgsi_to_qir_cmp },
925 [TGSI_OPCODE_MAD] = { 0, tgsi_to_qir_mad },
926 [TGSI_OPCODE_DP2] = { 0, tgsi_to_qir_dp2 },
927 [TGSI_OPCODE_DP3] = { 0, tgsi_to_qir_dp3 },
928 [TGSI_OPCODE_DP4] = { 0, tgsi_to_qir_dp4 },
929 [TGSI_OPCODE_RCP] = { QOP_RCP, tgsi_to_qir_alu },
930 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_alu },
931 [TGSI_OPCODE_EX2] = { QOP_EXP2, tgsi_to_qir_alu },
932 [TGSI_OPCODE_LG2] = { QOP_LOG2, tgsi_to_qir_alu },
933 [TGSI_OPCODE_LIT] = { 0, tgsi_to_qir_lit },
934 [TGSI_OPCODE_LRP] = { 0, tgsi_to_qir_lrp },
935 [TGSI_OPCODE_POW] = { 0, tgsi_to_qir_pow },
936 [TGSI_OPCODE_TRUNC] = { 0, tgsi_to_qir_trunc },
937 [TGSI_OPCODE_FRC] = { 0, tgsi_to_qir_frc },
938 [TGSI_OPCODE_FLR] = { 0, tgsi_to_qir_flr },
939 [TGSI_OPCODE_SIN] = { 0, tgsi_to_qir_sin },
940 [TGSI_OPCODE_COS] = { 0, tgsi_to_qir_cos },
941 };
942 static int asdf = 0;
943 uint32_t tgsi_op = tgsi_inst->Instruction.Opcode;
944
945 if (tgsi_op == TGSI_OPCODE_END)
946 return;
947
948 struct qreg src_regs[12];
949 for (int s = 0; s < 3; s++) {
950 for (int i = 0; i < 4; i++) {
951 src_regs[4 * s + i] =
952 get_src(trans, tgsi_inst->Instruction.Opcode,
953 &tgsi_inst->Src[s].Register, i);
954 }
955 }
956
957 switch (tgsi_op) {
958 case TGSI_OPCODE_TEX:
959 case TGSI_OPCODE_TXP:
960 case TGSI_OPCODE_TXB:
961 tgsi_to_qir_tex(trans, tgsi_inst,
962 op_trans[tgsi_op].op, src_regs);
963 return;
964 case TGSI_OPCODE_KILL:
965 trans->discard = qir_uniform_f(trans, 1.0);
966 return;
967 case TGSI_OPCODE_KILL_IF:
968 for (int i = 0; i < 4; i++)
969 tgsi_to_qir_kill_if(trans, src_regs, i);
970 return;
971 default:
972 break;
973 }
974
975 if (tgsi_op > ARRAY_SIZE(op_trans) || !(op_trans[tgsi_op].func)) {
976 fprintf(stderr, "unknown tgsi inst: ");
977 tgsi_dump_instruction(tgsi_inst, asdf++);
978 fprintf(stderr, "\n");
979 abort();
980 }
981
982 for (int i = 0; i < 4; i++) {
983 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
984 continue;
985
986 struct qreg result;
987
988 result = op_trans[tgsi_op].func(trans, tgsi_inst,
989 op_trans[tgsi_op].op,
990 src_regs, i);
991
992 if (tgsi_inst->Instruction.Saturate) {
993 float low = (tgsi_inst->Instruction.Saturate ==
994 TGSI_SAT_MINUS_PLUS_ONE ? -1.0 : 0.0);
995 result = qir_FMAX(c,
996 qir_FMIN(c,
997 result,
998 qir_uniform_f(trans, 1.0)),
999 qir_uniform_f(trans, low));
1000 }
1001
1002 update_dst(trans, tgsi_inst, i, result);
1003 }
1004 }
1005
1006 static void
1007 parse_tgsi_immediate(struct tgsi_to_qir *trans, struct tgsi_full_immediate *imm)
1008 {
1009 for (int i = 0; i < 4; i++) {
1010 unsigned n = trans->num_consts++;
1011 trans->consts[n] = qir_uniform_ui(trans, imm->u[i].Uint);
1012 }
1013 }
1014
1015 static struct qreg
1016 vc4_blend_channel(struct tgsi_to_qir *trans,
1017 struct qreg *dst,
1018 struct qreg *src,
1019 struct qreg val,
1020 unsigned factor,
1021 int channel)
1022 {
1023 struct qcompile *c = trans->c;
1024
1025 switch(factor) {
1026 case PIPE_BLENDFACTOR_ONE:
1027 return val;
1028 case PIPE_BLENDFACTOR_SRC_COLOR:
1029 return qir_FMUL(c, val, src[channel]);
1030 case PIPE_BLENDFACTOR_SRC_ALPHA:
1031 return qir_FMUL(c, val, src[3]);
1032 case PIPE_BLENDFACTOR_DST_ALPHA:
1033 return qir_FMUL(c, val, dst[3]);
1034 case PIPE_BLENDFACTOR_DST_COLOR:
1035 return qir_FMUL(c, val, dst[channel]);
1036 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
1037 return qir_FMIN(c, src[3], qir_FSUB(c,
1038 qir_uniform_f(trans, 1.0),
1039 dst[3]));
1040 case PIPE_BLENDFACTOR_CONST_COLOR:
1041 return qir_FMUL(c, val,
1042 get_temp_for_uniform(trans,
1043 QUNIFORM_BLEND_CONST_COLOR,
1044 channel));
1045 case PIPE_BLENDFACTOR_CONST_ALPHA:
1046 return qir_FMUL(c, val,
1047 get_temp_for_uniform(trans,
1048 QUNIFORM_BLEND_CONST_COLOR,
1049 3));
1050 case PIPE_BLENDFACTOR_ZERO:
1051 return qir_uniform_f(trans, 0.0);
1052 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
1053 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(trans, 1.0),
1054 src[channel]));
1055 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
1056 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(trans, 1.0),
1057 src[3]));
1058 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
1059 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(trans, 1.0),
1060 dst[3]));
1061 case PIPE_BLENDFACTOR_INV_DST_COLOR:
1062 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(trans, 1.0),
1063 dst[channel]));
1064 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
1065 return qir_FMUL(c, val,
1066 qir_FSUB(c, qir_uniform_f(trans, 1.0),
1067 get_temp_for_uniform(trans,
1068 QUNIFORM_BLEND_CONST_COLOR,
1069 channel)));
1070 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
1071 return qir_FMUL(c, val,
1072 qir_FSUB(c, qir_uniform_f(trans, 1.0),
1073 get_temp_for_uniform(trans,
1074 QUNIFORM_BLEND_CONST_COLOR,
1075 3)));
1076
1077 default:
1078 case PIPE_BLENDFACTOR_SRC1_COLOR:
1079 case PIPE_BLENDFACTOR_SRC1_ALPHA:
1080 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
1081 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
1082 /* Unsupported. */
1083 fprintf(stderr, "Unknown blend factor %d\n", factor);
1084 return val;
1085 }
1086 }
1087
1088 static struct qreg
1089 vc4_blend_func(struct tgsi_to_qir *trans,
1090 struct qreg src, struct qreg dst,
1091 unsigned func)
1092 {
1093 struct qcompile *c = trans->c;
1094
1095 switch (func) {
1096 case PIPE_BLEND_ADD:
1097 return qir_FADD(c, src, dst);
1098 case PIPE_BLEND_SUBTRACT:
1099 return qir_FSUB(c, src, dst);
1100 case PIPE_BLEND_REVERSE_SUBTRACT:
1101 return qir_FSUB(c, dst, src);
1102 case PIPE_BLEND_MIN:
1103 return qir_FMIN(c, src, dst);
1104 case PIPE_BLEND_MAX:
1105 return qir_FMAX(c, src, dst);
1106
1107 default:
1108 /* Unsupported. */
1109 fprintf(stderr, "Unknown blend func %d\n", func);
1110 return src;
1111
1112 }
1113 }
1114
1115 /**
1116 * Implements fixed function blending in shader code.
1117 *
1118 * VC4 doesn't have any hardware support for blending. Instead, you read the
1119 * current contents of the destination from the tile buffer after having
1120 * waited for the scoreboard (which is handled by vc4_qpu_emit.c), then do
1121 * math using your output color and that destination value, and update the
1122 * output color appropriately.
1123 */
1124 static void
1125 vc4_blend(struct tgsi_to_qir *trans, struct qreg *result,
1126 struct qreg *dst_color, struct qreg *src_color)
1127 {
1128 struct pipe_rt_blend_state *blend = &trans->fs_key->blend;
1129
1130 if (!blend->blend_enable) {
1131 for (int i = 0; i < 4; i++)
1132 result[i] = src_color[i];
1133 return;
1134 }
1135
1136 struct qreg src_blend[4], dst_blend[4];
1137 for (int i = 0; i < 3; i++) {
1138 src_blend[i] = vc4_blend_channel(trans,
1139 dst_color, src_color,
1140 src_color[i],
1141 blend->rgb_src_factor, i);
1142 dst_blend[i] = vc4_blend_channel(trans,
1143 dst_color, src_color,
1144 dst_color[i],
1145 blend->rgb_dst_factor, i);
1146 }
1147 src_blend[3] = vc4_blend_channel(trans,
1148 dst_color, src_color,
1149 src_color[3],
1150 blend->alpha_src_factor, 3);
1151 dst_blend[3] = vc4_blend_channel(trans,
1152 dst_color, src_color,
1153 dst_color[3],
1154 blend->alpha_dst_factor, 3);
1155
1156 for (int i = 0; i < 3; i++) {
1157 result[i] = vc4_blend_func(trans,
1158 src_blend[i], dst_blend[i],
1159 blend->rgb_func);
1160 }
1161 result[3] = vc4_blend_func(trans,
1162 src_blend[3], dst_blend[3],
1163 blend->alpha_func);
1164 }
1165
1166 static void
1167 emit_frag_end(struct tgsi_to_qir *trans)
1168 {
1169 struct qcompile *c = trans->c;
1170
1171 struct qreg src_color[4] = {
1172 trans->outputs[0], trans->outputs[1],
1173 trans->outputs[2], trans->outputs[3],
1174 };
1175
1176 enum pipe_format color_format = trans->fs_key->color_format;
1177 const uint8_t *format_swiz = vc4_get_format_swizzle(color_format);
1178 struct qreg tlb_read_color[4] = { c->undef, c->undef, c->undef, c->undef };
1179 struct qreg dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1180 if (trans->fs_key->blend.blend_enable ||
1181 trans->fs_key->blend.colormask != 0xf) {
1182 qir_emit(c, qir_inst(QOP_TLB_COLOR_READ, c->undef,
1183 c->undef, c->undef));
1184 for (int i = 0; i < 4; i++)
1185 tlb_read_color[i] = qir_R4_UNPACK(c, i);
1186 for (int i = 0; i < 4; i++)
1187 dst_color[i] = get_swizzled_channel(trans,
1188 tlb_read_color,
1189 format_swiz[i]);
1190 }
1191
1192 struct qreg blend_color[4];
1193 vc4_blend(trans, blend_color, dst_color, src_color);
1194
1195 /* If the bit isn't set in the color mask, then just return the
1196 * original dst color, instead.
1197 */
1198 for (int i = 0; i < 4; i++) {
1199 if (!(trans->fs_key->blend.colormask & (1 << i))) {
1200 blend_color[i] = dst_color[i];
1201 }
1202 }
1203
1204 /* Debug: Sometimes you're getting a black output and just want to see
1205 * if the FS is getting executed at all. Spam magenta into the color
1206 * output.
1207 */
1208 if (0) {
1209 blend_color[0] = qir_uniform_f(trans, 1.0);
1210 blend_color[1] = qir_uniform_f(trans, 0.0);
1211 blend_color[2] = qir_uniform_f(trans, 1.0);
1212 blend_color[3] = qir_uniform_f(trans, 0.5);
1213 }
1214
1215 struct qreg swizzled_outputs[4];
1216 for (int i = 0; i < 4; i++) {
1217 swizzled_outputs[i] = get_swizzled_channel(trans, blend_color,
1218 format_swiz[i]);
1219 }
1220
1221 if (trans->discard.file != QFILE_NULL)
1222 qir_TLB_DISCARD_SETUP(c, trans->discard);
1223
1224 if (trans->fs_key->depth_enabled) {
1225 qir_emit(c, qir_inst(QOP_TLB_PASSTHROUGH_Z_WRITE, c->undef,
1226 c->undef, c->undef));
1227 }
1228
1229 bool color_written = false;
1230 for (int i = 0; i < 4; i++) {
1231 if (swizzled_outputs[i].file != QFILE_NULL)
1232 color_written = true;
1233 }
1234
1235 struct qreg packed_color;
1236 if (color_written) {
1237 /* Fill in any undefined colors. The simulator will assertion
1238 * fail if we read something that wasn't written, and I don't
1239 * know what hardware does.
1240 */
1241 for (int i = 0; i < 4; i++) {
1242 if (swizzled_outputs[i].file == QFILE_NULL)
1243 swizzled_outputs[i] = qir_uniform_f(trans, 0.0);
1244 }
1245 packed_color = qir_get_temp(c);
1246 qir_emit(c, qir_inst4(QOP_PACK_COLORS, packed_color,
1247 swizzled_outputs[0],
1248 swizzled_outputs[1],
1249 swizzled_outputs[2],
1250 swizzled_outputs[3]));
1251 } else {
1252 packed_color = qir_uniform_ui(trans, 0);
1253 }
1254
1255 qir_emit(c, qir_inst(QOP_TLB_COLOR_WRITE, c->undef,
1256 packed_color, c->undef));
1257 }
1258
1259 static void
1260 emit_scaled_viewport_write(struct tgsi_to_qir *trans, struct qreg rcp_w)
1261 {
1262 struct qcompile *c = trans->c;
1263 struct qreg xyi[2];
1264
1265 for (int i = 0; i < 2; i++) {
1266 struct qreg scale =
1267 add_uniform(trans, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1268
1269 xyi[i] = qir_FTOI(c, qir_FMUL(c,
1270 qir_FMUL(c,
1271 trans->outputs[i],
1272 scale),
1273 rcp_w));
1274 }
1275
1276 qir_VPM_WRITE(c, qir_PACK_SCALED(c, xyi[0], xyi[1]));
1277 }
1278
1279 static void
1280 emit_zs_write(struct tgsi_to_qir *trans, struct qreg rcp_w)
1281 {
1282 struct qcompile *c = trans->c;
1283
1284 struct qreg zscale = add_uniform(trans, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1285 struct qreg zoffset = add_uniform(trans, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1286
1287 qir_VPM_WRITE(c, qir_FMUL(c, qir_FADD(c, qir_FMUL(c,
1288 trans->outputs[2],
1289 zscale),
1290 zoffset),
1291 rcp_w));
1292 }
1293
1294 static void
1295 emit_rcp_wc_write(struct tgsi_to_qir *trans, struct qreg rcp_w)
1296 {
1297 struct qcompile *c = trans->c;
1298
1299 qir_VPM_WRITE(c, rcp_w);
1300 }
1301
1302 static void
1303 emit_vert_end(struct tgsi_to_qir *trans)
1304 {
1305 struct qcompile *c = trans->c;
1306
1307 struct qreg rcp_w = qir_RCP(c, trans->outputs[3]);
1308
1309 emit_scaled_viewport_write(trans, rcp_w);
1310 emit_zs_write(trans, rcp_w);
1311 emit_rcp_wc_write(trans, rcp_w);
1312
1313 for (int i = 4; i < trans->num_outputs; i++) {
1314 qir_VPM_WRITE(c, trans->outputs[i]);
1315 }
1316 }
1317
1318 static void
1319 emit_coord_end(struct tgsi_to_qir *trans)
1320 {
1321 struct qcompile *c = trans->c;
1322
1323 struct qreg rcp_w = qir_RCP(c, trans->outputs[3]);
1324
1325 for (int i = 0; i < 4; i++)
1326 qir_VPM_WRITE(c, trans->outputs[i]);
1327
1328 emit_scaled_viewport_write(trans, rcp_w);
1329 emit_zs_write(trans, rcp_w);
1330 emit_rcp_wc_write(trans, rcp_w);
1331 }
1332
1333 static struct tgsi_to_qir *
1334 vc4_shader_tgsi_to_qir(struct vc4_compiled_shader *shader, enum qstage stage,
1335 struct vc4_key *key)
1336 {
1337 struct tgsi_to_qir *trans = CALLOC_STRUCT(tgsi_to_qir);
1338 struct qcompile *c;
1339 int ret;
1340
1341 c = qir_compile_init();
1342 c->stage = stage;
1343
1344 memset(trans, 0, sizeof(*trans));
1345 /* XXX sizing */
1346 trans->temps = calloc(sizeof(struct qreg), 1024);
1347 trans->inputs = calloc(sizeof(struct qreg), 8 * 4);
1348 trans->outputs = calloc(sizeof(struct qreg), 1024);
1349 trans->uniforms = calloc(sizeof(struct qreg), 1024);
1350 trans->consts = calloc(sizeof(struct qreg), 1024);
1351
1352 trans->uniform_data = calloc(sizeof(uint32_t), 1024);
1353 trans->uniform_contents = calloc(sizeof(enum quniform_contents), 1024);
1354
1355 trans->shader_state = key->shader_state;
1356 trans->c = c;
1357 ret = tgsi_parse_init(&trans->parser, trans->shader_state->tokens);
1358 assert(ret == TGSI_PARSE_OK);
1359
1360 if (vc4_debug & VC4_DEBUG_TGSI) {
1361 fprintf(stderr, "TGSI:\n");
1362 tgsi_dump(trans->shader_state->tokens, 0);
1363 }
1364
1365 trans->key = key;
1366 switch (stage) {
1367 case QSTAGE_FRAG:
1368 trans->fs_key = (struct vc4_fs_key *)key;
1369 if (trans->fs_key->is_points) {
1370 trans->point_x = emit_fragment_varying(trans, 0);
1371 trans->point_y = emit_fragment_varying(trans, 0);
1372 } else if (trans->fs_key->is_lines) {
1373 trans->line_x = emit_fragment_varying(trans, 0);
1374 }
1375 break;
1376 case QSTAGE_VERT:
1377 trans->vs_key = (struct vc4_vs_key *)key;
1378 break;
1379 case QSTAGE_COORD:
1380 trans->vs_key = (struct vc4_vs_key *)key;
1381 break;
1382 }
1383
1384 while (!tgsi_parse_end_of_tokens(&trans->parser)) {
1385 tgsi_parse_token(&trans->parser);
1386
1387 switch (trans->parser.FullToken.Token.Type) {
1388 case TGSI_TOKEN_TYPE_DECLARATION:
1389 emit_tgsi_declaration(trans,
1390 &trans->parser.FullToken.FullDeclaration);
1391 break;
1392
1393 case TGSI_TOKEN_TYPE_INSTRUCTION:
1394 emit_tgsi_instruction(trans,
1395 &trans->parser.FullToken.FullInstruction);
1396 break;
1397
1398 case TGSI_TOKEN_TYPE_IMMEDIATE:
1399 parse_tgsi_immediate(trans,
1400 &trans->parser.FullToken.FullImmediate);
1401 break;
1402 }
1403 }
1404
1405 switch (stage) {
1406 case QSTAGE_FRAG:
1407 emit_frag_end(trans);
1408 break;
1409 case QSTAGE_VERT:
1410 emit_vert_end(trans);
1411 break;
1412 case QSTAGE_COORD:
1413 emit_coord_end(trans);
1414 break;
1415 }
1416
1417 tgsi_parse_free(&trans->parser);
1418 free(trans->temps);
1419
1420 qir_optimize(c);
1421
1422 if (vc4_debug & VC4_DEBUG_QIR) {
1423 fprintf(stderr, "QIR:\n");
1424 qir_dump(c);
1425 }
1426 vc4_generate_code(c);
1427
1428 if (vc4_debug & VC4_DEBUG_SHADERDB) {
1429 fprintf(stderr, "SHADER-DB: %s: %d instructions\n",
1430 qir_get_stage_name(c->stage), c->qpu_inst_count);
1431 fprintf(stderr, "SHADER-DB: %s: %d uniforms\n",
1432 qir_get_stage_name(c->stage), trans->num_uniforms);
1433 }
1434
1435 return trans;
1436 }
1437
1438 static void *
1439 vc4_shader_state_create(struct pipe_context *pctx,
1440 const struct pipe_shader_state *cso)
1441 {
1442 struct pipe_shader_state *so = CALLOC_STRUCT(pipe_shader_state);
1443 if (!so)
1444 return NULL;
1445
1446 so->tokens = tgsi_dup_tokens(cso->tokens);
1447
1448 return so;
1449 }
1450
1451 static void
1452 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
1453 int shader_index,
1454 struct tgsi_to_qir *trans)
1455 {
1456 int count = trans->num_uniforms;
1457 struct vc4_shader_uniform_info *uinfo = &shader->uniforms[shader_index];
1458
1459 uinfo->count = count;
1460 uinfo->data = malloc(count * sizeof(*uinfo->data));
1461 memcpy(uinfo->data, trans->uniform_data,
1462 count * sizeof(*uinfo->data));
1463 uinfo->contents = malloc(count * sizeof(*uinfo->contents));
1464 memcpy(uinfo->contents, trans->uniform_contents,
1465 count * sizeof(*uinfo->contents));
1466 uinfo->num_texture_samples = trans->num_texture_samples;
1467 }
1468
1469 static void
1470 vc4_fs_compile(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1471 struct vc4_fs_key *key)
1472 {
1473 struct tgsi_to_qir *trans = vc4_shader_tgsi_to_qir(shader, QSTAGE_FRAG,
1474 &key->base);
1475 shader->num_inputs = trans->c->num_inputs;
1476 copy_uniform_state_to_shader(shader, 0, trans);
1477 shader->bo = vc4_bo_alloc_mem(vc4->screen, trans->c->qpu_insts,
1478 trans->c->qpu_inst_count * sizeof(uint64_t),
1479 "fs_code");
1480
1481 qir_compile_destroy(trans->c);
1482 free(trans);
1483 }
1484
1485 static void
1486 vc4_vs_compile(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1487 struct vc4_vs_key *key)
1488 {
1489 struct tgsi_to_qir *vs_trans = vc4_shader_tgsi_to_qir(shader,
1490 QSTAGE_VERT,
1491 &key->base);
1492 copy_uniform_state_to_shader(shader, 0, vs_trans);
1493
1494 struct tgsi_to_qir *cs_trans = vc4_shader_tgsi_to_qir(shader,
1495 QSTAGE_COORD,
1496 &key->base);
1497 copy_uniform_state_to_shader(shader, 1, cs_trans);
1498
1499 uint32_t vs_size = vs_trans->c->qpu_inst_count * sizeof(uint64_t);
1500 uint32_t cs_size = cs_trans->c->qpu_inst_count * sizeof(uint64_t);
1501 shader->coord_shader_offset = vs_size; /* XXX: alignment? */
1502 shader->bo = vc4_bo_alloc(vc4->screen,
1503 shader->coord_shader_offset + cs_size,
1504 "vs_code");
1505
1506 void *map = vc4_bo_map(shader->bo);
1507 memcpy(map, vs_trans->c->qpu_insts, vs_size);
1508 memcpy(map + shader->coord_shader_offset,
1509 cs_trans->c->qpu_insts, cs_size);
1510
1511 qir_compile_destroy(vs_trans->c);
1512 qir_compile_destroy(cs_trans->c);
1513 }
1514
1515 static void
1516 vc4_setup_shared_key(struct vc4_key *key, struct vc4_texture_stateobj *texstate)
1517 {
1518 for (int i = 0; i < texstate->num_textures; i++) {
1519 struct pipe_sampler_view *sampler = texstate->textures[i];
1520 if (sampler) {
1521 struct pipe_resource *prsc = sampler->texture;
1522 key->tex_format[i] = prsc->format;
1523 }
1524 }
1525 }
1526
1527 static void
1528 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
1529 {
1530 struct vc4_fs_key local_key;
1531 struct vc4_fs_key *key = &local_key;
1532
1533 memset(key, 0, sizeof(*key));
1534 vc4_setup_shared_key(&key->base, &vc4->fragtex);
1535 key->base.shader_state = vc4->prog.bind_fs;
1536 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
1537 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
1538 prim_mode <= PIPE_PRIM_LINE_STRIP);
1539 key->blend = vc4->blend->rt[0];
1540
1541 if (vc4->framebuffer.cbufs[0])
1542 key->color_format = vc4->framebuffer.cbufs[0]->format;
1543
1544 key->depth_enabled = vc4->zsa->base.depth.enabled;
1545
1546 vc4->prog.fs = util_hash_table_get(vc4->fs_cache, key);
1547 if (vc4->prog.fs)
1548 return;
1549
1550 key = malloc(sizeof(*key));
1551 memcpy(key, &local_key, sizeof(*key));
1552
1553 struct vc4_compiled_shader *shader = CALLOC_STRUCT(vc4_compiled_shader);
1554 vc4_fs_compile(vc4, shader, key);
1555 util_hash_table_set(vc4->fs_cache, key, shader);
1556
1557 vc4->prog.fs = shader;
1558 }
1559
1560 static void
1561 vc4_update_compiled_vs(struct vc4_context *vc4)
1562 {
1563 struct vc4_vs_key local_key;
1564 struct vc4_vs_key *key = &local_key;
1565
1566 memset(key, 0, sizeof(*key));
1567 vc4_setup_shared_key(&key->base, &vc4->verttex);
1568 key->base.shader_state = vc4->prog.bind_vs;
1569
1570 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
1571 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
1572
1573 vc4->prog.vs = util_hash_table_get(vc4->vs_cache, key);
1574 if (vc4->prog.vs)
1575 return;
1576
1577 key = malloc(sizeof(*key));
1578 memcpy(key, &local_key, sizeof(*key));
1579
1580 struct vc4_compiled_shader *shader = CALLOC_STRUCT(vc4_compiled_shader);
1581 vc4_vs_compile(vc4, shader, key);
1582 util_hash_table_set(vc4->vs_cache, key, shader);
1583
1584 vc4->prog.vs = shader;
1585 }
1586
1587 void
1588 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
1589 {
1590 vc4_update_compiled_fs(vc4, prim_mode);
1591 vc4_update_compiled_vs(vc4);
1592 }
1593
1594 static unsigned
1595 fs_cache_hash(void *key)
1596 {
1597 return util_hash_crc32(key, sizeof(struct vc4_fs_key));
1598 }
1599
1600 static unsigned
1601 vs_cache_hash(void *key)
1602 {
1603 return util_hash_crc32(key, sizeof(struct vc4_vs_key));
1604 }
1605
1606 static int
1607 fs_cache_compare(void *key1, void *key2)
1608 {
1609 return memcmp(key1, key2, sizeof(struct vc4_fs_key));
1610 }
1611
1612 static int
1613 vs_cache_compare(void *key1, void *key2)
1614 {
1615 return memcmp(key1, key2, sizeof(struct vc4_vs_key));
1616 }
1617
1618 struct delete_state {
1619 struct vc4_context *vc4;
1620 struct pipe_shader_state *shader_state;
1621 };
1622
1623 static enum pipe_error
1624 fs_delete_from_cache(void *in_key, void *in_value, void *data)
1625 {
1626 struct delete_state *del = data;
1627 struct vc4_fs_key *key = in_key;
1628 struct vc4_compiled_shader *shader = in_value;
1629
1630 if (key->base.shader_state == data) {
1631 util_hash_table_remove(del->vc4->fs_cache, key);
1632 vc4_bo_unreference(&shader->bo);
1633 free(shader);
1634 }
1635
1636 return 0;
1637 }
1638
1639 static enum pipe_error
1640 vs_delete_from_cache(void *in_key, void *in_value, void *data)
1641 {
1642 struct delete_state *del = data;
1643 struct vc4_vs_key *key = in_key;
1644 struct vc4_compiled_shader *shader = in_value;
1645
1646 if (key->base.shader_state == data) {
1647 util_hash_table_remove(del->vc4->vs_cache, key);
1648 vc4_bo_unreference(&shader->bo);
1649 free(shader);
1650 }
1651
1652 return 0;
1653 }
1654
1655 static void
1656 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
1657 {
1658 struct vc4_context *vc4 = vc4_context(pctx);
1659 struct pipe_shader_state *so = hwcso;
1660 struct delete_state del;
1661
1662 del.vc4 = vc4;
1663 del.shader_state = so;
1664 util_hash_table_foreach(vc4->fs_cache, fs_delete_from_cache, &del);
1665 util_hash_table_foreach(vc4->vs_cache, vs_delete_from_cache, &del);
1666
1667 free((void *)so->tokens);
1668 free(so);
1669 }
1670
1671 static uint32_t translate_wrap(uint32_t p_wrap)
1672 {
1673 switch (p_wrap) {
1674 case PIPE_TEX_WRAP_REPEAT:
1675 return 0;
1676 case PIPE_TEX_WRAP_CLAMP:
1677 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1678 return 1;
1679 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1680 return 2;
1681 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1682 return 3;
1683 default:
1684 fprintf(stderr, "Unknown wrap mode %d\n", p_wrap);
1685 assert(!"not reached");
1686 return 0;
1687 }
1688 }
1689
1690 static void
1691 write_texture_p0(struct vc4_context *vc4,
1692 struct vc4_texture_stateobj *texstate,
1693 uint32_t unit)
1694 {
1695 struct pipe_sampler_view *texture = texstate->textures[unit];
1696 struct vc4_resource *rsc = vc4_resource(texture->texture);
1697
1698 cl_reloc(vc4, &vc4->uniforms, rsc->bo,
1699 rsc->slices[0].offset | texture->u.tex.last_level |
1700 ((rsc->vc4_format & 7) << 4));
1701 }
1702
1703 static void
1704 write_texture_p1(struct vc4_context *vc4,
1705 struct vc4_texture_stateobj *texstate,
1706 uint32_t unit)
1707 {
1708 struct pipe_sampler_view *texture = texstate->textures[unit];
1709 struct vc4_resource *rsc = vc4_resource(texture->texture);
1710 struct pipe_sampler_state *sampler = texstate->samplers[unit];
1711 static const uint32_t mipfilter_map[] = {
1712 [PIPE_TEX_MIPFILTER_NEAREST] = 2,
1713 [PIPE_TEX_MIPFILTER_LINEAR] = 4,
1714 [PIPE_TEX_MIPFILTER_NONE] = 0
1715 };
1716 static const uint32_t imgfilter_map[] = {
1717 [PIPE_TEX_FILTER_NEAREST] = 1,
1718 [PIPE_TEX_FILTER_LINEAR] = 0,
1719 };
1720
1721 cl_u32(&vc4->uniforms,
1722 ((rsc->vc4_format >> 4) << 31) |
1723 (texture->texture->height0 << 20) |
1724 (texture->texture->width0 << 8) |
1725 (imgfilter_map[sampler->mag_img_filter] << 7) |
1726 ((imgfilter_map[sampler->min_img_filter] +
1727 mipfilter_map[sampler->min_mip_filter]) << 4) |
1728 (translate_wrap(sampler->wrap_t) << 2) |
1729 (translate_wrap(sampler->wrap_s) << 0));
1730 }
1731
1732 static uint32_t
1733 get_texrect_scale(struct vc4_texture_stateobj *texstate,
1734 enum quniform_contents contents,
1735 uint32_t data)
1736 {
1737 struct pipe_sampler_view *texture = texstate->textures[data];
1738 uint32_t dim;
1739
1740 if (contents == QUNIFORM_TEXRECT_SCALE_X)
1741 dim = texture->texture->width0;
1742 else
1743 dim = texture->texture->height0;
1744
1745 return fui(1.0f / dim);
1746 }
1747
1748 void
1749 vc4_write_uniforms(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1750 struct vc4_constbuf_stateobj *cb,
1751 struct vc4_texture_stateobj *texstate,
1752 int shader_index)
1753 {
1754 struct vc4_shader_uniform_info *uinfo = &shader->uniforms[shader_index];
1755 const uint32_t *gallium_uniforms = cb->cb[0].user_buffer;
1756
1757 cl_start_shader_reloc(&vc4->uniforms, uinfo->num_texture_samples);
1758
1759 for (int i = 0; i < uinfo->count; i++) {
1760
1761 switch (uinfo->contents[i]) {
1762 case QUNIFORM_CONSTANT:
1763 cl_u32(&vc4->uniforms, uinfo->data[i]);
1764 break;
1765 case QUNIFORM_UNIFORM:
1766 cl_u32(&vc4->uniforms,
1767 gallium_uniforms[uinfo->data[i]]);
1768 break;
1769 case QUNIFORM_VIEWPORT_X_SCALE:
1770 cl_f(&vc4->uniforms, vc4->viewport.scale[0] * 16.0f);
1771 break;
1772 case QUNIFORM_VIEWPORT_Y_SCALE:
1773 cl_f(&vc4->uniforms, vc4->viewport.scale[1] * 16.0f);
1774 break;
1775
1776 case QUNIFORM_VIEWPORT_Z_OFFSET:
1777 cl_f(&vc4->uniforms, vc4->viewport.translate[2]);
1778 break;
1779 case QUNIFORM_VIEWPORT_Z_SCALE:
1780 cl_f(&vc4->uniforms, vc4->viewport.scale[2]);
1781 break;
1782
1783 case QUNIFORM_TEXTURE_CONFIG_P0:
1784 write_texture_p0(vc4, texstate, uinfo->data[i]);
1785 break;
1786
1787 case QUNIFORM_TEXTURE_CONFIG_P1:
1788 write_texture_p1(vc4, texstate, uinfo->data[i]);
1789 break;
1790
1791 case QUNIFORM_TEXRECT_SCALE_X:
1792 case QUNIFORM_TEXRECT_SCALE_Y:
1793 cl_u32(&vc4->uniforms,
1794 get_texrect_scale(texstate,
1795 uinfo->contents[i],
1796 uinfo->data[i]));
1797 break;
1798
1799 case QUNIFORM_BLEND_CONST_COLOR:
1800 cl_f(&vc4->uniforms,
1801 vc4->blend_color.color[uinfo->data[i]]);
1802 break;
1803 }
1804 #if 0
1805 uint32_t written_val = *(uint32_t *)(vc4->uniforms.next - 4);
1806 fprintf(stderr, "%p/%d: %d: 0x%08x (%f)\n",
1807 shader, shader_index, i, written_val, uif(written_val));
1808 #endif
1809 }
1810 }
1811
1812 static void
1813 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
1814 {
1815 struct vc4_context *vc4 = vc4_context(pctx);
1816 vc4->prog.bind_fs = hwcso;
1817 vc4->prog.dirty |= VC4_SHADER_DIRTY_FP;
1818 vc4->dirty |= VC4_DIRTY_PROG;
1819 }
1820
1821 static void
1822 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
1823 {
1824 struct vc4_context *vc4 = vc4_context(pctx);
1825 vc4->prog.bind_vs = hwcso;
1826 vc4->prog.dirty |= VC4_SHADER_DIRTY_VP;
1827 vc4->dirty |= VC4_DIRTY_PROG;
1828 }
1829
1830 void
1831 vc4_program_init(struct pipe_context *pctx)
1832 {
1833 struct vc4_context *vc4 = vc4_context(pctx);
1834
1835 pctx->create_vs_state = vc4_shader_state_create;
1836 pctx->delete_vs_state = vc4_shader_state_delete;
1837
1838 pctx->create_fs_state = vc4_shader_state_create;
1839 pctx->delete_fs_state = vc4_shader_state_delete;
1840
1841 pctx->bind_fs_state = vc4_fp_state_bind;
1842 pctx->bind_vs_state = vc4_vp_state_bind;
1843
1844 vc4->fs_cache = util_hash_table_create(fs_cache_hash, fs_cache_compare);
1845 vc4->vs_cache = util_hash_table_create(vs_cache_hash, vs_cache_compare);
1846 }