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vc4: Move qir_uniform() and the constant-value versions to vc4_qir.c/h.
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "pipe/p_state.h"
27 #include "util/u_format.h"
28 #include "util/u_hash.h"
29 #include "util/u_memory.h"
30 #include "util/u_pack_color.h"
31 #include "util/format_srgb.h"
32 #include "util/ralloc.h"
33 #include "util/hash_table.h"
34 #include "tgsi/tgsi_dump.h"
35 #include "tgsi/tgsi_info.h"
36 #include "tgsi/tgsi_lowering.h"
37
38 #include "vc4_context.h"
39 #include "vc4_qpu.h"
40 #include "vc4_qir.h"
41 #ifdef USE_VC4_SIMULATOR
42 #include "simpenrose/simpenrose.h"
43 #endif
44
45 struct vc4_key {
46 struct vc4_uncompiled_shader *shader_state;
47 struct {
48 enum pipe_format format;
49 unsigned compare_mode:1;
50 unsigned compare_func:3;
51 unsigned wrap_s:3;
52 unsigned wrap_t:3;
53 uint8_t swizzle[4];
54 } tex[VC4_MAX_TEXTURE_SAMPLERS];
55 uint8_t ucp_enables;
56 };
57
58 struct vc4_fs_key {
59 struct vc4_key base;
60 enum pipe_format color_format;
61 bool depth_enabled;
62 bool stencil_enabled;
63 bool stencil_twoside;
64 bool stencil_full_writemasks;
65 bool is_points;
66 bool is_lines;
67 bool alpha_test;
68 bool point_coord_upper_left;
69 bool light_twoside;
70 uint8_t alpha_test_func;
71 uint8_t logicop_func;
72 uint32_t point_sprite_mask;
73
74 struct pipe_rt_blend_state blend;
75 };
76
77 struct vc4_vs_key {
78 struct vc4_key base;
79
80 /**
81 * This is a proxy for the array of FS input semantics, which is
82 * larger than we would want to put in the key.
83 */
84 uint64_t compiled_fs_id;
85
86 enum pipe_format attr_formats[8];
87 bool is_coord;
88 bool per_vertex_point_size;
89 };
90
91 static void
92 resize_qreg_array(struct vc4_compile *c,
93 struct qreg **regs,
94 uint32_t *size,
95 uint32_t decl_size)
96 {
97 if (*size >= decl_size)
98 return;
99
100 uint32_t old_size = *size;
101 *size = MAX2(*size * 2, decl_size);
102 *regs = reralloc(c, *regs, struct qreg, *size);
103 if (!*regs) {
104 fprintf(stderr, "Malloc failure\n");
105 abort();
106 }
107
108 for (uint32_t i = old_size; i < *size; i++)
109 (*regs)[i] = c->undef;
110 }
111
112 static struct qreg
113 indirect_uniform_load(struct vc4_compile *c,
114 struct tgsi_full_src_register *src, int swiz)
115 {
116 struct tgsi_ind_register *indirect = &src->Indirect;
117 struct vc4_compiler_ubo_range *range = &c->ubo_ranges[indirect->ArrayID];
118 if (!range->used) {
119 range->used = true;
120 range->dst_offset = c->next_ubo_dst_offset;
121 c->next_ubo_dst_offset += range->size;
122 c->num_ubo_ranges++;
123 };
124
125 assert(src->Register.Indirect);
126 assert(indirect->File == TGSI_FILE_ADDRESS);
127
128 struct qreg addr_val = c->addr[indirect->Swizzle];
129 struct qreg indirect_offset =
130 qir_ADD(c, addr_val, qir_uniform_ui(c,
131 range->dst_offset +
132 (src->Register.Index * 16)+
133 swiz * 4));
134 indirect_offset = qir_MIN(c, indirect_offset, qir_uniform_ui(c, (range->dst_offset +
135 range->size - 4)));
136
137 qir_TEX_DIRECT(c, indirect_offset, qir_uniform(c, QUNIFORM_UBO_ADDR, 0));
138 struct qreg r4 = qir_TEX_RESULT(c);
139 c->num_texture_samples++;
140 return qir_MOV(c, r4);
141 }
142
143 static struct qreg
144 get_src(struct vc4_compile *c, unsigned tgsi_op,
145 struct tgsi_full_src_register *full_src, int i)
146 {
147 struct tgsi_src_register *src = &full_src->Register;
148 struct qreg r = c->undef;
149
150 uint32_t s = i;
151 switch (i) {
152 case TGSI_SWIZZLE_X:
153 s = src->SwizzleX;
154 break;
155 case TGSI_SWIZZLE_Y:
156 s = src->SwizzleY;
157 break;
158 case TGSI_SWIZZLE_Z:
159 s = src->SwizzleZ;
160 break;
161 case TGSI_SWIZZLE_W:
162 s = src->SwizzleW;
163 break;
164 default:
165 abort();
166 }
167
168 switch (src->File) {
169 case TGSI_FILE_NULL:
170 return r;
171 case TGSI_FILE_TEMPORARY:
172 r = c->temps[src->Index * 4 + s];
173 break;
174 case TGSI_FILE_IMMEDIATE:
175 r = c->consts[src->Index * 4 + s];
176 break;
177 case TGSI_FILE_CONSTANT:
178 if (src->Indirect) {
179 r = indirect_uniform_load(c, full_src, s);
180 } else {
181 r = qir_uniform(c, QUNIFORM_UNIFORM, src->Index * 4 + s);
182 }
183 break;
184 case TGSI_FILE_INPUT:
185 r = c->inputs[src->Index * 4 + s];
186 break;
187 case TGSI_FILE_SAMPLER:
188 case TGSI_FILE_SAMPLER_VIEW:
189 r = c->undef;
190 break;
191 default:
192 fprintf(stderr, "unknown src file %d\n", src->File);
193 abort();
194 }
195
196 if (src->Absolute)
197 r = qir_FMAXABS(c, r, r);
198
199 if (src->Negate) {
200 switch (tgsi_opcode_infer_src_type(tgsi_op)) {
201 case TGSI_TYPE_SIGNED:
202 case TGSI_TYPE_UNSIGNED:
203 r = qir_SUB(c, qir_uniform_ui(c, 0), r);
204 break;
205 default:
206 r = qir_FSUB(c, qir_uniform_f(c, 0.0), r);
207 break;
208 }
209 }
210
211 return r;
212 };
213
214
215 static void
216 update_dst(struct vc4_compile *c, struct tgsi_full_instruction *tgsi_inst,
217 int i, struct qreg val)
218 {
219 struct tgsi_dst_register *tgsi_dst = &tgsi_inst->Dst[0].Register;
220
221 assert(!tgsi_dst->Indirect);
222
223 switch (tgsi_dst->File) {
224 case TGSI_FILE_TEMPORARY:
225 c->temps[tgsi_dst->Index * 4 + i] = val;
226 break;
227 case TGSI_FILE_OUTPUT:
228 c->outputs[tgsi_dst->Index * 4 + i] = val;
229 c->num_outputs = MAX2(c->num_outputs,
230 tgsi_dst->Index * 4 + i + 1);
231 break;
232 case TGSI_FILE_ADDRESS:
233 assert(tgsi_dst->Index == 0);
234 c->addr[i] = val;
235 break;
236 default:
237 fprintf(stderr, "unknown dst file %d\n", tgsi_dst->File);
238 abort();
239 }
240 };
241
242 static struct qreg
243 get_swizzled_channel(struct vc4_compile *c,
244 struct qreg *srcs, int swiz)
245 {
246 switch (swiz) {
247 default:
248 case UTIL_FORMAT_SWIZZLE_NONE:
249 fprintf(stderr, "warning: unknown swizzle\n");
250 /* FALLTHROUGH */
251 case UTIL_FORMAT_SWIZZLE_0:
252 return qir_uniform_f(c, 0.0);
253 case UTIL_FORMAT_SWIZZLE_1:
254 return qir_uniform_f(c, 1.0);
255 case UTIL_FORMAT_SWIZZLE_X:
256 case UTIL_FORMAT_SWIZZLE_Y:
257 case UTIL_FORMAT_SWIZZLE_Z:
258 case UTIL_FORMAT_SWIZZLE_W:
259 return srcs[swiz];
260 }
261 }
262
263 static inline struct qreg
264 qir_SAT(struct vc4_compile *c, struct qreg val)
265 {
266 return qir_FMAX(c,
267 qir_FMIN(c, val, qir_uniform_f(c, 1.0)),
268 qir_uniform_f(c, 0.0));
269 }
270
271 static struct qreg
272 tgsi_to_qir_alu(struct vc4_compile *c,
273 struct tgsi_full_instruction *tgsi_inst,
274 enum qop op, struct qreg *src, int i)
275 {
276 struct qreg dst = qir_get_temp(c);
277 qir_emit(c, qir_inst4(op, dst,
278 src[0 * 4 + i],
279 src[1 * 4 + i],
280 src[2 * 4 + i],
281 c->undef));
282 return dst;
283 }
284
285 static struct qreg
286 tgsi_to_qir_scalar(struct vc4_compile *c,
287 struct tgsi_full_instruction *tgsi_inst,
288 enum qop op, struct qreg *src, int i)
289 {
290 struct qreg dst = qir_get_temp(c);
291 qir_emit(c, qir_inst(op, dst,
292 src[0 * 4 + 0],
293 c->undef));
294 return dst;
295 }
296
297 static struct qreg
298 tgsi_to_qir_rcp(struct vc4_compile *c,
299 struct tgsi_full_instruction *tgsi_inst,
300 enum qop op, struct qreg *src, int i)
301 {
302 struct qreg x = src[0 * 4 + 0];
303 struct qreg r = qir_RCP(c, x);
304
305 /* Apply a Newton-Raphson step to improve the accuracy. */
306 r = qir_FMUL(c, r, qir_FSUB(c,
307 qir_uniform_f(c, 2.0),
308 qir_FMUL(c, x, r)));
309
310 return r;
311 }
312
313 static struct qreg
314 tgsi_to_qir_rsq(struct vc4_compile *c,
315 struct tgsi_full_instruction *tgsi_inst,
316 enum qop op, struct qreg *src, int i)
317 {
318 struct qreg x = src[0 * 4 + 0];
319 struct qreg r = qir_RSQ(c, x);
320
321 /* Apply a Newton-Raphson step to improve the accuracy. */
322 r = qir_FMUL(c, r, qir_FSUB(c,
323 qir_uniform_f(c, 1.5),
324 qir_FMUL(c,
325 qir_uniform_f(c, 0.5),
326 qir_FMUL(c, x,
327 qir_FMUL(c, r, r)))));
328
329 return r;
330 }
331
332 static struct qreg
333 qir_srgb_decode(struct vc4_compile *c, struct qreg srgb)
334 {
335 struct qreg low = qir_FMUL(c, srgb, qir_uniform_f(c, 1.0 / 12.92));
336 struct qreg high = qir_POW(c,
337 qir_FMUL(c,
338 qir_FADD(c,
339 srgb,
340 qir_uniform_f(c, 0.055)),
341 qir_uniform_f(c, 1.0 / 1.055)),
342 qir_uniform_f(c, 2.4));
343
344 qir_SF(c, qir_FSUB(c, srgb, qir_uniform_f(c, 0.04045)));
345 return qir_SEL_X_Y_NS(c, low, high);
346 }
347
348 static struct qreg
349 qir_srgb_encode(struct vc4_compile *c, struct qreg linear)
350 {
351 struct qreg low = qir_FMUL(c, linear, qir_uniform_f(c, 12.92));
352 struct qreg high = qir_FSUB(c,
353 qir_FMUL(c,
354 qir_uniform_f(c, 1.055),
355 qir_POW(c,
356 linear,
357 qir_uniform_f(c, 0.41666))),
358 qir_uniform_f(c, 0.055));
359
360 qir_SF(c, qir_FSUB(c, linear, qir_uniform_f(c, 0.0031308)));
361 return qir_SEL_X_Y_NS(c, low, high);
362 }
363
364 static struct qreg
365 tgsi_to_qir_umul(struct vc4_compile *c,
366 struct tgsi_full_instruction *tgsi_inst,
367 enum qop op, struct qreg *src, int i)
368 {
369 struct qreg src0_hi = qir_SHR(c, src[0 * 4 + i],
370 qir_uniform_ui(c, 16));
371 struct qreg src0_lo = qir_AND(c, src[0 * 4 + i],
372 qir_uniform_ui(c, 0xffff));
373 struct qreg src1_hi = qir_SHR(c, src[1 * 4 + i],
374 qir_uniform_ui(c, 16));
375 struct qreg src1_lo = qir_AND(c, src[1 * 4 + i],
376 qir_uniform_ui(c, 0xffff));
377
378 struct qreg hilo = qir_MUL24(c, src0_hi, src1_lo);
379 struct qreg lohi = qir_MUL24(c, src0_lo, src1_hi);
380 struct qreg lolo = qir_MUL24(c, src0_lo, src1_lo);
381
382 return qir_ADD(c, lolo, qir_SHL(c,
383 qir_ADD(c, hilo, lohi),
384 qir_uniform_ui(c, 16)));
385 }
386
387 static struct qreg
388 tgsi_to_qir_umad(struct vc4_compile *c,
389 struct tgsi_full_instruction *tgsi_inst,
390 enum qop op, struct qreg *src, int i)
391 {
392 return qir_ADD(c, tgsi_to_qir_umul(c, NULL, 0, src, i), src[2 * 4 + i]);
393 }
394
395 static struct qreg
396 tgsi_to_qir_idiv(struct vc4_compile *c,
397 struct tgsi_full_instruction *tgsi_inst,
398 enum qop op, struct qreg *src, int i)
399 {
400 return qir_FTOI(c, qir_FMUL(c,
401 qir_ITOF(c, src[0 * 4 + i]),
402 qir_RCP(c, qir_ITOF(c, src[1 * 4 + i]))));
403 }
404
405 static struct qreg
406 tgsi_to_qir_ineg(struct vc4_compile *c,
407 struct tgsi_full_instruction *tgsi_inst,
408 enum qop op, struct qreg *src, int i)
409 {
410 return qir_SUB(c, qir_uniform_ui(c, 0), src[0 * 4 + i]);
411 }
412
413 static struct qreg
414 tgsi_to_qir_seq(struct vc4_compile *c,
415 struct tgsi_full_instruction *tgsi_inst,
416 enum qop op, struct qreg *src, int i)
417 {
418 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
419 return qir_SEL_X_0_ZS(c, qir_uniform_f(c, 1.0));
420 }
421
422 static struct qreg
423 tgsi_to_qir_sne(struct vc4_compile *c,
424 struct tgsi_full_instruction *tgsi_inst,
425 enum qop op, struct qreg *src, int i)
426 {
427 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
428 return qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0));
429 }
430
431 static struct qreg
432 tgsi_to_qir_slt(struct vc4_compile *c,
433 struct tgsi_full_instruction *tgsi_inst,
434 enum qop op, struct qreg *src, int i)
435 {
436 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
437 return qir_SEL_X_0_NS(c, qir_uniform_f(c, 1.0));
438 }
439
440 static struct qreg
441 tgsi_to_qir_sge(struct vc4_compile *c,
442 struct tgsi_full_instruction *tgsi_inst,
443 enum qop op, struct qreg *src, int i)
444 {
445 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
446 return qir_SEL_X_0_NC(c, qir_uniform_f(c, 1.0));
447 }
448
449 static struct qreg
450 tgsi_to_qir_fseq(struct vc4_compile *c,
451 struct tgsi_full_instruction *tgsi_inst,
452 enum qop op, struct qreg *src, int i)
453 {
454 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
455 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
456 }
457
458 static struct qreg
459 tgsi_to_qir_fsne(struct vc4_compile *c,
460 struct tgsi_full_instruction *tgsi_inst,
461 enum qop op, struct qreg *src, int i)
462 {
463 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
464 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
465 }
466
467 static struct qreg
468 tgsi_to_qir_fslt(struct vc4_compile *c,
469 struct tgsi_full_instruction *tgsi_inst,
470 enum qop op, struct qreg *src, int i)
471 {
472 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
473 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
474 }
475
476 static struct qreg
477 tgsi_to_qir_fsge(struct vc4_compile *c,
478 struct tgsi_full_instruction *tgsi_inst,
479 enum qop op, struct qreg *src, int i)
480 {
481 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
482 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
483 }
484
485 static struct qreg
486 tgsi_to_qir_useq(struct vc4_compile *c,
487 struct tgsi_full_instruction *tgsi_inst,
488 enum qop op, struct qreg *src, int i)
489 {
490 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
491 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
492 }
493
494 static struct qreg
495 tgsi_to_qir_usne(struct vc4_compile *c,
496 struct tgsi_full_instruction *tgsi_inst,
497 enum qop op, struct qreg *src, int i)
498 {
499 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
500 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
501 }
502
503 static struct qreg
504 tgsi_to_qir_islt(struct vc4_compile *c,
505 struct tgsi_full_instruction *tgsi_inst,
506 enum qop op, struct qreg *src, int i)
507 {
508 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
509 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
510 }
511
512 static struct qreg
513 tgsi_to_qir_isge(struct vc4_compile *c,
514 struct tgsi_full_instruction *tgsi_inst,
515 enum qop op, struct qreg *src, int i)
516 {
517 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
518 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
519 }
520
521 static struct qreg
522 tgsi_to_qir_cmp(struct vc4_compile *c,
523 struct tgsi_full_instruction *tgsi_inst,
524 enum qop op, struct qreg *src, int i)
525 {
526 qir_SF(c, src[0 * 4 + i]);
527 return qir_SEL_X_Y_NS(c,
528 src[1 * 4 + i],
529 src[2 * 4 + i]);
530 }
531
532 static struct qreg
533 tgsi_to_qir_ucmp(struct vc4_compile *c,
534 struct tgsi_full_instruction *tgsi_inst,
535 enum qop op, struct qreg *src, int i)
536 {
537 qir_SF(c, src[0 * 4 + i]);
538 return qir_SEL_X_Y_ZC(c,
539 src[1 * 4 + i],
540 src[2 * 4 + i]);
541 }
542
543 static struct qreg
544 tgsi_to_qir_mad(struct vc4_compile *c,
545 struct tgsi_full_instruction *tgsi_inst,
546 enum qop op, struct qreg *src, int i)
547 {
548 return qir_FADD(c,
549 qir_FMUL(c,
550 src[0 * 4 + i],
551 src[1 * 4 + i]),
552 src[2 * 4 + i]);
553 }
554
555 static struct qreg
556 tgsi_to_qir_lrp(struct vc4_compile *c,
557 struct tgsi_full_instruction *tgsi_inst,
558 enum qop op, struct qreg *src, int i)
559 {
560 struct qreg src0 = src[0 * 4 + i];
561 struct qreg src1 = src[1 * 4 + i];
562 struct qreg src2 = src[2 * 4 + i];
563
564 /* LRP is:
565 * src0 * src1 + (1 - src0) * src2.
566 * -> src0 * src1 + src2 - src0 * src2
567 * -> src2 + src0 * (src1 - src2)
568 */
569 return qir_FADD(c, src2, qir_FMUL(c, src0, qir_FSUB(c, src1, src2)));
570
571 }
572
573 static void
574 tgsi_to_qir_tex(struct vc4_compile *c,
575 struct tgsi_full_instruction *tgsi_inst,
576 enum qop op, struct qreg *src)
577 {
578 assert(!tgsi_inst->Instruction.Saturate);
579
580 struct qreg s = src[0 * 4 + 0];
581 struct qreg t = src[0 * 4 + 1];
582 struct qreg r = src[0 * 4 + 2];
583 uint32_t unit = tgsi_inst->Src[1].Register.Index;
584 bool is_txl = tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL;
585
586 struct qreg proj = c->undef;
587 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
588 proj = qir_RCP(c, src[0 * 4 + 3]);
589 s = qir_FMUL(c, s, proj);
590 t = qir_FMUL(c, t, proj);
591 }
592
593 struct qreg texture_u[] = {
594 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit),
595 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
596 qir_uniform(c, QUNIFORM_CONSTANT, 0),
597 qir_uniform(c, QUNIFORM_CONSTANT, 0),
598 };
599 uint32_t next_texture_u = 0;
600
601 /* There is no native support for GL texture rectangle coordinates, so
602 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
603 * 1]).
604 */
605 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_RECT ||
606 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT) {
607 s = qir_FMUL(c, s,
608 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_X, unit));
609 t = qir_FMUL(c, t,
610 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_Y, unit));
611 }
612
613 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
614 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
615 is_txl) {
616 texture_u[2] = qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P2,
617 unit | (is_txl << 16));
618 }
619
620 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
621 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE) {
622 struct qreg ma = qir_FMAXABS(c, qir_FMAXABS(c, s, t), r);
623 struct qreg rcp_ma = qir_RCP(c, ma);
624 s = qir_FMUL(c, s, rcp_ma);
625 t = qir_FMUL(c, t, rcp_ma);
626 r = qir_FMUL(c, r, rcp_ma);
627
628 qir_TEX_R(c, r, texture_u[next_texture_u++]);
629 } else if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
630 c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP ||
631 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
632 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
633 qir_TEX_R(c, qir_uniform(c, QUNIFORM_TEXTURE_BORDER_COLOR, unit),
634 texture_u[next_texture_u++]);
635 }
636
637 if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP) {
638 s = qir_SAT(c, s);
639 }
640
641 if (c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
642 t = qir_SAT(c, t);
643 }
644
645 qir_TEX_T(c, t, texture_u[next_texture_u++]);
646
647 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
648 tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL)
649 qir_TEX_B(c, src[0 * 4 + 3], texture_u[next_texture_u++]);
650
651 qir_TEX_S(c, s, texture_u[next_texture_u++]);
652
653 c->num_texture_samples++;
654 struct qreg r4 = qir_TEX_RESULT(c);
655
656 enum pipe_format format = c->key->tex[unit].format;
657
658 struct qreg unpacked[4];
659 if (util_format_is_depth_or_stencil(format)) {
660 struct qreg depthf = qir_ITOF(c, qir_SHR(c, r4,
661 qir_uniform_ui(c, 8)));
662 struct qreg normalized = qir_FMUL(c, depthf,
663 qir_uniform_f(c, 1.0f/0xffffff));
664
665 struct qreg depth_output;
666
667 struct qreg one = qir_uniform_f(c, 1.0f);
668 if (c->key->tex[unit].compare_mode) {
669 struct qreg compare = src[0 * 4 + 2];
670
671 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP)
672 compare = qir_FMUL(c, compare, proj);
673
674 switch (c->key->tex[unit].compare_func) {
675 case PIPE_FUNC_NEVER:
676 depth_output = qir_uniform_f(c, 0.0f);
677 break;
678 case PIPE_FUNC_ALWAYS:
679 depth_output = one;
680 break;
681 case PIPE_FUNC_EQUAL:
682 qir_SF(c, qir_FSUB(c, compare, normalized));
683 depth_output = qir_SEL_X_0_ZS(c, one);
684 break;
685 case PIPE_FUNC_NOTEQUAL:
686 qir_SF(c, qir_FSUB(c, compare, normalized));
687 depth_output = qir_SEL_X_0_ZC(c, one);
688 break;
689 case PIPE_FUNC_GREATER:
690 qir_SF(c, qir_FSUB(c, compare, normalized));
691 depth_output = qir_SEL_X_0_NC(c, one);
692 break;
693 case PIPE_FUNC_GEQUAL:
694 qir_SF(c, qir_FSUB(c, normalized, compare));
695 depth_output = qir_SEL_X_0_NS(c, one);
696 break;
697 case PIPE_FUNC_LESS:
698 qir_SF(c, qir_FSUB(c, compare, normalized));
699 depth_output = qir_SEL_X_0_NS(c, one);
700 break;
701 case PIPE_FUNC_LEQUAL:
702 qir_SF(c, qir_FSUB(c, normalized, compare));
703 depth_output = qir_SEL_X_0_NC(c, one);
704 break;
705 }
706 } else {
707 depth_output = normalized;
708 }
709
710 for (int i = 0; i < 4; i++)
711 unpacked[i] = depth_output;
712 } else {
713 for (int i = 0; i < 4; i++)
714 unpacked[i] = qir_R4_UNPACK(c, r4, i);
715 }
716
717 const uint8_t *format_swiz = vc4_get_format_swizzle(format);
718 struct qreg texture_output[4];
719 for (int i = 0; i < 4; i++) {
720 texture_output[i] = get_swizzled_channel(c, unpacked,
721 format_swiz[i]);
722 }
723
724 if (util_format_is_srgb(format)) {
725 for (int i = 0; i < 3; i++)
726 texture_output[i] = qir_srgb_decode(c,
727 texture_output[i]);
728 }
729
730 for (int i = 0; i < 4; i++) {
731 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
732 continue;
733
734 update_dst(c, tgsi_inst, i,
735 get_swizzled_channel(c, texture_output,
736 c->key->tex[unit].swizzle[i]));
737 }
738 }
739
740 static struct qreg
741 tgsi_to_qir_trunc(struct vc4_compile *c,
742 struct tgsi_full_instruction *tgsi_inst,
743 enum qop op, struct qreg *src, int i)
744 {
745 return qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
746 }
747
748 /**
749 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
750 * to zero).
751 */
752 static struct qreg
753 tgsi_to_qir_frc(struct vc4_compile *c,
754 struct tgsi_full_instruction *tgsi_inst,
755 enum qop op, struct qreg *src, int i)
756 {
757 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
758 struct qreg diff = qir_FSUB(c, src[0 * 4 + i], trunc);
759 qir_SF(c, diff);
760 return qir_SEL_X_Y_NS(c,
761 qir_FADD(c, diff, qir_uniform_f(c, 1.0)),
762 diff);
763 }
764
765 /**
766 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
767 * zero).
768 */
769 static struct qreg
770 tgsi_to_qir_flr(struct vc4_compile *c,
771 struct tgsi_full_instruction *tgsi_inst,
772 enum qop op, struct qreg *src, int i)
773 {
774 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
775
776 /* This will be < 0 if we truncated and the truncation was of a value
777 * that was < 0 in the first place.
778 */
779 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], trunc));
780
781 return qir_SEL_X_Y_NS(c,
782 qir_FSUB(c, trunc, qir_uniform_f(c, 1.0)),
783 trunc);
784 }
785
786 /**
787 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
788 * zero).
789 */
790 static struct qreg
791 tgsi_to_qir_ceil(struct vc4_compile *c,
792 struct tgsi_full_instruction *tgsi_inst,
793 enum qop op, struct qreg *src, int i)
794 {
795 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
796
797 /* This will be < 0 if we truncated and the truncation was of a value
798 * that was > 0 in the first place.
799 */
800 qir_SF(c, qir_FSUB(c, trunc, src[0 * 4 + i]));
801
802 return qir_SEL_X_Y_NS(c,
803 qir_FADD(c, trunc, qir_uniform_f(c, 1.0)),
804 trunc);
805 }
806
807 static struct qreg
808 tgsi_to_qir_abs(struct vc4_compile *c,
809 struct tgsi_full_instruction *tgsi_inst,
810 enum qop op, struct qreg *src, int i)
811 {
812 struct qreg arg = src[0 * 4 + i];
813 return qir_FMAXABS(c, arg, arg);
814 }
815
816 /* Note that this instruction replicates its result from the x channel */
817 static struct qreg
818 tgsi_to_qir_sin(struct vc4_compile *c,
819 struct tgsi_full_instruction *tgsi_inst,
820 enum qop op, struct qreg *src, int i)
821 {
822 float coeff[] = {
823 -2.0 * M_PI,
824 pow(2.0 * M_PI, 3) / (3 * 2 * 1),
825 -pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
826 pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
827 -pow(2.0 * M_PI, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
828 };
829
830 struct qreg scaled_x =
831 qir_FMUL(c,
832 src[0 * 4 + 0],
833 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
834
835 struct qreg x = qir_FADD(c,
836 tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0),
837 qir_uniform_f(c, -0.5));
838 struct qreg x2 = qir_FMUL(c, x, x);
839 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
840 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
841 x = qir_FMUL(c, x, x2);
842 sum = qir_FADD(c,
843 sum,
844 qir_FMUL(c,
845 x,
846 qir_uniform_f(c, coeff[i])));
847 }
848 return sum;
849 }
850
851 /* Note that this instruction replicates its result from the x channel */
852 static struct qreg
853 tgsi_to_qir_cos(struct vc4_compile *c,
854 struct tgsi_full_instruction *tgsi_inst,
855 enum qop op, struct qreg *src, int i)
856 {
857 float coeff[] = {
858 -1.0f,
859 pow(2.0 * M_PI, 2) / (2 * 1),
860 -pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
861 pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
862 -pow(2.0 * M_PI, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
863 pow(2.0 * M_PI, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
864 };
865
866 struct qreg scaled_x =
867 qir_FMUL(c, src[0 * 4 + 0],
868 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
869 struct qreg x_frac = qir_FADD(c,
870 tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0),
871 qir_uniform_f(c, -0.5));
872
873 struct qreg sum = qir_uniform_f(c, coeff[0]);
874 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
875 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
876 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
877 if (i != 1)
878 x = qir_FMUL(c, x, x2);
879
880 struct qreg mul = qir_FMUL(c,
881 x,
882 qir_uniform_f(c, coeff[i]));
883 if (i == 0)
884 sum = mul;
885 else
886 sum = qir_FADD(c, sum, mul);
887 }
888 return sum;
889 }
890
891 static struct qreg
892 tgsi_to_qir_clamp(struct vc4_compile *c,
893 struct tgsi_full_instruction *tgsi_inst,
894 enum qop op, struct qreg *src, int i)
895 {
896 return qir_FMAX(c, qir_FMIN(c,
897 src[0 * 4 + i],
898 src[2 * 4 + i]),
899 src[1 * 4 + i]);
900 }
901
902 static struct qreg
903 tgsi_to_qir_ssg(struct vc4_compile *c,
904 struct tgsi_full_instruction *tgsi_inst,
905 enum qop op, struct qreg *src, int i)
906 {
907 qir_SF(c, src[0 * 4 + i]);
908 return qir_SEL_X_Y_NC(c,
909 qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0)),
910 qir_uniform_f(c, -1.0));
911 }
912
913 /* Compare to tgsi_to_qir_flr() for the floor logic. */
914 static struct qreg
915 tgsi_to_qir_arl(struct vc4_compile *c,
916 struct tgsi_full_instruction *tgsi_inst,
917 enum qop op, struct qreg *src, int i)
918 {
919 struct qreg trunc = qir_FTOI(c, src[0 * 4 + i]);
920 struct qreg scaled = qir_SHL(c, trunc, qir_uniform_ui(c, 4));
921
922 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], qir_ITOF(c, trunc)));
923
924 return qir_SEL_X_Y_NS(c, qir_SUB(c, scaled, qir_uniform_ui(c, 4)),
925 scaled);
926 }
927
928 static struct qreg
929 tgsi_to_qir_uarl(struct vc4_compile *c,
930 struct tgsi_full_instruction *tgsi_inst,
931 enum qop op, struct qreg *src, int i)
932 {
933 return qir_SHL(c, src[0 * 4 + i], qir_uniform_ui(c, 4));
934 }
935
936 static struct qreg
937 get_channel_from_vpm(struct vc4_compile *c,
938 struct qreg *vpm_reads,
939 uint8_t swiz,
940 const struct util_format_description *desc)
941 {
942 const struct util_format_channel_description *chan =
943 &desc->channel[swiz];
944 struct qreg temp;
945
946 if (swiz > UTIL_FORMAT_SWIZZLE_W)
947 return get_swizzled_channel(c, vpm_reads, swiz);
948 else if (chan->size == 32 &&
949 chan->type == UTIL_FORMAT_TYPE_FLOAT) {
950 return get_swizzled_channel(c, vpm_reads, swiz);
951 } else if (chan->size == 32 &&
952 chan->type == UTIL_FORMAT_TYPE_SIGNED) {
953 if (chan->normalized) {
954 return qir_FMUL(c,
955 qir_ITOF(c, vpm_reads[swiz]),
956 qir_uniform_f(c,
957 1.0 / 0x7fffffff));
958 } else {
959 return qir_ITOF(c, vpm_reads[swiz]);
960 }
961 } else if (chan->size == 8 &&
962 (chan->type == UTIL_FORMAT_TYPE_UNSIGNED ||
963 chan->type == UTIL_FORMAT_TYPE_SIGNED)) {
964 struct qreg vpm = vpm_reads[0];
965 if (chan->type == UTIL_FORMAT_TYPE_SIGNED) {
966 temp = qir_XOR(c, vpm, qir_uniform_ui(c, 0x80808080));
967 if (chan->normalized) {
968 return qir_FSUB(c, qir_FMUL(c,
969 qir_UNPACK_8_F(c, temp, swiz),
970 qir_uniform_f(c, 2.0)),
971 qir_uniform_f(c, 1.0));
972 } else {
973 return qir_FADD(c,
974 qir_ITOF(c,
975 qir_UNPACK_8_I(c, temp,
976 swiz)),
977 qir_uniform_f(c, -128.0));
978 }
979 } else {
980 if (chan->normalized) {
981 return qir_UNPACK_8_F(c, vpm, swiz);
982 } else {
983 return qir_ITOF(c, qir_UNPACK_8_I(c, vpm, swiz));
984 }
985 }
986 } else if (chan->size == 16 &&
987 (chan->type == UTIL_FORMAT_TYPE_UNSIGNED ||
988 chan->type == UTIL_FORMAT_TYPE_SIGNED)) {
989 struct qreg vpm = vpm_reads[swiz / 2];
990
991 /* Note that UNPACK_16F eats a half float, not ints, so we use
992 * UNPACK_16_I for all of these.
993 */
994 if (chan->type == UTIL_FORMAT_TYPE_SIGNED) {
995 temp = qir_ITOF(c, qir_UNPACK_16_I(c, vpm, swiz % 2));
996 if (chan->normalized) {
997 return qir_FMUL(c, temp,
998 qir_uniform_f(c, 1/32768.0f));
999 } else {
1000 return temp;
1001 }
1002 } else {
1003 /* UNPACK_16I sign-extends, so we have to emit ANDs. */
1004 temp = vpm;
1005 if (swiz == 1 || swiz == 3)
1006 temp = qir_UNPACK_16_I(c, temp, 1);
1007 temp = qir_AND(c, temp, qir_uniform_ui(c, 0xffff));
1008 temp = qir_ITOF(c, temp);
1009
1010 if (chan->normalized) {
1011 return qir_FMUL(c, temp,
1012 qir_uniform_f(c, 1 / 65535.0));
1013 } else {
1014 return temp;
1015 }
1016 }
1017 } else {
1018 return c->undef;
1019 }
1020 }
1021
1022 static void
1023 emit_vertex_input(struct vc4_compile *c, int attr)
1024 {
1025 enum pipe_format format = c->vs_key->attr_formats[attr];
1026 uint32_t attr_size = util_format_get_blocksize(format);
1027 struct qreg vpm_reads[4];
1028
1029 c->vattr_sizes[attr] = align(attr_size, 4);
1030 for (int i = 0; i < align(attr_size, 4) / 4; i++) {
1031 struct qreg vpm = { QFILE_VPM, attr * 4 + i };
1032 vpm_reads[i] = qir_MOV(c, vpm);
1033 c->num_inputs++;
1034 }
1035
1036 bool format_warned = false;
1037 const struct util_format_description *desc =
1038 util_format_description(format);
1039
1040 for (int i = 0; i < 4; i++) {
1041 uint8_t swiz = desc->swizzle[i];
1042 struct qreg result = get_channel_from_vpm(c, vpm_reads,
1043 swiz, desc);
1044
1045 if (result.file == QFILE_NULL) {
1046 if (!format_warned) {
1047 fprintf(stderr,
1048 "vtx element %d unsupported type: %s\n",
1049 attr, util_format_name(format));
1050 format_warned = true;
1051 }
1052 result = qir_uniform_f(c, 0.0);
1053 }
1054 c->inputs[attr * 4 + i] = result;
1055 }
1056 }
1057
1058 static void
1059 tgsi_to_qir_kill_if(struct vc4_compile *c, struct qreg *src, int i)
1060 {
1061 if (c->discard.file == QFILE_NULL)
1062 c->discard = qir_uniform_f(c, 0.0);
1063 qir_SF(c, src[0 * 4 + i]);
1064 c->discard = qir_SEL_X_Y_NS(c, qir_uniform_f(c, 1.0),
1065 c->discard);
1066 }
1067
1068 static void
1069 emit_fragcoord_input(struct vc4_compile *c, int attr)
1070 {
1071 c->inputs[attr * 4 + 0] = qir_FRAG_X(c);
1072 c->inputs[attr * 4 + 1] = qir_FRAG_Y(c);
1073 c->inputs[attr * 4 + 2] =
1074 qir_FMUL(c,
1075 qir_ITOF(c, qir_FRAG_Z(c)),
1076 qir_uniform_f(c, 1.0 / 0xffffff));
1077 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
1078 }
1079
1080 static void
1081 emit_point_coord_input(struct vc4_compile *c, int attr)
1082 {
1083 if (c->point_x.file == QFILE_NULL) {
1084 c->point_x = qir_uniform_f(c, 0.0);
1085 c->point_y = qir_uniform_f(c, 0.0);
1086 }
1087
1088 c->inputs[attr * 4 + 0] = c->point_x;
1089 if (c->fs_key->point_coord_upper_left) {
1090 c->inputs[attr * 4 + 1] = qir_FSUB(c,
1091 qir_uniform_f(c, 1.0),
1092 c->point_y);
1093 } else {
1094 c->inputs[attr * 4 + 1] = c->point_y;
1095 }
1096 c->inputs[attr * 4 + 2] = qir_uniform_f(c, 0.0);
1097 c->inputs[attr * 4 + 3] = qir_uniform_f(c, 1.0);
1098 }
1099
1100 static struct qreg
1101 emit_fragment_varying(struct vc4_compile *c, uint8_t semantic,
1102 uint8_t index, uint8_t swizzle)
1103 {
1104 uint32_t i = c->num_input_semantics++;
1105 struct qreg vary = {
1106 QFILE_VARY,
1107 i
1108 };
1109
1110 if (c->num_input_semantics >= c->input_semantics_array_size) {
1111 c->input_semantics_array_size =
1112 MAX2(4, c->input_semantics_array_size * 2);
1113
1114 c->input_semantics = reralloc(c, c->input_semantics,
1115 struct vc4_varying_semantic,
1116 c->input_semantics_array_size);
1117 }
1118
1119 c->input_semantics[i].semantic = semantic;
1120 c->input_semantics[i].index = index;
1121 c->input_semantics[i].swizzle = swizzle;
1122
1123 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
1124 }
1125
1126 static void
1127 emit_fragment_input(struct vc4_compile *c, int attr,
1128 struct tgsi_full_declaration *decl)
1129 {
1130 for (int i = 0; i < 4; i++) {
1131 c->inputs[attr * 4 + i] =
1132 emit_fragment_varying(c,
1133 decl->Semantic.Name,
1134 decl->Semantic.Index,
1135 i);
1136 c->num_inputs++;
1137 }
1138 }
1139
1140 static void
1141 emit_face_input(struct vc4_compile *c, int attr)
1142 {
1143 c->inputs[attr * 4 + 0] = qir_FSUB(c,
1144 qir_uniform_f(c, 1.0),
1145 qir_FMUL(c,
1146 qir_ITOF(c, qir_FRAG_REV_FLAG(c)),
1147 qir_uniform_f(c, 2.0)));
1148 c->inputs[attr * 4 + 1] = qir_uniform_f(c, 0.0);
1149 c->inputs[attr * 4 + 2] = qir_uniform_f(c, 0.0);
1150 c->inputs[attr * 4 + 3] = qir_uniform_f(c, 1.0);
1151 }
1152
1153 static void
1154 add_output(struct vc4_compile *c,
1155 uint32_t decl_offset,
1156 uint8_t semantic_name,
1157 uint8_t semantic_index,
1158 uint8_t semantic_swizzle)
1159 {
1160 uint32_t old_array_size = c->outputs_array_size;
1161 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
1162 decl_offset + 1);
1163
1164 if (old_array_size != c->outputs_array_size) {
1165 c->output_semantics = reralloc(c,
1166 c->output_semantics,
1167 struct vc4_varying_semantic,
1168 c->outputs_array_size);
1169 }
1170
1171 c->output_semantics[decl_offset].semantic = semantic_name;
1172 c->output_semantics[decl_offset].index = semantic_index;
1173 c->output_semantics[decl_offset].swizzle = semantic_swizzle;
1174 }
1175
1176 static void
1177 add_array_info(struct vc4_compile *c, uint32_t array_id,
1178 uint32_t start, uint32_t size)
1179 {
1180 if (array_id >= c->ubo_ranges_array_size) {
1181 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
1182 array_id + 1);
1183 c->ubo_ranges = reralloc(c, c->ubo_ranges,
1184 struct vc4_compiler_ubo_range,
1185 c->ubo_ranges_array_size);
1186 }
1187
1188 c->ubo_ranges[array_id].dst_offset = 0;
1189 c->ubo_ranges[array_id].src_offset = start;
1190 c->ubo_ranges[array_id].size = size;
1191 c->ubo_ranges[array_id].used = false;
1192 }
1193
1194 static void
1195 emit_tgsi_declaration(struct vc4_compile *c,
1196 struct tgsi_full_declaration *decl)
1197 {
1198 switch (decl->Declaration.File) {
1199 case TGSI_FILE_TEMPORARY: {
1200 uint32_t old_size = c->temps_array_size;
1201 resize_qreg_array(c, &c->temps, &c->temps_array_size,
1202 (decl->Range.Last + 1) * 4);
1203
1204 for (int i = old_size; i < c->temps_array_size; i++)
1205 c->temps[i] = qir_uniform_ui(c, 0);
1206 break;
1207 }
1208
1209 case TGSI_FILE_INPUT:
1210 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1211 (decl->Range.Last + 1) * 4);
1212
1213 for (int i = decl->Range.First;
1214 i <= decl->Range.Last;
1215 i++) {
1216 if (c->stage == QSTAGE_FRAG) {
1217 if (decl->Semantic.Name ==
1218 TGSI_SEMANTIC_POSITION) {
1219 emit_fragcoord_input(c, i);
1220 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
1221 emit_face_input(c, i);
1222 } else if (decl->Semantic.Name == TGSI_SEMANTIC_GENERIC &&
1223 (c->fs_key->point_sprite_mask &
1224 (1 << decl->Semantic.Index))) {
1225 emit_point_coord_input(c, i);
1226 } else {
1227 emit_fragment_input(c, i, decl);
1228 }
1229 } else {
1230 emit_vertex_input(c, i);
1231 }
1232 }
1233 break;
1234
1235 case TGSI_FILE_OUTPUT: {
1236 for (int i = 0; i < 4; i++) {
1237 add_output(c,
1238 decl->Range.First * 4 + i,
1239 decl->Semantic.Name,
1240 decl->Semantic.Index,
1241 i);
1242 }
1243
1244 switch (decl->Semantic.Name) {
1245 case TGSI_SEMANTIC_POSITION:
1246 c->output_position_index = decl->Range.First * 4;
1247 break;
1248 case TGSI_SEMANTIC_CLIPVERTEX:
1249 c->output_clipvertex_index = decl->Range.First * 4;
1250 break;
1251 case TGSI_SEMANTIC_COLOR:
1252 c->output_color_index = decl->Range.First * 4;
1253 break;
1254 case TGSI_SEMANTIC_PSIZE:
1255 c->output_point_size_index = decl->Range.First * 4;
1256 break;
1257 }
1258
1259 break;
1260
1261 case TGSI_FILE_CONSTANT:
1262 add_array_info(c,
1263 decl->Array.ArrayID,
1264 decl->Range.First * 16,
1265 (decl->Range.Last -
1266 decl->Range.First + 1) * 16);
1267 break;
1268 }
1269 }
1270 }
1271
1272 static void
1273 emit_tgsi_instruction(struct vc4_compile *c,
1274 struct tgsi_full_instruction *tgsi_inst)
1275 {
1276 static const struct {
1277 enum qop op;
1278 struct qreg (*func)(struct vc4_compile *c,
1279 struct tgsi_full_instruction *tgsi_inst,
1280 enum qop op,
1281 struct qreg *src, int i);
1282 } op_trans[] = {
1283 [TGSI_OPCODE_MOV] = { QOP_MOV, tgsi_to_qir_alu },
1284 [TGSI_OPCODE_ABS] = { 0, tgsi_to_qir_abs },
1285 [TGSI_OPCODE_MUL] = { QOP_FMUL, tgsi_to_qir_alu },
1286 [TGSI_OPCODE_ADD] = { QOP_FADD, tgsi_to_qir_alu },
1287 [TGSI_OPCODE_SUB] = { QOP_FSUB, tgsi_to_qir_alu },
1288 [TGSI_OPCODE_MIN] = { QOP_FMIN, tgsi_to_qir_alu },
1289 [TGSI_OPCODE_MAX] = { QOP_FMAX, tgsi_to_qir_alu },
1290 [TGSI_OPCODE_F2I] = { QOP_FTOI, tgsi_to_qir_alu },
1291 [TGSI_OPCODE_I2F] = { QOP_ITOF, tgsi_to_qir_alu },
1292 [TGSI_OPCODE_UADD] = { QOP_ADD, tgsi_to_qir_alu },
1293 [TGSI_OPCODE_USHR] = { QOP_SHR, tgsi_to_qir_alu },
1294 [TGSI_OPCODE_ISHR] = { QOP_ASR, tgsi_to_qir_alu },
1295 [TGSI_OPCODE_SHL] = { QOP_SHL, tgsi_to_qir_alu },
1296 [TGSI_OPCODE_IMIN] = { QOP_MIN, tgsi_to_qir_alu },
1297 [TGSI_OPCODE_IMAX] = { QOP_MAX, tgsi_to_qir_alu },
1298 [TGSI_OPCODE_AND] = { QOP_AND, tgsi_to_qir_alu },
1299 [TGSI_OPCODE_OR] = { QOP_OR, tgsi_to_qir_alu },
1300 [TGSI_OPCODE_XOR] = { QOP_XOR, tgsi_to_qir_alu },
1301 [TGSI_OPCODE_NOT] = { QOP_NOT, tgsi_to_qir_alu },
1302
1303 [TGSI_OPCODE_UMUL] = { 0, tgsi_to_qir_umul },
1304 [TGSI_OPCODE_UMAD] = { 0, tgsi_to_qir_umad },
1305 [TGSI_OPCODE_IDIV] = { 0, tgsi_to_qir_idiv },
1306 [TGSI_OPCODE_INEG] = { 0, tgsi_to_qir_ineg },
1307
1308 [TGSI_OPCODE_SEQ] = { 0, tgsi_to_qir_seq },
1309 [TGSI_OPCODE_SNE] = { 0, tgsi_to_qir_sne },
1310 [TGSI_OPCODE_SGE] = { 0, tgsi_to_qir_sge },
1311 [TGSI_OPCODE_SLT] = { 0, tgsi_to_qir_slt },
1312 [TGSI_OPCODE_FSEQ] = { 0, tgsi_to_qir_fseq },
1313 [TGSI_OPCODE_FSNE] = { 0, tgsi_to_qir_fsne },
1314 [TGSI_OPCODE_FSGE] = { 0, tgsi_to_qir_fsge },
1315 [TGSI_OPCODE_FSLT] = { 0, tgsi_to_qir_fslt },
1316 [TGSI_OPCODE_USEQ] = { 0, tgsi_to_qir_useq },
1317 [TGSI_OPCODE_USNE] = { 0, tgsi_to_qir_usne },
1318 [TGSI_OPCODE_ISGE] = { 0, tgsi_to_qir_isge },
1319 [TGSI_OPCODE_ISLT] = { 0, tgsi_to_qir_islt },
1320
1321 [TGSI_OPCODE_CMP] = { 0, tgsi_to_qir_cmp },
1322 [TGSI_OPCODE_UCMP] = { 0, tgsi_to_qir_ucmp },
1323 [TGSI_OPCODE_MAD] = { 0, tgsi_to_qir_mad },
1324 [TGSI_OPCODE_RCP] = { QOP_RCP, tgsi_to_qir_rcp },
1325 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_rsq },
1326 [TGSI_OPCODE_EX2] = { QOP_EXP2, tgsi_to_qir_scalar },
1327 [TGSI_OPCODE_LG2] = { QOP_LOG2, tgsi_to_qir_scalar },
1328 [TGSI_OPCODE_LRP] = { 0, tgsi_to_qir_lrp },
1329 [TGSI_OPCODE_TRUNC] = { 0, tgsi_to_qir_trunc },
1330 [TGSI_OPCODE_CEIL] = { 0, tgsi_to_qir_ceil },
1331 [TGSI_OPCODE_FRC] = { 0, tgsi_to_qir_frc },
1332 [TGSI_OPCODE_FLR] = { 0, tgsi_to_qir_flr },
1333 [TGSI_OPCODE_SIN] = { 0, tgsi_to_qir_sin },
1334 [TGSI_OPCODE_COS] = { 0, tgsi_to_qir_cos },
1335 [TGSI_OPCODE_CLAMP] = { 0, tgsi_to_qir_clamp },
1336 [TGSI_OPCODE_SSG] = { 0, tgsi_to_qir_ssg },
1337 [TGSI_OPCODE_ARL] = { 0, tgsi_to_qir_arl },
1338 [TGSI_OPCODE_UARL] = { 0, tgsi_to_qir_uarl },
1339 };
1340 static int asdf = 0;
1341 uint32_t tgsi_op = tgsi_inst->Instruction.Opcode;
1342
1343 if (tgsi_op == TGSI_OPCODE_END)
1344 return;
1345
1346 struct qreg src_regs[12];
1347 for (int s = 0; s < 3; s++) {
1348 for (int i = 0; i < 4; i++) {
1349 src_regs[4 * s + i] =
1350 get_src(c, tgsi_inst->Instruction.Opcode,
1351 &tgsi_inst->Src[s], i);
1352 }
1353 }
1354
1355 switch (tgsi_op) {
1356 case TGSI_OPCODE_TEX:
1357 case TGSI_OPCODE_TXP:
1358 case TGSI_OPCODE_TXB:
1359 case TGSI_OPCODE_TXL:
1360 tgsi_to_qir_tex(c, tgsi_inst,
1361 op_trans[tgsi_op].op, src_regs);
1362 return;
1363 case TGSI_OPCODE_KILL:
1364 c->discard = qir_uniform_f(c, 1.0);
1365 return;
1366 case TGSI_OPCODE_KILL_IF:
1367 for (int i = 0; i < 4; i++)
1368 tgsi_to_qir_kill_if(c, src_regs, i);
1369 return;
1370 default:
1371 break;
1372 }
1373
1374 if (tgsi_op > ARRAY_SIZE(op_trans) || !(op_trans[tgsi_op].func)) {
1375 fprintf(stderr, "unknown tgsi inst: ");
1376 tgsi_dump_instruction(tgsi_inst, asdf++);
1377 fprintf(stderr, "\n");
1378 abort();
1379 }
1380
1381 for (int i = 0; i < 4; i++) {
1382 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
1383 continue;
1384
1385 struct qreg result;
1386
1387 result = op_trans[tgsi_op].func(c, tgsi_inst,
1388 op_trans[tgsi_op].op,
1389 src_regs, i);
1390
1391 if (tgsi_inst->Instruction.Saturate) {
1392 float low = (tgsi_inst->Instruction.Saturate ==
1393 TGSI_SAT_MINUS_PLUS_ONE ? -1.0 : 0.0);
1394 result = qir_FMAX(c,
1395 qir_FMIN(c,
1396 result,
1397 qir_uniform_f(c, 1.0)),
1398 qir_uniform_f(c, low));
1399 }
1400
1401 update_dst(c, tgsi_inst, i, result);
1402 }
1403 }
1404
1405 static void
1406 parse_tgsi_immediate(struct vc4_compile *c, struct tgsi_full_immediate *imm)
1407 {
1408 for (int i = 0; i < 4; i++) {
1409 unsigned n = c->num_consts++;
1410 resize_qreg_array(c, &c->consts, &c->consts_array_size, n + 1);
1411 c->consts[n] = qir_uniform_ui(c, imm->u[i].Uint);
1412 }
1413 }
1414
1415 static struct qreg
1416 vc4_blend_channel(struct vc4_compile *c,
1417 struct qreg *dst,
1418 struct qreg *src,
1419 struct qreg val,
1420 unsigned factor,
1421 int channel)
1422 {
1423 switch(factor) {
1424 case PIPE_BLENDFACTOR_ONE:
1425 return val;
1426 case PIPE_BLENDFACTOR_SRC_COLOR:
1427 return qir_FMUL(c, val, src[channel]);
1428 case PIPE_BLENDFACTOR_SRC_ALPHA:
1429 return qir_FMUL(c, val, src[3]);
1430 case PIPE_BLENDFACTOR_DST_ALPHA:
1431 return qir_FMUL(c, val, dst[3]);
1432 case PIPE_BLENDFACTOR_DST_COLOR:
1433 return qir_FMUL(c, val, dst[channel]);
1434 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
1435 if (channel != 3) {
1436 return qir_FMUL(c,
1437 val,
1438 qir_FMIN(c,
1439 src[3],
1440 qir_FSUB(c,
1441 qir_uniform_f(c, 1.0),
1442 dst[3])));
1443 } else {
1444 return val;
1445 }
1446 case PIPE_BLENDFACTOR_CONST_COLOR:
1447 return qir_FMUL(c, val,
1448 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR,
1449 channel));
1450 case PIPE_BLENDFACTOR_CONST_ALPHA:
1451 return qir_FMUL(c, val,
1452 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR, 3));
1453 case PIPE_BLENDFACTOR_ZERO:
1454 return qir_uniform_f(c, 0.0);
1455 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
1456 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1457 src[channel]));
1458 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
1459 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1460 src[3]));
1461 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
1462 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1463 dst[3]));
1464 case PIPE_BLENDFACTOR_INV_DST_COLOR:
1465 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1466 dst[channel]));
1467 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
1468 return qir_FMUL(c, val,
1469 qir_FSUB(c, qir_uniform_f(c, 1.0),
1470 qir_uniform(c,
1471 QUNIFORM_BLEND_CONST_COLOR,
1472 channel)));
1473 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
1474 return qir_FMUL(c, val,
1475 qir_FSUB(c, qir_uniform_f(c, 1.0),
1476 qir_uniform(c,
1477 QUNIFORM_BLEND_CONST_COLOR,
1478 3)));
1479
1480 default:
1481 case PIPE_BLENDFACTOR_SRC1_COLOR:
1482 case PIPE_BLENDFACTOR_SRC1_ALPHA:
1483 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
1484 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
1485 /* Unsupported. */
1486 fprintf(stderr, "Unknown blend factor %d\n", factor);
1487 return val;
1488 }
1489 }
1490
1491 static struct qreg
1492 vc4_blend_func(struct vc4_compile *c,
1493 struct qreg src, struct qreg dst,
1494 unsigned func)
1495 {
1496 switch (func) {
1497 case PIPE_BLEND_ADD:
1498 return qir_FADD(c, src, dst);
1499 case PIPE_BLEND_SUBTRACT:
1500 return qir_FSUB(c, src, dst);
1501 case PIPE_BLEND_REVERSE_SUBTRACT:
1502 return qir_FSUB(c, dst, src);
1503 case PIPE_BLEND_MIN:
1504 return qir_FMIN(c, src, dst);
1505 case PIPE_BLEND_MAX:
1506 return qir_FMAX(c, src, dst);
1507
1508 default:
1509 /* Unsupported. */
1510 fprintf(stderr, "Unknown blend func %d\n", func);
1511 return src;
1512
1513 }
1514 }
1515
1516 /**
1517 * Implements fixed function blending in shader code.
1518 *
1519 * VC4 doesn't have any hardware support for blending. Instead, you read the
1520 * current contents of the destination from the tile buffer after having
1521 * waited for the scoreboard (which is handled by vc4_qpu_emit.c), then do
1522 * math using your output color and that destination value, and update the
1523 * output color appropriately.
1524 */
1525 static void
1526 vc4_blend(struct vc4_compile *c, struct qreg *result,
1527 struct qreg *dst_color, struct qreg *src_color)
1528 {
1529 struct pipe_rt_blend_state *blend = &c->fs_key->blend;
1530
1531 if (!blend->blend_enable) {
1532 for (int i = 0; i < 4; i++)
1533 result[i] = src_color[i];
1534 return;
1535 }
1536
1537 struct qreg clamped_src[4];
1538 struct qreg clamped_dst[4];
1539 for (int i = 0; i < 4; i++) {
1540 clamped_src[i] = qir_SAT(c, src_color[i]);
1541 clamped_dst[i] = qir_SAT(c, dst_color[i]);
1542 }
1543 src_color = clamped_src;
1544 dst_color = clamped_dst;
1545
1546 struct qreg src_blend[4], dst_blend[4];
1547 for (int i = 0; i < 3; i++) {
1548 src_blend[i] = vc4_blend_channel(c,
1549 dst_color, src_color,
1550 src_color[i],
1551 blend->rgb_src_factor, i);
1552 dst_blend[i] = vc4_blend_channel(c,
1553 dst_color, src_color,
1554 dst_color[i],
1555 blend->rgb_dst_factor, i);
1556 }
1557 src_blend[3] = vc4_blend_channel(c,
1558 dst_color, src_color,
1559 src_color[3],
1560 blend->alpha_src_factor, 3);
1561 dst_blend[3] = vc4_blend_channel(c,
1562 dst_color, src_color,
1563 dst_color[3],
1564 blend->alpha_dst_factor, 3);
1565
1566 for (int i = 0; i < 3; i++) {
1567 result[i] = vc4_blend_func(c,
1568 src_blend[i], dst_blend[i],
1569 blend->rgb_func);
1570 }
1571 result[3] = vc4_blend_func(c,
1572 src_blend[3], dst_blend[3],
1573 blend->alpha_func);
1574 }
1575
1576 static void
1577 clip_distance_discard(struct vc4_compile *c)
1578 {
1579 for (int i = 0; i < PIPE_MAX_CLIP_PLANES; i++) {
1580 if (!(c->key->ucp_enables & (1 << i)))
1581 continue;
1582
1583 struct qreg dist = emit_fragment_varying(c,
1584 TGSI_SEMANTIC_CLIPDIST,
1585 i,
1586 TGSI_SWIZZLE_X);
1587
1588 qir_SF(c, dist);
1589
1590 if (c->discard.file == QFILE_NULL)
1591 c->discard = qir_uniform_f(c, 0.0);
1592
1593 c->discard = qir_SEL_X_Y_NS(c, qir_uniform_f(c, 1.0),
1594 c->discard);
1595 }
1596 }
1597
1598 static void
1599 alpha_test_discard(struct vc4_compile *c)
1600 {
1601 struct qreg src_alpha;
1602 struct qreg alpha_ref = qir_uniform(c, QUNIFORM_ALPHA_REF, 0);
1603
1604 if (!c->fs_key->alpha_test)
1605 return;
1606
1607 if (c->output_color_index != -1)
1608 src_alpha = c->outputs[c->output_color_index + 3];
1609 else
1610 src_alpha = qir_uniform_f(c, 1.0);
1611
1612 if (c->discard.file == QFILE_NULL)
1613 c->discard = qir_uniform_f(c, 0.0);
1614
1615 switch (c->fs_key->alpha_test_func) {
1616 case PIPE_FUNC_NEVER:
1617 c->discard = qir_uniform_f(c, 1.0);
1618 break;
1619 case PIPE_FUNC_ALWAYS:
1620 break;
1621 case PIPE_FUNC_EQUAL:
1622 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1623 c->discard = qir_SEL_X_Y_ZS(c, c->discard,
1624 qir_uniform_f(c, 1.0));
1625 break;
1626 case PIPE_FUNC_NOTEQUAL:
1627 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1628 c->discard = qir_SEL_X_Y_ZC(c, c->discard,
1629 qir_uniform_f(c, 1.0));
1630 break;
1631 case PIPE_FUNC_GREATER:
1632 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1633 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1634 qir_uniform_f(c, 1.0));
1635 break;
1636 case PIPE_FUNC_GEQUAL:
1637 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1638 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1639 qir_uniform_f(c, 1.0));
1640 break;
1641 case PIPE_FUNC_LESS:
1642 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1643 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1644 qir_uniform_f(c, 1.0));
1645 break;
1646 case PIPE_FUNC_LEQUAL:
1647 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1648 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1649 qir_uniform_f(c, 1.0));
1650 break;
1651 }
1652 }
1653
1654 static struct qreg
1655 vc4_logicop(struct vc4_compile *c, struct qreg src, struct qreg dst)
1656 {
1657 switch (c->fs_key->logicop_func) {
1658 case PIPE_LOGICOP_CLEAR:
1659 return qir_uniform_f(c, 0.0);
1660 case PIPE_LOGICOP_NOR:
1661 return qir_NOT(c, qir_OR(c, src, dst));
1662 case PIPE_LOGICOP_AND_INVERTED:
1663 return qir_AND(c, qir_NOT(c, src), dst);
1664 case PIPE_LOGICOP_COPY_INVERTED:
1665 return qir_NOT(c, src);
1666 case PIPE_LOGICOP_AND_REVERSE:
1667 return qir_AND(c, src, qir_NOT(c, dst));
1668 case PIPE_LOGICOP_INVERT:
1669 return qir_NOT(c, dst);
1670 case PIPE_LOGICOP_XOR:
1671 return qir_XOR(c, src, dst);
1672 case PIPE_LOGICOP_NAND:
1673 return qir_NOT(c, qir_AND(c, src, dst));
1674 case PIPE_LOGICOP_AND:
1675 return qir_AND(c, src, dst);
1676 case PIPE_LOGICOP_EQUIV:
1677 return qir_NOT(c, qir_XOR(c, src, dst));
1678 case PIPE_LOGICOP_NOOP:
1679 return dst;
1680 case PIPE_LOGICOP_OR_INVERTED:
1681 return qir_OR(c, qir_NOT(c, src), dst);
1682 case PIPE_LOGICOP_OR_REVERSE:
1683 return qir_OR(c, src, qir_NOT(c, dst));
1684 case PIPE_LOGICOP_OR:
1685 return qir_OR(c, src, dst);
1686 case PIPE_LOGICOP_SET:
1687 return qir_uniform_ui(c, ~0);
1688 case PIPE_LOGICOP_COPY:
1689 default:
1690 return src;
1691 }
1692 }
1693
1694 static void
1695 emit_frag_end(struct vc4_compile *c)
1696 {
1697 clip_distance_discard(c);
1698 alpha_test_discard(c);
1699
1700 enum pipe_format color_format = c->fs_key->color_format;
1701 const uint8_t *format_swiz = vc4_get_format_swizzle(color_format);
1702 struct qreg tlb_read_color[4] = { c->undef, c->undef, c->undef, c->undef };
1703 struct qreg dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1704 struct qreg linear_dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1705 struct qreg packed_dst_color = c->undef;
1706
1707 if (c->fs_key->blend.blend_enable ||
1708 c->fs_key->blend.colormask != 0xf ||
1709 c->fs_key->logicop_func != PIPE_LOGICOP_COPY) {
1710 struct qreg r4 = qir_TLB_COLOR_READ(c);
1711 for (int i = 0; i < 4; i++)
1712 tlb_read_color[i] = qir_R4_UNPACK(c, r4, i);
1713 for (int i = 0; i < 4; i++) {
1714 dst_color[i] = get_swizzled_channel(c,
1715 tlb_read_color,
1716 format_swiz[i]);
1717 if (util_format_is_srgb(color_format) && i != 3) {
1718 linear_dst_color[i] =
1719 qir_srgb_decode(c, dst_color[i]);
1720 } else {
1721 linear_dst_color[i] = dst_color[i];
1722 }
1723 }
1724
1725 /* Save the packed value for logic ops. Can't reuse r4
1726 * becuase other things might smash it (like sRGB)
1727 */
1728 packed_dst_color = qir_MOV(c, r4);
1729 }
1730
1731 struct qreg blend_color[4];
1732 struct qreg undef_array[4] = {
1733 c->undef, c->undef, c->undef, c->undef
1734 };
1735 vc4_blend(c, blend_color, linear_dst_color,
1736 (c->output_color_index != -1 ?
1737 c->outputs + c->output_color_index :
1738 undef_array));
1739
1740 if (util_format_is_srgb(color_format)) {
1741 for (int i = 0; i < 3; i++)
1742 blend_color[i] = qir_srgb_encode(c, blend_color[i]);
1743 }
1744
1745 /* Debug: Sometimes you're getting a black output and just want to see
1746 * if the FS is getting executed at all. Spam magenta into the color
1747 * output.
1748 */
1749 if (0) {
1750 blend_color[0] = qir_uniform_f(c, 1.0);
1751 blend_color[1] = qir_uniform_f(c, 0.0);
1752 blend_color[2] = qir_uniform_f(c, 1.0);
1753 blend_color[3] = qir_uniform_f(c, 0.5);
1754 }
1755
1756 struct qreg swizzled_outputs[4];
1757 for (int i = 0; i < 4; i++) {
1758 swizzled_outputs[i] = get_swizzled_channel(c, blend_color,
1759 format_swiz[i]);
1760 }
1761
1762 if (c->discard.file != QFILE_NULL)
1763 qir_TLB_DISCARD_SETUP(c, c->discard);
1764
1765 if (c->fs_key->stencil_enabled) {
1766 qir_TLB_STENCIL_SETUP(c, qir_uniform(c, QUNIFORM_STENCIL, 0));
1767 if (c->fs_key->stencil_twoside) {
1768 qir_TLB_STENCIL_SETUP(c, qir_uniform(c, QUNIFORM_STENCIL, 1));
1769 }
1770 if (c->fs_key->stencil_full_writemasks) {
1771 qir_TLB_STENCIL_SETUP(c, qir_uniform(c, QUNIFORM_STENCIL, 2));
1772 }
1773 }
1774
1775 if (c->fs_key->depth_enabled) {
1776 struct qreg z;
1777 if (c->output_position_index != -1) {
1778 z = qir_FTOI(c, qir_FMUL(c, c->outputs[c->output_position_index + 2],
1779 qir_uniform_f(c, 0xffffff)));
1780 } else {
1781 z = qir_FRAG_Z(c);
1782 }
1783 qir_TLB_Z_WRITE(c, z);
1784 }
1785
1786 struct qreg packed_color = c->undef;
1787 for (int i = 0; i < 4; i++) {
1788 if (swizzled_outputs[i].file == QFILE_NULL)
1789 continue;
1790 if (packed_color.file == QFILE_NULL) {
1791 packed_color = qir_PACK_8888_F(c, swizzled_outputs[i]);
1792 } else {
1793 packed_color = qir_PACK_8_F(c,
1794 packed_color,
1795 swizzled_outputs[i],
1796 i);
1797 }
1798 }
1799
1800 if (packed_color.file == QFILE_NULL)
1801 packed_color = qir_uniform_ui(c, 0);
1802
1803 if (c->fs_key->logicop_func != PIPE_LOGICOP_COPY) {
1804 packed_color = vc4_logicop(c, packed_color, packed_dst_color);
1805 }
1806
1807 /* If the bit isn't set in the color mask, then just return the
1808 * original dst color, instead.
1809 */
1810 uint32_t colormask = 0xffffffff;
1811 for (int i = 0; i < 4; i++) {
1812 if (format_swiz[i] < 4 &&
1813 !(c->fs_key->blend.colormask & (1 << format_swiz[i]))) {
1814 colormask &= ~(0xff << (i * 8));
1815 }
1816 }
1817 if (colormask != 0xffffffff) {
1818 packed_color = qir_OR(c,
1819 qir_AND(c, packed_color,
1820 qir_uniform_ui(c, colormask)),
1821 qir_AND(c, packed_dst_color,
1822 qir_uniform_ui(c, ~colormask)));
1823 }
1824
1825 qir_emit(c, qir_inst(QOP_TLB_COLOR_WRITE, c->undef,
1826 packed_color, c->undef));
1827 }
1828
1829 static void
1830 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1831 {
1832 struct qreg xyi[2];
1833
1834 for (int i = 0; i < 2; i++) {
1835 struct qreg scale =
1836 qir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1837
1838 xyi[i] = qir_FTOI(c, qir_FMUL(c,
1839 qir_FMUL(c,
1840 c->outputs[c->output_position_index + i],
1841 scale),
1842 rcp_w));
1843 }
1844
1845 qir_VPM_WRITE(c, qir_PACK_SCALED(c, xyi[0], xyi[1]));
1846 }
1847
1848 static void
1849 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1850 {
1851 struct qreg zscale = qir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1852 struct qreg zoffset = qir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1853
1854 qir_VPM_WRITE(c, qir_FADD(c, qir_FMUL(c, qir_FMUL(c,
1855 c->outputs[c->output_position_index + 2],
1856 zscale),
1857 rcp_w),
1858 zoffset));
1859 }
1860
1861 static void
1862 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1863 {
1864 qir_VPM_WRITE(c, rcp_w);
1865 }
1866
1867 static void
1868 emit_point_size_write(struct vc4_compile *c)
1869 {
1870 struct qreg point_size;
1871
1872 if (c->output_point_size_index != -1)
1873 point_size = c->outputs[c->output_point_size_index + 3];
1874 else
1875 point_size = qir_uniform_f(c, 1.0);
1876
1877 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1878 * BCM21553).
1879 */
1880 point_size = qir_FMAX(c, point_size, qir_uniform_f(c, .125));
1881
1882 qir_VPM_WRITE(c, point_size);
1883 }
1884
1885 /**
1886 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1887 *
1888 * The simulator insists that there be at least one vertex attribute, so
1889 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also
1890 * insists that all vertex attributes loaded get read by the VS/CS, so we have
1891 * to consume it here.
1892 */
1893 static void
1894 emit_stub_vpm_read(struct vc4_compile *c)
1895 {
1896 if (c->num_inputs)
1897 return;
1898
1899 c->vattr_sizes[0] = 4;
1900 struct qreg vpm = { QFILE_VPM, 0 };
1901 (void)qir_MOV(c, vpm);
1902 c->num_inputs++;
1903 }
1904
1905 static void
1906 emit_ucp_clipdistance(struct vc4_compile *c)
1907 {
1908 unsigned cv;
1909 if (c->output_clipvertex_index != -1)
1910 cv = c->output_clipvertex_index;
1911 else if (c->output_position_index != -1)
1912 cv = c->output_position_index;
1913 else
1914 return;
1915
1916 for (int plane = 0; plane < PIPE_MAX_CLIP_PLANES; plane++) {
1917 if (!(c->key->ucp_enables & (1 << plane)))
1918 continue;
1919
1920 /* Pick the next outputs[] that hasn't been written to, since
1921 * there are no other program writes left to be processed at
1922 * this point. If something had been declared but not written
1923 * (like a w component), we'll just smash over the top of it.
1924 */
1925 uint32_t output_index = c->num_outputs++;
1926 add_output(c, output_index,
1927 TGSI_SEMANTIC_CLIPDIST,
1928 plane,
1929 TGSI_SWIZZLE_X);
1930
1931
1932 struct qreg dist = qir_uniform_f(c, 0.0);
1933 for (int i = 0; i < 4; i++) {
1934 struct qreg pos_chan = c->outputs[cv + i];
1935 struct qreg ucp =
1936 qir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1937 plane * 4 + i);
1938 dist = qir_FADD(c, dist, qir_FMUL(c, pos_chan, ucp));
1939 }
1940
1941 c->outputs[output_index] = dist;
1942 }
1943 }
1944
1945 static void
1946 emit_vert_end(struct vc4_compile *c,
1947 struct vc4_varying_semantic *fs_inputs,
1948 uint32_t num_fs_inputs)
1949 {
1950 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1951
1952 emit_stub_vpm_read(c);
1953 emit_ucp_clipdistance(c);
1954
1955 emit_scaled_viewport_write(c, rcp_w);
1956 emit_zs_write(c, rcp_w);
1957 emit_rcp_wc_write(c, rcp_w);
1958 if (c->vs_key->per_vertex_point_size)
1959 emit_point_size_write(c);
1960
1961 for (int i = 0; i < num_fs_inputs; i++) {
1962 struct vc4_varying_semantic *input = &fs_inputs[i];
1963 int j;
1964
1965 for (j = 0; j < c->num_outputs; j++) {
1966 struct vc4_varying_semantic *output =
1967 &c->output_semantics[j];
1968
1969 if (input->semantic == output->semantic &&
1970 input->index == output->index &&
1971 input->swizzle == output->swizzle) {
1972 qir_VPM_WRITE(c, c->outputs[j]);
1973 break;
1974 }
1975 }
1976 /* Emit padding if we didn't find a declared VS output for
1977 * this FS input.
1978 */
1979 if (j == c->num_outputs)
1980 qir_VPM_WRITE(c, qir_uniform_f(c, 0.0));
1981 }
1982 }
1983
1984 static void
1985 emit_coord_end(struct vc4_compile *c)
1986 {
1987 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1988
1989 emit_stub_vpm_read(c);
1990
1991 for (int i = 0; i < 4; i++)
1992 qir_VPM_WRITE(c, c->outputs[c->output_position_index + i]);
1993
1994 emit_scaled_viewport_write(c, rcp_w);
1995 emit_zs_write(c, rcp_w);
1996 emit_rcp_wc_write(c, rcp_w);
1997 if (c->vs_key->per_vertex_point_size)
1998 emit_point_size_write(c);
1999 }
2000
2001 static struct vc4_compile *
2002 vc4_shader_tgsi_to_qir(struct vc4_context *vc4, enum qstage stage,
2003 struct vc4_key *key)
2004 {
2005 struct vc4_compile *c = qir_compile_init();
2006 int ret;
2007
2008 c->stage = stage;
2009 for (int i = 0; i < 4; i++)
2010 c->addr[i] = qir_uniform_f(c, 0.0);
2011
2012 c->shader_state = &key->shader_state->base;
2013 c->program_id = key->shader_state->program_id;
2014 c->variant_id = key->shader_state->compiled_variant_count++;
2015
2016 c->key = key;
2017 switch (stage) {
2018 case QSTAGE_FRAG:
2019 c->fs_key = (struct vc4_fs_key *)key;
2020 if (c->fs_key->is_points) {
2021 c->point_x = emit_fragment_varying(c, ~0, ~0, 0);
2022 c->point_y = emit_fragment_varying(c, ~0, ~0, 0);
2023 } else if (c->fs_key->is_lines) {
2024 c->line_x = emit_fragment_varying(c, ~0, ~0, 0);
2025 }
2026 break;
2027 case QSTAGE_VERT:
2028 c->vs_key = (struct vc4_vs_key *)key;
2029 break;
2030 case QSTAGE_COORD:
2031 c->vs_key = (struct vc4_vs_key *)key;
2032 break;
2033 }
2034
2035 const struct tgsi_token *tokens = key->shader_state->base.tokens;
2036 if (c->fs_key && c->fs_key->light_twoside) {
2037 if (!key->shader_state->twoside_tokens) {
2038 const struct tgsi_lowering_config lowering_config = {
2039 .color_two_side = true,
2040 };
2041 struct tgsi_shader_info info;
2042 key->shader_state->twoside_tokens =
2043 tgsi_transform_lowering(&lowering_config,
2044 key->shader_state->base.tokens,
2045 &info);
2046
2047 /* If no transformation occurred, then NULL is
2048 * returned and we just use our original tokens.
2049 */
2050 if (!key->shader_state->twoside_tokens) {
2051 key->shader_state->twoside_tokens =
2052 key->shader_state->base.tokens;
2053 }
2054 }
2055 tokens = key->shader_state->twoside_tokens;
2056 }
2057
2058 ret = tgsi_parse_init(&c->parser, tokens);
2059 assert(ret == TGSI_PARSE_OK);
2060
2061 if (vc4_debug & VC4_DEBUG_TGSI) {
2062 fprintf(stderr, "%s prog %d/%d TGSI:\n",
2063 qir_get_stage_name(c->stage),
2064 c->program_id, c->variant_id);
2065 tgsi_dump(tokens, 0);
2066 }
2067
2068 while (!tgsi_parse_end_of_tokens(&c->parser)) {
2069 tgsi_parse_token(&c->parser);
2070
2071 switch (c->parser.FullToken.Token.Type) {
2072 case TGSI_TOKEN_TYPE_DECLARATION:
2073 emit_tgsi_declaration(c,
2074 &c->parser.FullToken.FullDeclaration);
2075 break;
2076
2077 case TGSI_TOKEN_TYPE_INSTRUCTION:
2078 emit_tgsi_instruction(c,
2079 &c->parser.FullToken.FullInstruction);
2080 break;
2081
2082 case TGSI_TOKEN_TYPE_IMMEDIATE:
2083 parse_tgsi_immediate(c,
2084 &c->parser.FullToken.FullImmediate);
2085 break;
2086 }
2087 }
2088
2089 switch (stage) {
2090 case QSTAGE_FRAG:
2091 emit_frag_end(c);
2092 break;
2093 case QSTAGE_VERT:
2094 emit_vert_end(c,
2095 vc4->prog.fs->input_semantics,
2096 vc4->prog.fs->num_inputs);
2097 break;
2098 case QSTAGE_COORD:
2099 emit_coord_end(c);
2100 break;
2101 }
2102
2103 tgsi_parse_free(&c->parser);
2104 if (vc4_debug & VC4_DEBUG_QIR) {
2105 fprintf(stderr, "%s prog %d/%d pre-opt QIR:\n",
2106 qir_get_stage_name(c->stage),
2107 c->program_id, c->variant_id);
2108 qir_dump(c);
2109 }
2110
2111 qir_optimize(c);
2112 qir_lower_uniforms(c);
2113
2114 if (vc4_debug & VC4_DEBUG_QIR) {
2115 fprintf(stderr, "%s prog %d/%d QIR:\n",
2116 qir_get_stage_name(c->stage),
2117 c->program_id, c->variant_id);
2118 qir_dump(c);
2119 }
2120 qir_reorder_uniforms(c);
2121 vc4_generate_code(vc4, c);
2122
2123 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2124 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d instructions\n",
2125 qir_get_stage_name(c->stage),
2126 c->program_id, c->variant_id,
2127 c->qpu_inst_count);
2128 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d uniforms\n",
2129 qir_get_stage_name(c->stage),
2130 c->program_id, c->variant_id,
2131 c->num_uniforms);
2132 }
2133
2134 return c;
2135 }
2136
2137 static void *
2138 vc4_shader_state_create(struct pipe_context *pctx,
2139 const struct pipe_shader_state *cso)
2140 {
2141 struct vc4_context *vc4 = vc4_context(pctx);
2142 struct vc4_uncompiled_shader *so = CALLOC_STRUCT(vc4_uncompiled_shader);
2143 if (!so)
2144 return NULL;
2145
2146 const struct tgsi_lowering_config lowering_config = {
2147 .lower_DST = true,
2148 .lower_XPD = true,
2149 .lower_SCS = true,
2150 .lower_POW = true,
2151 .lower_LIT = true,
2152 .lower_EXP = true,
2153 .lower_LOG = true,
2154 .lower_DP4 = true,
2155 .lower_DP3 = true,
2156 .lower_DPH = true,
2157 .lower_DP2 = true,
2158 .lower_DP2A = true,
2159 };
2160
2161 struct tgsi_shader_info info;
2162 so->base.tokens = tgsi_transform_lowering(&lowering_config, cso->tokens, &info);
2163 if (!so->base.tokens)
2164 so->base.tokens = tgsi_dup_tokens(cso->tokens);
2165 so->program_id = vc4->next_uncompiled_program_id++;
2166
2167 return so;
2168 }
2169
2170 static void
2171 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
2172 struct vc4_compile *c)
2173 {
2174 int count = c->num_uniforms;
2175 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
2176
2177 uinfo->count = count;
2178 uinfo->data = ralloc_array(shader, uint32_t, count);
2179 memcpy(uinfo->data, c->uniform_data,
2180 count * sizeof(*uinfo->data));
2181 uinfo->contents = ralloc_array(shader, enum quniform_contents, count);
2182 memcpy(uinfo->contents, c->uniform_contents,
2183 count * sizeof(*uinfo->contents));
2184 uinfo->num_texture_samples = c->num_texture_samples;
2185 }
2186
2187 static struct vc4_compiled_shader *
2188 vc4_get_compiled_shader(struct vc4_context *vc4, enum qstage stage,
2189 struct vc4_key *key)
2190 {
2191 struct hash_table *ht;
2192 uint32_t key_size;
2193 if (stage == QSTAGE_FRAG) {
2194 ht = vc4->fs_cache;
2195 key_size = sizeof(struct vc4_fs_key);
2196 } else {
2197 ht = vc4->vs_cache;
2198 key_size = sizeof(struct vc4_vs_key);
2199 }
2200
2201 struct vc4_compiled_shader *shader;
2202 struct hash_entry *entry = _mesa_hash_table_search(ht, key);
2203 if (entry)
2204 return entry->data;
2205
2206 struct vc4_compile *c = vc4_shader_tgsi_to_qir(vc4, stage, key);
2207 shader = rzalloc(NULL, struct vc4_compiled_shader);
2208
2209 shader->program_id = vc4->next_compiled_program_id++;
2210 if (stage == QSTAGE_FRAG) {
2211 bool input_live[c->num_input_semantics];
2212 struct simple_node *node;
2213
2214 memset(input_live, 0, sizeof(input_live));
2215 foreach(node, &c->instructions) {
2216 struct qinst *inst = (struct qinst *)node;
2217 for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) {
2218 if (inst->src[i].file == QFILE_VARY)
2219 input_live[inst->src[i].index] = true;
2220 }
2221 }
2222
2223 shader->input_semantics = ralloc_array(shader,
2224 struct vc4_varying_semantic,
2225 c->num_input_semantics);
2226
2227 for (int i = 0; i < c->num_input_semantics; i++) {
2228 struct vc4_varying_semantic *sem = &c->input_semantics[i];
2229
2230 if (!input_live[i])
2231 continue;
2232
2233 /* Skip non-VS-output inputs. */
2234 if (sem->semantic == (uint8_t)~0)
2235 continue;
2236
2237 if (sem->semantic == TGSI_SEMANTIC_COLOR ||
2238 sem->semantic == TGSI_SEMANTIC_BCOLOR) {
2239 shader->color_inputs |= (1 << shader->num_inputs);
2240 }
2241
2242 shader->input_semantics[shader->num_inputs] = *sem;
2243 shader->num_inputs++;
2244 }
2245 } else {
2246 shader->num_inputs = c->num_inputs;
2247
2248 shader->vattr_offsets[0] = 0;
2249 for (int i = 0; i < 8; i++) {
2250 shader->vattr_offsets[i + 1] =
2251 shader->vattr_offsets[i] + c->vattr_sizes[i];
2252
2253 if (c->vattr_sizes[i])
2254 shader->vattrs_live |= (1 << i);
2255 }
2256 }
2257
2258 copy_uniform_state_to_shader(shader, c);
2259 shader->bo = vc4_bo_alloc_mem(vc4->screen, c->qpu_insts,
2260 c->qpu_inst_count * sizeof(uint64_t),
2261 "code");
2262
2263 /* Copy the compiler UBO range state to the compiled shader, dropping
2264 * out arrays that were never referenced by an indirect load.
2265 *
2266 * (Note that QIR dead code elimination of an array access still
2267 * leaves that array alive, though)
2268 */
2269 if (c->num_ubo_ranges) {
2270 shader->num_ubo_ranges = c->num_ubo_ranges;
2271 shader->ubo_ranges = ralloc_array(shader, struct vc4_ubo_range,
2272 c->num_ubo_ranges);
2273 uint32_t j = 0;
2274 for (int i = 0; i < c->ubo_ranges_array_size; i++) {
2275 struct vc4_compiler_ubo_range *range =
2276 &c->ubo_ranges[i];
2277 if (!range->used)
2278 continue;
2279
2280 shader->ubo_ranges[j].dst_offset = range->dst_offset;
2281 shader->ubo_ranges[j].src_offset = range->src_offset;
2282 shader->ubo_ranges[j].size = range->size;
2283 shader->ubo_size += c->ubo_ranges[i].size;
2284 j++;
2285 }
2286 }
2287
2288 qir_compile_destroy(c);
2289
2290 struct vc4_key *dup_key;
2291 dup_key = ralloc_size(shader, key_size);
2292 memcpy(dup_key, key, key_size);
2293 _mesa_hash_table_insert(ht, dup_key, shader);
2294
2295 return shader;
2296 }
2297
2298 static void
2299 vc4_setup_shared_key(struct vc4_context *vc4, struct vc4_key *key,
2300 struct vc4_texture_stateobj *texstate)
2301 {
2302 for (int i = 0; i < texstate->num_textures; i++) {
2303 struct pipe_sampler_view *sampler = texstate->textures[i];
2304 struct pipe_sampler_state *sampler_state =
2305 texstate->samplers[i];
2306
2307 if (sampler) {
2308 key->tex[i].format = sampler->format;
2309 key->tex[i].swizzle[0] = sampler->swizzle_r;
2310 key->tex[i].swizzle[1] = sampler->swizzle_g;
2311 key->tex[i].swizzle[2] = sampler->swizzle_b;
2312 key->tex[i].swizzle[3] = sampler->swizzle_a;
2313 key->tex[i].compare_mode = sampler_state->compare_mode;
2314 key->tex[i].compare_func = sampler_state->compare_func;
2315 key->tex[i].wrap_s = sampler_state->wrap_s;
2316 key->tex[i].wrap_t = sampler_state->wrap_t;
2317 }
2318 }
2319
2320 key->ucp_enables = vc4->rasterizer->base.clip_plane_enable;
2321 }
2322
2323 static void
2324 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
2325 {
2326 struct vc4_fs_key local_key;
2327 struct vc4_fs_key *key = &local_key;
2328
2329 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2330 VC4_DIRTY_BLEND |
2331 VC4_DIRTY_FRAMEBUFFER |
2332 VC4_DIRTY_ZSA |
2333 VC4_DIRTY_RASTERIZER |
2334 VC4_DIRTY_FRAGTEX |
2335 VC4_DIRTY_TEXSTATE |
2336 VC4_DIRTY_UNCOMPILED_FS))) {
2337 return;
2338 }
2339
2340 memset(key, 0, sizeof(*key));
2341 vc4_setup_shared_key(vc4, &key->base, &vc4->fragtex);
2342 key->base.shader_state = vc4->prog.bind_fs;
2343 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
2344 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
2345 prim_mode <= PIPE_PRIM_LINE_STRIP);
2346 key->blend = vc4->blend->rt[0];
2347 if (vc4->blend->logicop_enable) {
2348 key->logicop_func = vc4->blend->logicop_func;
2349 } else {
2350 key->logicop_func = PIPE_LOGICOP_COPY;
2351 }
2352 if (vc4->framebuffer.cbufs[0])
2353 key->color_format = vc4->framebuffer.cbufs[0]->format;
2354
2355 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
2356 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
2357 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
2358 key->depth_enabled = (vc4->zsa->base.depth.enabled ||
2359 key->stencil_enabled);
2360 if (vc4->zsa->base.alpha.enabled) {
2361 key->alpha_test = true;
2362 key->alpha_test_func = vc4->zsa->base.alpha.func;
2363 }
2364
2365 if (key->is_points) {
2366 key->point_sprite_mask =
2367 vc4->rasterizer->base.sprite_coord_enable;
2368 key->point_coord_upper_left =
2369 (vc4->rasterizer->base.sprite_coord_mode ==
2370 PIPE_SPRITE_COORD_UPPER_LEFT);
2371 }
2372
2373 key->light_twoside = vc4->rasterizer->base.light_twoside;
2374
2375 struct vc4_compiled_shader *old_fs = vc4->prog.fs;
2376 vc4->prog.fs = vc4_get_compiled_shader(vc4, QSTAGE_FRAG, &key->base);
2377 if (vc4->prog.fs == old_fs)
2378 return;
2379
2380 vc4->dirty |= VC4_DIRTY_COMPILED_FS;
2381 if (vc4->rasterizer->base.flatshade &&
2382 old_fs && vc4->prog.fs->color_inputs != old_fs->color_inputs) {
2383 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
2384 }
2385 }
2386
2387 static void
2388 vc4_update_compiled_vs(struct vc4_context *vc4, uint8_t prim_mode)
2389 {
2390 struct vc4_vs_key local_key;
2391 struct vc4_vs_key *key = &local_key;
2392
2393 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2394 VC4_DIRTY_RASTERIZER |
2395 VC4_DIRTY_VERTTEX |
2396 VC4_DIRTY_TEXSTATE |
2397 VC4_DIRTY_VTXSTATE |
2398 VC4_DIRTY_UNCOMPILED_VS |
2399 VC4_DIRTY_COMPILED_FS))) {
2400 return;
2401 }
2402
2403 memset(key, 0, sizeof(*key));
2404 vc4_setup_shared_key(vc4, &key->base, &vc4->verttex);
2405 key->base.shader_state = vc4->prog.bind_vs;
2406 key->compiled_fs_id = vc4->prog.fs->program_id;
2407
2408 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
2409 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
2410
2411 key->per_vertex_point_size =
2412 (prim_mode == PIPE_PRIM_POINTS &&
2413 vc4->rasterizer->base.point_size_per_vertex);
2414
2415 vc4->prog.vs = vc4_get_compiled_shader(vc4, QSTAGE_VERT, &key->base);
2416 key->is_coord = true;
2417 vc4->prog.cs = vc4_get_compiled_shader(vc4, QSTAGE_COORD, &key->base);
2418 }
2419
2420 void
2421 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
2422 {
2423 vc4_update_compiled_fs(vc4, prim_mode);
2424 vc4_update_compiled_vs(vc4, prim_mode);
2425 }
2426
2427 static uint32_t
2428 fs_cache_hash(const void *key)
2429 {
2430 return _mesa_hash_data(key, sizeof(struct vc4_fs_key));
2431 }
2432
2433 static uint32_t
2434 vs_cache_hash(const void *key)
2435 {
2436 return _mesa_hash_data(key, sizeof(struct vc4_vs_key));
2437 }
2438
2439 static bool
2440 fs_cache_compare(const void *key1, const void *key2)
2441 {
2442 return memcmp(key1, key2, sizeof(struct vc4_fs_key)) == 0;
2443 }
2444
2445 static bool
2446 vs_cache_compare(const void *key1, const void *key2)
2447 {
2448 return memcmp(key1, key2, sizeof(struct vc4_vs_key)) == 0;
2449 }
2450
2451 static void
2452 delete_from_cache_if_matches(struct hash_table *ht,
2453 struct hash_entry *entry,
2454 struct vc4_uncompiled_shader *so)
2455 {
2456 const struct vc4_key *key = entry->key;
2457
2458 if (key->shader_state == so) {
2459 struct vc4_compiled_shader *shader = entry->data;
2460 _mesa_hash_table_remove(ht, entry);
2461 vc4_bo_unreference(&shader->bo);
2462 ralloc_free(shader);
2463 }
2464 }
2465
2466 static void
2467 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
2468 {
2469 struct vc4_context *vc4 = vc4_context(pctx);
2470 struct vc4_uncompiled_shader *so = hwcso;
2471
2472 struct hash_entry *entry;
2473 hash_table_foreach(vc4->fs_cache, entry)
2474 delete_from_cache_if_matches(vc4->fs_cache, entry, so);
2475 hash_table_foreach(vc4->vs_cache, entry)
2476 delete_from_cache_if_matches(vc4->vs_cache, entry, so);
2477
2478 if (so->twoside_tokens != so->base.tokens)
2479 free((void *)so->twoside_tokens);
2480 free((void *)so->base.tokens);
2481 free(so);
2482 }
2483
2484 static uint32_t translate_wrap(uint32_t p_wrap, bool using_nearest)
2485 {
2486 switch (p_wrap) {
2487 case PIPE_TEX_WRAP_REPEAT:
2488 return 0;
2489 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
2490 return 1;
2491 case PIPE_TEX_WRAP_MIRROR_REPEAT:
2492 return 2;
2493 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
2494 return 3;
2495 case PIPE_TEX_WRAP_CLAMP:
2496 return (using_nearest ? 1 : 3);
2497 default:
2498 fprintf(stderr, "Unknown wrap mode %d\n", p_wrap);
2499 assert(!"not reached");
2500 return 0;
2501 }
2502 }
2503
2504 static void
2505 write_texture_p0(struct vc4_context *vc4,
2506 struct vc4_texture_stateobj *texstate,
2507 uint32_t unit)
2508 {
2509 struct pipe_sampler_view *texture = texstate->textures[unit];
2510 struct vc4_resource *rsc = vc4_resource(texture->texture);
2511
2512 cl_reloc(vc4, &vc4->uniforms, rsc->bo,
2513 VC4_SET_FIELD(rsc->slices[0].offset >> 12, VC4_TEX_P0_OFFSET) |
2514 VC4_SET_FIELD(texture->u.tex.last_level -
2515 texture->u.tex.first_level, VC4_TEX_P0_MIPLVLS) |
2516 VC4_SET_FIELD(texture->target == PIPE_TEXTURE_CUBE,
2517 VC4_TEX_P0_CMMODE) |
2518 VC4_SET_FIELD(rsc->vc4_format & 15, VC4_TEX_P0_TYPE));
2519 }
2520
2521 static void
2522 write_texture_p1(struct vc4_context *vc4,
2523 struct vc4_texture_stateobj *texstate,
2524 uint32_t unit)
2525 {
2526 struct pipe_sampler_view *texture = texstate->textures[unit];
2527 struct vc4_resource *rsc = vc4_resource(texture->texture);
2528 struct pipe_sampler_state *sampler = texstate->samplers[unit];
2529 static const uint8_t minfilter_map[6] = {
2530 VC4_TEX_P1_MINFILT_NEAR_MIP_NEAR,
2531 VC4_TEX_P1_MINFILT_LIN_MIP_NEAR,
2532 VC4_TEX_P1_MINFILT_NEAR_MIP_LIN,
2533 VC4_TEX_P1_MINFILT_LIN_MIP_LIN,
2534 VC4_TEX_P1_MINFILT_NEAREST,
2535 VC4_TEX_P1_MINFILT_LINEAR,
2536 };
2537 static const uint32_t magfilter_map[] = {
2538 [PIPE_TEX_FILTER_NEAREST] = VC4_TEX_P1_MAGFILT_NEAREST,
2539 [PIPE_TEX_FILTER_LINEAR] = VC4_TEX_P1_MAGFILT_LINEAR,
2540 };
2541
2542 bool either_nearest =
2543 (sampler->mag_img_filter == PIPE_TEX_MIPFILTER_NEAREST ||
2544 sampler->min_img_filter == PIPE_TEX_MIPFILTER_NEAREST);
2545
2546 cl_aligned_u32(&vc4->uniforms,
2547 VC4_SET_FIELD(rsc->vc4_format >> 4, VC4_TEX_P1_TYPE4) |
2548 VC4_SET_FIELD(texture->texture->height0 & 2047,
2549 VC4_TEX_P1_HEIGHT) |
2550 VC4_SET_FIELD(texture->texture->width0 & 2047,
2551 VC4_TEX_P1_WIDTH) |
2552 VC4_SET_FIELD(magfilter_map[sampler->mag_img_filter],
2553 VC4_TEX_P1_MAGFILT) |
2554 VC4_SET_FIELD(minfilter_map[sampler->min_mip_filter * 2 +
2555 sampler->min_img_filter],
2556 VC4_TEX_P1_MINFILT) |
2557 VC4_SET_FIELD(translate_wrap(sampler->wrap_s, either_nearest),
2558 VC4_TEX_P1_WRAP_S) |
2559 VC4_SET_FIELD(translate_wrap(sampler->wrap_t, either_nearest),
2560 VC4_TEX_P1_WRAP_T));
2561 }
2562
2563 static void
2564 write_texture_p2(struct vc4_context *vc4,
2565 struct vc4_texture_stateobj *texstate,
2566 uint32_t data)
2567 {
2568 uint32_t unit = data & 0xffff;
2569 struct pipe_sampler_view *texture = texstate->textures[unit];
2570 struct vc4_resource *rsc = vc4_resource(texture->texture);
2571
2572 cl_aligned_u32(&vc4->uniforms,
2573 VC4_SET_FIELD(VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE,
2574 VC4_TEX_P2_PTYPE) |
2575 VC4_SET_FIELD(rsc->cube_map_stride >> 12, VC4_TEX_P2_CMST) |
2576 VC4_SET_FIELD((data >> 16) & 1, VC4_TEX_P2_BSLOD));
2577 }
2578
2579
2580 #define SWIZ(x,y,z,w) { \
2581 UTIL_FORMAT_SWIZZLE_##x, \
2582 UTIL_FORMAT_SWIZZLE_##y, \
2583 UTIL_FORMAT_SWIZZLE_##z, \
2584 UTIL_FORMAT_SWIZZLE_##w \
2585 }
2586
2587 static void
2588 write_texture_border_color(struct vc4_context *vc4,
2589 struct vc4_texture_stateobj *texstate,
2590 uint32_t unit)
2591 {
2592 struct pipe_sampler_state *sampler = texstate->samplers[unit];
2593 struct pipe_sampler_view *texture = texstate->textures[unit];
2594 struct vc4_resource *rsc = vc4_resource(texture->texture);
2595 union util_color uc;
2596
2597 const struct util_format_description *tex_format_desc =
2598 util_format_description(texture->format);
2599
2600 float border_color[4];
2601 for (int i = 0; i < 4; i++)
2602 border_color[i] = sampler->border_color.f[i];
2603 if (util_format_is_srgb(texture->format)) {
2604 for (int i = 0; i < 3; i++)
2605 border_color[i] =
2606 util_format_linear_to_srgb_float(border_color[i]);
2607 }
2608
2609 /* Turn the border color into the layout of channels that it would
2610 * have when stored as texture contents.
2611 */
2612 float storage_color[4];
2613 util_format_unswizzle_4f(storage_color,
2614 border_color,
2615 tex_format_desc->swizzle);
2616
2617 /* Now, pack so that when the vc4_format-sampled texture contents are
2618 * replaced with our border color, the vc4_get_format_swizzle()
2619 * swizzling will get the right channels.
2620 */
2621 if (util_format_is_depth_or_stencil(texture->format)) {
2622 uc.ui[0] = util_pack_z(PIPE_FORMAT_Z24X8_UNORM,
2623 sampler->border_color.f[0]) << 8;
2624 } else {
2625 switch (rsc->vc4_format) {
2626 default:
2627 case VC4_TEXTURE_TYPE_RGBA8888:
2628 util_pack_color(storage_color,
2629 PIPE_FORMAT_R8G8B8A8_UNORM, &uc);
2630 break;
2631 case VC4_TEXTURE_TYPE_RGBA4444:
2632 util_pack_color(storage_color,
2633 PIPE_FORMAT_A8B8G8R8_UNORM, &uc);
2634 break;
2635 case VC4_TEXTURE_TYPE_RGB565:
2636 util_pack_color(storage_color,
2637 PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
2638 break;
2639 case VC4_TEXTURE_TYPE_ALPHA:
2640 uc.ui[0] = float_to_ubyte(storage_color[0]) << 24;
2641 break;
2642 case VC4_TEXTURE_TYPE_LUMALPHA:
2643 uc.ui[0] = ((float_to_ubyte(storage_color[1]) << 24) |
2644 (float_to_ubyte(storage_color[0]) << 0));
2645 break;
2646 }
2647 }
2648
2649 cl_aligned_u32(&vc4->uniforms, uc.ui[0]);
2650 }
2651
2652 static uint32_t
2653 get_texrect_scale(struct vc4_texture_stateobj *texstate,
2654 enum quniform_contents contents,
2655 uint32_t data)
2656 {
2657 struct pipe_sampler_view *texture = texstate->textures[data];
2658 uint32_t dim;
2659
2660 if (contents == QUNIFORM_TEXRECT_SCALE_X)
2661 dim = texture->texture->width0;
2662 else
2663 dim = texture->texture->height0;
2664
2665 return fui(1.0f / dim);
2666 }
2667
2668 static struct vc4_bo *
2669 vc4_upload_ubo(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
2670 const uint32_t *gallium_uniforms)
2671 {
2672 if (!shader->ubo_size)
2673 return NULL;
2674
2675 struct vc4_bo *ubo = vc4_bo_alloc(vc4->screen, shader->ubo_size, "ubo");
2676 uint32_t *data = vc4_bo_map(ubo);
2677 for (uint32_t i = 0; i < shader->num_ubo_ranges; i++) {
2678 memcpy(data + shader->ubo_ranges[i].dst_offset,
2679 gallium_uniforms + shader->ubo_ranges[i].src_offset,
2680 shader->ubo_ranges[i].size);
2681 }
2682
2683 return ubo;
2684 }
2685
2686 void
2687 vc4_write_uniforms(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
2688 struct vc4_constbuf_stateobj *cb,
2689 struct vc4_texture_stateobj *texstate)
2690 {
2691 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
2692 const uint32_t *gallium_uniforms = cb->cb[0].user_buffer;
2693 struct vc4_bo *ubo = vc4_upload_ubo(vc4, shader, gallium_uniforms);
2694
2695 cl_ensure_space(&vc4->uniforms, (uinfo->count +
2696 uinfo->num_texture_samples) * 4);
2697
2698 cl_start_shader_reloc(&vc4->uniforms, uinfo->num_texture_samples);
2699
2700 for (int i = 0; i < uinfo->count; i++) {
2701
2702 switch (uinfo->contents[i]) {
2703 case QUNIFORM_CONSTANT:
2704 cl_aligned_u32(&vc4->uniforms, uinfo->data[i]);
2705 break;
2706 case QUNIFORM_UNIFORM:
2707 cl_aligned_u32(&vc4->uniforms,
2708 gallium_uniforms[uinfo->data[i]]);
2709 break;
2710 case QUNIFORM_VIEWPORT_X_SCALE:
2711 cl_aligned_f(&vc4->uniforms, vc4->viewport.scale[0] * 16.0f);
2712 break;
2713 case QUNIFORM_VIEWPORT_Y_SCALE:
2714 cl_aligned_f(&vc4->uniforms, vc4->viewport.scale[1] * 16.0f);
2715 break;
2716
2717 case QUNIFORM_VIEWPORT_Z_OFFSET:
2718 cl_aligned_f(&vc4->uniforms, vc4->viewport.translate[2]);
2719 break;
2720 case QUNIFORM_VIEWPORT_Z_SCALE:
2721 cl_aligned_f(&vc4->uniforms, vc4->viewport.scale[2]);
2722 break;
2723
2724 case QUNIFORM_USER_CLIP_PLANE:
2725 cl_aligned_f(&vc4->uniforms,
2726 vc4->clip.ucp[uinfo->data[i] / 4][uinfo->data[i] % 4]);
2727 break;
2728
2729 case QUNIFORM_TEXTURE_CONFIG_P0:
2730 write_texture_p0(vc4, texstate, uinfo->data[i]);
2731 break;
2732
2733 case QUNIFORM_TEXTURE_CONFIG_P1:
2734 write_texture_p1(vc4, texstate, uinfo->data[i]);
2735 break;
2736
2737 case QUNIFORM_TEXTURE_CONFIG_P2:
2738 write_texture_p2(vc4, texstate, uinfo->data[i]);
2739 break;
2740
2741 case QUNIFORM_UBO_ADDR:
2742 cl_aligned_reloc(vc4, &vc4->uniforms, ubo, 0);
2743 break;
2744
2745 case QUNIFORM_TEXTURE_BORDER_COLOR:
2746 write_texture_border_color(vc4, texstate, uinfo->data[i]);
2747 break;
2748
2749 case QUNIFORM_TEXRECT_SCALE_X:
2750 case QUNIFORM_TEXRECT_SCALE_Y:
2751 cl_aligned_u32(&vc4->uniforms,
2752 get_texrect_scale(texstate,
2753 uinfo->contents[i],
2754 uinfo->data[i]));
2755 break;
2756
2757 case QUNIFORM_BLEND_CONST_COLOR:
2758 cl_aligned_f(&vc4->uniforms,
2759 CLAMP(vc4->blend_color.color[uinfo->data[i]], 0, 1));
2760 break;
2761
2762 case QUNIFORM_STENCIL:
2763 cl_aligned_u32(&vc4->uniforms,
2764 vc4->zsa->stencil_uniforms[uinfo->data[i]] |
2765 (uinfo->data[i] <= 1 ?
2766 (vc4->stencil_ref.ref_value[uinfo->data[i]] << 8) :
2767 0));
2768 break;
2769
2770 case QUNIFORM_ALPHA_REF:
2771 cl_aligned_f(&vc4->uniforms,
2772 vc4->zsa->base.alpha.ref_value);
2773 break;
2774 }
2775 #if 0
2776 uint32_t written_val = *(uint32_t *)(vc4->uniforms.next - 4);
2777 fprintf(stderr, "%p: %d / 0x%08x (%f)\n",
2778 shader, i, written_val, uif(written_val));
2779 #endif
2780 }
2781 }
2782
2783 static void
2784 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
2785 {
2786 struct vc4_context *vc4 = vc4_context(pctx);
2787 vc4->prog.bind_fs = hwcso;
2788 vc4->dirty |= VC4_DIRTY_UNCOMPILED_FS;
2789 }
2790
2791 static void
2792 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
2793 {
2794 struct vc4_context *vc4 = vc4_context(pctx);
2795 vc4->prog.bind_vs = hwcso;
2796 vc4->dirty |= VC4_DIRTY_UNCOMPILED_VS;
2797 }
2798
2799 void
2800 vc4_program_init(struct pipe_context *pctx)
2801 {
2802 struct vc4_context *vc4 = vc4_context(pctx);
2803
2804 pctx->create_vs_state = vc4_shader_state_create;
2805 pctx->delete_vs_state = vc4_shader_state_delete;
2806
2807 pctx->create_fs_state = vc4_shader_state_create;
2808 pctx->delete_fs_state = vc4_shader_state_delete;
2809
2810 pctx->bind_fs_state = vc4_fp_state_bind;
2811 pctx->bind_vs_state = vc4_vp_state_bind;
2812
2813 vc4->fs_cache = _mesa_hash_table_create(pctx, fs_cache_hash,
2814 fs_cache_compare);
2815 vc4->vs_cache = _mesa_hash_table_create(pctx, vs_cache_hash,
2816 vs_cache_compare);
2817 }
2818
2819 void
2820 vc4_program_fini(struct pipe_context *pctx)
2821 {
2822 struct vc4_context *vc4 = vc4_context(pctx);
2823
2824 struct hash_entry *entry;
2825 hash_table_foreach(vc4->fs_cache, entry) {
2826 struct vc4_compiled_shader *shader = entry->data;
2827 vc4_bo_unreference(&shader->bo);
2828 ralloc_free(shader);
2829 _mesa_hash_table_remove(vc4->fs_cache, entry);
2830 }
2831
2832 hash_table_foreach(vc4->vs_cache, entry) {
2833 struct vc4_compiled_shader *shader = entry->data;
2834 vc4_bo_unreference(&shader->bo);
2835 ralloc_free(shader);
2836 _mesa_hash_table_remove(vc4->vs_cache, entry);
2837 }
2838 }