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vc4: Reuse uniform_data/contents indices when making uniforms.
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "pipe/p_state.h"
27 #include "util/u_format.h"
28 #include "util/u_hash_table.h"
29 #include "util/u_hash.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include "util/format_srgb.h"
33 #include "util/ralloc.h"
34 #include "util/hash_table.h"
35 #include "tgsi/tgsi_dump.h"
36 #include "tgsi/tgsi_info.h"
37 #include "tgsi/tgsi_lowering.h"
38
39 #include "vc4_context.h"
40 #include "vc4_qpu.h"
41 #include "vc4_qir.h"
42 #ifdef USE_VC4_SIMULATOR
43 #include "simpenrose/simpenrose.h"
44 #endif
45
46 struct vc4_key {
47 struct vc4_uncompiled_shader *shader_state;
48 struct {
49 enum pipe_format format;
50 unsigned compare_mode:1;
51 unsigned compare_func:3;
52 unsigned wrap_s:3;
53 unsigned wrap_t:3;
54 uint8_t swizzle[4];
55 } tex[VC4_MAX_TEXTURE_SAMPLERS];
56 uint8_t ucp_enables;
57 };
58
59 struct vc4_fs_key {
60 struct vc4_key base;
61 enum pipe_format color_format;
62 bool depth_enabled;
63 bool stencil_enabled;
64 bool stencil_twoside;
65 bool stencil_full_writemasks;
66 bool is_points;
67 bool is_lines;
68 bool alpha_test;
69 bool point_coord_upper_left;
70 bool light_twoside;
71 uint8_t alpha_test_func;
72 uint32_t point_sprite_mask;
73
74 struct pipe_rt_blend_state blend;
75 };
76
77 struct vc4_vs_key {
78 struct vc4_key base;
79
80 /**
81 * This is a proxy for the array of FS input semantics, which is
82 * larger than we would want to put in the key.
83 */
84 uint64_t compiled_fs_id;
85
86 enum pipe_format attr_formats[8];
87 bool is_coord;
88 bool per_vertex_point_size;
89 };
90
91 static void
92 resize_qreg_array(struct vc4_compile *c,
93 struct qreg **regs,
94 uint32_t *size,
95 uint32_t decl_size)
96 {
97 if (*size >= decl_size)
98 return;
99
100 uint32_t old_size = *size;
101 *size = MAX2(*size * 2, decl_size);
102 *regs = reralloc(c, *regs, struct qreg, *size);
103 if (!*regs) {
104 fprintf(stderr, "Malloc failure\n");
105 abort();
106 }
107
108 for (uint32_t i = old_size; i < *size; i++)
109 (*regs)[i] = c->undef;
110 }
111
112 static struct qreg
113 add_uniform(struct vc4_compile *c,
114 enum quniform_contents contents,
115 uint32_t data)
116 {
117 for (int i = 0; i < c->num_uniforms; i++) {
118 if (c->uniform_contents[i] == contents &&
119 c->uniform_data[i] == data) {
120 return (struct qreg) { QFILE_UNIF, i };
121 }
122 }
123
124 uint32_t uniform = c->num_uniforms++;
125 struct qreg u = { QFILE_UNIF, uniform };
126
127 if (uniform >= c->uniform_array_size) {
128 c->uniform_array_size = MAX2(MAX2(16, uniform + 1),
129 c->uniform_array_size * 2);
130
131 c->uniform_data = reralloc(c, c->uniform_data,
132 uint32_t,
133 c->uniform_array_size);
134 c->uniform_contents = reralloc(c, c->uniform_contents,
135 enum quniform_contents,
136 c->uniform_array_size);
137 }
138
139 c->uniform_contents[uniform] = contents;
140 c->uniform_data[uniform] = data;
141
142 return u;
143 }
144
145 static struct qreg
146 get_temp_for_uniform(struct vc4_compile *c, enum quniform_contents contents,
147 uint32_t data)
148 {
149 struct qreg u = add_uniform(c, contents, data);
150 struct qreg t = qir_MOV(c, u);
151 return t;
152 }
153
154 static struct qreg
155 qir_uniform_ui(struct vc4_compile *c, uint32_t ui)
156 {
157 return get_temp_for_uniform(c, QUNIFORM_CONSTANT, ui);
158 }
159
160 static struct qreg
161 qir_uniform_f(struct vc4_compile *c, float f)
162 {
163 return qir_uniform_ui(c, fui(f));
164 }
165
166 static struct qreg
167 get_src(struct vc4_compile *c, unsigned tgsi_op,
168 struct tgsi_src_register *src, int i)
169 {
170 struct qreg r = c->undef;
171
172 uint32_t s = i;
173 switch (i) {
174 case TGSI_SWIZZLE_X:
175 s = src->SwizzleX;
176 break;
177 case TGSI_SWIZZLE_Y:
178 s = src->SwizzleY;
179 break;
180 case TGSI_SWIZZLE_Z:
181 s = src->SwizzleZ;
182 break;
183 case TGSI_SWIZZLE_W:
184 s = src->SwizzleW;
185 break;
186 default:
187 abort();
188 }
189
190 assert(!src->Indirect);
191
192 switch (src->File) {
193 case TGSI_FILE_NULL:
194 return r;
195 case TGSI_FILE_TEMPORARY:
196 r = c->temps[src->Index * 4 + s];
197 break;
198 case TGSI_FILE_IMMEDIATE:
199 r = c->consts[src->Index * 4 + s];
200 break;
201 case TGSI_FILE_CONSTANT:
202 r = get_temp_for_uniform(c, QUNIFORM_UNIFORM,
203 src->Index * 4 + s);
204 break;
205 case TGSI_FILE_INPUT:
206 r = c->inputs[src->Index * 4 + s];
207 break;
208 case TGSI_FILE_SAMPLER:
209 case TGSI_FILE_SAMPLER_VIEW:
210 r = c->undef;
211 break;
212 default:
213 fprintf(stderr, "unknown src file %d\n", src->File);
214 abort();
215 }
216
217 if (src->Absolute)
218 r = qir_FMAXABS(c, r, r);
219
220 if (src->Negate) {
221 switch (tgsi_opcode_infer_src_type(tgsi_op)) {
222 case TGSI_TYPE_SIGNED:
223 case TGSI_TYPE_UNSIGNED:
224 r = qir_SUB(c, qir_uniform_ui(c, 0), r);
225 break;
226 default:
227 r = qir_FSUB(c, qir_uniform_f(c, 0.0), r);
228 break;
229 }
230 }
231
232 return r;
233 };
234
235
236 static void
237 update_dst(struct vc4_compile *c, struct tgsi_full_instruction *tgsi_inst,
238 int i, struct qreg val)
239 {
240 struct tgsi_dst_register *tgsi_dst = &tgsi_inst->Dst[0].Register;
241
242 assert(!tgsi_dst->Indirect);
243
244 switch (tgsi_dst->File) {
245 case TGSI_FILE_TEMPORARY:
246 c->temps[tgsi_dst->Index * 4 + i] = val;
247 break;
248 case TGSI_FILE_OUTPUT:
249 c->outputs[tgsi_dst->Index * 4 + i] = val;
250 c->num_outputs = MAX2(c->num_outputs,
251 tgsi_dst->Index * 4 + i + 1);
252 break;
253 default:
254 fprintf(stderr, "unknown dst file %d\n", tgsi_dst->File);
255 abort();
256 }
257 };
258
259 static struct qreg
260 get_swizzled_channel(struct vc4_compile *c,
261 struct qreg *srcs, int swiz)
262 {
263 switch (swiz) {
264 default:
265 case UTIL_FORMAT_SWIZZLE_NONE:
266 fprintf(stderr, "warning: unknown swizzle\n");
267 /* FALLTHROUGH */
268 case UTIL_FORMAT_SWIZZLE_0:
269 return qir_uniform_f(c, 0.0);
270 case UTIL_FORMAT_SWIZZLE_1:
271 return qir_uniform_f(c, 1.0);
272 case UTIL_FORMAT_SWIZZLE_X:
273 case UTIL_FORMAT_SWIZZLE_Y:
274 case UTIL_FORMAT_SWIZZLE_Z:
275 case UTIL_FORMAT_SWIZZLE_W:
276 return srcs[swiz];
277 }
278 }
279
280 static struct qreg
281 tgsi_to_qir_alu(struct vc4_compile *c,
282 struct tgsi_full_instruction *tgsi_inst,
283 enum qop op, struct qreg *src, int i)
284 {
285 struct qreg dst = qir_get_temp(c);
286 qir_emit(c, qir_inst4(op, dst,
287 src[0 * 4 + i],
288 src[1 * 4 + i],
289 src[2 * 4 + i],
290 c->undef));
291 return dst;
292 }
293
294 static struct qreg
295 tgsi_to_qir_scalar(struct vc4_compile *c,
296 struct tgsi_full_instruction *tgsi_inst,
297 enum qop op, struct qreg *src, int i)
298 {
299 struct qreg dst = qir_get_temp(c);
300 qir_emit(c, qir_inst(op, dst,
301 src[0 * 4 + 0],
302 c->undef));
303 return dst;
304 }
305
306 static struct qreg
307 tgsi_to_qir_rcp(struct vc4_compile *c,
308 struct tgsi_full_instruction *tgsi_inst,
309 enum qop op, struct qreg *src, int i)
310 {
311 struct qreg x = src[0 * 4 + 0];
312 struct qreg r = qir_RCP(c, x);
313
314 /* Apply a Newton-Raphson step to improve the accuracy. */
315 r = qir_FMUL(c, r, qir_FSUB(c,
316 qir_uniform_f(c, 2.0),
317 qir_FMUL(c, x, r)));
318
319 return r;
320 }
321
322 static struct qreg
323 tgsi_to_qir_rsq(struct vc4_compile *c,
324 struct tgsi_full_instruction *tgsi_inst,
325 enum qop op, struct qreg *src, int i)
326 {
327 struct qreg x = src[0 * 4 + 0];
328 struct qreg r = qir_RSQ(c, x);
329
330 /* Apply a Newton-Raphson step to improve the accuracy. */
331 r = qir_FMUL(c, r, qir_FSUB(c,
332 qir_uniform_f(c, 1.5),
333 qir_FMUL(c,
334 qir_uniform_f(c, 0.5),
335 qir_FMUL(c, x,
336 qir_FMUL(c, r, r)))));
337
338 return r;
339 }
340
341 static struct qreg
342 qir_srgb_decode(struct vc4_compile *c, struct qreg srgb)
343 {
344 struct qreg low = qir_FMUL(c, srgb, qir_uniform_f(c, 1.0 / 12.92));
345 struct qreg high = qir_POW(c,
346 qir_FMUL(c,
347 qir_FADD(c,
348 srgb,
349 qir_uniform_f(c, 0.055)),
350 qir_uniform_f(c, 1.0 / 1.055)),
351 qir_uniform_f(c, 2.4));
352
353 qir_SF(c, qir_FSUB(c, srgb, qir_uniform_f(c, 0.04045)));
354 return qir_SEL_X_Y_NS(c, low, high);
355 }
356
357 static struct qreg
358 qir_srgb_encode(struct vc4_compile *c, struct qreg linear)
359 {
360 struct qreg low = qir_FMUL(c, linear, qir_uniform_f(c, 12.92));
361 struct qreg high = qir_FSUB(c,
362 qir_FMUL(c,
363 qir_uniform_f(c, 1.055),
364 qir_POW(c,
365 linear,
366 qir_uniform_f(c, 0.41666))),
367 qir_uniform_f(c, 0.055));
368
369 qir_SF(c, qir_FSUB(c, linear, qir_uniform_f(c, 0.0031308)));
370 return qir_SEL_X_Y_NS(c, low, high);
371 }
372
373 static struct qreg
374 tgsi_to_qir_umul(struct vc4_compile *c,
375 struct tgsi_full_instruction *tgsi_inst,
376 enum qop op, struct qreg *src, int i)
377 {
378 struct qreg src0_hi = qir_SHR(c, src[0 * 4 + i],
379 qir_uniform_ui(c, 16));
380 struct qreg src0_lo = qir_AND(c, src[0 * 4 + i],
381 qir_uniform_ui(c, 0xffff));
382 struct qreg src1_hi = qir_SHR(c, src[1 * 4 + i],
383 qir_uniform_ui(c, 16));
384 struct qreg src1_lo = qir_AND(c, src[1 * 4 + i],
385 qir_uniform_ui(c, 0xffff));
386
387 struct qreg hilo = qir_MUL24(c, src0_hi, src1_lo);
388 struct qreg lohi = qir_MUL24(c, src0_lo, src1_hi);
389 struct qreg lolo = qir_MUL24(c, src0_lo, src1_lo);
390
391 return qir_ADD(c, lolo, qir_SHL(c,
392 qir_ADD(c, hilo, lohi),
393 qir_uniform_ui(c, 16)));
394 }
395
396 static struct qreg
397 tgsi_to_qir_idiv(struct vc4_compile *c,
398 struct tgsi_full_instruction *tgsi_inst,
399 enum qop op, struct qreg *src, int i)
400 {
401 return qir_FTOI(c, qir_FMUL(c,
402 qir_ITOF(c, src[0 * 4 + i]),
403 qir_RCP(c, qir_ITOF(c, src[1 * 4 + i]))));
404 }
405
406 static struct qreg
407 tgsi_to_qir_ineg(struct vc4_compile *c,
408 struct tgsi_full_instruction *tgsi_inst,
409 enum qop op, struct qreg *src, int i)
410 {
411 return qir_SUB(c, qir_uniform_ui(c, 0), src[0 * 4 + i]);
412 }
413
414 static struct qreg
415 tgsi_to_qir_seq(struct vc4_compile *c,
416 struct tgsi_full_instruction *tgsi_inst,
417 enum qop op, struct qreg *src, int i)
418 {
419 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
420 return qir_SEL_X_0_ZS(c, qir_uniform_f(c, 1.0));
421 }
422
423 static struct qreg
424 tgsi_to_qir_sne(struct vc4_compile *c,
425 struct tgsi_full_instruction *tgsi_inst,
426 enum qop op, struct qreg *src, int i)
427 {
428 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
429 return qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0));
430 }
431
432 static struct qreg
433 tgsi_to_qir_slt(struct vc4_compile *c,
434 struct tgsi_full_instruction *tgsi_inst,
435 enum qop op, struct qreg *src, int i)
436 {
437 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
438 return qir_SEL_X_0_NS(c, qir_uniform_f(c, 1.0));
439 }
440
441 static struct qreg
442 tgsi_to_qir_sge(struct vc4_compile *c,
443 struct tgsi_full_instruction *tgsi_inst,
444 enum qop op, struct qreg *src, int i)
445 {
446 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
447 return qir_SEL_X_0_NC(c, qir_uniform_f(c, 1.0));
448 }
449
450 static struct qreg
451 tgsi_to_qir_fseq(struct vc4_compile *c,
452 struct tgsi_full_instruction *tgsi_inst,
453 enum qop op, struct qreg *src, int i)
454 {
455 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
456 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
457 }
458
459 static struct qreg
460 tgsi_to_qir_fsne(struct vc4_compile *c,
461 struct tgsi_full_instruction *tgsi_inst,
462 enum qop op, struct qreg *src, int i)
463 {
464 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
465 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
466 }
467
468 static struct qreg
469 tgsi_to_qir_fslt(struct vc4_compile *c,
470 struct tgsi_full_instruction *tgsi_inst,
471 enum qop op, struct qreg *src, int i)
472 {
473 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
474 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
475 }
476
477 static struct qreg
478 tgsi_to_qir_fsge(struct vc4_compile *c,
479 struct tgsi_full_instruction *tgsi_inst,
480 enum qop op, struct qreg *src, int i)
481 {
482 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
483 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
484 }
485
486 static struct qreg
487 tgsi_to_qir_useq(struct vc4_compile *c,
488 struct tgsi_full_instruction *tgsi_inst,
489 enum qop op, struct qreg *src, int i)
490 {
491 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
492 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
493 }
494
495 static struct qreg
496 tgsi_to_qir_usne(struct vc4_compile *c,
497 struct tgsi_full_instruction *tgsi_inst,
498 enum qop op, struct qreg *src, int i)
499 {
500 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
501 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
502 }
503
504 static struct qreg
505 tgsi_to_qir_islt(struct vc4_compile *c,
506 struct tgsi_full_instruction *tgsi_inst,
507 enum qop op, struct qreg *src, int i)
508 {
509 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
510 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
511 }
512
513 static struct qreg
514 tgsi_to_qir_isge(struct vc4_compile *c,
515 struct tgsi_full_instruction *tgsi_inst,
516 enum qop op, struct qreg *src, int i)
517 {
518 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
519 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
520 }
521
522 static struct qreg
523 tgsi_to_qir_cmp(struct vc4_compile *c,
524 struct tgsi_full_instruction *tgsi_inst,
525 enum qop op, struct qreg *src, int i)
526 {
527 qir_SF(c, src[0 * 4 + i]);
528 return qir_SEL_X_Y_NS(c,
529 src[1 * 4 + i],
530 src[2 * 4 + i]);
531 }
532
533 static struct qreg
534 tgsi_to_qir_mad(struct vc4_compile *c,
535 struct tgsi_full_instruction *tgsi_inst,
536 enum qop op, struct qreg *src, int i)
537 {
538 return qir_FADD(c,
539 qir_FMUL(c,
540 src[0 * 4 + i],
541 src[1 * 4 + i]),
542 src[2 * 4 + i]);
543 }
544
545 static struct qreg
546 tgsi_to_qir_lrp(struct vc4_compile *c,
547 struct tgsi_full_instruction *tgsi_inst,
548 enum qop op, struct qreg *src, int i)
549 {
550 struct qreg src0 = src[0 * 4 + i];
551 struct qreg src1 = src[1 * 4 + i];
552 struct qreg src2 = src[2 * 4 + i];
553
554 /* LRP is:
555 * src0 * src1 + (1 - src0) * src2.
556 * -> src0 * src1 + src2 - src0 * src2
557 * -> src2 + src0 * (src1 - src2)
558 */
559 return qir_FADD(c, src2, qir_FMUL(c, src0, qir_FSUB(c, src1, src2)));
560
561 }
562
563 static void
564 tgsi_to_qir_tex(struct vc4_compile *c,
565 struct tgsi_full_instruction *tgsi_inst,
566 enum qop op, struct qreg *src)
567 {
568 assert(!tgsi_inst->Instruction.Saturate);
569
570 struct qreg s = src[0 * 4 + 0];
571 struct qreg t = src[0 * 4 + 1];
572 struct qreg r = src[0 * 4 + 2];
573 uint32_t unit = tgsi_inst->Src[1].Register.Index;
574 bool is_txl = tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL;
575
576 struct qreg proj = c->undef;
577 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
578 proj = qir_RCP(c, src[0 * 4 + 3]);
579 s = qir_FMUL(c, s, proj);
580 t = qir_FMUL(c, t, proj);
581 }
582
583 struct qreg texture_u[] = {
584 add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit),
585 add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
586 add_uniform(c, QUNIFORM_CONSTANT, 0),
587 add_uniform(c, QUNIFORM_CONSTANT, 0),
588 };
589 uint32_t next_texture_u = 0;
590
591 /* There is no native support for GL texture rectangle coordinates, so
592 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
593 * 1]).
594 */
595 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_RECT ||
596 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT) {
597 s = qir_FMUL(c, s,
598 get_temp_for_uniform(c,
599 QUNIFORM_TEXRECT_SCALE_X,
600 unit));
601 t = qir_FMUL(c, t,
602 get_temp_for_uniform(c,
603 QUNIFORM_TEXRECT_SCALE_Y,
604 unit));
605 }
606
607 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
608 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
609 is_txl) {
610 texture_u[2] = add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P2,
611 unit | (is_txl << 16));
612 }
613
614 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
615 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE) {
616 struct qreg ma = qir_FMAXABS(c, qir_FMAXABS(c, s, t), r);
617 struct qreg rcp_ma = qir_RCP(c, ma);
618 s = qir_FMUL(c, s, rcp_ma);
619 t = qir_FMUL(c, t, rcp_ma);
620 r = qir_FMUL(c, r, rcp_ma);
621
622 qir_TEX_R(c, r, texture_u[next_texture_u++]);
623 } else if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
624 c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP ||
625 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
626 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
627 qir_TEX_R(c, get_temp_for_uniform(c, QUNIFORM_TEXTURE_BORDER_COLOR, unit),
628 texture_u[next_texture_u++]);
629 }
630
631 if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP) {
632 s = qir_FMIN(c, qir_FMAX(c, s, qir_uniform_f(c, 0.0)),
633 qir_uniform_f(c, 1.0));
634 }
635
636 if (c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
637 t = qir_FMIN(c, qir_FMAX(c, t, qir_uniform_f(c, 0.0)),
638 qir_uniform_f(c, 1.0));
639 }
640
641 qir_TEX_T(c, t, texture_u[next_texture_u++]);
642
643 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
644 tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL)
645 qir_TEX_B(c, src[0 * 4 + 3], texture_u[next_texture_u++]);
646
647 qir_TEX_S(c, s, texture_u[next_texture_u++]);
648
649 c->num_texture_samples++;
650 struct qreg r4 = qir_TEX_RESULT(c);
651
652 enum pipe_format format = c->key->tex[unit].format;
653
654 struct qreg unpacked[4];
655 if (util_format_is_depth_or_stencil(format)) {
656 struct qreg depthf = qir_ITOF(c, qir_SHR(c, r4,
657 qir_uniform_ui(c, 8)));
658 struct qreg normalized = qir_FMUL(c, depthf,
659 qir_uniform_f(c, 1.0f/0xffffff));
660
661 struct qreg depth_output;
662
663 struct qreg one = qir_uniform_f(c, 1.0f);
664 if (c->key->tex[unit].compare_mode) {
665 struct qreg compare = src[0 * 4 + 2];
666
667 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP)
668 compare = qir_FMUL(c, compare, proj);
669
670 switch (c->key->tex[unit].compare_func) {
671 case PIPE_FUNC_NEVER:
672 depth_output = qir_uniform_f(c, 0.0f);
673 break;
674 case PIPE_FUNC_ALWAYS:
675 depth_output = one;
676 break;
677 case PIPE_FUNC_EQUAL:
678 qir_SF(c, qir_FSUB(c, compare, normalized));
679 depth_output = qir_SEL_X_0_ZS(c, one);
680 break;
681 case PIPE_FUNC_NOTEQUAL:
682 qir_SF(c, qir_FSUB(c, compare, normalized));
683 depth_output = qir_SEL_X_0_ZC(c, one);
684 break;
685 case PIPE_FUNC_GREATER:
686 qir_SF(c, qir_FSUB(c, compare, normalized));
687 depth_output = qir_SEL_X_0_NC(c, one);
688 break;
689 case PIPE_FUNC_GEQUAL:
690 qir_SF(c, qir_FSUB(c, normalized, compare));
691 depth_output = qir_SEL_X_0_NS(c, one);
692 break;
693 case PIPE_FUNC_LESS:
694 qir_SF(c, qir_FSUB(c, compare, normalized));
695 depth_output = qir_SEL_X_0_NS(c, one);
696 break;
697 case PIPE_FUNC_LEQUAL:
698 qir_SF(c, qir_FSUB(c, normalized, compare));
699 depth_output = qir_SEL_X_0_NC(c, one);
700 break;
701 }
702 } else {
703 depth_output = normalized;
704 }
705
706 for (int i = 0; i < 4; i++)
707 unpacked[i] = depth_output;
708 } else {
709 for (int i = 0; i < 4; i++)
710 unpacked[i] = qir_R4_UNPACK(c, r4, i);
711 }
712
713 const uint8_t *format_swiz = vc4_get_format_swizzle(format);
714 struct qreg texture_output[4];
715 for (int i = 0; i < 4; i++) {
716 texture_output[i] = get_swizzled_channel(c, unpacked,
717 format_swiz[i]);
718 }
719
720 if (util_format_is_srgb(format)) {
721 for (int i = 0; i < 3; i++)
722 texture_output[i] = qir_srgb_decode(c,
723 texture_output[i]);
724 }
725
726 for (int i = 0; i < 4; i++) {
727 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
728 continue;
729
730 update_dst(c, tgsi_inst, i,
731 get_swizzled_channel(c, texture_output,
732 c->key->tex[unit].swizzle[i]));
733 }
734 }
735
736 static struct qreg
737 tgsi_to_qir_trunc(struct vc4_compile *c,
738 struct tgsi_full_instruction *tgsi_inst,
739 enum qop op, struct qreg *src, int i)
740 {
741 return qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
742 }
743
744 /**
745 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
746 * to zero).
747 */
748 static struct qreg
749 tgsi_to_qir_frc(struct vc4_compile *c,
750 struct tgsi_full_instruction *tgsi_inst,
751 enum qop op, struct qreg *src, int i)
752 {
753 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
754 struct qreg diff = qir_FSUB(c, src[0 * 4 + i], trunc);
755 qir_SF(c, diff);
756 return qir_SEL_X_Y_NS(c,
757 qir_FADD(c, diff, qir_uniform_f(c, 1.0)),
758 diff);
759 }
760
761 /**
762 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
763 * zero).
764 */
765 static struct qreg
766 tgsi_to_qir_flr(struct vc4_compile *c,
767 struct tgsi_full_instruction *tgsi_inst,
768 enum qop op, struct qreg *src, int i)
769 {
770 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
771
772 /* This will be < 0 if we truncated and the truncation was of a value
773 * that was < 0 in the first place.
774 */
775 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], trunc));
776
777 return qir_SEL_X_Y_NS(c,
778 qir_FSUB(c, trunc, qir_uniform_f(c, 1.0)),
779 trunc);
780 }
781
782 /**
783 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
784 * zero).
785 */
786 static struct qreg
787 tgsi_to_qir_ceil(struct vc4_compile *c,
788 struct tgsi_full_instruction *tgsi_inst,
789 enum qop op, struct qreg *src, int i)
790 {
791 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
792
793 /* This will be < 0 if we truncated and the truncation was of a value
794 * that was > 0 in the first place.
795 */
796 qir_SF(c, qir_FSUB(c, trunc, src[0 * 4 + i]));
797
798 return qir_SEL_X_Y_NS(c,
799 qir_FADD(c, trunc, qir_uniform_f(c, 1.0)),
800 trunc);
801 }
802
803 static struct qreg
804 tgsi_to_qir_abs(struct vc4_compile *c,
805 struct tgsi_full_instruction *tgsi_inst,
806 enum qop op, struct qreg *src, int i)
807 {
808 struct qreg arg = src[0 * 4 + i];
809 return qir_FMAXABS(c, arg, arg);
810 }
811
812 /* Note that this instruction replicates its result from the x channel */
813 static struct qreg
814 tgsi_to_qir_sin(struct vc4_compile *c,
815 struct tgsi_full_instruction *tgsi_inst,
816 enum qop op, struct qreg *src, int i)
817 {
818 float coeff[] = {
819 -2.0 * M_PI,
820 pow(2.0 * M_PI, 3) / (3 * 2 * 1),
821 -pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
822 pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
823 -pow(2.0 * M_PI, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
824 };
825
826 struct qreg scaled_x =
827 qir_FMUL(c,
828 src[0 * 4 + 0],
829 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
830
831 struct qreg x = qir_FADD(c,
832 tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0),
833 qir_uniform_f(c, -0.5));
834 struct qreg x2 = qir_FMUL(c, x, x);
835 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
836 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
837 x = qir_FMUL(c, x, x2);
838 sum = qir_FADD(c,
839 sum,
840 qir_FMUL(c,
841 x,
842 qir_uniform_f(c, coeff[i])));
843 }
844 return sum;
845 }
846
847 /* Note that this instruction replicates its result from the x channel */
848 static struct qreg
849 tgsi_to_qir_cos(struct vc4_compile *c,
850 struct tgsi_full_instruction *tgsi_inst,
851 enum qop op, struct qreg *src, int i)
852 {
853 float coeff[] = {
854 -1.0f,
855 pow(2.0 * M_PI, 2) / (2 * 1),
856 -pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
857 pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
858 -pow(2.0 * M_PI, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
859 pow(2.0 * M_PI, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
860 };
861
862 struct qreg scaled_x =
863 qir_FMUL(c, src[0 * 4 + 0],
864 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
865 struct qreg x_frac = qir_FADD(c,
866 tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0),
867 qir_uniform_f(c, -0.5));
868
869 struct qreg sum = qir_uniform_f(c, coeff[0]);
870 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
871 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
872 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
873 if (i != 1)
874 x = qir_FMUL(c, x, x2);
875
876 struct qreg mul = qir_FMUL(c,
877 x,
878 qir_uniform_f(c, coeff[i]));
879 if (i == 0)
880 sum = mul;
881 else
882 sum = qir_FADD(c, sum, mul);
883 }
884 return sum;
885 }
886
887 static struct qreg
888 tgsi_to_qir_clamp(struct vc4_compile *c,
889 struct tgsi_full_instruction *tgsi_inst,
890 enum qop op, struct qreg *src, int i)
891 {
892 return qir_FMAX(c, qir_FMIN(c,
893 src[0 * 4 + i],
894 src[2 * 4 + i]),
895 src[1 * 4 + i]);
896 }
897
898 static struct qreg
899 tgsi_to_qir_ssg(struct vc4_compile *c,
900 struct tgsi_full_instruction *tgsi_inst,
901 enum qop op, struct qreg *src, int i)
902 {
903 qir_SF(c, src[0 * 4 + i]);
904 return qir_SEL_X_Y_NC(c,
905 qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0)),
906 qir_uniform_f(c, -1.0));
907 }
908
909 static void
910 emit_vertex_input(struct vc4_compile *c, int attr)
911 {
912 enum pipe_format format = c->vs_key->attr_formats[attr];
913 struct qreg vpm_reads[4];
914
915 /* Right now, we're setting the VPM offsets to be 16 bytes wide every
916 * time, so we always read 4 32-bit VPM entries.
917 */
918 for (int i = 0; i < 4; i++) {
919 vpm_reads[i] = qir_get_temp(c);
920 qir_emit(c, qir_inst(QOP_VPM_READ,
921 vpm_reads[i],
922 c->undef,
923 c->undef));
924 c->num_inputs++;
925 }
926
927 bool format_warned = false;
928 const struct util_format_description *desc =
929 util_format_description(format);
930
931 for (int i = 0; i < 4; i++) {
932 uint8_t swiz = desc->swizzle[i];
933 struct qreg result;
934
935 if (swiz > UTIL_FORMAT_SWIZZLE_W)
936 result = get_swizzled_channel(c, vpm_reads, swiz);
937 else if (desc->channel[swiz].size == 32 &&
938 desc->channel[swiz].type == UTIL_FORMAT_TYPE_FLOAT) {
939 result = get_swizzled_channel(c, vpm_reads, swiz);
940 } else if (desc->channel[swiz].size == 8 &&
941 (desc->channel[swiz].type == UTIL_FORMAT_TYPE_UNSIGNED ||
942 desc->channel[swiz].type == UTIL_FORMAT_TYPE_SIGNED) &&
943 desc->channel[swiz].normalized) {
944 struct qreg vpm = vpm_reads[0];
945 if (desc->channel[swiz].type == UTIL_FORMAT_TYPE_SIGNED)
946 vpm = qir_XOR(c, vpm, qir_uniform_ui(c, 0x80808080));
947 result = qir_UNPACK_8(c, vpm, swiz);
948 } else {
949 if (!format_warned) {
950 fprintf(stderr,
951 "vtx element %d unsupported type: %s\n",
952 attr, util_format_name(format));
953 format_warned = true;
954 }
955 result = qir_uniform_f(c, 0.0);
956 }
957
958 if (desc->channel[swiz].normalized &&
959 desc->channel[swiz].type == UTIL_FORMAT_TYPE_SIGNED) {
960 result = qir_FSUB(c,
961 qir_FMUL(c,
962 result,
963 qir_uniform_f(c, 2.0)),
964 qir_uniform_f(c, 1.0));
965 }
966
967 c->inputs[attr * 4 + i] = result;
968 }
969 }
970
971 static void
972 tgsi_to_qir_kill_if(struct vc4_compile *c, struct qreg *src, int i)
973 {
974 if (c->discard.file == QFILE_NULL)
975 c->discard = qir_uniform_f(c, 0.0);
976 qir_SF(c, src[0 * 4 + i]);
977 c->discard = qir_SEL_X_Y_NS(c, qir_uniform_f(c, 1.0),
978 c->discard);
979 }
980
981 static void
982 emit_fragcoord_input(struct vc4_compile *c, int attr)
983 {
984 c->inputs[attr * 4 + 0] = qir_FRAG_X(c);
985 c->inputs[attr * 4 + 1] = qir_FRAG_Y(c);
986 c->inputs[attr * 4 + 2] =
987 qir_FMUL(c,
988 qir_ITOF(c, qir_FRAG_Z(c)),
989 qir_uniform_f(c, 1.0 / 0xffffff));
990 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
991 }
992
993 static void
994 emit_point_coord_input(struct vc4_compile *c, int attr)
995 {
996 if (c->point_x.file == QFILE_NULL) {
997 c->point_x = qir_uniform_f(c, 0.0);
998 c->point_y = qir_uniform_f(c, 0.0);
999 }
1000
1001 c->inputs[attr * 4 + 0] = c->point_x;
1002 if (c->fs_key->point_coord_upper_left) {
1003 c->inputs[attr * 4 + 1] = qir_FSUB(c,
1004 qir_uniform_f(c, 1.0),
1005 c->point_y);
1006 } else {
1007 c->inputs[attr * 4 + 1] = c->point_y;
1008 }
1009 c->inputs[attr * 4 + 2] = qir_uniform_f(c, 0.0);
1010 c->inputs[attr * 4 + 3] = qir_uniform_f(c, 1.0);
1011 }
1012
1013 static struct qreg
1014 emit_fragment_varying(struct vc4_compile *c, uint8_t semantic,
1015 uint8_t index, uint8_t swizzle)
1016 {
1017 uint32_t i = c->num_input_semantics++;
1018 struct qreg vary = {
1019 QFILE_VARY,
1020 i
1021 };
1022
1023 if (c->num_input_semantics >= c->input_semantics_array_size) {
1024 c->input_semantics_array_size =
1025 MAX2(4, c->input_semantics_array_size * 2);
1026
1027 c->input_semantics = reralloc(c, c->input_semantics,
1028 struct vc4_varying_semantic,
1029 c->input_semantics_array_size);
1030 }
1031
1032 c->input_semantics[i].semantic = semantic;
1033 c->input_semantics[i].index = index;
1034 c->input_semantics[i].swizzle = swizzle;
1035
1036 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
1037 }
1038
1039 static void
1040 emit_fragment_input(struct vc4_compile *c, int attr,
1041 struct tgsi_full_declaration *decl)
1042 {
1043 for (int i = 0; i < 4; i++) {
1044 c->inputs[attr * 4 + i] =
1045 emit_fragment_varying(c,
1046 decl->Semantic.Name,
1047 decl->Semantic.Index,
1048 i);
1049 c->num_inputs++;
1050 }
1051 }
1052
1053 static void
1054 emit_face_input(struct vc4_compile *c, int attr)
1055 {
1056 c->inputs[attr * 4 + 0] = qir_FSUB(c,
1057 qir_uniform_f(c, 1.0),
1058 qir_FMUL(c,
1059 qir_ITOF(c, qir_FRAG_REV_FLAG(c)),
1060 qir_uniform_f(c, 2.0)));
1061 c->inputs[attr * 4 + 1] = qir_uniform_f(c, 0.0);
1062 c->inputs[attr * 4 + 2] = qir_uniform_f(c, 0.0);
1063 c->inputs[attr * 4 + 3] = qir_uniform_f(c, 1.0);
1064 }
1065
1066 static void
1067 add_output(struct vc4_compile *c,
1068 uint32_t decl_offset,
1069 uint8_t semantic_name,
1070 uint8_t semantic_index,
1071 uint8_t semantic_swizzle)
1072 {
1073 uint32_t old_array_size = c->outputs_array_size;
1074 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
1075 decl_offset + 1);
1076
1077 if (old_array_size != c->outputs_array_size) {
1078 c->output_semantics = reralloc(c,
1079 c->output_semantics,
1080 struct vc4_varying_semantic,
1081 c->outputs_array_size);
1082 }
1083
1084 c->output_semantics[decl_offset].semantic = semantic_name;
1085 c->output_semantics[decl_offset].index = semantic_index;
1086 c->output_semantics[decl_offset].swizzle = semantic_swizzle;
1087 }
1088
1089 static void
1090 emit_tgsi_declaration(struct vc4_compile *c,
1091 struct tgsi_full_declaration *decl)
1092 {
1093 switch (decl->Declaration.File) {
1094 case TGSI_FILE_TEMPORARY: {
1095 uint32_t old_size = c->temps_array_size;
1096 resize_qreg_array(c, &c->temps, &c->temps_array_size,
1097 (decl->Range.Last + 1) * 4);
1098
1099 for (int i = old_size; i < c->temps_array_size; i++)
1100 c->temps[i] = qir_uniform_ui(c, 0);
1101 break;
1102 }
1103
1104 case TGSI_FILE_INPUT:
1105 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1106 (decl->Range.Last + 1) * 4);
1107
1108 for (int i = decl->Range.First;
1109 i <= decl->Range.Last;
1110 i++) {
1111 if (c->stage == QSTAGE_FRAG) {
1112 if (decl->Semantic.Name ==
1113 TGSI_SEMANTIC_POSITION) {
1114 emit_fragcoord_input(c, i);
1115 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
1116 emit_face_input(c, i);
1117 } else if (decl->Semantic.Name == TGSI_SEMANTIC_GENERIC &&
1118 (c->fs_key->point_sprite_mask &
1119 (1 << decl->Semantic.Index))) {
1120 emit_point_coord_input(c, i);
1121 } else {
1122 emit_fragment_input(c, i, decl);
1123 }
1124 } else {
1125 emit_vertex_input(c, i);
1126 }
1127 }
1128 break;
1129
1130 case TGSI_FILE_OUTPUT: {
1131 for (int i = 0; i < 4; i++) {
1132 add_output(c,
1133 decl->Range.First * 4 + i,
1134 decl->Semantic.Name,
1135 decl->Semantic.Index,
1136 i);
1137 }
1138
1139 switch (decl->Semantic.Name) {
1140 case TGSI_SEMANTIC_POSITION:
1141 c->output_position_index = decl->Range.First * 4;
1142 break;
1143 case TGSI_SEMANTIC_CLIPVERTEX:
1144 c->output_clipvertex_index = decl->Range.First * 4;
1145 break;
1146 case TGSI_SEMANTIC_COLOR:
1147 c->output_color_index = decl->Range.First * 4;
1148 break;
1149 case TGSI_SEMANTIC_PSIZE:
1150 c->output_point_size_index = decl->Range.First * 4;
1151 break;
1152 }
1153
1154 break;
1155 }
1156 }
1157 }
1158
1159 static void
1160 emit_tgsi_instruction(struct vc4_compile *c,
1161 struct tgsi_full_instruction *tgsi_inst)
1162 {
1163 struct {
1164 enum qop op;
1165 struct qreg (*func)(struct vc4_compile *c,
1166 struct tgsi_full_instruction *tgsi_inst,
1167 enum qop op,
1168 struct qreg *src, int i);
1169 } op_trans[] = {
1170 [TGSI_OPCODE_MOV] = { QOP_MOV, tgsi_to_qir_alu },
1171 [TGSI_OPCODE_ABS] = { 0, tgsi_to_qir_abs },
1172 [TGSI_OPCODE_MUL] = { QOP_FMUL, tgsi_to_qir_alu },
1173 [TGSI_OPCODE_ADD] = { QOP_FADD, tgsi_to_qir_alu },
1174 [TGSI_OPCODE_SUB] = { QOP_FSUB, tgsi_to_qir_alu },
1175 [TGSI_OPCODE_MIN] = { QOP_FMIN, tgsi_to_qir_alu },
1176 [TGSI_OPCODE_MAX] = { QOP_FMAX, tgsi_to_qir_alu },
1177 [TGSI_OPCODE_F2I] = { QOP_FTOI, tgsi_to_qir_alu },
1178 [TGSI_OPCODE_I2F] = { QOP_ITOF, tgsi_to_qir_alu },
1179 [TGSI_OPCODE_UADD] = { QOP_ADD, tgsi_to_qir_alu },
1180 [TGSI_OPCODE_USHR] = { QOP_SHR, tgsi_to_qir_alu },
1181 [TGSI_OPCODE_ISHR] = { QOP_ASR, tgsi_to_qir_alu },
1182 [TGSI_OPCODE_SHL] = { QOP_SHL, tgsi_to_qir_alu },
1183 [TGSI_OPCODE_IMIN] = { QOP_MIN, tgsi_to_qir_alu },
1184 [TGSI_OPCODE_IMAX] = { QOP_MAX, tgsi_to_qir_alu },
1185 [TGSI_OPCODE_AND] = { QOP_AND, tgsi_to_qir_alu },
1186 [TGSI_OPCODE_OR] = { QOP_OR, tgsi_to_qir_alu },
1187 [TGSI_OPCODE_XOR] = { QOP_XOR, tgsi_to_qir_alu },
1188 [TGSI_OPCODE_NOT] = { QOP_NOT, tgsi_to_qir_alu },
1189
1190 [TGSI_OPCODE_UMUL] = { 0, tgsi_to_qir_umul },
1191 [TGSI_OPCODE_IDIV] = { 0, tgsi_to_qir_idiv },
1192 [TGSI_OPCODE_INEG] = { 0, tgsi_to_qir_ineg },
1193
1194 [TGSI_OPCODE_SEQ] = { 0, tgsi_to_qir_seq },
1195 [TGSI_OPCODE_SNE] = { 0, tgsi_to_qir_sne },
1196 [TGSI_OPCODE_SGE] = { 0, tgsi_to_qir_sge },
1197 [TGSI_OPCODE_SLT] = { 0, tgsi_to_qir_slt },
1198 [TGSI_OPCODE_FSEQ] = { 0, tgsi_to_qir_fseq },
1199 [TGSI_OPCODE_FSNE] = { 0, tgsi_to_qir_fsne },
1200 [TGSI_OPCODE_FSGE] = { 0, tgsi_to_qir_fsge },
1201 [TGSI_OPCODE_FSLT] = { 0, tgsi_to_qir_fslt },
1202 [TGSI_OPCODE_USEQ] = { 0, tgsi_to_qir_useq },
1203 [TGSI_OPCODE_USNE] = { 0, tgsi_to_qir_usne },
1204 [TGSI_OPCODE_ISGE] = { 0, tgsi_to_qir_isge },
1205 [TGSI_OPCODE_ISLT] = { 0, tgsi_to_qir_islt },
1206
1207 [TGSI_OPCODE_CMP] = { 0, tgsi_to_qir_cmp },
1208 [TGSI_OPCODE_MAD] = { 0, tgsi_to_qir_mad },
1209 [TGSI_OPCODE_RCP] = { QOP_RCP, tgsi_to_qir_rcp },
1210 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_rsq },
1211 [TGSI_OPCODE_EX2] = { QOP_EXP2, tgsi_to_qir_scalar },
1212 [TGSI_OPCODE_LG2] = { QOP_LOG2, tgsi_to_qir_scalar },
1213 [TGSI_OPCODE_LRP] = { 0, tgsi_to_qir_lrp },
1214 [TGSI_OPCODE_TRUNC] = { 0, tgsi_to_qir_trunc },
1215 [TGSI_OPCODE_CEIL] = { 0, tgsi_to_qir_ceil },
1216 [TGSI_OPCODE_FRC] = { 0, tgsi_to_qir_frc },
1217 [TGSI_OPCODE_FLR] = { 0, tgsi_to_qir_flr },
1218 [TGSI_OPCODE_SIN] = { 0, tgsi_to_qir_sin },
1219 [TGSI_OPCODE_COS] = { 0, tgsi_to_qir_cos },
1220 [TGSI_OPCODE_CLAMP] = { 0, tgsi_to_qir_clamp },
1221 [TGSI_OPCODE_SSG] = { 0, tgsi_to_qir_ssg },
1222 };
1223 static int asdf = 0;
1224 uint32_t tgsi_op = tgsi_inst->Instruction.Opcode;
1225
1226 if (tgsi_op == TGSI_OPCODE_END)
1227 return;
1228
1229 struct qreg src_regs[12];
1230 for (int s = 0; s < 3; s++) {
1231 for (int i = 0; i < 4; i++) {
1232 src_regs[4 * s + i] =
1233 get_src(c, tgsi_inst->Instruction.Opcode,
1234 &tgsi_inst->Src[s].Register, i);
1235 }
1236 }
1237
1238 switch (tgsi_op) {
1239 case TGSI_OPCODE_TEX:
1240 case TGSI_OPCODE_TXP:
1241 case TGSI_OPCODE_TXB:
1242 case TGSI_OPCODE_TXL:
1243 tgsi_to_qir_tex(c, tgsi_inst,
1244 op_trans[tgsi_op].op, src_regs);
1245 return;
1246 case TGSI_OPCODE_KILL:
1247 c->discard = qir_uniform_f(c, 1.0);
1248 return;
1249 case TGSI_OPCODE_KILL_IF:
1250 for (int i = 0; i < 4; i++)
1251 tgsi_to_qir_kill_if(c, src_regs, i);
1252 return;
1253 default:
1254 break;
1255 }
1256
1257 if (tgsi_op > ARRAY_SIZE(op_trans) || !(op_trans[tgsi_op].func)) {
1258 fprintf(stderr, "unknown tgsi inst: ");
1259 tgsi_dump_instruction(tgsi_inst, asdf++);
1260 fprintf(stderr, "\n");
1261 abort();
1262 }
1263
1264 for (int i = 0; i < 4; i++) {
1265 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
1266 continue;
1267
1268 struct qreg result;
1269
1270 result = op_trans[tgsi_op].func(c, tgsi_inst,
1271 op_trans[tgsi_op].op,
1272 src_regs, i);
1273
1274 if (tgsi_inst->Instruction.Saturate) {
1275 float low = (tgsi_inst->Instruction.Saturate ==
1276 TGSI_SAT_MINUS_PLUS_ONE ? -1.0 : 0.0);
1277 result = qir_FMAX(c,
1278 qir_FMIN(c,
1279 result,
1280 qir_uniform_f(c, 1.0)),
1281 qir_uniform_f(c, low));
1282 }
1283
1284 update_dst(c, tgsi_inst, i, result);
1285 }
1286 }
1287
1288 static void
1289 parse_tgsi_immediate(struct vc4_compile *c, struct tgsi_full_immediate *imm)
1290 {
1291 for (int i = 0; i < 4; i++) {
1292 unsigned n = c->num_consts++;
1293 resize_qreg_array(c, &c->consts, &c->consts_array_size, n + 1);
1294 c->consts[n] = qir_uniform_ui(c, imm->u[i].Uint);
1295 }
1296 }
1297
1298 static struct qreg
1299 vc4_blend_channel(struct vc4_compile *c,
1300 struct qreg *dst,
1301 struct qreg *src,
1302 struct qreg val,
1303 unsigned factor,
1304 int channel)
1305 {
1306 switch(factor) {
1307 case PIPE_BLENDFACTOR_ONE:
1308 return val;
1309 case PIPE_BLENDFACTOR_SRC_COLOR:
1310 return qir_FMUL(c, val, src[channel]);
1311 case PIPE_BLENDFACTOR_SRC_ALPHA:
1312 return qir_FMUL(c, val, src[3]);
1313 case PIPE_BLENDFACTOR_DST_ALPHA:
1314 return qir_FMUL(c, val, dst[3]);
1315 case PIPE_BLENDFACTOR_DST_COLOR:
1316 return qir_FMUL(c, val, dst[channel]);
1317 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
1318 if (channel != 3) {
1319 return qir_FMUL(c,
1320 val,
1321 qir_FMIN(c,
1322 src[3],
1323 qir_FSUB(c,
1324 qir_uniform_f(c, 1.0),
1325 dst[3])));
1326 } else {
1327 return val;
1328 }
1329 case PIPE_BLENDFACTOR_CONST_COLOR:
1330 return qir_FMUL(c, val,
1331 get_temp_for_uniform(c,
1332 QUNIFORM_BLEND_CONST_COLOR,
1333 channel));
1334 case PIPE_BLENDFACTOR_CONST_ALPHA:
1335 return qir_FMUL(c, val,
1336 get_temp_for_uniform(c,
1337 QUNIFORM_BLEND_CONST_COLOR,
1338 3));
1339 case PIPE_BLENDFACTOR_ZERO:
1340 return qir_uniform_f(c, 0.0);
1341 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
1342 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1343 src[channel]));
1344 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
1345 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1346 src[3]));
1347 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
1348 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1349 dst[3]));
1350 case PIPE_BLENDFACTOR_INV_DST_COLOR:
1351 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1352 dst[channel]));
1353 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
1354 return qir_FMUL(c, val,
1355 qir_FSUB(c, qir_uniform_f(c, 1.0),
1356 get_temp_for_uniform(c,
1357 QUNIFORM_BLEND_CONST_COLOR,
1358 channel)));
1359 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
1360 return qir_FMUL(c, val,
1361 qir_FSUB(c, qir_uniform_f(c, 1.0),
1362 get_temp_for_uniform(c,
1363 QUNIFORM_BLEND_CONST_COLOR,
1364 3)));
1365
1366 default:
1367 case PIPE_BLENDFACTOR_SRC1_COLOR:
1368 case PIPE_BLENDFACTOR_SRC1_ALPHA:
1369 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
1370 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
1371 /* Unsupported. */
1372 fprintf(stderr, "Unknown blend factor %d\n", factor);
1373 return val;
1374 }
1375 }
1376
1377 static struct qreg
1378 vc4_blend_func(struct vc4_compile *c,
1379 struct qreg src, struct qreg dst,
1380 unsigned func)
1381 {
1382 switch (func) {
1383 case PIPE_BLEND_ADD:
1384 return qir_FADD(c, src, dst);
1385 case PIPE_BLEND_SUBTRACT:
1386 return qir_FSUB(c, src, dst);
1387 case PIPE_BLEND_REVERSE_SUBTRACT:
1388 return qir_FSUB(c, dst, src);
1389 case PIPE_BLEND_MIN:
1390 return qir_FMIN(c, src, dst);
1391 case PIPE_BLEND_MAX:
1392 return qir_FMAX(c, src, dst);
1393
1394 default:
1395 /* Unsupported. */
1396 fprintf(stderr, "Unknown blend func %d\n", func);
1397 return src;
1398
1399 }
1400 }
1401
1402 /**
1403 * Implements fixed function blending in shader code.
1404 *
1405 * VC4 doesn't have any hardware support for blending. Instead, you read the
1406 * current contents of the destination from the tile buffer after having
1407 * waited for the scoreboard (which is handled by vc4_qpu_emit.c), then do
1408 * math using your output color and that destination value, and update the
1409 * output color appropriately.
1410 */
1411 static void
1412 vc4_blend(struct vc4_compile *c, struct qreg *result,
1413 struct qreg *dst_color, struct qreg *src_color)
1414 {
1415 struct pipe_rt_blend_state *blend = &c->fs_key->blend;
1416
1417 if (!blend->blend_enable) {
1418 for (int i = 0; i < 4; i++)
1419 result[i] = src_color[i];
1420 return;
1421 }
1422
1423 struct qreg src_blend[4], dst_blend[4];
1424 for (int i = 0; i < 3; i++) {
1425 src_blend[i] = vc4_blend_channel(c,
1426 dst_color, src_color,
1427 src_color[i],
1428 blend->rgb_src_factor, i);
1429 dst_blend[i] = vc4_blend_channel(c,
1430 dst_color, src_color,
1431 dst_color[i],
1432 blend->rgb_dst_factor, i);
1433 }
1434 src_blend[3] = vc4_blend_channel(c,
1435 dst_color, src_color,
1436 src_color[3],
1437 blend->alpha_src_factor, 3);
1438 dst_blend[3] = vc4_blend_channel(c,
1439 dst_color, src_color,
1440 dst_color[3],
1441 blend->alpha_dst_factor, 3);
1442
1443 for (int i = 0; i < 3; i++) {
1444 result[i] = vc4_blend_func(c,
1445 src_blend[i], dst_blend[i],
1446 blend->rgb_func);
1447 }
1448 result[3] = vc4_blend_func(c,
1449 src_blend[3], dst_blend[3],
1450 blend->alpha_func);
1451 }
1452
1453 static void
1454 clip_distance_discard(struct vc4_compile *c)
1455 {
1456 for (int i = 0; i < PIPE_MAX_CLIP_PLANES; i++) {
1457 if (!(c->key->ucp_enables & (1 << i)))
1458 continue;
1459
1460 struct qreg dist = emit_fragment_varying(c,
1461 TGSI_SEMANTIC_CLIPDIST,
1462 i,
1463 TGSI_SWIZZLE_X);
1464
1465 qir_SF(c, dist);
1466
1467 if (c->discard.file == QFILE_NULL)
1468 c->discard = qir_uniform_f(c, 0.0);
1469
1470 c->discard = qir_SEL_X_Y_NS(c, qir_uniform_f(c, 1.0),
1471 c->discard);
1472 }
1473 }
1474
1475 static void
1476 alpha_test_discard(struct vc4_compile *c)
1477 {
1478 struct qreg src_alpha;
1479 struct qreg alpha_ref = get_temp_for_uniform(c, QUNIFORM_ALPHA_REF, 0);
1480
1481 if (!c->fs_key->alpha_test)
1482 return;
1483
1484 if (c->output_color_index != -1)
1485 src_alpha = c->outputs[c->output_color_index + 3];
1486 else
1487 src_alpha = qir_uniform_f(c, 1.0);
1488
1489 if (c->discard.file == QFILE_NULL)
1490 c->discard = qir_uniform_f(c, 0.0);
1491
1492 switch (c->fs_key->alpha_test_func) {
1493 case PIPE_FUNC_NEVER:
1494 c->discard = qir_uniform_f(c, 1.0);
1495 break;
1496 case PIPE_FUNC_ALWAYS:
1497 break;
1498 case PIPE_FUNC_EQUAL:
1499 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1500 c->discard = qir_SEL_X_Y_ZS(c, c->discard,
1501 qir_uniform_f(c, 1.0));
1502 break;
1503 case PIPE_FUNC_NOTEQUAL:
1504 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1505 c->discard = qir_SEL_X_Y_ZC(c, c->discard,
1506 qir_uniform_f(c, 1.0));
1507 break;
1508 case PIPE_FUNC_GREATER:
1509 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1510 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1511 qir_uniform_f(c, 1.0));
1512 break;
1513 case PIPE_FUNC_GEQUAL:
1514 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1515 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1516 qir_uniform_f(c, 1.0));
1517 break;
1518 case PIPE_FUNC_LESS:
1519 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1520 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1521 qir_uniform_f(c, 1.0));
1522 break;
1523 case PIPE_FUNC_LEQUAL:
1524 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1525 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1526 qir_uniform_f(c, 1.0));
1527 break;
1528 }
1529 }
1530
1531 static void
1532 emit_frag_end(struct vc4_compile *c)
1533 {
1534 clip_distance_discard(c);
1535 alpha_test_discard(c);
1536
1537 enum pipe_format color_format = c->fs_key->color_format;
1538 const uint8_t *format_swiz = vc4_get_format_swizzle(color_format);
1539 struct qreg tlb_read_color[4] = { c->undef, c->undef, c->undef, c->undef };
1540 struct qreg dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1541 struct qreg linear_dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1542 if (c->fs_key->blend.blend_enable ||
1543 c->fs_key->blend.colormask != 0xf) {
1544 struct qreg r4 = qir_TLB_COLOR_READ(c);
1545 for (int i = 0; i < 4; i++)
1546 tlb_read_color[i] = qir_R4_UNPACK(c, r4, i);
1547 for (int i = 0; i < 4; i++) {
1548 dst_color[i] = get_swizzled_channel(c,
1549 tlb_read_color,
1550 format_swiz[i]);
1551 if (util_format_is_srgb(color_format) && i != 3) {
1552 linear_dst_color[i] =
1553 qir_srgb_decode(c, dst_color[i]);
1554 } else {
1555 linear_dst_color[i] = dst_color[i];
1556 }
1557 }
1558 }
1559
1560 struct qreg blend_color[4];
1561 struct qreg undef_array[4] = {
1562 c->undef, c->undef, c->undef, c->undef
1563 };
1564 vc4_blend(c, blend_color, linear_dst_color,
1565 (c->output_color_index != -1 ?
1566 c->outputs + c->output_color_index :
1567 undef_array));
1568
1569 if (util_format_is_srgb(color_format)) {
1570 for (int i = 0; i < 3; i++)
1571 blend_color[i] = qir_srgb_encode(c, blend_color[i]);
1572 }
1573
1574 /* If the bit isn't set in the color mask, then just return the
1575 * original dst color, instead.
1576 */
1577 for (int i = 0; i < 4; i++) {
1578 if (!(c->fs_key->blend.colormask & (1 << i))) {
1579 blend_color[i] = dst_color[i];
1580 }
1581 }
1582
1583 /* Debug: Sometimes you're getting a black output and just want to see
1584 * if the FS is getting executed at all. Spam magenta into the color
1585 * output.
1586 */
1587 if (0) {
1588 blend_color[0] = qir_uniform_f(c, 1.0);
1589 blend_color[1] = qir_uniform_f(c, 0.0);
1590 blend_color[2] = qir_uniform_f(c, 1.0);
1591 blend_color[3] = qir_uniform_f(c, 0.5);
1592 }
1593
1594 struct qreg swizzled_outputs[4];
1595 for (int i = 0; i < 4; i++) {
1596 swizzled_outputs[i] = get_swizzled_channel(c, blend_color,
1597 format_swiz[i]);
1598 }
1599
1600 if (c->discard.file != QFILE_NULL)
1601 qir_TLB_DISCARD_SETUP(c, c->discard);
1602
1603 if (c->fs_key->stencil_enabled) {
1604 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 0));
1605 if (c->fs_key->stencil_twoside) {
1606 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 1));
1607 }
1608 if (c->fs_key->stencil_full_writemasks) {
1609 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 2));
1610 }
1611 }
1612
1613 if (c->fs_key->depth_enabled) {
1614 struct qreg z;
1615 if (c->output_position_index != -1) {
1616 z = qir_FTOI(c, qir_FMUL(c, c->outputs[c->output_position_index + 2],
1617 qir_uniform_f(c, 0xffffff)));
1618 } else {
1619 z = qir_FRAG_Z(c);
1620 }
1621 qir_TLB_Z_WRITE(c, z);
1622 }
1623
1624 bool color_written = false;
1625 for (int i = 0; i < 4; i++) {
1626 if (swizzled_outputs[i].file != QFILE_NULL)
1627 color_written = true;
1628 }
1629
1630 struct qreg packed_color;
1631 if (color_written) {
1632 /* Fill in any undefined colors. The simulator will assertion
1633 * fail if we read something that wasn't written, and I don't
1634 * know what hardware does.
1635 */
1636 for (int i = 0; i < 4; i++) {
1637 if (swizzled_outputs[i].file == QFILE_NULL)
1638 swizzled_outputs[i] = qir_uniform_f(c, 0.0);
1639 }
1640 packed_color = qir_get_temp(c);
1641 qir_emit(c, qir_inst4(QOP_PACK_COLORS, packed_color,
1642 swizzled_outputs[0],
1643 swizzled_outputs[1],
1644 swizzled_outputs[2],
1645 swizzled_outputs[3]));
1646 } else {
1647 packed_color = qir_uniform_ui(c, 0);
1648 }
1649
1650 qir_emit(c, qir_inst(QOP_TLB_COLOR_WRITE, c->undef,
1651 packed_color, c->undef));
1652 }
1653
1654 static void
1655 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1656 {
1657 struct qreg xyi[2];
1658
1659 for (int i = 0; i < 2; i++) {
1660 struct qreg scale =
1661 add_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1662
1663 xyi[i] = qir_FTOI(c, qir_FMUL(c,
1664 qir_FMUL(c,
1665 c->outputs[i],
1666 scale),
1667 rcp_w));
1668 }
1669
1670 qir_VPM_WRITE(c, qir_PACK_SCALED(c, xyi[0], xyi[1]));
1671 }
1672
1673 static void
1674 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1675 {
1676 struct qreg zscale = add_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1677 struct qreg zoffset = add_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1678
1679 qir_VPM_WRITE(c, qir_FMUL(c, qir_FADD(c, qir_FMUL(c,
1680 c->outputs[2],
1681 zscale),
1682 zoffset),
1683 rcp_w));
1684 }
1685
1686 static void
1687 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1688 {
1689 qir_VPM_WRITE(c, rcp_w);
1690 }
1691
1692 static void
1693 emit_point_size_write(struct vc4_compile *c)
1694 {
1695 struct qreg point_size;
1696
1697 if (c->output_point_size_index)
1698 point_size = c->outputs[c->output_point_size_index + 3];
1699 else
1700 point_size = qir_uniform_f(c, 1.0);
1701
1702 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1703 * BCM21553).
1704 */
1705 point_size = qir_FMAX(c, point_size, qir_uniform_f(c, .125));
1706
1707 qir_VPM_WRITE(c, point_size);
1708 }
1709
1710 /**
1711 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1712 *
1713 * The simulator insists that there be at least one vertex attribute, so
1714 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also
1715 * insists that all vertex attributes loaded get read by the VS/CS, so we have
1716 * to consume it here.
1717 */
1718 static void
1719 emit_stub_vpm_read(struct vc4_compile *c)
1720 {
1721 if (c->num_inputs)
1722 return;
1723
1724 for (int i = 0; i < 4; i++) {
1725 qir_emit(c, qir_inst(QOP_VPM_READ,
1726 qir_get_temp(c),
1727 c->undef,
1728 c->undef));
1729 c->num_inputs++;
1730 }
1731 }
1732
1733 static void
1734 emit_ucp_clipdistance(struct vc4_compile *c)
1735 {
1736 struct qreg *clipvertex;
1737
1738 if (c->output_clipvertex_index != -1)
1739 clipvertex = &c->outputs[c->output_clipvertex_index];
1740 else if (c->output_position_index != -1)
1741 clipvertex = &c->outputs[c->output_position_index];
1742 else
1743 return;
1744
1745 for (int plane = 0; plane < PIPE_MAX_CLIP_PLANES; plane++) {
1746 if (!(c->key->ucp_enables & (1 << plane)))
1747 continue;
1748
1749 /* Pick the next outputs[] that hasn't been written to, since
1750 * there are no other program writes left to be processed at
1751 * this point. If something had been declared but not written
1752 * (like a w component), we'll just smash over the top of it.
1753 */
1754 uint32_t output_index = c->num_outputs++;
1755 add_output(c, output_index,
1756 TGSI_SEMANTIC_CLIPDIST,
1757 plane,
1758 TGSI_SWIZZLE_X);
1759
1760 struct qreg dist = qir_uniform_f(c, 0.0);
1761 for (int i = 0; i < 4; i++) {
1762 struct qreg ucp =
1763 add_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1764 plane * 4 + i);
1765 dist = qir_FADD(c, dist, qir_FMUL(c, clipvertex[i], ucp));
1766 }
1767
1768 c->outputs[output_index] = dist;
1769 }
1770 }
1771
1772 static void
1773 emit_vert_end(struct vc4_compile *c,
1774 struct vc4_varying_semantic *fs_inputs,
1775 uint32_t num_fs_inputs)
1776 {
1777 struct qreg rcp_w = qir_RCP(c, c->outputs[3]);
1778
1779 emit_stub_vpm_read(c);
1780 emit_ucp_clipdistance(c);
1781
1782 emit_scaled_viewport_write(c, rcp_w);
1783 emit_zs_write(c, rcp_w);
1784 emit_rcp_wc_write(c, rcp_w);
1785 if (c->vs_key->per_vertex_point_size)
1786 emit_point_size_write(c);
1787
1788 for (int i = 0; i < num_fs_inputs; i++) {
1789 struct vc4_varying_semantic *input = &fs_inputs[i];
1790 int j;
1791
1792 for (j = 0; j < c->num_outputs; j++) {
1793 struct vc4_varying_semantic *output =
1794 &c->output_semantics[j];
1795
1796 if (input->semantic == output->semantic &&
1797 input->index == output->index &&
1798 input->swizzle == output->swizzle) {
1799 qir_VPM_WRITE(c, c->outputs[j]);
1800 break;
1801 }
1802 }
1803 /* Emit padding if we didn't find a declared VS output for
1804 * this FS input.
1805 */
1806 if (j == c->num_outputs)
1807 qir_VPM_WRITE(c, qir_uniform_f(c, 0.0));
1808 }
1809 }
1810
1811 static void
1812 emit_coord_end(struct vc4_compile *c)
1813 {
1814 struct qreg rcp_w = qir_RCP(c, c->outputs[3]);
1815
1816 emit_stub_vpm_read(c);
1817
1818 for (int i = 0; i < 4; i++)
1819 qir_VPM_WRITE(c, c->outputs[i]);
1820
1821 emit_scaled_viewport_write(c, rcp_w);
1822 emit_zs_write(c, rcp_w);
1823 emit_rcp_wc_write(c, rcp_w);
1824 if (c->vs_key->per_vertex_point_size)
1825 emit_point_size_write(c);
1826 }
1827
1828 static struct vc4_compile *
1829 vc4_shader_tgsi_to_qir(struct vc4_context *vc4, enum qstage stage,
1830 struct vc4_key *key)
1831 {
1832 struct vc4_compile *c = qir_compile_init();
1833 int ret;
1834
1835 c->stage = stage;
1836 c->shader_state = &key->shader_state->base;
1837 c->program_id = key->shader_state->program_id;
1838 c->variant_id = key->shader_state->compiled_variant_count++;
1839
1840 c->key = key;
1841 switch (stage) {
1842 case QSTAGE_FRAG:
1843 c->fs_key = (struct vc4_fs_key *)key;
1844 if (c->fs_key->is_points) {
1845 c->point_x = emit_fragment_varying(c, ~0, ~0, 0);
1846 c->point_y = emit_fragment_varying(c, ~0, ~0, 0);
1847 } else if (c->fs_key->is_lines) {
1848 c->line_x = emit_fragment_varying(c, ~0, ~0, 0);
1849 }
1850 break;
1851 case QSTAGE_VERT:
1852 c->vs_key = (struct vc4_vs_key *)key;
1853 break;
1854 case QSTAGE_COORD:
1855 c->vs_key = (struct vc4_vs_key *)key;
1856 break;
1857 }
1858
1859 const struct tgsi_token *tokens = key->shader_state->base.tokens;
1860 if (c->fs_key && c->fs_key->light_twoside) {
1861 if (!key->shader_state->twoside_tokens) {
1862 const struct tgsi_lowering_config lowering_config = {
1863 .color_two_side = true,
1864 };
1865 struct tgsi_shader_info info;
1866 key->shader_state->twoside_tokens =
1867 tgsi_transform_lowering(&lowering_config,
1868 key->shader_state->base.tokens,
1869 &info);
1870
1871 /* If no transformation occurred, then NULL is
1872 * returned and we just use our original tokens.
1873 */
1874 if (!key->shader_state->twoside_tokens) {
1875 key->shader_state->twoside_tokens =
1876 key->shader_state->base.tokens;
1877 }
1878 }
1879 tokens = key->shader_state->twoside_tokens;
1880 }
1881
1882 ret = tgsi_parse_init(&c->parser, tokens);
1883 assert(ret == TGSI_PARSE_OK);
1884
1885 if (vc4_debug & VC4_DEBUG_TGSI) {
1886 fprintf(stderr, "%s prog %d/%d TGSI:\n",
1887 qir_get_stage_name(c->stage),
1888 c->program_id, c->variant_id);
1889 tgsi_dump(tokens, 0);
1890 }
1891
1892 while (!tgsi_parse_end_of_tokens(&c->parser)) {
1893 tgsi_parse_token(&c->parser);
1894
1895 switch (c->parser.FullToken.Token.Type) {
1896 case TGSI_TOKEN_TYPE_DECLARATION:
1897 emit_tgsi_declaration(c,
1898 &c->parser.FullToken.FullDeclaration);
1899 break;
1900
1901 case TGSI_TOKEN_TYPE_INSTRUCTION:
1902 emit_tgsi_instruction(c,
1903 &c->parser.FullToken.FullInstruction);
1904 break;
1905
1906 case TGSI_TOKEN_TYPE_IMMEDIATE:
1907 parse_tgsi_immediate(c,
1908 &c->parser.FullToken.FullImmediate);
1909 break;
1910 }
1911 }
1912
1913 switch (stage) {
1914 case QSTAGE_FRAG:
1915 emit_frag_end(c);
1916 break;
1917 case QSTAGE_VERT:
1918 emit_vert_end(c,
1919 vc4->prog.fs->input_semantics,
1920 vc4->prog.fs->num_inputs);
1921 break;
1922 case QSTAGE_COORD:
1923 emit_coord_end(c);
1924 break;
1925 }
1926
1927 tgsi_parse_free(&c->parser);
1928
1929 qir_optimize(c);
1930
1931 if (vc4_debug & VC4_DEBUG_QIR) {
1932 fprintf(stderr, "%s prog %d/%d QIR:\n",
1933 qir_get_stage_name(c->stage),
1934 c->program_id, c->variant_id);
1935 qir_dump(c);
1936 }
1937 qir_reorder_uniforms(c);
1938 vc4_generate_code(vc4, c);
1939
1940 if (vc4_debug & VC4_DEBUG_SHADERDB) {
1941 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d instructions\n",
1942 qir_get_stage_name(c->stage),
1943 c->program_id, c->variant_id,
1944 c->qpu_inst_count);
1945 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d uniforms\n",
1946 qir_get_stage_name(c->stage),
1947 c->program_id, c->variant_id,
1948 c->num_uniforms);
1949 }
1950
1951 return c;
1952 }
1953
1954 static void *
1955 vc4_shader_state_create(struct pipe_context *pctx,
1956 const struct pipe_shader_state *cso)
1957 {
1958 struct vc4_context *vc4 = vc4_context(pctx);
1959 struct vc4_uncompiled_shader *so = CALLOC_STRUCT(vc4_uncompiled_shader);
1960 if (!so)
1961 return NULL;
1962
1963 const struct tgsi_lowering_config lowering_config = {
1964 .lower_DST = true,
1965 .lower_XPD = true,
1966 .lower_SCS = true,
1967 .lower_POW = true,
1968 .lower_LIT = true,
1969 .lower_EXP = true,
1970 .lower_LOG = true,
1971 .lower_DP4 = true,
1972 .lower_DP3 = true,
1973 .lower_DPH = true,
1974 .lower_DP2 = true,
1975 .lower_DP2A = true,
1976 };
1977
1978 struct tgsi_shader_info info;
1979 so->base.tokens = tgsi_transform_lowering(&lowering_config, cso->tokens, &info);
1980 if (!so->base.tokens)
1981 so->base.tokens = tgsi_dup_tokens(cso->tokens);
1982 so->program_id = vc4->next_uncompiled_program_id++;
1983
1984 return so;
1985 }
1986
1987 static void
1988 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
1989 struct vc4_compile *c)
1990 {
1991 int count = c->num_uniforms;
1992 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
1993
1994 uinfo->count = count;
1995 uinfo->data = ralloc_array(shader, uint32_t, count);
1996 memcpy(uinfo->data, c->uniform_data,
1997 count * sizeof(*uinfo->data));
1998 uinfo->contents = ralloc_array(shader, enum quniform_contents, count);
1999 memcpy(uinfo->contents, c->uniform_contents,
2000 count * sizeof(*uinfo->contents));
2001 uinfo->num_texture_samples = c->num_texture_samples;
2002 }
2003
2004 static struct vc4_compiled_shader *
2005 vc4_get_compiled_shader(struct vc4_context *vc4, enum qstage stage,
2006 struct vc4_key *key)
2007 {
2008 struct util_hash_table *ht;
2009 uint32_t key_size;
2010 if (stage == QSTAGE_FRAG) {
2011 ht = vc4->fs_cache;
2012 key_size = sizeof(struct vc4_fs_key);
2013 } else {
2014 ht = vc4->vs_cache;
2015 key_size = sizeof(struct vc4_vs_key);
2016 }
2017
2018 struct vc4_compiled_shader *shader;
2019 shader = util_hash_table_get(ht, key);
2020 if (shader)
2021 return shader;
2022
2023 struct vc4_compile *c = vc4_shader_tgsi_to_qir(vc4, stage, key);
2024 shader = rzalloc(NULL, struct vc4_compiled_shader);
2025
2026 shader->program_id = vc4->next_compiled_program_id++;
2027 if (stage == QSTAGE_FRAG) {
2028 bool input_live[c->num_input_semantics];
2029 struct simple_node *node;
2030
2031 memset(input_live, 0, sizeof(input_live));
2032 foreach(node, &c->instructions) {
2033 struct qinst *inst = (struct qinst *)node;
2034 for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) {
2035 if (inst->src[i].file == QFILE_VARY)
2036 input_live[inst->src[i].index] = true;
2037 }
2038 }
2039
2040 shader->input_semantics = ralloc_array(shader,
2041 struct vc4_varying_semantic,
2042 c->num_input_semantics);
2043
2044 for (int i = 0; i < c->num_input_semantics; i++) {
2045 struct vc4_varying_semantic *sem = &c->input_semantics[i];
2046
2047 if (!input_live[i])
2048 continue;
2049
2050 /* Skip non-VS-output inputs. */
2051 if (sem->semantic == (uint8_t)~0)
2052 continue;
2053
2054 if (sem->semantic == TGSI_SEMANTIC_COLOR)
2055 shader->color_inputs |= (1 << shader->num_inputs);
2056 shader->input_semantics[shader->num_inputs] = *sem;
2057 shader->num_inputs++;
2058 }
2059 } else {
2060 shader->num_inputs = c->num_inputs;
2061 }
2062
2063 copy_uniform_state_to_shader(shader, c);
2064 shader->bo = vc4_bo_alloc_mem(vc4->screen, c->qpu_insts,
2065 c->qpu_inst_count * sizeof(uint64_t),
2066 "code");
2067
2068 qir_compile_destroy(c);
2069
2070 struct vc4_key *dup_key;
2071 dup_key = malloc(key_size);
2072 memcpy(dup_key, key, key_size);
2073 util_hash_table_set(ht, dup_key, shader);
2074
2075 return shader;
2076 }
2077
2078 static void
2079 vc4_setup_shared_key(struct vc4_context *vc4, struct vc4_key *key,
2080 struct vc4_texture_stateobj *texstate)
2081 {
2082 for (int i = 0; i < texstate->num_textures; i++) {
2083 struct pipe_sampler_view *sampler = texstate->textures[i];
2084 struct pipe_sampler_state *sampler_state =
2085 texstate->samplers[i];
2086
2087 if (sampler) {
2088 key->tex[i].format = sampler->format;
2089 key->tex[i].swizzle[0] = sampler->swizzle_r;
2090 key->tex[i].swizzle[1] = sampler->swizzle_g;
2091 key->tex[i].swizzle[2] = sampler->swizzle_b;
2092 key->tex[i].swizzle[3] = sampler->swizzle_a;
2093 key->tex[i].compare_mode = sampler_state->compare_mode;
2094 key->tex[i].compare_func = sampler_state->compare_func;
2095 key->tex[i].wrap_s = sampler_state->wrap_s;
2096 key->tex[i].wrap_t = sampler_state->wrap_t;
2097 }
2098 }
2099
2100 key->ucp_enables = vc4->rasterizer->base.clip_plane_enable;
2101 }
2102
2103 static void
2104 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
2105 {
2106 struct vc4_fs_key local_key;
2107 struct vc4_fs_key *key = &local_key;
2108
2109 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2110 VC4_DIRTY_BLEND |
2111 VC4_DIRTY_FRAMEBUFFER |
2112 VC4_DIRTY_ZSA |
2113 VC4_DIRTY_RASTERIZER |
2114 VC4_DIRTY_FRAGTEX |
2115 VC4_DIRTY_TEXSTATE |
2116 VC4_DIRTY_PROG))) {
2117 return;
2118 }
2119
2120 memset(key, 0, sizeof(*key));
2121 vc4_setup_shared_key(vc4, &key->base, &vc4->fragtex);
2122 key->base.shader_state = vc4->prog.bind_fs;
2123 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
2124 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
2125 prim_mode <= PIPE_PRIM_LINE_STRIP);
2126 key->blend = vc4->blend->rt[0];
2127
2128 if (vc4->framebuffer.cbufs[0])
2129 key->color_format = vc4->framebuffer.cbufs[0]->format;
2130
2131 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
2132 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
2133 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
2134 key->depth_enabled = (vc4->zsa->base.depth.enabled ||
2135 key->stencil_enabled);
2136 if (vc4->zsa->base.alpha.enabled) {
2137 key->alpha_test = true;
2138 key->alpha_test_func = vc4->zsa->base.alpha.func;
2139 }
2140
2141 if (key->is_points) {
2142 key->point_sprite_mask =
2143 vc4->rasterizer->base.sprite_coord_enable;
2144 key->point_coord_upper_left =
2145 (vc4->rasterizer->base.sprite_coord_mode ==
2146 PIPE_SPRITE_COORD_UPPER_LEFT);
2147 }
2148
2149 key->light_twoside = vc4->rasterizer->base.light_twoside;
2150
2151 struct vc4_compiled_shader *old_fs = vc4->prog.fs;
2152 vc4->prog.fs = vc4_get_compiled_shader(vc4, QSTAGE_FRAG, &key->base);
2153 if (vc4->prog.fs == old_fs)
2154 return;
2155
2156 if (vc4->rasterizer->base.flatshade &&
2157 old_fs && vc4->prog.fs->color_inputs != old_fs->color_inputs) {
2158 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
2159 }
2160 }
2161
2162 static void
2163 vc4_update_compiled_vs(struct vc4_context *vc4, uint8_t prim_mode)
2164 {
2165 struct vc4_vs_key local_key;
2166 struct vc4_vs_key *key = &local_key;
2167
2168 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2169 VC4_DIRTY_RASTERIZER |
2170 VC4_DIRTY_VERTTEX |
2171 VC4_DIRTY_TEXSTATE |
2172 VC4_DIRTY_VTXSTATE |
2173 VC4_DIRTY_PROG))) {
2174 return;
2175 }
2176
2177 memset(key, 0, sizeof(*key));
2178 vc4_setup_shared_key(vc4, &key->base, &vc4->verttex);
2179 key->base.shader_state = vc4->prog.bind_vs;
2180 key->compiled_fs_id = vc4->prog.fs->program_id;
2181
2182 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
2183 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
2184
2185 key->per_vertex_point_size =
2186 (prim_mode == PIPE_PRIM_POINTS &&
2187 vc4->rasterizer->base.point_size_per_vertex);
2188
2189 vc4->prog.vs = vc4_get_compiled_shader(vc4, QSTAGE_VERT, &key->base);
2190 key->is_coord = true;
2191 vc4->prog.cs = vc4_get_compiled_shader(vc4, QSTAGE_COORD, &key->base);
2192 }
2193
2194 void
2195 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
2196 {
2197 vc4_update_compiled_fs(vc4, prim_mode);
2198 vc4_update_compiled_vs(vc4, prim_mode);
2199 }
2200
2201 static unsigned
2202 fs_cache_hash(void *key)
2203 {
2204 return _mesa_hash_data(key, sizeof(struct vc4_fs_key));
2205 }
2206
2207 static unsigned
2208 vs_cache_hash(void *key)
2209 {
2210 return _mesa_hash_data(key, sizeof(struct vc4_vs_key));
2211 }
2212
2213 static int
2214 fs_cache_compare(void *key1, void *key2)
2215 {
2216 return memcmp(key1, key2, sizeof(struct vc4_fs_key));
2217 }
2218
2219 static int
2220 vs_cache_compare(void *key1, void *key2)
2221 {
2222 return memcmp(key1, key2, sizeof(struct vc4_vs_key));
2223 }
2224
2225 struct delete_state {
2226 struct vc4_context *vc4;
2227 struct vc4_uncompiled_shader *shader_state;
2228 };
2229
2230 static enum pipe_error
2231 fs_delete_from_cache(void *in_key, void *in_value, void *data)
2232 {
2233 struct delete_state *del = data;
2234 struct vc4_fs_key *key = in_key;
2235 struct vc4_compiled_shader *shader = in_value;
2236
2237 if (key->base.shader_state == data) {
2238 util_hash_table_remove(del->vc4->fs_cache, key);
2239 vc4_bo_unreference(&shader->bo);
2240 ralloc_free(shader);
2241 }
2242
2243 return 0;
2244 }
2245
2246 static enum pipe_error
2247 vs_delete_from_cache(void *in_key, void *in_value, void *data)
2248 {
2249 struct delete_state *del = data;
2250 struct vc4_vs_key *key = in_key;
2251 struct vc4_compiled_shader *shader = in_value;
2252
2253 if (key->base.shader_state == data) {
2254 util_hash_table_remove(del->vc4->vs_cache, key);
2255 vc4_bo_unreference(&shader->bo);
2256 ralloc_free(shader);
2257 }
2258
2259 return 0;
2260 }
2261
2262 static void
2263 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
2264 {
2265 struct vc4_context *vc4 = vc4_context(pctx);
2266 struct vc4_uncompiled_shader *so = hwcso;
2267 struct delete_state del;
2268
2269 del.vc4 = vc4;
2270 del.shader_state = so;
2271 util_hash_table_foreach(vc4->fs_cache, fs_delete_from_cache, &del);
2272 util_hash_table_foreach(vc4->vs_cache, vs_delete_from_cache, &del);
2273
2274 if (so->twoside_tokens != so->base.tokens)
2275 free((void *)so->twoside_tokens);
2276 free((void *)so->base.tokens);
2277 free(so);
2278 }
2279
2280 static uint32_t translate_wrap(uint32_t p_wrap, bool using_nearest)
2281 {
2282 switch (p_wrap) {
2283 case PIPE_TEX_WRAP_REPEAT:
2284 return 0;
2285 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
2286 return 1;
2287 case PIPE_TEX_WRAP_MIRROR_REPEAT:
2288 return 2;
2289 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
2290 return 3;
2291 case PIPE_TEX_WRAP_CLAMP:
2292 return (using_nearest ? 1 : 3);
2293 default:
2294 fprintf(stderr, "Unknown wrap mode %d\n", p_wrap);
2295 assert(!"not reached");
2296 return 0;
2297 }
2298 }
2299
2300 static void
2301 write_texture_p0(struct vc4_context *vc4,
2302 struct vc4_texture_stateobj *texstate,
2303 uint32_t unit)
2304 {
2305 struct pipe_sampler_view *texture = texstate->textures[unit];
2306 struct vc4_resource *rsc = vc4_resource(texture->texture);
2307
2308 cl_reloc(vc4, &vc4->uniforms, rsc->bo,
2309 VC4_SET_FIELD(rsc->slices[0].offset >> 12, VC4_TEX_P0_OFFSET) |
2310 VC4_SET_FIELD(texture->u.tex.last_level -
2311 texture->u.tex.first_level, VC4_TEX_P0_MIPLVLS) |
2312 VC4_SET_FIELD(texture->target == PIPE_TEXTURE_CUBE,
2313 VC4_TEX_P0_CMMODE) |
2314 VC4_SET_FIELD(rsc->vc4_format & 7, VC4_TEX_P0_TYPE));
2315 }
2316
2317 static void
2318 write_texture_p1(struct vc4_context *vc4,
2319 struct vc4_texture_stateobj *texstate,
2320 uint32_t unit)
2321 {
2322 struct pipe_sampler_view *texture = texstate->textures[unit];
2323 struct vc4_resource *rsc = vc4_resource(texture->texture);
2324 struct pipe_sampler_state *sampler = texstate->samplers[unit];
2325 static const uint8_t minfilter_map[6] = {
2326 VC4_TEX_P1_MINFILT_NEAR_MIP_NEAR,
2327 VC4_TEX_P1_MINFILT_LIN_MIP_NEAR,
2328 VC4_TEX_P1_MINFILT_NEAR_MIP_LIN,
2329 VC4_TEX_P1_MINFILT_LIN_MIP_LIN,
2330 VC4_TEX_P1_MINFILT_NEAREST,
2331 VC4_TEX_P1_MINFILT_LINEAR,
2332 };
2333 static const uint32_t magfilter_map[] = {
2334 [PIPE_TEX_FILTER_NEAREST] = VC4_TEX_P1_MAGFILT_NEAREST,
2335 [PIPE_TEX_FILTER_LINEAR] = VC4_TEX_P1_MAGFILT_LINEAR,
2336 };
2337
2338 bool either_nearest =
2339 (sampler->mag_img_filter == PIPE_TEX_MIPFILTER_NEAREST ||
2340 sampler->min_img_filter == PIPE_TEX_MIPFILTER_NEAREST);
2341
2342 cl_u32(&vc4->uniforms,
2343 VC4_SET_FIELD(rsc->vc4_format >> 4, VC4_TEX_P1_TYPE4) |
2344 VC4_SET_FIELD(texture->texture->height0 & 2047,
2345 VC4_TEX_P1_HEIGHT) |
2346 VC4_SET_FIELD(texture->texture->width0 & 2047,
2347 VC4_TEX_P1_WIDTH) |
2348 VC4_SET_FIELD(magfilter_map[sampler->mag_img_filter],
2349 VC4_TEX_P1_MAGFILT) |
2350 VC4_SET_FIELD(minfilter_map[sampler->min_mip_filter * 2 +
2351 sampler->min_img_filter],
2352 VC4_TEX_P1_MINFILT) |
2353 VC4_SET_FIELD(translate_wrap(sampler->wrap_s, either_nearest),
2354 VC4_TEX_P1_WRAP_S) |
2355 VC4_SET_FIELD(translate_wrap(sampler->wrap_t, either_nearest),
2356 VC4_TEX_P1_WRAP_T));
2357 }
2358
2359 static void
2360 write_texture_p2(struct vc4_context *vc4,
2361 struct vc4_texture_stateobj *texstate,
2362 uint32_t data)
2363 {
2364 uint32_t unit = data & 0xffff;
2365 struct pipe_sampler_view *texture = texstate->textures[unit];
2366 struct vc4_resource *rsc = vc4_resource(texture->texture);
2367
2368 cl_u32(&vc4->uniforms,
2369 VC4_SET_FIELD(VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE,
2370 VC4_TEX_P2_PTYPE) |
2371 VC4_SET_FIELD(rsc->cube_map_stride >> 12, VC4_TEX_P2_CMST) |
2372 VC4_SET_FIELD((data >> 16) & 1, VC4_TEX_P2_BSLOD));
2373 }
2374
2375
2376 #define SWIZ(x,y,z,w) { \
2377 UTIL_FORMAT_SWIZZLE_##x, \
2378 UTIL_FORMAT_SWIZZLE_##y, \
2379 UTIL_FORMAT_SWIZZLE_##z, \
2380 UTIL_FORMAT_SWIZZLE_##w \
2381 }
2382
2383 static void
2384 write_texture_border_color(struct vc4_context *vc4,
2385 struct vc4_texture_stateobj *texstate,
2386 uint32_t unit)
2387 {
2388 struct pipe_sampler_state *sampler = texstate->samplers[unit];
2389 struct pipe_sampler_view *texture = texstate->textures[unit];
2390 struct vc4_resource *rsc = vc4_resource(texture->texture);
2391 union util_color uc;
2392
2393 const struct util_format_description *tex_format_desc =
2394 util_format_description(texture->format);
2395
2396 float border_color[4];
2397 for (int i = 0; i < 4; i++)
2398 border_color[i] = sampler->border_color.f[i];
2399 if (util_format_is_srgb(texture->format)) {
2400 for (int i = 0; i < 3; i++)
2401 border_color[i] =
2402 util_format_linear_to_srgb_float(border_color[i]);
2403 }
2404
2405 /* Turn the border color into the layout of channels that it would
2406 * have when stored as texture contents.
2407 */
2408 float storage_color[4];
2409 util_format_unswizzle_4f(storage_color,
2410 border_color,
2411 tex_format_desc->swizzle);
2412
2413 /* Now, pack so that when the vc4_format-sampled texture contents are
2414 * replaced with our border color, the vc4_get_format_swizzle()
2415 * swizzling will get the right channels.
2416 */
2417 if (util_format_is_depth_or_stencil(texture->format)) {
2418 uc.ui[0] = util_pack_z(PIPE_FORMAT_Z24X8_UNORM,
2419 sampler->border_color.f[0]) << 8;
2420 } else {
2421 switch (rsc->vc4_format) {
2422 default:
2423 case VC4_TEXTURE_TYPE_RGBA8888:
2424 util_pack_color(storage_color,
2425 PIPE_FORMAT_R8G8B8A8_UNORM, &uc);
2426 break;
2427 case VC4_TEXTURE_TYPE_RGBA4444:
2428 util_pack_color(storage_color,
2429 PIPE_FORMAT_A8B8G8R8_UNORM, &uc);
2430 break;
2431 case VC4_TEXTURE_TYPE_RGB565:
2432 util_pack_color(storage_color,
2433 PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
2434 break;
2435 case VC4_TEXTURE_TYPE_ALPHA:
2436 uc.ui[0] = float_to_ubyte(storage_color[0]) << 24;
2437 break;
2438 case VC4_TEXTURE_TYPE_LUMALPHA:
2439 uc.ui[0] = ((float_to_ubyte(storage_color[1]) << 24) |
2440 (float_to_ubyte(storage_color[0]) << 0));
2441 break;
2442 }
2443 }
2444
2445 cl_u32(&vc4->uniforms, uc.ui[0]);
2446 }
2447
2448 static uint32_t
2449 get_texrect_scale(struct vc4_texture_stateobj *texstate,
2450 enum quniform_contents contents,
2451 uint32_t data)
2452 {
2453 struct pipe_sampler_view *texture = texstate->textures[data];
2454 uint32_t dim;
2455
2456 if (contents == QUNIFORM_TEXRECT_SCALE_X)
2457 dim = texture->texture->width0;
2458 else
2459 dim = texture->texture->height0;
2460
2461 return fui(1.0f / dim);
2462 }
2463
2464 void
2465 vc4_write_uniforms(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
2466 struct vc4_constbuf_stateobj *cb,
2467 struct vc4_texture_stateobj *texstate)
2468 {
2469 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
2470 const uint32_t *gallium_uniforms = cb->cb[0].user_buffer;
2471
2472 cl_start_shader_reloc(&vc4->uniforms, uinfo->num_texture_samples);
2473
2474 for (int i = 0; i < uinfo->count; i++) {
2475
2476 switch (uinfo->contents[i]) {
2477 case QUNIFORM_CONSTANT:
2478 cl_u32(&vc4->uniforms, uinfo->data[i]);
2479 break;
2480 case QUNIFORM_UNIFORM:
2481 cl_u32(&vc4->uniforms,
2482 gallium_uniforms[uinfo->data[i]]);
2483 break;
2484 case QUNIFORM_VIEWPORT_X_SCALE:
2485 cl_f(&vc4->uniforms, vc4->viewport.scale[0] * 16.0f);
2486 break;
2487 case QUNIFORM_VIEWPORT_Y_SCALE:
2488 cl_f(&vc4->uniforms, vc4->viewport.scale[1] * 16.0f);
2489 break;
2490
2491 case QUNIFORM_VIEWPORT_Z_OFFSET:
2492 cl_f(&vc4->uniforms, vc4->viewport.translate[2]);
2493 break;
2494 case QUNIFORM_VIEWPORT_Z_SCALE:
2495 cl_f(&vc4->uniforms, vc4->viewport.scale[2]);
2496 break;
2497
2498 case QUNIFORM_USER_CLIP_PLANE:
2499 cl_f(&vc4->uniforms,
2500 vc4->clip.ucp[uinfo->data[i] / 4][uinfo->data[i] % 4]);
2501 break;
2502
2503 case QUNIFORM_TEXTURE_CONFIG_P0:
2504 write_texture_p0(vc4, texstate, uinfo->data[i]);
2505 break;
2506
2507 case QUNIFORM_TEXTURE_CONFIG_P1:
2508 write_texture_p1(vc4, texstate, uinfo->data[i]);
2509 break;
2510
2511 case QUNIFORM_TEXTURE_CONFIG_P2:
2512 write_texture_p2(vc4, texstate, uinfo->data[i]);
2513 break;
2514
2515 case QUNIFORM_TEXTURE_BORDER_COLOR:
2516 write_texture_border_color(vc4, texstate, uinfo->data[i]);
2517 break;
2518
2519 case QUNIFORM_TEXRECT_SCALE_X:
2520 case QUNIFORM_TEXRECT_SCALE_Y:
2521 cl_u32(&vc4->uniforms,
2522 get_texrect_scale(texstate,
2523 uinfo->contents[i],
2524 uinfo->data[i]));
2525 break;
2526
2527 case QUNIFORM_BLEND_CONST_COLOR:
2528 cl_f(&vc4->uniforms,
2529 vc4->blend_color.color[uinfo->data[i]]);
2530 break;
2531
2532 case QUNIFORM_STENCIL:
2533 cl_u32(&vc4->uniforms,
2534 vc4->zsa->stencil_uniforms[uinfo->data[i]] |
2535 (uinfo->data[i] <= 1 ?
2536 (vc4->stencil_ref.ref_value[uinfo->data[i]] << 8) :
2537 0));
2538 break;
2539
2540 case QUNIFORM_ALPHA_REF:
2541 cl_f(&vc4->uniforms, vc4->zsa->base.alpha.ref_value);
2542 break;
2543 }
2544 #if 0
2545 uint32_t written_val = *(uint32_t *)(vc4->uniforms.next - 4);
2546 fprintf(stderr, "%p: %d / 0x%08x (%f)\n",
2547 shader, i, written_val, uif(written_val));
2548 #endif
2549 }
2550 }
2551
2552 static void
2553 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
2554 {
2555 struct vc4_context *vc4 = vc4_context(pctx);
2556 vc4->prog.bind_fs = hwcso;
2557 vc4->prog.dirty |= VC4_SHADER_DIRTY_FP;
2558 vc4->dirty |= VC4_DIRTY_PROG;
2559 }
2560
2561 static void
2562 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
2563 {
2564 struct vc4_context *vc4 = vc4_context(pctx);
2565 vc4->prog.bind_vs = hwcso;
2566 vc4->prog.dirty |= VC4_SHADER_DIRTY_VP;
2567 vc4->dirty |= VC4_DIRTY_PROG;
2568 }
2569
2570 void
2571 vc4_program_init(struct pipe_context *pctx)
2572 {
2573 struct vc4_context *vc4 = vc4_context(pctx);
2574
2575 pctx->create_vs_state = vc4_shader_state_create;
2576 pctx->delete_vs_state = vc4_shader_state_delete;
2577
2578 pctx->create_fs_state = vc4_shader_state_create;
2579 pctx->delete_fs_state = vc4_shader_state_delete;
2580
2581 pctx->bind_fs_state = vc4_fp_state_bind;
2582 pctx->bind_vs_state = vc4_vp_state_bind;
2583
2584 vc4->fs_cache = util_hash_table_create(fs_cache_hash, fs_cache_compare);
2585 vc4->vs_cache = util_hash_table_create(vs_cache_hash, vs_cache_compare);
2586 }