projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
vc4: Pack VPM attr contents according to just the size of the attribute.
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "pipe/p_state.h"
27 #include "util/u_format.h"
28 #include "util/u_hash.h"
29 #include "util/u_memory.h"
30 #include "util/u_pack_color.h"
31 #include "util/format_srgb.h"
32 #include "util/ralloc.h"
33 #include "util/hash_table.h"
34 #include "tgsi/tgsi_dump.h"
35 #include "tgsi/tgsi_info.h"
36 #include "tgsi/tgsi_lowering.h"
37
38 #include "vc4_context.h"
39 #include "vc4_qpu.h"
40 #include "vc4_qir.h"
41 #ifdef USE_VC4_SIMULATOR
42 #include "simpenrose/simpenrose.h"
43 #endif
44
45 struct vc4_key {
46 struct vc4_uncompiled_shader *shader_state;
47 struct {
48 enum pipe_format format;
49 unsigned compare_mode:1;
50 unsigned compare_func:3;
51 unsigned wrap_s:3;
52 unsigned wrap_t:3;
53 uint8_t swizzle[4];
54 } tex[VC4_MAX_TEXTURE_SAMPLERS];
55 uint8_t ucp_enables;
56 };
57
58 struct vc4_fs_key {
59 struct vc4_key base;
60 enum pipe_format color_format;
61 bool depth_enabled;
62 bool stencil_enabled;
63 bool stencil_twoside;
64 bool stencil_full_writemasks;
65 bool is_points;
66 bool is_lines;
67 bool alpha_test;
68 bool point_coord_upper_left;
69 bool light_twoside;
70 uint8_t alpha_test_func;
71 uint8_t logicop_func;
72 uint32_t point_sprite_mask;
73
74 struct pipe_rt_blend_state blend;
75 };
76
77 struct vc4_vs_key {
78 struct vc4_key base;
79
80 /**
81 * This is a proxy for the array of FS input semantics, which is
82 * larger than we would want to put in the key.
83 */
84 uint64_t compiled_fs_id;
85
86 enum pipe_format attr_formats[8];
87 bool is_coord;
88 bool per_vertex_point_size;
89 };
90
91 static void
92 resize_qreg_array(struct vc4_compile *c,
93 struct qreg **regs,
94 uint32_t *size,
95 uint32_t decl_size)
96 {
97 if (*size >= decl_size)
98 return;
99
100 uint32_t old_size = *size;
101 *size = MAX2(*size * 2, decl_size);
102 *regs = reralloc(c, *regs, struct qreg, *size);
103 if (!*regs) {
104 fprintf(stderr, "Malloc failure\n");
105 abort();
106 }
107
108 for (uint32_t i = old_size; i < *size; i++)
109 (*regs)[i] = c->undef;
110 }
111
112 static struct qreg
113 add_uniform(struct vc4_compile *c,
114 enum quniform_contents contents,
115 uint32_t data)
116 {
117 for (int i = 0; i < c->num_uniforms; i++) {
118 if (c->uniform_contents[i] == contents &&
119 c->uniform_data[i] == data) {
120 return (struct qreg) { QFILE_UNIF, i };
121 }
122 }
123
124 uint32_t uniform = c->num_uniforms++;
125 struct qreg u = { QFILE_UNIF, uniform };
126
127 if (uniform >= c->uniform_array_size) {
128 c->uniform_array_size = MAX2(MAX2(16, uniform + 1),
129 c->uniform_array_size * 2);
130
131 c->uniform_data = reralloc(c, c->uniform_data,
132 uint32_t,
133 c->uniform_array_size);
134 c->uniform_contents = reralloc(c, c->uniform_contents,
135 enum quniform_contents,
136 c->uniform_array_size);
137 }
138
139 c->uniform_contents[uniform] = contents;
140 c->uniform_data[uniform] = data;
141
142 return u;
143 }
144
145 static struct qreg
146 get_temp_for_uniform(struct vc4_compile *c, enum quniform_contents contents,
147 uint32_t data)
148 {
149 struct qreg u = add_uniform(c, contents, data);
150 struct qreg t = qir_MOV(c, u);
151 return t;
152 }
153
154 static struct qreg
155 qir_uniform_ui(struct vc4_compile *c, uint32_t ui)
156 {
157 return get_temp_for_uniform(c, QUNIFORM_CONSTANT, ui);
158 }
159
160 static struct qreg
161 qir_uniform_f(struct vc4_compile *c, float f)
162 {
163 return qir_uniform_ui(c, fui(f));
164 }
165
166 static struct qreg
167 indirect_uniform_load(struct vc4_compile *c,
168 struct tgsi_full_src_register *src, int swiz)
169 {
170 struct tgsi_ind_register *indirect = &src->Indirect;
171 struct vc4_compiler_ubo_range *range = &c->ubo_ranges[indirect->ArrayID];
172 if (!range->used) {
173 range->used = true;
174 range->dst_offset = c->next_ubo_dst_offset;
175 c->next_ubo_dst_offset += range->size;
176 c->num_ubo_ranges++;
177 };
178
179 assert(src->Register.Indirect);
180 assert(indirect->File == TGSI_FILE_ADDRESS);
181
182 struct qreg addr_val = c->addr[indirect->Swizzle];
183 struct qreg indirect_offset =
184 qir_ADD(c, addr_val, qir_uniform_ui(c,
185 range->dst_offset +
186 (src->Register.Index * 16)+
187 swiz * 4));
188 indirect_offset = qir_MIN(c, indirect_offset, qir_uniform_ui(c, (range->dst_offset +
189 range->size - 4)));
190
191 qir_TEX_DIRECT(c, indirect_offset, add_uniform(c, QUNIFORM_UBO_ADDR, 0));
192 struct qreg r4 = qir_TEX_RESULT(c);
193 c->num_texture_samples++;
194 return qir_MOV(c, r4);
195 }
196
197 static struct qreg
198 get_src(struct vc4_compile *c, unsigned tgsi_op,
199 struct tgsi_full_src_register *full_src, int i)
200 {
201 struct tgsi_src_register *src = &full_src->Register;
202 struct qreg r = c->undef;
203
204 uint32_t s = i;
205 switch (i) {
206 case TGSI_SWIZZLE_X:
207 s = src->SwizzleX;
208 break;
209 case TGSI_SWIZZLE_Y:
210 s = src->SwizzleY;
211 break;
212 case TGSI_SWIZZLE_Z:
213 s = src->SwizzleZ;
214 break;
215 case TGSI_SWIZZLE_W:
216 s = src->SwizzleW;
217 break;
218 default:
219 abort();
220 }
221
222 switch (src->File) {
223 case TGSI_FILE_NULL:
224 return r;
225 case TGSI_FILE_TEMPORARY:
226 r = c->temps[src->Index * 4 + s];
227 break;
228 case TGSI_FILE_IMMEDIATE:
229 r = c->consts[src->Index * 4 + s];
230 break;
231 case TGSI_FILE_CONSTANT:
232 if (src->Indirect) {
233 r = indirect_uniform_load(c, full_src, s);
234 } else {
235 r = get_temp_for_uniform(c, QUNIFORM_UNIFORM,
236 src->Index * 4 + s);
237 }
238 break;
239 case TGSI_FILE_INPUT:
240 r = c->inputs[src->Index * 4 + s];
241 break;
242 case TGSI_FILE_SAMPLER:
243 case TGSI_FILE_SAMPLER_VIEW:
244 r = c->undef;
245 break;
246 default:
247 fprintf(stderr, "unknown src file %d\n", src->File);
248 abort();
249 }
250
251 if (src->Absolute)
252 r = qir_FMAXABS(c, r, r);
253
254 if (src->Negate) {
255 switch (tgsi_opcode_infer_src_type(tgsi_op)) {
256 case TGSI_TYPE_SIGNED:
257 case TGSI_TYPE_UNSIGNED:
258 r = qir_SUB(c, qir_uniform_ui(c, 0), r);
259 break;
260 default:
261 r = qir_FSUB(c, qir_uniform_f(c, 0.0), r);
262 break;
263 }
264 }
265
266 return r;
267 };
268
269
270 static void
271 update_dst(struct vc4_compile *c, struct tgsi_full_instruction *tgsi_inst,
272 int i, struct qreg val)
273 {
274 struct tgsi_dst_register *tgsi_dst = &tgsi_inst->Dst[0].Register;
275
276 assert(!tgsi_dst->Indirect);
277
278 switch (tgsi_dst->File) {
279 case TGSI_FILE_TEMPORARY:
280 c->temps[tgsi_dst->Index * 4 + i] = val;
281 break;
282 case TGSI_FILE_OUTPUT:
283 c->outputs[tgsi_dst->Index * 4 + i] = val;
284 c->num_outputs = MAX2(c->num_outputs,
285 tgsi_dst->Index * 4 + i + 1);
286 break;
287 case TGSI_FILE_ADDRESS:
288 assert(tgsi_dst->Index == 0);
289 c->addr[i] = val;
290 break;
291 default:
292 fprintf(stderr, "unknown dst file %d\n", tgsi_dst->File);
293 abort();
294 }
295 };
296
297 static struct qreg
298 get_swizzled_channel(struct vc4_compile *c,
299 struct qreg *srcs, int swiz)
300 {
301 switch (swiz) {
302 default:
303 case UTIL_FORMAT_SWIZZLE_NONE:
304 fprintf(stderr, "warning: unknown swizzle\n");
305 /* FALLTHROUGH */
306 case UTIL_FORMAT_SWIZZLE_0:
307 return qir_uniform_f(c, 0.0);
308 case UTIL_FORMAT_SWIZZLE_1:
309 return qir_uniform_f(c, 1.0);
310 case UTIL_FORMAT_SWIZZLE_X:
311 case UTIL_FORMAT_SWIZZLE_Y:
312 case UTIL_FORMAT_SWIZZLE_Z:
313 case UTIL_FORMAT_SWIZZLE_W:
314 return srcs[swiz];
315 }
316 }
317
318 static struct qreg
319 tgsi_to_qir_alu(struct vc4_compile *c,
320 struct tgsi_full_instruction *tgsi_inst,
321 enum qop op, struct qreg *src, int i)
322 {
323 struct qreg dst = qir_get_temp(c);
324 qir_emit(c, qir_inst4(op, dst,
325 src[0 * 4 + i],
326 src[1 * 4 + i],
327 src[2 * 4 + i],
328 c->undef));
329 return dst;
330 }
331
332 static struct qreg
333 tgsi_to_qir_scalar(struct vc4_compile *c,
334 struct tgsi_full_instruction *tgsi_inst,
335 enum qop op, struct qreg *src, int i)
336 {
337 struct qreg dst = qir_get_temp(c);
338 qir_emit(c, qir_inst(op, dst,
339 src[0 * 4 + 0],
340 c->undef));
341 return dst;
342 }
343
344 static struct qreg
345 tgsi_to_qir_rcp(struct vc4_compile *c,
346 struct tgsi_full_instruction *tgsi_inst,
347 enum qop op, struct qreg *src, int i)
348 {
349 struct qreg x = src[0 * 4 + 0];
350 struct qreg r = qir_RCP(c, x);
351
352 /* Apply a Newton-Raphson step to improve the accuracy. */
353 r = qir_FMUL(c, r, qir_FSUB(c,
354 qir_uniform_f(c, 2.0),
355 qir_FMUL(c, x, r)));
356
357 return r;
358 }
359
360 static struct qreg
361 tgsi_to_qir_rsq(struct vc4_compile *c,
362 struct tgsi_full_instruction *tgsi_inst,
363 enum qop op, struct qreg *src, int i)
364 {
365 struct qreg x = src[0 * 4 + 0];
366 struct qreg r = qir_RSQ(c, x);
367
368 /* Apply a Newton-Raphson step to improve the accuracy. */
369 r = qir_FMUL(c, r, qir_FSUB(c,
370 qir_uniform_f(c, 1.5),
371 qir_FMUL(c,
372 qir_uniform_f(c, 0.5),
373 qir_FMUL(c, x,
374 qir_FMUL(c, r, r)))));
375
376 return r;
377 }
378
379 static struct qreg
380 qir_srgb_decode(struct vc4_compile *c, struct qreg srgb)
381 {
382 struct qreg low = qir_FMUL(c, srgb, qir_uniform_f(c, 1.0 / 12.92));
383 struct qreg high = qir_POW(c,
384 qir_FMUL(c,
385 qir_FADD(c,
386 srgb,
387 qir_uniform_f(c, 0.055)),
388 qir_uniform_f(c, 1.0 / 1.055)),
389 qir_uniform_f(c, 2.4));
390
391 qir_SF(c, qir_FSUB(c, srgb, qir_uniform_f(c, 0.04045)));
392 return qir_SEL_X_Y_NS(c, low, high);
393 }
394
395 static struct qreg
396 qir_srgb_encode(struct vc4_compile *c, struct qreg linear)
397 {
398 struct qreg low = qir_FMUL(c, linear, qir_uniform_f(c, 12.92));
399 struct qreg high = qir_FSUB(c,
400 qir_FMUL(c,
401 qir_uniform_f(c, 1.055),
402 qir_POW(c,
403 linear,
404 qir_uniform_f(c, 0.41666))),
405 qir_uniform_f(c, 0.055));
406
407 qir_SF(c, qir_FSUB(c, linear, qir_uniform_f(c, 0.0031308)));
408 return qir_SEL_X_Y_NS(c, low, high);
409 }
410
411 static struct qreg
412 tgsi_to_qir_umul(struct vc4_compile *c,
413 struct tgsi_full_instruction *tgsi_inst,
414 enum qop op, struct qreg *src, int i)
415 {
416 struct qreg src0_hi = qir_SHR(c, src[0 * 4 + i],
417 qir_uniform_ui(c, 16));
418 struct qreg src0_lo = qir_AND(c, src[0 * 4 + i],
419 qir_uniform_ui(c, 0xffff));
420 struct qreg src1_hi = qir_SHR(c, src[1 * 4 + i],
421 qir_uniform_ui(c, 16));
422 struct qreg src1_lo = qir_AND(c, src[1 * 4 + i],
423 qir_uniform_ui(c, 0xffff));
424
425 struct qreg hilo = qir_MUL24(c, src0_hi, src1_lo);
426 struct qreg lohi = qir_MUL24(c, src0_lo, src1_hi);
427 struct qreg lolo = qir_MUL24(c, src0_lo, src1_lo);
428
429 return qir_ADD(c, lolo, qir_SHL(c,
430 qir_ADD(c, hilo, lohi),
431 qir_uniform_ui(c, 16)));
432 }
433
434 static struct qreg
435 tgsi_to_qir_umad(struct vc4_compile *c,
436 struct tgsi_full_instruction *tgsi_inst,
437 enum qop op, struct qreg *src, int i)
438 {
439 return qir_ADD(c, tgsi_to_qir_umul(c, NULL, 0, src, i), src[2 * 4 + i]);
440 }
441
442 static struct qreg
443 tgsi_to_qir_idiv(struct vc4_compile *c,
444 struct tgsi_full_instruction *tgsi_inst,
445 enum qop op, struct qreg *src, int i)
446 {
447 return qir_FTOI(c, qir_FMUL(c,
448 qir_ITOF(c, src[0 * 4 + i]),
449 qir_RCP(c, qir_ITOF(c, src[1 * 4 + i]))));
450 }
451
452 static struct qreg
453 tgsi_to_qir_ineg(struct vc4_compile *c,
454 struct tgsi_full_instruction *tgsi_inst,
455 enum qop op, struct qreg *src, int i)
456 {
457 return qir_SUB(c, qir_uniform_ui(c, 0), src[0 * 4 + i]);
458 }
459
460 static struct qreg
461 tgsi_to_qir_seq(struct vc4_compile *c,
462 struct tgsi_full_instruction *tgsi_inst,
463 enum qop op, struct qreg *src, int i)
464 {
465 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
466 return qir_SEL_X_0_ZS(c, qir_uniform_f(c, 1.0));
467 }
468
469 static struct qreg
470 tgsi_to_qir_sne(struct vc4_compile *c,
471 struct tgsi_full_instruction *tgsi_inst,
472 enum qop op, struct qreg *src, int i)
473 {
474 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
475 return qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0));
476 }
477
478 static struct qreg
479 tgsi_to_qir_slt(struct vc4_compile *c,
480 struct tgsi_full_instruction *tgsi_inst,
481 enum qop op, struct qreg *src, int i)
482 {
483 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
484 return qir_SEL_X_0_NS(c, qir_uniform_f(c, 1.0));
485 }
486
487 static struct qreg
488 tgsi_to_qir_sge(struct vc4_compile *c,
489 struct tgsi_full_instruction *tgsi_inst,
490 enum qop op, struct qreg *src, int i)
491 {
492 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
493 return qir_SEL_X_0_NC(c, qir_uniform_f(c, 1.0));
494 }
495
496 static struct qreg
497 tgsi_to_qir_fseq(struct vc4_compile *c,
498 struct tgsi_full_instruction *tgsi_inst,
499 enum qop op, struct qreg *src, int i)
500 {
501 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
502 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
503 }
504
505 static struct qreg
506 tgsi_to_qir_fsne(struct vc4_compile *c,
507 struct tgsi_full_instruction *tgsi_inst,
508 enum qop op, struct qreg *src, int i)
509 {
510 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
511 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
512 }
513
514 static struct qreg
515 tgsi_to_qir_fslt(struct vc4_compile *c,
516 struct tgsi_full_instruction *tgsi_inst,
517 enum qop op, struct qreg *src, int i)
518 {
519 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
520 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
521 }
522
523 static struct qreg
524 tgsi_to_qir_fsge(struct vc4_compile *c,
525 struct tgsi_full_instruction *tgsi_inst,
526 enum qop op, struct qreg *src, int i)
527 {
528 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
529 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
530 }
531
532 static struct qreg
533 tgsi_to_qir_useq(struct vc4_compile *c,
534 struct tgsi_full_instruction *tgsi_inst,
535 enum qop op, struct qreg *src, int i)
536 {
537 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
538 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
539 }
540
541 static struct qreg
542 tgsi_to_qir_usne(struct vc4_compile *c,
543 struct tgsi_full_instruction *tgsi_inst,
544 enum qop op, struct qreg *src, int i)
545 {
546 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
547 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
548 }
549
550 static struct qreg
551 tgsi_to_qir_islt(struct vc4_compile *c,
552 struct tgsi_full_instruction *tgsi_inst,
553 enum qop op, struct qreg *src, int i)
554 {
555 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
556 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
557 }
558
559 static struct qreg
560 tgsi_to_qir_isge(struct vc4_compile *c,
561 struct tgsi_full_instruction *tgsi_inst,
562 enum qop op, struct qreg *src, int i)
563 {
564 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
565 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
566 }
567
568 static struct qreg
569 tgsi_to_qir_cmp(struct vc4_compile *c,
570 struct tgsi_full_instruction *tgsi_inst,
571 enum qop op, struct qreg *src, int i)
572 {
573 qir_SF(c, src[0 * 4 + i]);
574 return qir_SEL_X_Y_NS(c,
575 src[1 * 4 + i],
576 src[2 * 4 + i]);
577 }
578
579 static struct qreg
580 tgsi_to_qir_ucmp(struct vc4_compile *c,
581 struct tgsi_full_instruction *tgsi_inst,
582 enum qop op, struct qreg *src, int i)
583 {
584 qir_SF(c, src[0 * 4 + i]);
585 return qir_SEL_X_Y_ZC(c,
586 src[1 * 4 + i],
587 src[2 * 4 + i]);
588 }
589
590 static struct qreg
591 tgsi_to_qir_mad(struct vc4_compile *c,
592 struct tgsi_full_instruction *tgsi_inst,
593 enum qop op, struct qreg *src, int i)
594 {
595 return qir_FADD(c,
596 qir_FMUL(c,
597 src[0 * 4 + i],
598 src[1 * 4 + i]),
599 src[2 * 4 + i]);
600 }
601
602 static struct qreg
603 tgsi_to_qir_lrp(struct vc4_compile *c,
604 struct tgsi_full_instruction *tgsi_inst,
605 enum qop op, struct qreg *src, int i)
606 {
607 struct qreg src0 = src[0 * 4 + i];
608 struct qreg src1 = src[1 * 4 + i];
609 struct qreg src2 = src[2 * 4 + i];
610
611 /* LRP is:
612 * src0 * src1 + (1 - src0) * src2.
613 * -> src0 * src1 + src2 - src0 * src2
614 * -> src2 + src0 * (src1 - src2)
615 */
616 return qir_FADD(c, src2, qir_FMUL(c, src0, qir_FSUB(c, src1, src2)));
617
618 }
619
620 static void
621 tgsi_to_qir_tex(struct vc4_compile *c,
622 struct tgsi_full_instruction *tgsi_inst,
623 enum qop op, struct qreg *src)
624 {
625 assert(!tgsi_inst->Instruction.Saturate);
626
627 struct qreg s = src[0 * 4 + 0];
628 struct qreg t = src[0 * 4 + 1];
629 struct qreg r = src[0 * 4 + 2];
630 uint32_t unit = tgsi_inst->Src[1].Register.Index;
631 bool is_txl = tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL;
632
633 struct qreg proj = c->undef;
634 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
635 proj = qir_RCP(c, src[0 * 4 + 3]);
636 s = qir_FMUL(c, s, proj);
637 t = qir_FMUL(c, t, proj);
638 }
639
640 struct qreg texture_u[] = {
641 add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit),
642 add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
643 add_uniform(c, QUNIFORM_CONSTANT, 0),
644 add_uniform(c, QUNIFORM_CONSTANT, 0),
645 };
646 uint32_t next_texture_u = 0;
647
648 /* There is no native support for GL texture rectangle coordinates, so
649 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
650 * 1]).
651 */
652 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_RECT ||
653 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT) {
654 s = qir_FMUL(c, s,
655 get_temp_for_uniform(c,
656 QUNIFORM_TEXRECT_SCALE_X,
657 unit));
658 t = qir_FMUL(c, t,
659 get_temp_for_uniform(c,
660 QUNIFORM_TEXRECT_SCALE_Y,
661 unit));
662 }
663
664 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
665 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
666 is_txl) {
667 texture_u[2] = add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P2,
668 unit | (is_txl << 16));
669 }
670
671 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
672 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE) {
673 struct qreg ma = qir_FMAXABS(c, qir_FMAXABS(c, s, t), r);
674 struct qreg rcp_ma = qir_RCP(c, ma);
675 s = qir_FMUL(c, s, rcp_ma);
676 t = qir_FMUL(c, t, rcp_ma);
677 r = qir_FMUL(c, r, rcp_ma);
678
679 qir_TEX_R(c, r, texture_u[next_texture_u++]);
680 } else if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
681 c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP ||
682 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
683 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
684 qir_TEX_R(c, get_temp_for_uniform(c, QUNIFORM_TEXTURE_BORDER_COLOR, unit),
685 texture_u[next_texture_u++]);
686 }
687
688 if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP) {
689 s = qir_FMIN(c, qir_FMAX(c, s, qir_uniform_f(c, 0.0)),
690 qir_uniform_f(c, 1.0));
691 }
692
693 if (c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
694 t = qir_FMIN(c, qir_FMAX(c, t, qir_uniform_f(c, 0.0)),
695 qir_uniform_f(c, 1.0));
696 }
697
698 qir_TEX_T(c, t, texture_u[next_texture_u++]);
699
700 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
701 tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL)
702 qir_TEX_B(c, src[0 * 4 + 3], texture_u[next_texture_u++]);
703
704 qir_TEX_S(c, s, texture_u[next_texture_u++]);
705
706 c->num_texture_samples++;
707 struct qreg r4 = qir_TEX_RESULT(c);
708
709 enum pipe_format format = c->key->tex[unit].format;
710
711 struct qreg unpacked[4];
712 if (util_format_is_depth_or_stencil(format)) {
713 struct qreg depthf = qir_ITOF(c, qir_SHR(c, r4,
714 qir_uniform_ui(c, 8)));
715 struct qreg normalized = qir_FMUL(c, depthf,
716 qir_uniform_f(c, 1.0f/0xffffff));
717
718 struct qreg depth_output;
719
720 struct qreg one = qir_uniform_f(c, 1.0f);
721 if (c->key->tex[unit].compare_mode) {
722 struct qreg compare = src[0 * 4 + 2];
723
724 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP)
725 compare = qir_FMUL(c, compare, proj);
726
727 switch (c->key->tex[unit].compare_func) {
728 case PIPE_FUNC_NEVER:
729 depth_output = qir_uniform_f(c, 0.0f);
730 break;
731 case PIPE_FUNC_ALWAYS:
732 depth_output = one;
733 break;
734 case PIPE_FUNC_EQUAL:
735 qir_SF(c, qir_FSUB(c, compare, normalized));
736 depth_output = qir_SEL_X_0_ZS(c, one);
737 break;
738 case PIPE_FUNC_NOTEQUAL:
739 qir_SF(c, qir_FSUB(c, compare, normalized));
740 depth_output = qir_SEL_X_0_ZC(c, one);
741 break;
742 case PIPE_FUNC_GREATER:
743 qir_SF(c, qir_FSUB(c, compare, normalized));
744 depth_output = qir_SEL_X_0_NC(c, one);
745 break;
746 case PIPE_FUNC_GEQUAL:
747 qir_SF(c, qir_FSUB(c, normalized, compare));
748 depth_output = qir_SEL_X_0_NS(c, one);
749 break;
750 case PIPE_FUNC_LESS:
751 qir_SF(c, qir_FSUB(c, compare, normalized));
752 depth_output = qir_SEL_X_0_NS(c, one);
753 break;
754 case PIPE_FUNC_LEQUAL:
755 qir_SF(c, qir_FSUB(c, normalized, compare));
756 depth_output = qir_SEL_X_0_NC(c, one);
757 break;
758 }
759 } else {
760 depth_output = normalized;
761 }
762
763 for (int i = 0; i < 4; i++)
764 unpacked[i] = depth_output;
765 } else {
766 for (int i = 0; i < 4; i++)
767 unpacked[i] = qir_R4_UNPACK(c, r4, i);
768 }
769
770 const uint8_t *format_swiz = vc4_get_format_swizzle(format);
771 struct qreg texture_output[4];
772 for (int i = 0; i < 4; i++) {
773 texture_output[i] = get_swizzled_channel(c, unpacked,
774 format_swiz[i]);
775 }
776
777 if (util_format_is_srgb(format)) {
778 for (int i = 0; i < 3; i++)
779 texture_output[i] = qir_srgb_decode(c,
780 texture_output[i]);
781 }
782
783 for (int i = 0; i < 4; i++) {
784 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
785 continue;
786
787 update_dst(c, tgsi_inst, i,
788 get_swizzled_channel(c, texture_output,
789 c->key->tex[unit].swizzle[i]));
790 }
791 }
792
793 static struct qreg
794 tgsi_to_qir_trunc(struct vc4_compile *c,
795 struct tgsi_full_instruction *tgsi_inst,
796 enum qop op, struct qreg *src, int i)
797 {
798 return qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
799 }
800
801 /**
802 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
803 * to zero).
804 */
805 static struct qreg
806 tgsi_to_qir_frc(struct vc4_compile *c,
807 struct tgsi_full_instruction *tgsi_inst,
808 enum qop op, struct qreg *src, int i)
809 {
810 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
811 struct qreg diff = qir_FSUB(c, src[0 * 4 + i], trunc);
812 qir_SF(c, diff);
813 return qir_SEL_X_Y_NS(c,
814 qir_FADD(c, diff, qir_uniform_f(c, 1.0)),
815 diff);
816 }
817
818 /**
819 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
820 * zero).
821 */
822 static struct qreg
823 tgsi_to_qir_flr(struct vc4_compile *c,
824 struct tgsi_full_instruction *tgsi_inst,
825 enum qop op, struct qreg *src, int i)
826 {
827 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
828
829 /* This will be < 0 if we truncated and the truncation was of a value
830 * that was < 0 in the first place.
831 */
832 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], trunc));
833
834 return qir_SEL_X_Y_NS(c,
835 qir_FSUB(c, trunc, qir_uniform_f(c, 1.0)),
836 trunc);
837 }
838
839 /**
840 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
841 * zero).
842 */
843 static struct qreg
844 tgsi_to_qir_ceil(struct vc4_compile *c,
845 struct tgsi_full_instruction *tgsi_inst,
846 enum qop op, struct qreg *src, int i)
847 {
848 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
849
850 /* This will be < 0 if we truncated and the truncation was of a value
851 * that was > 0 in the first place.
852 */
853 qir_SF(c, qir_FSUB(c, trunc, src[0 * 4 + i]));
854
855 return qir_SEL_X_Y_NS(c,
856 qir_FADD(c, trunc, qir_uniform_f(c, 1.0)),
857 trunc);
858 }
859
860 static struct qreg
861 tgsi_to_qir_abs(struct vc4_compile *c,
862 struct tgsi_full_instruction *tgsi_inst,
863 enum qop op, struct qreg *src, int i)
864 {
865 struct qreg arg = src[0 * 4 + i];
866 return qir_FMAXABS(c, arg, arg);
867 }
868
869 /* Note that this instruction replicates its result from the x channel */
870 static struct qreg
871 tgsi_to_qir_sin(struct vc4_compile *c,
872 struct tgsi_full_instruction *tgsi_inst,
873 enum qop op, struct qreg *src, int i)
874 {
875 float coeff[] = {
876 -2.0 * M_PI,
877 pow(2.0 * M_PI, 3) / (3 * 2 * 1),
878 -pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
879 pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
880 -pow(2.0 * M_PI, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
881 };
882
883 struct qreg scaled_x =
884 qir_FMUL(c,
885 src[0 * 4 + 0],
886 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
887
888 struct qreg x = qir_FADD(c,
889 tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0),
890 qir_uniform_f(c, -0.5));
891 struct qreg x2 = qir_FMUL(c, x, x);
892 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
893 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
894 x = qir_FMUL(c, x, x2);
895 sum = qir_FADD(c,
896 sum,
897 qir_FMUL(c,
898 x,
899 qir_uniform_f(c, coeff[i])));
900 }
901 return sum;
902 }
903
904 /* Note that this instruction replicates its result from the x channel */
905 static struct qreg
906 tgsi_to_qir_cos(struct vc4_compile *c,
907 struct tgsi_full_instruction *tgsi_inst,
908 enum qop op, struct qreg *src, int i)
909 {
910 float coeff[] = {
911 -1.0f,
912 pow(2.0 * M_PI, 2) / (2 * 1),
913 -pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
914 pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
915 -pow(2.0 * M_PI, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
916 pow(2.0 * M_PI, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
917 };
918
919 struct qreg scaled_x =
920 qir_FMUL(c, src[0 * 4 + 0],
921 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
922 struct qreg x_frac = qir_FADD(c,
923 tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0),
924 qir_uniform_f(c, -0.5));
925
926 struct qreg sum = qir_uniform_f(c, coeff[0]);
927 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
928 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
929 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
930 if (i != 1)
931 x = qir_FMUL(c, x, x2);
932
933 struct qreg mul = qir_FMUL(c,
934 x,
935 qir_uniform_f(c, coeff[i]));
936 if (i == 0)
937 sum = mul;
938 else
939 sum = qir_FADD(c, sum, mul);
940 }
941 return sum;
942 }
943
944 static struct qreg
945 tgsi_to_qir_clamp(struct vc4_compile *c,
946 struct tgsi_full_instruction *tgsi_inst,
947 enum qop op, struct qreg *src, int i)
948 {
949 return qir_FMAX(c, qir_FMIN(c,
950 src[0 * 4 + i],
951 src[2 * 4 + i]),
952 src[1 * 4 + i]);
953 }
954
955 static struct qreg
956 tgsi_to_qir_ssg(struct vc4_compile *c,
957 struct tgsi_full_instruction *tgsi_inst,
958 enum qop op, struct qreg *src, int i)
959 {
960 qir_SF(c, src[0 * 4 + i]);
961 return qir_SEL_X_Y_NC(c,
962 qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0)),
963 qir_uniform_f(c, -1.0));
964 }
965
966 /* Compare to tgsi_to_qir_flr() for the floor logic. */
967 static struct qreg
968 tgsi_to_qir_arl(struct vc4_compile *c,
969 struct tgsi_full_instruction *tgsi_inst,
970 enum qop op, struct qreg *src, int i)
971 {
972 struct qreg trunc = qir_FTOI(c, src[0 * 4 + i]);
973 struct qreg scaled = qir_SHL(c, trunc, qir_uniform_ui(c, 4));
974
975 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], qir_ITOF(c, trunc)));
976
977 return qir_SEL_X_Y_NS(c, qir_SUB(c, scaled, qir_uniform_ui(c, 4)),
978 scaled);
979 }
980
981 static struct qreg
982 tgsi_to_qir_uarl(struct vc4_compile *c,
983 struct tgsi_full_instruction *tgsi_inst,
984 enum qop op, struct qreg *src, int i)
985 {
986 return qir_SHL(c, src[0 * 4 + i], qir_uniform_ui(c, 4));
987 }
988
989 static struct qreg
990 get_channel_from_vpm(struct vc4_compile *c,
991 struct qreg *vpm_reads,
992 uint8_t swiz,
993 const struct util_format_description *desc)
994 {
995 const struct util_format_channel_description *chan =
996 &desc->channel[swiz];
997 struct qreg temp;
998
999 if (swiz > UTIL_FORMAT_SWIZZLE_W)
1000 return get_swizzled_channel(c, vpm_reads, swiz);
1001 else if (chan->size == 32 &&
1002 chan->type == UTIL_FORMAT_TYPE_FLOAT) {
1003 return get_swizzled_channel(c, vpm_reads, swiz);
1004 } else if (chan->size == 32 &&
1005 chan->type == UTIL_FORMAT_TYPE_SIGNED) {
1006 if (chan->normalized) {
1007 return qir_FMUL(c,
1008 qir_ITOF(c, vpm_reads[swiz]),
1009 qir_uniform_f(c,
1010 1.0 / 0x7fffffff));
1011 } else {
1012 return qir_ITOF(c, vpm_reads[swiz]);
1013 }
1014 } else if (chan->size == 8 &&
1015 (chan->type == UTIL_FORMAT_TYPE_UNSIGNED ||
1016 chan->type == UTIL_FORMAT_TYPE_SIGNED)) {
1017 struct qreg vpm = vpm_reads[0];
1018 if (chan->type == UTIL_FORMAT_TYPE_SIGNED) {
1019 temp = qir_XOR(c, vpm, qir_uniform_ui(c, 0x80808080));
1020 if (chan->normalized) {
1021 return qir_FSUB(c, qir_FMUL(c,
1022 qir_UNPACK_8_F(c, temp, swiz),
1023 qir_uniform_f(c, 2.0)),
1024 qir_uniform_f(c, 1.0));
1025 } else {
1026 return qir_FADD(c,
1027 qir_ITOF(c,
1028 qir_UNPACK_8_I(c, temp,
1029 swiz)),
1030 qir_uniform_f(c, -128.0));
1031 }
1032 } else {
1033 if (chan->normalized) {
1034 return qir_UNPACK_8_F(c, vpm, swiz);
1035 } else {
1036 return qir_ITOF(c, qir_UNPACK_8_I(c, vpm, swiz));
1037 }
1038 }
1039 } else if (chan->size == 16 &&
1040 (chan->type == UTIL_FORMAT_TYPE_UNSIGNED ||
1041 chan->type == UTIL_FORMAT_TYPE_SIGNED)) {
1042 struct qreg vpm = vpm_reads[swiz / 2];
1043
1044 /* Note that UNPACK_16F eats a half float, not ints, so we use
1045 * UNPACK_16_I for all of these.
1046 */
1047 if (chan->type == UTIL_FORMAT_TYPE_SIGNED) {
1048 temp = qir_ITOF(c, qir_UNPACK_16_I(c, vpm, swiz % 2));
1049 if (chan->normalized) {
1050 return qir_FMUL(c, temp,
1051 qir_uniform_f(c, 1/32768.0f));
1052 } else {
1053 return temp;
1054 }
1055 } else {
1056 /* UNPACK_16I sign-extends, so we have to emit ANDs. */
1057 temp = vpm;
1058 if (swiz == 1 || swiz == 3)
1059 temp = qir_UNPACK_16_I(c, temp, 1);
1060 temp = qir_AND(c, temp, qir_uniform_ui(c, 0xffff));
1061 temp = qir_ITOF(c, temp);
1062
1063 if (chan->normalized) {
1064 return qir_FMUL(c, temp,
1065 qir_uniform_f(c, 1 / 65535.0));
1066 } else {
1067 return temp;
1068 }
1069 }
1070 } else {
1071 return c->undef;
1072 }
1073 }
1074
1075 static void
1076 emit_vertex_input(struct vc4_compile *c, int attr)
1077 {
1078 enum pipe_format format = c->vs_key->attr_formats[attr];
1079 uint32_t attr_size = util_format_get_blocksize(format);
1080 struct qreg vpm_reads[4];
1081
1082 for (int i = 0; i < align(attr_size, 4) / 4; i++) {
1083 vpm_reads[i] = qir_VPM_READ(c);
1084 c->num_inputs++;
1085 }
1086
1087 bool format_warned = false;
1088 const struct util_format_description *desc =
1089 util_format_description(format);
1090
1091 for (int i = 0; i < 4; i++) {
1092 uint8_t swiz = desc->swizzle[i];
1093 struct qreg result = get_channel_from_vpm(c, vpm_reads,
1094 swiz, desc);
1095
1096 if (result.file == QFILE_NULL) {
1097 if (!format_warned) {
1098 fprintf(stderr,
1099 "vtx element %d unsupported type: %s\n",
1100 attr, util_format_name(format));
1101 format_warned = true;
1102 }
1103 result = qir_uniform_f(c, 0.0);
1104 }
1105 c->inputs[attr * 4 + i] = result;
1106 }
1107 }
1108
1109 static void
1110 tgsi_to_qir_kill_if(struct vc4_compile *c, struct qreg *src, int i)
1111 {
1112 if (c->discard.file == QFILE_NULL)
1113 c->discard = qir_uniform_f(c, 0.0);
1114 qir_SF(c, src[0 * 4 + i]);
1115 c->discard = qir_SEL_X_Y_NS(c, qir_uniform_f(c, 1.0),
1116 c->discard);
1117 }
1118
1119 static void
1120 emit_fragcoord_input(struct vc4_compile *c, int attr)
1121 {
1122 c->inputs[attr * 4 + 0] = qir_FRAG_X(c);
1123 c->inputs[attr * 4 + 1] = qir_FRAG_Y(c);
1124 c->inputs[attr * 4 + 2] =
1125 qir_FMUL(c,
1126 qir_ITOF(c, qir_FRAG_Z(c)),
1127 qir_uniform_f(c, 1.0 / 0xffffff));
1128 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
1129 }
1130
1131 static void
1132 emit_point_coord_input(struct vc4_compile *c, int attr)
1133 {
1134 if (c->point_x.file == QFILE_NULL) {
1135 c->point_x = qir_uniform_f(c, 0.0);
1136 c->point_y = qir_uniform_f(c, 0.0);
1137 }
1138
1139 c->inputs[attr * 4 + 0] = c->point_x;
1140 if (c->fs_key->point_coord_upper_left) {
1141 c->inputs[attr * 4 + 1] = qir_FSUB(c,
1142 qir_uniform_f(c, 1.0),
1143 c->point_y);
1144 } else {
1145 c->inputs[attr * 4 + 1] = c->point_y;
1146 }
1147 c->inputs[attr * 4 + 2] = qir_uniform_f(c, 0.0);
1148 c->inputs[attr * 4 + 3] = qir_uniform_f(c, 1.0);
1149 }
1150
1151 static struct qreg
1152 emit_fragment_varying(struct vc4_compile *c, uint8_t semantic,
1153 uint8_t index, uint8_t swizzle)
1154 {
1155 uint32_t i = c->num_input_semantics++;
1156 struct qreg vary = {
1157 QFILE_VARY,
1158 i
1159 };
1160
1161 if (c->num_input_semantics >= c->input_semantics_array_size) {
1162 c->input_semantics_array_size =
1163 MAX2(4, c->input_semantics_array_size * 2);
1164
1165 c->input_semantics = reralloc(c, c->input_semantics,
1166 struct vc4_varying_semantic,
1167 c->input_semantics_array_size);
1168 }
1169
1170 c->input_semantics[i].semantic = semantic;
1171 c->input_semantics[i].index = index;
1172 c->input_semantics[i].swizzle = swizzle;
1173
1174 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
1175 }
1176
1177 static void
1178 emit_fragment_input(struct vc4_compile *c, int attr,
1179 struct tgsi_full_declaration *decl)
1180 {
1181 for (int i = 0; i < 4; i++) {
1182 c->inputs[attr * 4 + i] =
1183 emit_fragment_varying(c,
1184 decl->Semantic.Name,
1185 decl->Semantic.Index,
1186 i);
1187 c->num_inputs++;
1188 }
1189 }
1190
1191 static void
1192 emit_face_input(struct vc4_compile *c, int attr)
1193 {
1194 c->inputs[attr * 4 + 0] = qir_FSUB(c,
1195 qir_uniform_f(c, 1.0),
1196 qir_FMUL(c,
1197 qir_ITOF(c, qir_FRAG_REV_FLAG(c)),
1198 qir_uniform_f(c, 2.0)));
1199 c->inputs[attr * 4 + 1] = qir_uniform_f(c, 0.0);
1200 c->inputs[attr * 4 + 2] = qir_uniform_f(c, 0.0);
1201 c->inputs[attr * 4 + 3] = qir_uniform_f(c, 1.0);
1202 }
1203
1204 static void
1205 add_output(struct vc4_compile *c,
1206 uint32_t decl_offset,
1207 uint8_t semantic_name,
1208 uint8_t semantic_index,
1209 uint8_t semantic_swizzle)
1210 {
1211 uint32_t old_array_size = c->outputs_array_size;
1212 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
1213 decl_offset + 1);
1214
1215 if (old_array_size != c->outputs_array_size) {
1216 c->output_semantics = reralloc(c,
1217 c->output_semantics,
1218 struct vc4_varying_semantic,
1219 c->outputs_array_size);
1220 }
1221
1222 c->output_semantics[decl_offset].semantic = semantic_name;
1223 c->output_semantics[decl_offset].index = semantic_index;
1224 c->output_semantics[decl_offset].swizzle = semantic_swizzle;
1225 }
1226
1227 static void
1228 add_array_info(struct vc4_compile *c, uint32_t array_id,
1229 uint32_t start, uint32_t size)
1230 {
1231 if (array_id >= c->ubo_ranges_array_size) {
1232 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
1233 array_id + 1);
1234 c->ubo_ranges = reralloc(c, c->ubo_ranges,
1235 struct vc4_compiler_ubo_range,
1236 c->ubo_ranges_array_size);
1237 }
1238
1239 c->ubo_ranges[array_id].dst_offset = 0;
1240 c->ubo_ranges[array_id].src_offset = start;
1241 c->ubo_ranges[array_id].size = size;
1242 c->ubo_ranges[array_id].used = false;
1243 }
1244
1245 static void
1246 emit_tgsi_declaration(struct vc4_compile *c,
1247 struct tgsi_full_declaration *decl)
1248 {
1249 switch (decl->Declaration.File) {
1250 case TGSI_FILE_TEMPORARY: {
1251 uint32_t old_size = c->temps_array_size;
1252 resize_qreg_array(c, &c->temps, &c->temps_array_size,
1253 (decl->Range.Last + 1) * 4);
1254
1255 for (int i = old_size; i < c->temps_array_size; i++)
1256 c->temps[i] = qir_uniform_ui(c, 0);
1257 break;
1258 }
1259
1260 case TGSI_FILE_INPUT:
1261 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1262 (decl->Range.Last + 1) * 4);
1263
1264 for (int i = decl->Range.First;
1265 i <= decl->Range.Last;
1266 i++) {
1267 if (c->stage == QSTAGE_FRAG) {
1268 if (decl->Semantic.Name ==
1269 TGSI_SEMANTIC_POSITION) {
1270 emit_fragcoord_input(c, i);
1271 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
1272 emit_face_input(c, i);
1273 } else if (decl->Semantic.Name == TGSI_SEMANTIC_GENERIC &&
1274 (c->fs_key->point_sprite_mask &
1275 (1 << decl->Semantic.Index))) {
1276 emit_point_coord_input(c, i);
1277 } else {
1278 emit_fragment_input(c, i, decl);
1279 }
1280 } else {
1281 emit_vertex_input(c, i);
1282 }
1283 }
1284 break;
1285
1286 case TGSI_FILE_OUTPUT: {
1287 for (int i = 0; i < 4; i++) {
1288 add_output(c,
1289 decl->Range.First * 4 + i,
1290 decl->Semantic.Name,
1291 decl->Semantic.Index,
1292 i);
1293 }
1294
1295 switch (decl->Semantic.Name) {
1296 case TGSI_SEMANTIC_POSITION:
1297 c->output_position_index = decl->Range.First * 4;
1298 break;
1299 case TGSI_SEMANTIC_CLIPVERTEX:
1300 c->output_clipvertex_index = decl->Range.First * 4;
1301 break;
1302 case TGSI_SEMANTIC_COLOR:
1303 c->output_color_index = decl->Range.First * 4;
1304 break;
1305 case TGSI_SEMANTIC_PSIZE:
1306 c->output_point_size_index = decl->Range.First * 4;
1307 break;
1308 }
1309
1310 break;
1311
1312 case TGSI_FILE_CONSTANT:
1313 add_array_info(c,
1314 decl->Array.ArrayID,
1315 decl->Range.First * 16,
1316 (decl->Range.Last -
1317 decl->Range.First + 1) * 16);
1318 break;
1319 }
1320 }
1321 }
1322
1323 static void
1324 emit_tgsi_instruction(struct vc4_compile *c,
1325 struct tgsi_full_instruction *tgsi_inst)
1326 {
1327 static const struct {
1328 enum qop op;
1329 struct qreg (*func)(struct vc4_compile *c,
1330 struct tgsi_full_instruction *tgsi_inst,
1331 enum qop op,
1332 struct qreg *src, int i);
1333 } op_trans[] = {
1334 [TGSI_OPCODE_MOV] = { QOP_MOV, tgsi_to_qir_alu },
1335 [TGSI_OPCODE_ABS] = { 0, tgsi_to_qir_abs },
1336 [TGSI_OPCODE_MUL] = { QOP_FMUL, tgsi_to_qir_alu },
1337 [TGSI_OPCODE_ADD] = { QOP_FADD, tgsi_to_qir_alu },
1338 [TGSI_OPCODE_SUB] = { QOP_FSUB, tgsi_to_qir_alu },
1339 [TGSI_OPCODE_MIN] = { QOP_FMIN, tgsi_to_qir_alu },
1340 [TGSI_OPCODE_MAX] = { QOP_FMAX, tgsi_to_qir_alu },
1341 [TGSI_OPCODE_F2I] = { QOP_FTOI, tgsi_to_qir_alu },
1342 [TGSI_OPCODE_I2F] = { QOP_ITOF, tgsi_to_qir_alu },
1343 [TGSI_OPCODE_UADD] = { QOP_ADD, tgsi_to_qir_alu },
1344 [TGSI_OPCODE_USHR] = { QOP_SHR, tgsi_to_qir_alu },
1345 [TGSI_OPCODE_ISHR] = { QOP_ASR, tgsi_to_qir_alu },
1346 [TGSI_OPCODE_SHL] = { QOP_SHL, tgsi_to_qir_alu },
1347 [TGSI_OPCODE_IMIN] = { QOP_MIN, tgsi_to_qir_alu },
1348 [TGSI_OPCODE_IMAX] = { QOP_MAX, tgsi_to_qir_alu },
1349 [TGSI_OPCODE_AND] = { QOP_AND, tgsi_to_qir_alu },
1350 [TGSI_OPCODE_OR] = { QOP_OR, tgsi_to_qir_alu },
1351 [TGSI_OPCODE_XOR] = { QOP_XOR, tgsi_to_qir_alu },
1352 [TGSI_OPCODE_NOT] = { QOP_NOT, tgsi_to_qir_alu },
1353
1354 [TGSI_OPCODE_UMUL] = { 0, tgsi_to_qir_umul },
1355 [TGSI_OPCODE_UMAD] = { 0, tgsi_to_qir_umad },
1356 [TGSI_OPCODE_IDIV] = { 0, tgsi_to_qir_idiv },
1357 [TGSI_OPCODE_INEG] = { 0, tgsi_to_qir_ineg },
1358
1359 [TGSI_OPCODE_SEQ] = { 0, tgsi_to_qir_seq },
1360 [TGSI_OPCODE_SNE] = { 0, tgsi_to_qir_sne },
1361 [TGSI_OPCODE_SGE] = { 0, tgsi_to_qir_sge },
1362 [TGSI_OPCODE_SLT] = { 0, tgsi_to_qir_slt },
1363 [TGSI_OPCODE_FSEQ] = { 0, tgsi_to_qir_fseq },
1364 [TGSI_OPCODE_FSNE] = { 0, tgsi_to_qir_fsne },
1365 [TGSI_OPCODE_FSGE] = { 0, tgsi_to_qir_fsge },
1366 [TGSI_OPCODE_FSLT] = { 0, tgsi_to_qir_fslt },
1367 [TGSI_OPCODE_USEQ] = { 0, tgsi_to_qir_useq },
1368 [TGSI_OPCODE_USNE] = { 0, tgsi_to_qir_usne },
1369 [TGSI_OPCODE_ISGE] = { 0, tgsi_to_qir_isge },
1370 [TGSI_OPCODE_ISLT] = { 0, tgsi_to_qir_islt },
1371
1372 [TGSI_OPCODE_CMP] = { 0, tgsi_to_qir_cmp },
1373 [TGSI_OPCODE_UCMP] = { 0, tgsi_to_qir_ucmp },
1374 [TGSI_OPCODE_MAD] = { 0, tgsi_to_qir_mad },
1375 [TGSI_OPCODE_RCP] = { QOP_RCP, tgsi_to_qir_rcp },
1376 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_rsq },
1377 [TGSI_OPCODE_EX2] = { QOP_EXP2, tgsi_to_qir_scalar },
1378 [TGSI_OPCODE_LG2] = { QOP_LOG2, tgsi_to_qir_scalar },
1379 [TGSI_OPCODE_LRP] = { 0, tgsi_to_qir_lrp },
1380 [TGSI_OPCODE_TRUNC] = { 0, tgsi_to_qir_trunc },
1381 [TGSI_OPCODE_CEIL] = { 0, tgsi_to_qir_ceil },
1382 [TGSI_OPCODE_FRC] = { 0, tgsi_to_qir_frc },
1383 [TGSI_OPCODE_FLR] = { 0, tgsi_to_qir_flr },
1384 [TGSI_OPCODE_SIN] = { 0, tgsi_to_qir_sin },
1385 [TGSI_OPCODE_COS] = { 0, tgsi_to_qir_cos },
1386 [TGSI_OPCODE_CLAMP] = { 0, tgsi_to_qir_clamp },
1387 [TGSI_OPCODE_SSG] = { 0, tgsi_to_qir_ssg },
1388 [TGSI_OPCODE_ARL] = { 0, tgsi_to_qir_arl },
1389 [TGSI_OPCODE_UARL] = { 0, tgsi_to_qir_uarl },
1390 };
1391 static int asdf = 0;
1392 uint32_t tgsi_op = tgsi_inst->Instruction.Opcode;
1393
1394 if (tgsi_op == TGSI_OPCODE_END)
1395 return;
1396
1397 struct qreg src_regs[12];
1398 for (int s = 0; s < 3; s++) {
1399 for (int i = 0; i < 4; i++) {
1400 src_regs[4 * s + i] =
1401 get_src(c, tgsi_inst->Instruction.Opcode,
1402 &tgsi_inst->Src[s], i);
1403 }
1404 }
1405
1406 switch (tgsi_op) {
1407 case TGSI_OPCODE_TEX:
1408 case TGSI_OPCODE_TXP:
1409 case TGSI_OPCODE_TXB:
1410 case TGSI_OPCODE_TXL:
1411 tgsi_to_qir_tex(c, tgsi_inst,
1412 op_trans[tgsi_op].op, src_regs);
1413 return;
1414 case TGSI_OPCODE_KILL:
1415 c->discard = qir_uniform_f(c, 1.0);
1416 return;
1417 case TGSI_OPCODE_KILL_IF:
1418 for (int i = 0; i < 4; i++)
1419 tgsi_to_qir_kill_if(c, src_regs, i);
1420 return;
1421 default:
1422 break;
1423 }
1424
1425 if (tgsi_op > ARRAY_SIZE(op_trans) || !(op_trans[tgsi_op].func)) {
1426 fprintf(stderr, "unknown tgsi inst: ");
1427 tgsi_dump_instruction(tgsi_inst, asdf++);
1428 fprintf(stderr, "\n");
1429 abort();
1430 }
1431
1432 for (int i = 0; i < 4; i++) {
1433 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
1434 continue;
1435
1436 struct qreg result;
1437
1438 result = op_trans[tgsi_op].func(c, tgsi_inst,
1439 op_trans[tgsi_op].op,
1440 src_regs, i);
1441
1442 if (tgsi_inst->Instruction.Saturate) {
1443 float low = (tgsi_inst->Instruction.Saturate ==
1444 TGSI_SAT_MINUS_PLUS_ONE ? -1.0 : 0.0);
1445 result = qir_FMAX(c,
1446 qir_FMIN(c,
1447 result,
1448 qir_uniform_f(c, 1.0)),
1449 qir_uniform_f(c, low));
1450 }
1451
1452 update_dst(c, tgsi_inst, i, result);
1453 }
1454 }
1455
1456 static void
1457 parse_tgsi_immediate(struct vc4_compile *c, struct tgsi_full_immediate *imm)
1458 {
1459 for (int i = 0; i < 4; i++) {
1460 unsigned n = c->num_consts++;
1461 resize_qreg_array(c, &c->consts, &c->consts_array_size, n + 1);
1462 c->consts[n] = qir_uniform_ui(c, imm->u[i].Uint);
1463 }
1464 }
1465
1466 static struct qreg
1467 vc4_blend_channel(struct vc4_compile *c,
1468 struct qreg *dst,
1469 struct qreg *src,
1470 struct qreg val,
1471 unsigned factor,
1472 int channel)
1473 {
1474 switch(factor) {
1475 case PIPE_BLENDFACTOR_ONE:
1476 return val;
1477 case PIPE_BLENDFACTOR_SRC_COLOR:
1478 return qir_FMUL(c, val, src[channel]);
1479 case PIPE_BLENDFACTOR_SRC_ALPHA:
1480 return qir_FMUL(c, val, src[3]);
1481 case PIPE_BLENDFACTOR_DST_ALPHA:
1482 return qir_FMUL(c, val, dst[3]);
1483 case PIPE_BLENDFACTOR_DST_COLOR:
1484 return qir_FMUL(c, val, dst[channel]);
1485 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
1486 if (channel != 3) {
1487 return qir_FMUL(c,
1488 val,
1489 qir_FMIN(c,
1490 src[3],
1491 qir_FSUB(c,
1492 qir_uniform_f(c, 1.0),
1493 dst[3])));
1494 } else {
1495 return val;
1496 }
1497 case PIPE_BLENDFACTOR_CONST_COLOR:
1498 return qir_FMUL(c, val,
1499 get_temp_for_uniform(c,
1500 QUNIFORM_BLEND_CONST_COLOR,
1501 channel));
1502 case PIPE_BLENDFACTOR_CONST_ALPHA:
1503 return qir_FMUL(c, val,
1504 get_temp_for_uniform(c,
1505 QUNIFORM_BLEND_CONST_COLOR,
1506 3));
1507 case PIPE_BLENDFACTOR_ZERO:
1508 return qir_uniform_f(c, 0.0);
1509 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
1510 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1511 src[channel]));
1512 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
1513 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1514 src[3]));
1515 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
1516 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1517 dst[3]));
1518 case PIPE_BLENDFACTOR_INV_DST_COLOR:
1519 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1520 dst[channel]));
1521 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
1522 return qir_FMUL(c, val,
1523 qir_FSUB(c, qir_uniform_f(c, 1.0),
1524 get_temp_for_uniform(c,
1525 QUNIFORM_BLEND_CONST_COLOR,
1526 channel)));
1527 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
1528 return qir_FMUL(c, val,
1529 qir_FSUB(c, qir_uniform_f(c, 1.0),
1530 get_temp_for_uniform(c,
1531 QUNIFORM_BLEND_CONST_COLOR,
1532 3)));
1533
1534 default:
1535 case PIPE_BLENDFACTOR_SRC1_COLOR:
1536 case PIPE_BLENDFACTOR_SRC1_ALPHA:
1537 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
1538 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
1539 /* Unsupported. */
1540 fprintf(stderr, "Unknown blend factor %d\n", factor);
1541 return val;
1542 }
1543 }
1544
1545 static struct qreg
1546 vc4_blend_func(struct vc4_compile *c,
1547 struct qreg src, struct qreg dst,
1548 unsigned func)
1549 {
1550 switch (func) {
1551 case PIPE_BLEND_ADD:
1552 return qir_FADD(c, src, dst);
1553 case PIPE_BLEND_SUBTRACT:
1554 return qir_FSUB(c, src, dst);
1555 case PIPE_BLEND_REVERSE_SUBTRACT:
1556 return qir_FSUB(c, dst, src);
1557 case PIPE_BLEND_MIN:
1558 return qir_FMIN(c, src, dst);
1559 case PIPE_BLEND_MAX:
1560 return qir_FMAX(c, src, dst);
1561
1562 default:
1563 /* Unsupported. */
1564 fprintf(stderr, "Unknown blend func %d\n", func);
1565 return src;
1566
1567 }
1568 }
1569
1570 /**
1571 * Implements fixed function blending in shader code.
1572 *
1573 * VC4 doesn't have any hardware support for blending. Instead, you read the
1574 * current contents of the destination from the tile buffer after having
1575 * waited for the scoreboard (which is handled by vc4_qpu_emit.c), then do
1576 * math using your output color and that destination value, and update the
1577 * output color appropriately.
1578 */
1579 static void
1580 vc4_blend(struct vc4_compile *c, struct qreg *result,
1581 struct qreg *dst_color, struct qreg *src_color)
1582 {
1583 struct pipe_rt_blend_state *blend = &c->fs_key->blend;
1584
1585 if (!blend->blend_enable) {
1586 for (int i = 0; i < 4; i++)
1587 result[i] = src_color[i];
1588 return;
1589 }
1590
1591 struct qreg src_blend[4], dst_blend[4];
1592 for (int i = 0; i < 3; i++) {
1593 src_blend[i] = vc4_blend_channel(c,
1594 dst_color, src_color,
1595 src_color[i],
1596 blend->rgb_src_factor, i);
1597 dst_blend[i] = vc4_blend_channel(c,
1598 dst_color, src_color,
1599 dst_color[i],
1600 blend->rgb_dst_factor, i);
1601 }
1602 src_blend[3] = vc4_blend_channel(c,
1603 dst_color, src_color,
1604 src_color[3],
1605 blend->alpha_src_factor, 3);
1606 dst_blend[3] = vc4_blend_channel(c,
1607 dst_color, src_color,
1608 dst_color[3],
1609 blend->alpha_dst_factor, 3);
1610
1611 for (int i = 0; i < 3; i++) {
1612 result[i] = vc4_blend_func(c,
1613 src_blend[i], dst_blend[i],
1614 blend->rgb_func);
1615 }
1616 result[3] = vc4_blend_func(c,
1617 src_blend[3], dst_blend[3],
1618 blend->alpha_func);
1619 }
1620
1621 static void
1622 clip_distance_discard(struct vc4_compile *c)
1623 {
1624 for (int i = 0; i < PIPE_MAX_CLIP_PLANES; i++) {
1625 if (!(c->key->ucp_enables & (1 << i)))
1626 continue;
1627
1628 struct qreg dist = emit_fragment_varying(c,
1629 TGSI_SEMANTIC_CLIPDIST,
1630 i,
1631 TGSI_SWIZZLE_X);
1632
1633 qir_SF(c, dist);
1634
1635 if (c->discard.file == QFILE_NULL)
1636 c->discard = qir_uniform_f(c, 0.0);
1637
1638 c->discard = qir_SEL_X_Y_NS(c, qir_uniform_f(c, 1.0),
1639 c->discard);
1640 }
1641 }
1642
1643 static void
1644 alpha_test_discard(struct vc4_compile *c)
1645 {
1646 struct qreg src_alpha;
1647 struct qreg alpha_ref = get_temp_for_uniform(c, QUNIFORM_ALPHA_REF, 0);
1648
1649 if (!c->fs_key->alpha_test)
1650 return;
1651
1652 if (c->output_color_index != -1)
1653 src_alpha = c->outputs[c->output_color_index + 3];
1654 else
1655 src_alpha = qir_uniform_f(c, 1.0);
1656
1657 if (c->discard.file == QFILE_NULL)
1658 c->discard = qir_uniform_f(c, 0.0);
1659
1660 switch (c->fs_key->alpha_test_func) {
1661 case PIPE_FUNC_NEVER:
1662 c->discard = qir_uniform_f(c, 1.0);
1663 break;
1664 case PIPE_FUNC_ALWAYS:
1665 break;
1666 case PIPE_FUNC_EQUAL:
1667 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1668 c->discard = qir_SEL_X_Y_ZS(c, c->discard,
1669 qir_uniform_f(c, 1.0));
1670 break;
1671 case PIPE_FUNC_NOTEQUAL:
1672 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1673 c->discard = qir_SEL_X_Y_ZC(c, c->discard,
1674 qir_uniform_f(c, 1.0));
1675 break;
1676 case PIPE_FUNC_GREATER:
1677 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1678 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1679 qir_uniform_f(c, 1.0));
1680 break;
1681 case PIPE_FUNC_GEQUAL:
1682 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1683 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1684 qir_uniform_f(c, 1.0));
1685 break;
1686 case PIPE_FUNC_LESS:
1687 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1688 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1689 qir_uniform_f(c, 1.0));
1690 break;
1691 case PIPE_FUNC_LEQUAL:
1692 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1693 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1694 qir_uniform_f(c, 1.0));
1695 break;
1696 }
1697 }
1698
1699 static struct qreg
1700 vc4_logicop(struct vc4_compile *c, struct qreg src, struct qreg dst)
1701 {
1702 switch (c->fs_key->logicop_func) {
1703 case PIPE_LOGICOP_CLEAR:
1704 return qir_uniform_f(c, 0.0);
1705 case PIPE_LOGICOP_NOR:
1706 return qir_NOT(c, qir_OR(c, src, dst));
1707 case PIPE_LOGICOP_AND_INVERTED:
1708 return qir_AND(c, qir_NOT(c, src), dst);
1709 case PIPE_LOGICOP_COPY_INVERTED:
1710 return qir_NOT(c, src);
1711 case PIPE_LOGICOP_AND_REVERSE:
1712 return qir_AND(c, src, qir_NOT(c, dst));
1713 case PIPE_LOGICOP_INVERT:
1714 return qir_NOT(c, dst);
1715 case PIPE_LOGICOP_XOR:
1716 return qir_XOR(c, src, dst);
1717 case PIPE_LOGICOP_NAND:
1718 return qir_NOT(c, qir_AND(c, src, dst));
1719 case PIPE_LOGICOP_AND:
1720 return qir_AND(c, src, dst);
1721 case PIPE_LOGICOP_EQUIV:
1722 return qir_NOT(c, qir_XOR(c, src, dst));
1723 case PIPE_LOGICOP_NOOP:
1724 return dst;
1725 case PIPE_LOGICOP_OR_INVERTED:
1726 return qir_OR(c, qir_NOT(c, src), dst);
1727 case PIPE_LOGICOP_OR_REVERSE:
1728 return qir_OR(c, src, qir_NOT(c, dst));
1729 case PIPE_LOGICOP_OR:
1730 return qir_OR(c, src, dst);
1731 case PIPE_LOGICOP_SET:
1732 return qir_uniform_ui(c, ~0);
1733 case PIPE_LOGICOP_COPY:
1734 default:
1735 return src;
1736 }
1737 }
1738
1739 static void
1740 emit_frag_end(struct vc4_compile *c)
1741 {
1742 clip_distance_discard(c);
1743 alpha_test_discard(c);
1744
1745 enum pipe_format color_format = c->fs_key->color_format;
1746 const uint8_t *format_swiz = vc4_get_format_swizzle(color_format);
1747 struct qreg tlb_read_color[4] = { c->undef, c->undef, c->undef, c->undef };
1748 struct qreg dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1749 struct qreg linear_dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1750 struct qreg packed_dst_color = c->undef;
1751
1752 if (c->fs_key->blend.blend_enable ||
1753 c->fs_key->blend.colormask != 0xf ||
1754 c->fs_key->logicop_func != PIPE_LOGICOP_COPY) {
1755 struct qreg r4 = qir_TLB_COLOR_READ(c);
1756 for (int i = 0; i < 4; i++)
1757 tlb_read_color[i] = qir_R4_UNPACK(c, r4, i);
1758 for (int i = 0; i < 4; i++) {
1759 dst_color[i] = get_swizzled_channel(c,
1760 tlb_read_color,
1761 format_swiz[i]);
1762 if (util_format_is_srgb(color_format) && i != 3) {
1763 linear_dst_color[i] =
1764 qir_srgb_decode(c, dst_color[i]);
1765 } else {
1766 linear_dst_color[i] = dst_color[i];
1767 }
1768 }
1769
1770 /* Save the packed value for logic ops. Can't reuse r4
1771 * becuase other things might smash it (like sRGB)
1772 */
1773 packed_dst_color = qir_MOV(c, r4);
1774 }
1775
1776 struct qreg blend_color[4];
1777 struct qreg undef_array[4] = {
1778 c->undef, c->undef, c->undef, c->undef
1779 };
1780 vc4_blend(c, blend_color, linear_dst_color,
1781 (c->output_color_index != -1 ?
1782 c->outputs + c->output_color_index :
1783 undef_array));
1784
1785 if (util_format_is_srgb(color_format)) {
1786 for (int i = 0; i < 3; i++)
1787 blend_color[i] = qir_srgb_encode(c, blend_color[i]);
1788 }
1789
1790 /* If the bit isn't set in the color mask, then just return the
1791 * original dst color, instead.
1792 */
1793 for (int i = 0; i < 4; i++) {
1794 if (!(c->fs_key->blend.colormask & (1 << i))) {
1795 blend_color[i] = dst_color[i];
1796 }
1797 }
1798
1799 /* Debug: Sometimes you're getting a black output and just want to see
1800 * if the FS is getting executed at all. Spam magenta into the color
1801 * output.
1802 */
1803 if (0) {
1804 blend_color[0] = qir_uniform_f(c, 1.0);
1805 blend_color[1] = qir_uniform_f(c, 0.0);
1806 blend_color[2] = qir_uniform_f(c, 1.0);
1807 blend_color[3] = qir_uniform_f(c, 0.5);
1808 }
1809
1810 struct qreg swizzled_outputs[4];
1811 for (int i = 0; i < 4; i++) {
1812 swizzled_outputs[i] = get_swizzled_channel(c, blend_color,
1813 format_swiz[i]);
1814 }
1815
1816 if (c->discard.file != QFILE_NULL)
1817 qir_TLB_DISCARD_SETUP(c, c->discard);
1818
1819 if (c->fs_key->stencil_enabled) {
1820 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 0));
1821 if (c->fs_key->stencil_twoside) {
1822 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 1));
1823 }
1824 if (c->fs_key->stencil_full_writemasks) {
1825 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 2));
1826 }
1827 }
1828
1829 if (c->fs_key->depth_enabled) {
1830 struct qreg z;
1831 if (c->output_position_index != -1) {
1832 z = qir_FTOI(c, qir_FMUL(c, c->outputs[c->output_position_index + 2],
1833 qir_uniform_f(c, 0xffffff)));
1834 } else {
1835 z = qir_FRAG_Z(c);
1836 }
1837 qir_TLB_Z_WRITE(c, z);
1838 }
1839
1840 struct qreg packed_color = c->undef;
1841 for (int i = 0; i < 4; i++) {
1842 if (swizzled_outputs[i].file == QFILE_NULL)
1843 continue;
1844 if (packed_color.file == QFILE_NULL) {
1845 packed_color = qir_PACK_8888_F(c, swizzled_outputs[i]);
1846 } else {
1847 packed_color = qir_PACK_8_F(c,
1848 packed_color,
1849 swizzled_outputs[i],
1850 i);
1851 }
1852 }
1853
1854 if (packed_color.file == QFILE_NULL)
1855 packed_color = qir_uniform_ui(c, 0);
1856
1857 if (c->fs_key->logicop_func != PIPE_LOGICOP_COPY) {
1858 packed_color = vc4_logicop(c, packed_color, packed_dst_color);
1859 }
1860
1861 qir_emit(c, qir_inst(QOP_TLB_COLOR_WRITE, c->undef,
1862 packed_color, c->undef));
1863 }
1864
1865 static void
1866 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1867 {
1868 struct qreg xyi[2];
1869
1870 for (int i = 0; i < 2; i++) {
1871 struct qreg scale =
1872 add_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1873
1874 xyi[i] = qir_FTOI(c, qir_FMUL(c,
1875 qir_FMUL(c,
1876 c->outputs[c->output_position_index + i],
1877 scale),
1878 rcp_w));
1879 }
1880
1881 qir_VPM_WRITE(c, qir_PACK_SCALED(c, xyi[0], xyi[1]));
1882 }
1883
1884 static void
1885 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1886 {
1887 struct qreg zscale = add_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1888 struct qreg zoffset = add_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1889
1890 qir_VPM_WRITE(c, qir_FADD(c, qir_FMUL(c, qir_FMUL(c,
1891 c->outputs[c->output_position_index + 2],
1892 zscale),
1893 rcp_w),
1894 zoffset));
1895 }
1896
1897 static void
1898 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1899 {
1900 qir_VPM_WRITE(c, rcp_w);
1901 }
1902
1903 static void
1904 emit_point_size_write(struct vc4_compile *c)
1905 {
1906 struct qreg point_size;
1907
1908 if (c->output_point_size_index)
1909 point_size = c->outputs[c->output_point_size_index + 3];
1910 else
1911 point_size = qir_uniform_f(c, 1.0);
1912
1913 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1914 * BCM21553).
1915 */
1916 point_size = qir_FMAX(c, point_size, qir_uniform_f(c, .125));
1917
1918 qir_VPM_WRITE(c, point_size);
1919 }
1920
1921 /**
1922 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1923 *
1924 * The simulator insists that there be at least one vertex attribute, so
1925 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also
1926 * insists that all vertex attributes loaded get read by the VS/CS, so we have
1927 * to consume it here.
1928 */
1929 static void
1930 emit_stub_vpm_read(struct vc4_compile *c)
1931 {
1932 if (c->num_inputs)
1933 return;
1934
1935 for (int i = 0; i < 4; i++) {
1936 qir_emit(c, qir_inst(QOP_VPM_READ,
1937 qir_get_temp(c),
1938 c->undef,
1939 c->undef));
1940 c->num_inputs++;
1941 }
1942 }
1943
1944 static void
1945 emit_ucp_clipdistance(struct vc4_compile *c)
1946 {
1947 unsigned cv;
1948 if (c->output_clipvertex_index != -1)
1949 cv = c->output_clipvertex_index;
1950 else if (c->output_position_index != -1)
1951 cv = c->output_position_index;
1952 else
1953 return;
1954
1955 for (int plane = 0; plane < PIPE_MAX_CLIP_PLANES; plane++) {
1956 if (!(c->key->ucp_enables & (1 << plane)))
1957 continue;
1958
1959 /* Pick the next outputs[] that hasn't been written to, since
1960 * there are no other program writes left to be processed at
1961 * this point. If something had been declared but not written
1962 * (like a w component), we'll just smash over the top of it.
1963 */
1964 uint32_t output_index = c->num_outputs++;
1965 add_output(c, output_index,
1966 TGSI_SEMANTIC_CLIPDIST,
1967 plane,
1968 TGSI_SWIZZLE_X);
1969
1970
1971 struct qreg dist = qir_uniform_f(c, 0.0);
1972 for (int i = 0; i < 4; i++) {
1973 struct qreg pos_chan = c->outputs[cv + i];
1974 struct qreg ucp =
1975 add_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1976 plane * 4 + i);
1977 dist = qir_FADD(c, dist, qir_FMUL(c, pos_chan, ucp));
1978 }
1979
1980 c->outputs[output_index] = dist;
1981 }
1982 }
1983
1984 static void
1985 emit_vert_end(struct vc4_compile *c,
1986 struct vc4_varying_semantic *fs_inputs,
1987 uint32_t num_fs_inputs)
1988 {
1989 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1990
1991 emit_stub_vpm_read(c);
1992 emit_ucp_clipdistance(c);
1993
1994 emit_scaled_viewport_write(c, rcp_w);
1995 emit_zs_write(c, rcp_w);
1996 emit_rcp_wc_write(c, rcp_w);
1997 if (c->vs_key->per_vertex_point_size)
1998 emit_point_size_write(c);
1999
2000 for (int i = 0; i < num_fs_inputs; i++) {
2001 struct vc4_varying_semantic *input = &fs_inputs[i];
2002 int j;
2003
2004 for (j = 0; j < c->num_outputs; j++) {
2005 struct vc4_varying_semantic *output =
2006 &c->output_semantics[j];
2007
2008 if (input->semantic == output->semantic &&
2009 input->index == output->index &&
2010 input->swizzle == output->swizzle) {
2011 qir_VPM_WRITE(c, c->outputs[j]);
2012 break;
2013 }
2014 }
2015 /* Emit padding if we didn't find a declared VS output for
2016 * this FS input.
2017 */
2018 if (j == c->num_outputs)
2019 qir_VPM_WRITE(c, qir_uniform_f(c, 0.0));
2020 }
2021 }
2022
2023 static void
2024 emit_coord_end(struct vc4_compile *c)
2025 {
2026 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
2027
2028 emit_stub_vpm_read(c);
2029
2030 for (int i = 0; i < 4; i++)
2031 qir_VPM_WRITE(c, c->outputs[c->output_position_index + i]);
2032
2033 emit_scaled_viewport_write(c, rcp_w);
2034 emit_zs_write(c, rcp_w);
2035 emit_rcp_wc_write(c, rcp_w);
2036 if (c->vs_key->per_vertex_point_size)
2037 emit_point_size_write(c);
2038 }
2039
2040 static struct vc4_compile *
2041 vc4_shader_tgsi_to_qir(struct vc4_context *vc4, enum qstage stage,
2042 struct vc4_key *key)
2043 {
2044 struct vc4_compile *c = qir_compile_init();
2045 int ret;
2046
2047 c->stage = stage;
2048 for (int i = 0; i < 4; i++)
2049 c->addr[i] = qir_uniform_f(c, 0.0);
2050
2051 c->shader_state = &key->shader_state->base;
2052 c->program_id = key->shader_state->program_id;
2053 c->variant_id = key->shader_state->compiled_variant_count++;
2054
2055 c->key = key;
2056 switch (stage) {
2057 case QSTAGE_FRAG:
2058 c->fs_key = (struct vc4_fs_key *)key;
2059 if (c->fs_key->is_points) {
2060 c->point_x = emit_fragment_varying(c, ~0, ~0, 0);
2061 c->point_y = emit_fragment_varying(c, ~0, ~0, 0);
2062 } else if (c->fs_key->is_lines) {
2063 c->line_x = emit_fragment_varying(c, ~0, ~0, 0);
2064 }
2065 break;
2066 case QSTAGE_VERT:
2067 c->vs_key = (struct vc4_vs_key *)key;
2068 break;
2069 case QSTAGE_COORD:
2070 c->vs_key = (struct vc4_vs_key *)key;
2071 break;
2072 }
2073
2074 const struct tgsi_token *tokens = key->shader_state->base.tokens;
2075 if (c->fs_key && c->fs_key->light_twoside) {
2076 if (!key->shader_state->twoside_tokens) {
2077 const struct tgsi_lowering_config lowering_config = {
2078 .color_two_side = true,
2079 };
2080 struct tgsi_shader_info info;
2081 key->shader_state->twoside_tokens =
2082 tgsi_transform_lowering(&lowering_config,
2083 key->shader_state->base.tokens,
2084 &info);
2085
2086 /* If no transformation occurred, then NULL is
2087 * returned and we just use our original tokens.
2088 */
2089 if (!key->shader_state->twoside_tokens) {
2090 key->shader_state->twoside_tokens =
2091 key->shader_state->base.tokens;
2092 }
2093 }
2094 tokens = key->shader_state->twoside_tokens;
2095 }
2096
2097 ret = tgsi_parse_init(&c->parser, tokens);
2098 assert(ret == TGSI_PARSE_OK);
2099
2100 if (vc4_debug & VC4_DEBUG_TGSI) {
2101 fprintf(stderr, "%s prog %d/%d TGSI:\n",
2102 qir_get_stage_name(c->stage),
2103 c->program_id, c->variant_id);
2104 tgsi_dump(tokens, 0);
2105 }
2106
2107 while (!tgsi_parse_end_of_tokens(&c->parser)) {
2108 tgsi_parse_token(&c->parser);
2109
2110 switch (c->parser.FullToken.Token.Type) {
2111 case TGSI_TOKEN_TYPE_DECLARATION:
2112 emit_tgsi_declaration(c,
2113 &c->parser.FullToken.FullDeclaration);
2114 break;
2115
2116 case TGSI_TOKEN_TYPE_INSTRUCTION:
2117 emit_tgsi_instruction(c,
2118 &c->parser.FullToken.FullInstruction);
2119 break;
2120
2121 case TGSI_TOKEN_TYPE_IMMEDIATE:
2122 parse_tgsi_immediate(c,
2123 &c->parser.FullToken.FullImmediate);
2124 break;
2125 }
2126 }
2127
2128 switch (stage) {
2129 case QSTAGE_FRAG:
2130 emit_frag_end(c);
2131 break;
2132 case QSTAGE_VERT:
2133 emit_vert_end(c,
2134 vc4->prog.fs->input_semantics,
2135 vc4->prog.fs->num_inputs);
2136 break;
2137 case QSTAGE_COORD:
2138 emit_coord_end(c);
2139 break;
2140 }
2141
2142 tgsi_parse_free(&c->parser);
2143
2144 qir_optimize(c);
2145
2146 if (vc4_debug & VC4_DEBUG_QIR) {
2147 fprintf(stderr, "%s prog %d/%d QIR:\n",
2148 qir_get_stage_name(c->stage),
2149 c->program_id, c->variant_id);
2150 qir_dump(c);
2151 }
2152 qir_reorder_uniforms(c);
2153 vc4_generate_code(vc4, c);
2154
2155 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2156 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d instructions\n",
2157 qir_get_stage_name(c->stage),
2158 c->program_id, c->variant_id,
2159 c->qpu_inst_count);
2160 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d uniforms\n",
2161 qir_get_stage_name(c->stage),
2162 c->program_id, c->variant_id,
2163 c->num_uniforms);
2164 }
2165
2166 return c;
2167 }
2168
2169 static void *
2170 vc4_shader_state_create(struct pipe_context *pctx,
2171 const struct pipe_shader_state *cso)
2172 {
2173 struct vc4_context *vc4 = vc4_context(pctx);
2174 struct vc4_uncompiled_shader *so = CALLOC_STRUCT(vc4_uncompiled_shader);
2175 if (!so)
2176 return NULL;
2177
2178 const struct tgsi_lowering_config lowering_config = {
2179 .lower_DST = true,
2180 .lower_XPD = true,
2181 .lower_SCS = true,
2182 .lower_POW = true,
2183 .lower_LIT = true,
2184 .lower_EXP = true,
2185 .lower_LOG = true,
2186 .lower_DP4 = true,
2187 .lower_DP3 = true,
2188 .lower_DPH = true,
2189 .lower_DP2 = true,
2190 .lower_DP2A = true,
2191 };
2192
2193 struct tgsi_shader_info info;
2194 so->base.tokens = tgsi_transform_lowering(&lowering_config, cso->tokens, &info);
2195 if (!so->base.tokens)
2196 so->base.tokens = tgsi_dup_tokens(cso->tokens);
2197 so->program_id = vc4->next_uncompiled_program_id++;
2198
2199 return so;
2200 }
2201
2202 static void
2203 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
2204 struct vc4_compile *c)
2205 {
2206 int count = c->num_uniforms;
2207 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
2208
2209 uinfo->count = count;
2210 uinfo->data = ralloc_array(shader, uint32_t, count);
2211 memcpy(uinfo->data, c->uniform_data,
2212 count * sizeof(*uinfo->data));
2213 uinfo->contents = ralloc_array(shader, enum quniform_contents, count);
2214 memcpy(uinfo->contents, c->uniform_contents,
2215 count * sizeof(*uinfo->contents));
2216 uinfo->num_texture_samples = c->num_texture_samples;
2217 }
2218
2219 static struct vc4_compiled_shader *
2220 vc4_get_compiled_shader(struct vc4_context *vc4, enum qstage stage,
2221 struct vc4_key *key)
2222 {
2223 struct hash_table *ht;
2224 uint32_t key_size;
2225 if (stage == QSTAGE_FRAG) {
2226 ht = vc4->fs_cache;
2227 key_size = sizeof(struct vc4_fs_key);
2228 } else {
2229 ht = vc4->vs_cache;
2230 key_size = sizeof(struct vc4_vs_key);
2231 }
2232
2233 struct vc4_compiled_shader *shader;
2234 struct hash_entry *entry = _mesa_hash_table_search(ht, key);
2235 if (entry)
2236 return entry->data;
2237
2238 struct vc4_compile *c = vc4_shader_tgsi_to_qir(vc4, stage, key);
2239 shader = rzalloc(NULL, struct vc4_compiled_shader);
2240
2241 shader->program_id = vc4->next_compiled_program_id++;
2242 if (stage == QSTAGE_FRAG) {
2243 bool input_live[c->num_input_semantics];
2244 struct simple_node *node;
2245
2246 memset(input_live, 0, sizeof(input_live));
2247 foreach(node, &c->instructions) {
2248 struct qinst *inst = (struct qinst *)node;
2249 for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) {
2250 if (inst->src[i].file == QFILE_VARY)
2251 input_live[inst->src[i].index] = true;
2252 }
2253 }
2254
2255 shader->input_semantics = ralloc_array(shader,
2256 struct vc4_varying_semantic,
2257 c->num_input_semantics);
2258
2259 for (int i = 0; i < c->num_input_semantics; i++) {
2260 struct vc4_varying_semantic *sem = &c->input_semantics[i];
2261
2262 if (!input_live[i])
2263 continue;
2264
2265 /* Skip non-VS-output inputs. */
2266 if (sem->semantic == (uint8_t)~0)
2267 continue;
2268
2269 if (sem->semantic == TGSI_SEMANTIC_COLOR ||
2270 sem->semantic == TGSI_SEMANTIC_BCOLOR) {
2271 shader->color_inputs |= (1 << shader->num_inputs);
2272 }
2273
2274 shader->input_semantics[shader->num_inputs] = *sem;
2275 shader->num_inputs++;
2276 }
2277 } else {
2278 shader->num_inputs = c->num_inputs;
2279 }
2280
2281 copy_uniform_state_to_shader(shader, c);
2282 shader->bo = vc4_bo_alloc_mem(vc4->screen, c->qpu_insts,
2283 c->qpu_inst_count * sizeof(uint64_t),
2284 "code");
2285
2286 /* Copy the compiler UBO range state to the compiled shader, dropping
2287 * out arrays that were never referenced by an indirect load.
2288 *
2289 * (Note that QIR dead code elimination of an array access still
2290 * leaves that array alive, though)
2291 */
2292 if (c->num_ubo_ranges) {
2293 shader->num_ubo_ranges = c->num_ubo_ranges;
2294 shader->ubo_ranges = ralloc_array(shader, struct vc4_ubo_range,
2295 c->num_ubo_ranges);
2296 uint32_t j = 0;
2297 for (int i = 0; i < c->ubo_ranges_array_size; i++) {
2298 struct vc4_compiler_ubo_range *range =
2299 &c->ubo_ranges[i];
2300 if (!range->used)
2301 continue;
2302
2303 shader->ubo_ranges[j].dst_offset = range->dst_offset;
2304 shader->ubo_ranges[j].src_offset = range->src_offset;
2305 shader->ubo_ranges[j].size = range->size;
2306 shader->ubo_size += c->ubo_ranges[i].size;
2307 j++;
2308 }
2309 }
2310
2311 qir_compile_destroy(c);
2312
2313 struct vc4_key *dup_key;
2314 dup_key = ralloc_size(shader, key_size);
2315 memcpy(dup_key, key, key_size);
2316 _mesa_hash_table_insert(ht, dup_key, shader);
2317
2318 return shader;
2319 }
2320
2321 static void
2322 vc4_setup_shared_key(struct vc4_context *vc4, struct vc4_key *key,
2323 struct vc4_texture_stateobj *texstate)
2324 {
2325 for (int i = 0; i < texstate->num_textures; i++) {
2326 struct pipe_sampler_view *sampler = texstate->textures[i];
2327 struct pipe_sampler_state *sampler_state =
2328 texstate->samplers[i];
2329
2330 if (sampler) {
2331 key->tex[i].format = sampler->format;
2332 key->tex[i].swizzle[0] = sampler->swizzle_r;
2333 key->tex[i].swizzle[1] = sampler->swizzle_g;
2334 key->tex[i].swizzle[2] = sampler->swizzle_b;
2335 key->tex[i].swizzle[3] = sampler->swizzle_a;
2336 key->tex[i].compare_mode = sampler_state->compare_mode;
2337 key->tex[i].compare_func = sampler_state->compare_func;
2338 key->tex[i].wrap_s = sampler_state->wrap_s;
2339 key->tex[i].wrap_t = sampler_state->wrap_t;
2340 }
2341 }
2342
2343 key->ucp_enables = vc4->rasterizer->base.clip_plane_enable;
2344 }
2345
2346 static void
2347 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
2348 {
2349 struct vc4_fs_key local_key;
2350 struct vc4_fs_key *key = &local_key;
2351
2352 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2353 VC4_DIRTY_BLEND |
2354 VC4_DIRTY_FRAMEBUFFER |
2355 VC4_DIRTY_ZSA |
2356 VC4_DIRTY_RASTERIZER |
2357 VC4_DIRTY_FRAGTEX |
2358 VC4_DIRTY_TEXSTATE |
2359 VC4_DIRTY_PROG))) {
2360 return;
2361 }
2362
2363 memset(key, 0, sizeof(*key));
2364 vc4_setup_shared_key(vc4, &key->base, &vc4->fragtex);
2365 key->base.shader_state = vc4->prog.bind_fs;
2366 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
2367 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
2368 prim_mode <= PIPE_PRIM_LINE_STRIP);
2369 key->blend = vc4->blend->rt[0];
2370 if (vc4->blend->logicop_enable) {
2371 key->logicop_func = vc4->blend->logicop_func;
2372 } else {
2373 key->logicop_func = PIPE_LOGICOP_COPY;
2374 }
2375 if (vc4->framebuffer.cbufs[0])
2376 key->color_format = vc4->framebuffer.cbufs[0]->format;
2377
2378 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
2379 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
2380 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
2381 key->depth_enabled = (vc4->zsa->base.depth.enabled ||
2382 key->stencil_enabled);
2383 if (vc4->zsa->base.alpha.enabled) {
2384 key->alpha_test = true;
2385 key->alpha_test_func = vc4->zsa->base.alpha.func;
2386 }
2387
2388 if (key->is_points) {
2389 key->point_sprite_mask =
2390 vc4->rasterizer->base.sprite_coord_enable;
2391 key->point_coord_upper_left =
2392 (vc4->rasterizer->base.sprite_coord_mode ==
2393 PIPE_SPRITE_COORD_UPPER_LEFT);
2394 }
2395
2396 key->light_twoside = vc4->rasterizer->base.light_twoside;
2397
2398 struct vc4_compiled_shader *old_fs = vc4->prog.fs;
2399 vc4->prog.fs = vc4_get_compiled_shader(vc4, QSTAGE_FRAG, &key->base);
2400 if (vc4->prog.fs == old_fs)
2401 return;
2402
2403 if (vc4->rasterizer->base.flatshade &&
2404 old_fs && vc4->prog.fs->color_inputs != old_fs->color_inputs) {
2405 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
2406 }
2407 }
2408
2409 static void
2410 vc4_update_compiled_vs(struct vc4_context *vc4, uint8_t prim_mode)
2411 {
2412 struct vc4_vs_key local_key;
2413 struct vc4_vs_key *key = &local_key;
2414
2415 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2416 VC4_DIRTY_RASTERIZER |
2417 VC4_DIRTY_VERTTEX |
2418 VC4_DIRTY_TEXSTATE |
2419 VC4_DIRTY_VTXSTATE |
2420 VC4_DIRTY_PROG))) {
2421 return;
2422 }
2423
2424 memset(key, 0, sizeof(*key));
2425 vc4_setup_shared_key(vc4, &key->base, &vc4->verttex);
2426 key->base.shader_state = vc4->prog.bind_vs;
2427 key->compiled_fs_id = vc4->prog.fs->program_id;
2428
2429 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
2430 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
2431
2432 key->per_vertex_point_size =
2433 (prim_mode == PIPE_PRIM_POINTS &&
2434 vc4->rasterizer->base.point_size_per_vertex);
2435
2436 vc4->prog.vs = vc4_get_compiled_shader(vc4, QSTAGE_VERT, &key->base);
2437 key->is_coord = true;
2438 vc4->prog.cs = vc4_get_compiled_shader(vc4, QSTAGE_COORD, &key->base);
2439 }
2440
2441 void
2442 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
2443 {
2444 vc4_update_compiled_fs(vc4, prim_mode);
2445 vc4_update_compiled_vs(vc4, prim_mode);
2446 }
2447
2448 static uint32_t
2449 fs_cache_hash(const void *key)
2450 {
2451 return _mesa_hash_data(key, sizeof(struct vc4_fs_key));
2452 }
2453
2454 static uint32_t
2455 vs_cache_hash(const void *key)
2456 {
2457 return _mesa_hash_data(key, sizeof(struct vc4_vs_key));
2458 }
2459
2460 static bool
2461 fs_cache_compare(const void *key1, const void *key2)
2462 {
2463 return memcmp(key1, key2, sizeof(struct vc4_fs_key)) == 0;
2464 }
2465
2466 static bool
2467 vs_cache_compare(const void *key1, const void *key2)
2468 {
2469 return memcmp(key1, key2, sizeof(struct vc4_vs_key)) == 0;
2470 }
2471
2472 static void
2473 delete_from_cache_if_matches(struct hash_table *ht,
2474 struct hash_entry *entry,
2475 struct vc4_uncompiled_shader *so)
2476 {
2477 const struct vc4_key *key = entry->key;
2478
2479 if (key->shader_state == so) {
2480 struct vc4_compiled_shader *shader = entry->data;
2481 _mesa_hash_table_remove(ht, entry);
2482 vc4_bo_unreference(&shader->bo);
2483 ralloc_free(shader);
2484 }
2485 }
2486
2487 static void
2488 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
2489 {
2490 struct vc4_context *vc4 = vc4_context(pctx);
2491 struct vc4_uncompiled_shader *so = hwcso;
2492
2493 struct hash_entry *entry;
2494 hash_table_foreach(vc4->fs_cache, entry)
2495 delete_from_cache_if_matches(vc4->fs_cache, entry, so);
2496 hash_table_foreach(vc4->vs_cache, entry)
2497 delete_from_cache_if_matches(vc4->vs_cache, entry, so);
2498
2499 if (so->twoside_tokens != so->base.tokens)
2500 free((void *)so->twoside_tokens);
2501 free((void *)so->base.tokens);
2502 free(so);
2503 }
2504
2505 static uint32_t translate_wrap(uint32_t p_wrap, bool using_nearest)
2506 {
2507 switch (p_wrap) {
2508 case PIPE_TEX_WRAP_REPEAT:
2509 return 0;
2510 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
2511 return 1;
2512 case PIPE_TEX_WRAP_MIRROR_REPEAT:
2513 return 2;
2514 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
2515 return 3;
2516 case PIPE_TEX_WRAP_CLAMP:
2517 return (using_nearest ? 1 : 3);
2518 default:
2519 fprintf(stderr, "Unknown wrap mode %d\n", p_wrap);
2520 assert(!"not reached");
2521 return 0;
2522 }
2523 }
2524
2525 static void
2526 write_texture_p0(struct vc4_context *vc4,
2527 struct vc4_texture_stateobj *texstate,
2528 uint32_t unit)
2529 {
2530 struct pipe_sampler_view *texture = texstate->textures[unit];
2531 struct vc4_resource *rsc = vc4_resource(texture->texture);
2532
2533 cl_reloc(vc4, &vc4->uniforms, rsc->bo,
2534 VC4_SET_FIELD(rsc->slices[0].offset >> 12, VC4_TEX_P0_OFFSET) |
2535 VC4_SET_FIELD(texture->u.tex.last_level -
2536 texture->u.tex.first_level, VC4_TEX_P0_MIPLVLS) |
2537 VC4_SET_FIELD(texture->target == PIPE_TEXTURE_CUBE,
2538 VC4_TEX_P0_CMMODE) |
2539 VC4_SET_FIELD(rsc->vc4_format & 7, VC4_TEX_P0_TYPE));
2540 }
2541
2542 static void
2543 write_texture_p1(struct vc4_context *vc4,
2544 struct vc4_texture_stateobj *texstate,
2545 uint32_t unit)
2546 {
2547 struct pipe_sampler_view *texture = texstate->textures[unit];
2548 struct vc4_resource *rsc = vc4_resource(texture->texture);
2549 struct pipe_sampler_state *sampler = texstate->samplers[unit];
2550 static const uint8_t minfilter_map[6] = {
2551 VC4_TEX_P1_MINFILT_NEAR_MIP_NEAR,
2552 VC4_TEX_P1_MINFILT_LIN_MIP_NEAR,
2553 VC4_TEX_P1_MINFILT_NEAR_MIP_LIN,
2554 VC4_TEX_P1_MINFILT_LIN_MIP_LIN,
2555 VC4_TEX_P1_MINFILT_NEAREST,
2556 VC4_TEX_P1_MINFILT_LINEAR,
2557 };
2558 static const uint32_t magfilter_map[] = {
2559 [PIPE_TEX_FILTER_NEAREST] = VC4_TEX_P1_MAGFILT_NEAREST,
2560 [PIPE_TEX_FILTER_LINEAR] = VC4_TEX_P1_MAGFILT_LINEAR,
2561 };
2562
2563 bool either_nearest =
2564 (sampler->mag_img_filter == PIPE_TEX_MIPFILTER_NEAREST ||
2565 sampler->min_img_filter == PIPE_TEX_MIPFILTER_NEAREST);
2566
2567 cl_aligned_u32(&vc4->uniforms,
2568 VC4_SET_FIELD(rsc->vc4_format >> 4, VC4_TEX_P1_TYPE4) |
2569 VC4_SET_FIELD(texture->texture->height0 & 2047,
2570 VC4_TEX_P1_HEIGHT) |
2571 VC4_SET_FIELD(texture->texture->width0 & 2047,
2572 VC4_TEX_P1_WIDTH) |
2573 VC4_SET_FIELD(magfilter_map[sampler->mag_img_filter],
2574 VC4_TEX_P1_MAGFILT) |
2575 VC4_SET_FIELD(minfilter_map[sampler->min_mip_filter * 2 +
2576 sampler->min_img_filter],
2577 VC4_TEX_P1_MINFILT) |
2578 VC4_SET_FIELD(translate_wrap(sampler->wrap_s, either_nearest),
2579 VC4_TEX_P1_WRAP_S) |
2580 VC4_SET_FIELD(translate_wrap(sampler->wrap_t, either_nearest),
2581 VC4_TEX_P1_WRAP_T));
2582 }
2583
2584 static void
2585 write_texture_p2(struct vc4_context *vc4,
2586 struct vc4_texture_stateobj *texstate,
2587 uint32_t data)
2588 {
2589 uint32_t unit = data & 0xffff;
2590 struct pipe_sampler_view *texture = texstate->textures[unit];
2591 struct vc4_resource *rsc = vc4_resource(texture->texture);
2592
2593 cl_aligned_u32(&vc4->uniforms,
2594 VC4_SET_FIELD(VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE,
2595 VC4_TEX_P2_PTYPE) |
2596 VC4_SET_FIELD(rsc->cube_map_stride >> 12, VC4_TEX_P2_CMST) |
2597 VC4_SET_FIELD((data >> 16) & 1, VC4_TEX_P2_BSLOD));
2598 }
2599
2600
2601 #define SWIZ(x,y,z,w) { \
2602 UTIL_FORMAT_SWIZZLE_##x, \
2603 UTIL_FORMAT_SWIZZLE_##y, \
2604 UTIL_FORMAT_SWIZZLE_##z, \
2605 UTIL_FORMAT_SWIZZLE_##w \
2606 }
2607
2608 static void
2609 write_texture_border_color(struct vc4_context *vc4,
2610 struct vc4_texture_stateobj *texstate,
2611 uint32_t unit)
2612 {
2613 struct pipe_sampler_state *sampler = texstate->samplers[unit];
2614 struct pipe_sampler_view *texture = texstate->textures[unit];
2615 struct vc4_resource *rsc = vc4_resource(texture->texture);
2616 union util_color uc;
2617
2618 const struct util_format_description *tex_format_desc =
2619 util_format_description(texture->format);
2620
2621 float border_color[4];
2622 for (int i = 0; i < 4; i++)
2623 border_color[i] = sampler->border_color.f[i];
2624 if (util_format_is_srgb(texture->format)) {
2625 for (int i = 0; i < 3; i++)
2626 border_color[i] =
2627 util_format_linear_to_srgb_float(border_color[i]);
2628 }
2629
2630 /* Turn the border color into the layout of channels that it would
2631 * have when stored as texture contents.
2632 */
2633 float storage_color[4];
2634 util_format_unswizzle_4f(storage_color,
2635 border_color,
2636 tex_format_desc->swizzle);
2637
2638 /* Now, pack so that when the vc4_format-sampled texture contents are
2639 * replaced with our border color, the vc4_get_format_swizzle()
2640 * swizzling will get the right channels.
2641 */
2642 if (util_format_is_depth_or_stencil(texture->format)) {
2643 uc.ui[0] = util_pack_z(PIPE_FORMAT_Z24X8_UNORM,
2644 sampler->border_color.f[0]) << 8;
2645 } else {
2646 switch (rsc->vc4_format) {
2647 default:
2648 case VC4_TEXTURE_TYPE_RGBA8888:
2649 util_pack_color(storage_color,
2650 PIPE_FORMAT_R8G8B8A8_UNORM, &uc);
2651 break;
2652 case VC4_TEXTURE_TYPE_RGBA4444:
2653 util_pack_color(storage_color,
2654 PIPE_FORMAT_A8B8G8R8_UNORM, &uc);
2655 break;
2656 case VC4_TEXTURE_TYPE_RGB565:
2657 util_pack_color(storage_color,
2658 PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
2659 break;
2660 case VC4_TEXTURE_TYPE_ALPHA:
2661 uc.ui[0] = float_to_ubyte(storage_color[0]) << 24;
2662 break;
2663 case VC4_TEXTURE_TYPE_LUMALPHA:
2664 uc.ui[0] = ((float_to_ubyte(storage_color[1]) << 24) |
2665 (float_to_ubyte(storage_color[0]) << 0));
2666 break;
2667 }
2668 }
2669
2670 cl_aligned_u32(&vc4->uniforms, uc.ui[0]);
2671 }
2672
2673 static uint32_t
2674 get_texrect_scale(struct vc4_texture_stateobj *texstate,
2675 enum quniform_contents contents,
2676 uint32_t data)
2677 {
2678 struct pipe_sampler_view *texture = texstate->textures[data];
2679 uint32_t dim;
2680
2681 if (contents == QUNIFORM_TEXRECT_SCALE_X)
2682 dim = texture->texture->width0;
2683 else
2684 dim = texture->texture->height0;
2685
2686 return fui(1.0f / dim);
2687 }
2688
2689 static struct vc4_bo *
2690 vc4_upload_ubo(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
2691 const uint32_t *gallium_uniforms)
2692 {
2693 if (!shader->ubo_size)
2694 return NULL;
2695
2696 struct vc4_bo *ubo = vc4_bo_alloc(vc4->screen, shader->ubo_size, "ubo");
2697 uint32_t *data = vc4_bo_map(ubo);
2698 for (uint32_t i = 0; i < shader->num_ubo_ranges; i++) {
2699 memcpy(data + shader->ubo_ranges[i].dst_offset,
2700 gallium_uniforms + shader->ubo_ranges[i].src_offset,
2701 shader->ubo_ranges[i].size);
2702 }
2703
2704 return ubo;
2705 }
2706
2707 void
2708 vc4_write_uniforms(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
2709 struct vc4_constbuf_stateobj *cb,
2710 struct vc4_texture_stateobj *texstate)
2711 {
2712 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
2713 const uint32_t *gallium_uniforms = cb->cb[0].user_buffer;
2714 struct vc4_bo *ubo = vc4_upload_ubo(vc4, shader, gallium_uniforms);
2715
2716 cl_ensure_space(&vc4->uniforms, (uinfo->count +
2717 uinfo->num_texture_samples) * 4);
2718
2719 cl_start_shader_reloc(&vc4->uniforms, uinfo->num_texture_samples);
2720
2721 for (int i = 0; i < uinfo->count; i++) {
2722
2723 switch (uinfo->contents[i]) {
2724 case QUNIFORM_CONSTANT:
2725 cl_aligned_u32(&vc4->uniforms, uinfo->data[i]);
2726 break;
2727 case QUNIFORM_UNIFORM:
2728 cl_aligned_u32(&vc4->uniforms,
2729 gallium_uniforms[uinfo->data[i]]);
2730 break;
2731 case QUNIFORM_VIEWPORT_X_SCALE:
2732 cl_aligned_f(&vc4->uniforms, vc4->viewport.scale[0] * 16.0f);
2733 break;
2734 case QUNIFORM_VIEWPORT_Y_SCALE:
2735 cl_aligned_f(&vc4->uniforms, vc4->viewport.scale[1] * 16.0f);
2736 break;
2737
2738 case QUNIFORM_VIEWPORT_Z_OFFSET:
2739 cl_aligned_f(&vc4->uniforms, vc4->viewport.translate[2]);
2740 break;
2741 case QUNIFORM_VIEWPORT_Z_SCALE:
2742 cl_aligned_f(&vc4->uniforms, vc4->viewport.scale[2]);
2743 break;
2744
2745 case QUNIFORM_USER_CLIP_PLANE:
2746 cl_aligned_f(&vc4->uniforms,
2747 vc4->clip.ucp[uinfo->data[i] / 4][uinfo->data[i] % 4]);
2748 break;
2749
2750 case QUNIFORM_TEXTURE_CONFIG_P0:
2751 write_texture_p0(vc4, texstate, uinfo->data[i]);
2752 break;
2753
2754 case QUNIFORM_TEXTURE_CONFIG_P1:
2755 write_texture_p1(vc4, texstate, uinfo->data[i]);
2756 break;
2757
2758 case QUNIFORM_TEXTURE_CONFIG_P2:
2759 write_texture_p2(vc4, texstate, uinfo->data[i]);
2760 break;
2761
2762 case QUNIFORM_UBO_ADDR:
2763 cl_aligned_reloc(vc4, &vc4->uniforms, ubo, 0);
2764 break;
2765
2766 case QUNIFORM_TEXTURE_BORDER_COLOR:
2767 write_texture_border_color(vc4, texstate, uinfo->data[i]);
2768 break;
2769
2770 case QUNIFORM_TEXRECT_SCALE_X:
2771 case QUNIFORM_TEXRECT_SCALE_Y:
2772 cl_aligned_u32(&vc4->uniforms,
2773 get_texrect_scale(texstate,
2774 uinfo->contents[i],
2775 uinfo->data[i]));
2776 break;
2777
2778 case QUNIFORM_BLEND_CONST_COLOR:
2779 cl_aligned_f(&vc4->uniforms,
2780 vc4->blend_color.color[uinfo->data[i]]);
2781 break;
2782
2783 case QUNIFORM_STENCIL:
2784 cl_aligned_u32(&vc4->uniforms,
2785 vc4->zsa->stencil_uniforms[uinfo->data[i]] |
2786 (uinfo->data[i] <= 1 ?
2787 (vc4->stencil_ref.ref_value[uinfo->data[i]] << 8) :
2788 0));
2789 break;
2790
2791 case QUNIFORM_ALPHA_REF:
2792 cl_aligned_f(&vc4->uniforms,
2793 vc4->zsa->base.alpha.ref_value);
2794 break;
2795 }
2796 #if 0
2797 uint32_t written_val = *(uint32_t *)(vc4->uniforms.next - 4);
2798 fprintf(stderr, "%p: %d / 0x%08x (%f)\n",
2799 shader, i, written_val, uif(written_val));
2800 #endif
2801 }
2802 }
2803
2804 static void
2805 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
2806 {
2807 struct vc4_context *vc4 = vc4_context(pctx);
2808 vc4->prog.bind_fs = hwcso;
2809 vc4->prog.dirty |= VC4_SHADER_DIRTY_FP;
2810 vc4->dirty |= VC4_DIRTY_PROG;
2811 }
2812
2813 static void
2814 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
2815 {
2816 struct vc4_context *vc4 = vc4_context(pctx);
2817 vc4->prog.bind_vs = hwcso;
2818 vc4->prog.dirty |= VC4_SHADER_DIRTY_VP;
2819 vc4->dirty |= VC4_DIRTY_PROG;
2820 }
2821
2822 void
2823 vc4_program_init(struct pipe_context *pctx)
2824 {
2825 struct vc4_context *vc4 = vc4_context(pctx);
2826
2827 pctx->create_vs_state = vc4_shader_state_create;
2828 pctx->delete_vs_state = vc4_shader_state_delete;
2829
2830 pctx->create_fs_state = vc4_shader_state_create;
2831 pctx->delete_fs_state = vc4_shader_state_delete;
2832
2833 pctx->bind_fs_state = vc4_fp_state_bind;
2834 pctx->bind_vs_state = vc4_vp_state_bind;
2835
2836 vc4->fs_cache = _mesa_hash_table_create(pctx, fs_cache_hash,
2837 fs_cache_compare);
2838 vc4->vs_cache = _mesa_hash_table_create(pctx, vs_cache_hash,
2839 vs_cache_compare);
2840 }
2841
2842 void
2843 vc4_program_fini(struct pipe_context *pctx)
2844 {
2845 struct vc4_context *vc4 = vc4_context(pctx);
2846
2847 struct hash_entry *entry;
2848 hash_table_foreach(vc4->fs_cache, entry) {
2849 struct vc4_compiled_shader *shader = entry->data;
2850 vc4_bo_unreference(&shader->bo);
2851 ralloc_free(shader);
2852 _mesa_hash_table_remove(vc4->fs_cache, entry);
2853 }
2854
2855 hash_table_foreach(vc4->vs_cache, entry) {
2856 struct vc4_compiled_shader *shader = entry->data;
2857 vc4_bo_unreference(&shader->bo);
2858 ralloc_free(shader);
2859 _mesa_hash_table_remove(vc4->vs_cache, entry);
2860 }
2861 }