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vc4: Fix viewport handling in the uniforms upload.
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <stdio.h>
26 #include <inttypes.h>
27 #include "pipe/p_state.h"
28 #include "util/u_format.h"
29 #include "util/u_hash_table.h"
30 #include "util/u_hash.h"
31 #include "util/u_memory.h"
32 #include "tgsi/tgsi_parse.h"
33 #include "tgsi/tgsi_dump.h"
34
35 #include "vc4_context.h"
36 #include "vc4_qpu.h"
37 #include "vc4_qir.h"
38 #ifdef USE_VC4_SIMULATOR
39 #include "simpenrose/simpenrose.h"
40 #endif
41
42 struct tgsi_to_qir {
43 struct tgsi_parse_context parser;
44 struct qcompile *c;
45 struct qreg *temps;
46 struct qreg *inputs;
47 struct qreg *outputs;
48 struct qreg *uniforms;
49 struct qreg *consts;
50 struct qreg line_x, point_x, point_y;
51
52 uint32_t num_consts;
53
54 struct pipe_shader_state *shader_state;
55 struct vc4_fs_key *fs_key;
56 struct vc4_vs_key *vs_key;
57
58 uint32_t *uniform_data;
59 enum quniform_contents *uniform_contents;
60 uint32_t num_uniforms;
61 uint32_t num_outputs;
62 uint32_t num_texture_samples;
63 };
64
65 struct vc4_key {
66 struct pipe_shader_state *shader_state;
67 };
68
69 struct vc4_fs_key {
70 struct vc4_key base;
71 enum pipe_format color_format;
72 bool depth_enabled;
73 bool is_points;
74 bool is_lines;
75
76 struct pipe_rt_blend_state blend;
77 };
78
79 struct vc4_vs_key {
80 struct vc4_key base;
81 enum pipe_format attr_formats[8];
82 };
83
84 static struct qreg
85 add_uniform(struct tgsi_to_qir *trans,
86 enum quniform_contents contents,
87 uint32_t data)
88 {
89 uint32_t uniform = trans->num_uniforms++;
90 struct qreg u = { QFILE_UNIF, uniform };
91
92 trans->uniform_contents[uniform] = contents;
93 trans->uniform_data[uniform] = data;
94
95 return u;
96 }
97
98 static struct qreg
99 get_temp_for_uniform(struct tgsi_to_qir *trans, enum quniform_contents contents,
100 uint32_t data)
101 {
102 struct qcompile *c = trans->c;
103
104 for (int i = 0; i < trans->num_uniforms; i++) {
105 if (trans->uniform_contents[i] == contents &&
106 trans->uniform_data[i] == data)
107 return trans->uniforms[i];
108 }
109
110 struct qreg u = add_uniform(trans, contents, data);
111 struct qreg t = qir_MOV(c, u);
112
113 trans->uniforms[u.index] = t;
114 return t;
115 }
116
117 static struct qreg
118 qir_uniform_ui(struct tgsi_to_qir *trans, uint32_t ui)
119 {
120 return get_temp_for_uniform(trans, QUNIFORM_CONSTANT, ui);
121 }
122
123 static struct qreg
124 qir_uniform_f(struct tgsi_to_qir *trans, float f)
125 {
126 return qir_uniform_ui(trans, fui(f));
127 }
128
129 static struct qreg
130 get_src(struct tgsi_to_qir *trans, struct tgsi_src_register *src, int i)
131 {
132 struct qcompile *c = trans->c;
133 struct qreg r = c->undef;
134
135 uint32_t s = i;
136 switch (i) {
137 case TGSI_SWIZZLE_X:
138 s = src->SwizzleX;
139 break;
140 case TGSI_SWIZZLE_Y:
141 s = src->SwizzleY;
142 break;
143 case TGSI_SWIZZLE_Z:
144 s = src->SwizzleZ;
145 break;
146 case TGSI_SWIZZLE_W:
147 s = src->SwizzleW;
148 break;
149 default:
150 abort();
151 }
152
153 assert(!src->Indirect);
154
155 switch (src->File) {
156 case TGSI_FILE_NULL:
157 return r;
158 case TGSI_FILE_TEMPORARY:
159 r = trans->temps[src->Index * 4 + s];
160 break;
161 case TGSI_FILE_IMMEDIATE:
162 r = trans->consts[src->Index * 4 + s];
163 break;
164 case TGSI_FILE_CONSTANT:
165 r = get_temp_for_uniform(trans, QUNIFORM_UNIFORM,
166 src->Index * 4 + s);
167 break;
168 case TGSI_FILE_INPUT:
169 r = trans->inputs[src->Index * 4 + s];
170 break;
171 case TGSI_FILE_SAMPLER:
172 case TGSI_FILE_SAMPLER_VIEW:
173 r = c->undef;
174 break;
175 default:
176 fprintf(stderr, "unknown src file %d\n", src->File);
177 abort();
178 }
179
180 if (src->Absolute)
181 r = qir_FMAXABS(c, r, r);
182
183 if (src->Negate)
184 r = qir_FSUB(c, qir_uniform_f(trans, 0), r);
185
186 return r;
187 };
188
189
190 static void
191 update_dst(struct tgsi_to_qir *trans, struct tgsi_full_instruction *tgsi_inst,
192 int i, struct qreg val)
193 {
194 struct tgsi_dst_register *tgsi_dst = &tgsi_inst->Dst[0].Register;
195
196 assert(!tgsi_dst->Indirect);
197
198 switch (tgsi_dst->File) {
199 case TGSI_FILE_TEMPORARY:
200 trans->temps[tgsi_dst->Index * 4 + i] = val;
201 break;
202 case TGSI_FILE_OUTPUT:
203 trans->outputs[tgsi_dst->Index * 4 + i] = val;
204 trans->num_outputs = MAX2(trans->num_outputs,
205 tgsi_dst->Index * 4 + i + 1);
206 break;
207 default:
208 fprintf(stderr, "unknown dst file %d\n", tgsi_dst->File);
209 abort();
210 }
211 };
212
213 static struct qreg
214 tgsi_to_qir_alu(struct tgsi_to_qir *trans,
215 struct tgsi_full_instruction *tgsi_inst,
216 enum qop op, struct qreg *src, int i)
217 {
218 struct qcompile *c = trans->c;
219 struct qreg dst = qir_get_temp(c);
220 qir_emit(c, qir_inst4(op, dst,
221 src[0 * 4 + i],
222 src[1 * 4 + i],
223 src[2 * 4 + i],
224 c->undef));
225 return dst;
226 }
227
228 static struct qreg
229 tgsi_to_qir_mad(struct tgsi_to_qir *trans,
230 struct tgsi_full_instruction *tgsi_inst,
231 enum qop op, struct qreg *src, int i)
232 {
233 struct qcompile *c = trans->c;
234 return qir_FADD(c,
235 qir_FMUL(c,
236 src[0 * 4 + i],
237 src[1 * 4 + i]),
238 src[2 * 4 + i]);
239 }
240
241 static struct qreg
242 tgsi_to_qir_lit(struct tgsi_to_qir *trans,
243 struct tgsi_full_instruction *tgsi_inst,
244 enum qop op, struct qreg *src, int i)
245 {
246 struct qcompile *c = trans->c;
247 struct qreg x = src[0 * 4 + 0];
248 struct qreg y = src[0 * 4 + 1];
249 struct qreg w = src[0 * 4 + 3];
250
251 switch (i) {
252 case 0:
253 case 3:
254 return qir_uniform_f(trans, 1.0);
255 case 1:
256 return qir_FMAX(c, src[0 * 4 + 0], qir_uniform_f(trans, 0.0));
257 case 2: {
258 struct qreg zero = qir_uniform_f(trans, 0.0);
259
260 /* XXX: Clamp w to -128..128 */
261 return qir_CMP(c,
262 x,
263 zero,
264 qir_EXP2(c, qir_FMUL(c,
265 w,
266 qir_LOG2(c,
267 qir_FMAX(c,
268 y,
269 zero)))));
270 }
271 default:
272 assert(!"not reached");
273 return c->undef;
274 }
275 }
276
277 static struct qreg
278 tgsi_to_qir_lrp(struct tgsi_to_qir *trans,
279 struct tgsi_full_instruction *tgsi_inst,
280 enum qop op, struct qreg *src, int i)
281 {
282 struct qcompile *c = trans->c;
283 struct qreg src0 = src[0 * 4 + i];
284 struct qreg src1 = src[1 * 4 + i];
285 struct qreg src2 = src[2 * 4 + i];
286
287 /* LRP is:
288 * src0 * src1 + (1 - src0) * src2.
289 * -> src0 * src1 + src2 - src0 * src2
290 * -> src2 + src0 * (src1 - src2)
291 */
292 return qir_FADD(c, src2, qir_FMUL(c, src0, qir_FSUB(c, src1, src2)));
293
294 }
295
296 static void
297 tgsi_to_qir_tex(struct tgsi_to_qir *trans,
298 struct tgsi_full_instruction *tgsi_inst,
299 enum qop op, struct qreg *src)
300 {
301 struct qcompile *c = trans->c;
302
303 assert(!tgsi_inst->Instruction.Saturate);
304
305 struct qreg s = src[0 * 4 + 0];
306 struct qreg t = src[0 * 4 + 1];
307
308 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
309 struct qreg proj = qir_RCP(c, src[0 * 4 + 3]);
310 s = qir_FMUL(c, s, proj);
311 t = qir_FMUL(c, t, proj);
312 }
313
314 /* There is no native support for GL texture rectangle coordinates, so
315 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
316 * 1]).
317 */
318 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_RECT) {
319 uint32_t sampler = 0; /* XXX */
320 s = qir_FMUL(c, s,
321 get_temp_for_uniform(trans,
322 QUNIFORM_TEXRECT_SCALE_X,
323 sampler));
324 t = qir_FMUL(c, t,
325 get_temp_for_uniform(trans,
326 QUNIFORM_TEXRECT_SCALE_Y,
327 sampler));
328 }
329
330 uint32_t tex_and_sampler = 0; /* XXX */
331 qir_TEX_T(c, t, add_uniform(trans, QUNIFORM_TEXTURE_CONFIG_P0,
332 tex_and_sampler));
333
334 struct qreg sampler_p1 = add_uniform(trans, QUNIFORM_TEXTURE_CONFIG_P1,
335 tex_and_sampler);
336 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB) {
337 qir_TEX_B(c, src[0 * 4 + 3], sampler_p1);
338 qir_TEX_S(c, s, add_uniform(trans, QUNIFORM_CONSTANT, 0));
339 } else {
340 qir_TEX_S(c, s, sampler_p1);
341 }
342
343 trans->num_texture_samples++;
344 qir_emit(c, qir_inst(QOP_TEX_RESULT, c->undef, c->undef, c->undef));
345
346 for (int i = 0; i < 4; i++) {
347 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
348 continue;
349
350 struct qreg dst = qir_get_temp(c);
351 qir_emit(c, qir_inst(QOP_R4_UNPACK_A + i,
352 dst,
353 c->undef, c->undef));
354 update_dst(trans, tgsi_inst, i, dst);
355 }
356 }
357
358 static struct qreg
359 tgsi_to_qir_pow(struct tgsi_to_qir *trans,
360 struct tgsi_full_instruction *tgsi_inst,
361 enum qop op, struct qreg *src, int i)
362 {
363 struct qcompile *c = trans->c;
364
365 /* Note that this instruction replicates its result from the x channel
366 */
367 return qir_EXP2(c, qir_FMUL(c,
368 src[1 * 4 + 0],
369 qir_LOG2(c, src[0 * 4 + 0])));
370 }
371
372 static struct qreg
373 tgsi_to_qir_trunc(struct tgsi_to_qir *trans,
374 struct tgsi_full_instruction *tgsi_inst,
375 enum qop op, struct qreg *src, int i)
376 {
377 struct qcompile *c = trans->c;
378 return qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
379 }
380
381 /**
382 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
383 * to zero).
384 */
385 static struct qreg
386 tgsi_to_qir_frc(struct tgsi_to_qir *trans,
387 struct tgsi_full_instruction *tgsi_inst,
388 enum qop op, struct qreg *src, int i)
389 {
390 struct qcompile *c = trans->c;
391 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
392 struct qreg diff = qir_FSUB(c, src[0 * 4 + i], trunc);
393 return qir_CMP(c,
394 diff,
395 qir_FADD(c, diff, qir_uniform_f(trans, 1.0)),
396 diff);
397 }
398
399 /**
400 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
401 * zero).
402 */
403 static struct qreg
404 tgsi_to_qir_flr(struct tgsi_to_qir *trans,
405 struct tgsi_full_instruction *tgsi_inst,
406 enum qop op, struct qreg *src, int i)
407 {
408 struct qcompile *c = trans->c;
409 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
410 return qir_CMP(c,
411 src[0 * 4 + i],
412 qir_FSUB(c, trunc, qir_uniform_f(trans, 1.0)),
413 trunc);
414 }
415
416 static struct qreg
417 tgsi_to_qir_dp(struct tgsi_to_qir *trans,
418 struct tgsi_full_instruction *tgsi_inst,
419 int num, struct qreg *src, int i)
420 {
421 struct qcompile *c = trans->c;
422
423 struct qreg sum = qir_FMUL(c, src[0 * 4 + 0], src[1 * 4 + 0]);
424 for (int j = 1; j < num; j++) {
425 sum = qir_FADD(c, sum, qir_FMUL(c,
426 src[0 * 4 + j],
427 src[1 * 4 + j]));
428 }
429 return sum;
430 }
431
432 static struct qreg
433 tgsi_to_qir_dp2(struct tgsi_to_qir *trans,
434 struct tgsi_full_instruction *tgsi_inst,
435 enum qop op, struct qreg *src, int i)
436 {
437 return tgsi_to_qir_dp(trans, tgsi_inst, 2, src, i);
438 }
439
440 static struct qreg
441 tgsi_to_qir_dp3(struct tgsi_to_qir *trans,
442 struct tgsi_full_instruction *tgsi_inst,
443 enum qop op, struct qreg *src, int i)
444 {
445 return tgsi_to_qir_dp(trans, tgsi_inst, 3, src, i);
446 }
447
448 static struct qreg
449 tgsi_to_qir_dp4(struct tgsi_to_qir *trans,
450 struct tgsi_full_instruction *tgsi_inst,
451 enum qop op, struct qreg *src, int i)
452 {
453 return tgsi_to_qir_dp(trans, tgsi_inst, 4, src, i);
454 }
455
456 static struct qreg
457 tgsi_to_qir_abs(struct tgsi_to_qir *trans,
458 struct tgsi_full_instruction *tgsi_inst,
459 enum qop op, struct qreg *src, int i)
460 {
461 struct qcompile *c = trans->c;
462 struct qreg arg = src[0 * 4 + i];
463 return qir_FMAXABS(c, arg, arg);
464 }
465
466 /* Note that this instruction replicates its result from the x channel */
467 static struct qreg
468 tgsi_to_qir_sin(struct tgsi_to_qir *trans,
469 struct tgsi_full_instruction *tgsi_inst,
470 enum qop op, struct qreg *src, int i)
471 {
472 struct qcompile *c = trans->c;
473 float coeff[] = {
474 2.0 * M_PI,
475 -pow(2.0 * M_PI, 3) / (3 * 2 * 1),
476 pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
477 -pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
478 };
479
480 struct qreg scaled_x =
481 qir_FMUL(c,
482 src[0 * 4 + 0],
483 qir_uniform_f(trans, 1.0f / (M_PI * 2.0f)));
484
485
486 struct qreg x = tgsi_to_qir_frc(trans, NULL, 0, &scaled_x, 0);
487 struct qreg x2 = qir_FMUL(c, x, x);
488 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(trans, coeff[0]));
489 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
490 x = qir_FMUL(c, x, x2);
491 sum = qir_FADD(c,
492 sum,
493 qir_FMUL(c,
494 x,
495 qir_uniform_f(trans, coeff[i])));
496 }
497 return sum;
498 }
499
500 /* Note that this instruction replicates its result from the x channel */
501 static struct qreg
502 tgsi_to_qir_cos(struct tgsi_to_qir *trans,
503 struct tgsi_full_instruction *tgsi_inst,
504 enum qop op, struct qreg *src, int i)
505 {
506 struct qcompile *c = trans->c;
507 float coeff[] = {
508 1.0f,
509 -pow(2.0 * M_PI, 2) / (2 * 1),
510 pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
511 -pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
512 };
513
514 struct qreg scaled_x =
515 qir_FMUL(c, src[0 * 4 + 0],
516 qir_uniform_f(trans, 1.0f / (M_PI * 2.0f)));
517 struct qreg x_frac = tgsi_to_qir_frc(trans, NULL, 0, &scaled_x, 0);
518
519 struct qreg sum = qir_uniform_f(trans, coeff[0]);
520 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
521 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
522 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
523 if (i != 1)
524 x = qir_FMUL(c, x, x2);
525
526 struct qreg mul = qir_FMUL(c,
527 x,
528 qir_uniform_f(trans, coeff[i]));
529 if (i == 0)
530 sum = mul;
531 else
532 sum = qir_FADD(c, sum, mul);
533 }
534 return sum;
535 }
536
537 static void
538 emit_vertex_input(struct tgsi_to_qir *trans, int attr)
539 {
540 enum pipe_format format = trans->vs_key->attr_formats[attr];
541 struct qcompile *c = trans->c;
542 struct qreg vpm_reads[4];
543
544 /* Right now, we're setting the VPM offsets to be 16 bytes wide every
545 * time, so we always read 4 32-bit VPM entries.
546 */
547 for (int i = 0; i < 4; i++) {
548 vpm_reads[i] = qir_get_temp(c);
549 qir_emit(c, qir_inst(QOP_VPM_READ,
550 vpm_reads[i],
551 c->undef,
552 c->undef));
553 c->num_inputs++;
554 }
555
556 bool format_warned = false;
557 const struct util_format_description *desc =
558 util_format_description(format);
559
560 for (int i = 0; i < 4; i++) {
561 uint8_t swiz = desc->swizzle[i];
562
563 switch (swiz) {
564 case UTIL_FORMAT_SWIZZLE_NONE:
565 if (!format_warned) {
566 fprintf(stderr,
567 "vtx element %d NONE swizzle: %s\n",
568 attr, util_format_name(format));
569 format_warned = true;
570 }
571 /* FALLTHROUGH */
572 case UTIL_FORMAT_SWIZZLE_0:
573 trans->inputs[attr * 4 + i] = qir_uniform_f(trans, 0.0);
574 break;
575 case UTIL_FORMAT_SWIZZLE_1:
576 trans->inputs[attr * 4 + i] = qir_uniform_f(trans, 1.0);
577 break;
578 default:
579 if (!format_warned &&
580 (desc->channel[swiz].type != UTIL_FORMAT_TYPE_FLOAT ||
581 desc->channel[swiz].size != 32)) {
582 fprintf(stderr,
583 "vtx element %d unsupported type: %s\n",
584 attr, util_format_name(format));
585 format_warned = true;
586 }
587
588 trans->inputs[attr * 4 + i] = vpm_reads[swiz];
589 break;
590 }
591 }
592 }
593
594 static void
595 emit_fragcoord_input(struct tgsi_to_qir *trans, int attr)
596 {
597 struct qcompile *c = trans->c;
598
599 trans->inputs[attr * 4 + 0] = qir_FRAG_X(c);
600 trans->inputs[attr * 4 + 1] = qir_FRAG_Y(c);
601 trans->inputs[attr * 4 + 2] =
602 qir_FMUL(c,
603 qir_FRAG_Z(c),
604 qir_uniform_f(trans, 1.0 / 0xffffff));
605 trans->inputs[attr * 4 + 3] = qir_FRAG_RCP_W(c);
606 }
607
608 static struct qreg
609 emit_fragment_varying(struct tgsi_to_qir *trans, int index)
610 {
611 struct qcompile *c = trans->c;
612
613 struct qreg vary = {
614 QFILE_VARY,
615 index
616 };
617
618 /* XXX: multiply by W */
619 return qir_VARY_ADD_C(c, qir_MOV(c, vary));
620 }
621
622 static void
623 emit_fragment_input(struct tgsi_to_qir *trans, int attr)
624 {
625 struct qcompile *c = trans->c;
626
627 for (int i = 0; i < 4; i++) {
628 trans->inputs[attr * 4 + i] =
629 emit_fragment_varying(trans, attr * 4 + i);
630 c->num_inputs++;
631 }
632 }
633
634 static void
635 emit_tgsi_declaration(struct tgsi_to_qir *trans,
636 struct tgsi_full_declaration *decl)
637 {
638 struct qcompile *c = trans->c;
639
640 switch (decl->Declaration.File) {
641 case TGSI_FILE_INPUT:
642 for (int i = decl->Range.First;
643 i <= decl->Range.Last;
644 i++) {
645 if (c->stage == QSTAGE_FRAG) {
646 if (decl->Semantic.Name ==
647 TGSI_SEMANTIC_POSITION) {
648 emit_fragcoord_input(trans, i);
649 } else {
650 emit_fragment_input(trans, i);
651 }
652 } else {
653 emit_vertex_input(trans, i);
654 }
655 }
656 break;
657 }
658 }
659
660 static void
661 emit_tgsi_instruction(struct tgsi_to_qir *trans,
662 struct tgsi_full_instruction *tgsi_inst)
663 {
664 struct qcompile *c = trans->c;
665 struct {
666 enum qop op;
667 struct qreg (*func)(struct tgsi_to_qir *trans,
668 struct tgsi_full_instruction *tgsi_inst,
669 enum qop op,
670 struct qreg *src, int i);
671 } op_trans[] = {
672 [TGSI_OPCODE_MOV] = { QOP_MOV, tgsi_to_qir_alu },
673 [TGSI_OPCODE_ABS] = { 0, tgsi_to_qir_abs },
674 [TGSI_OPCODE_MUL] = { QOP_FMUL, tgsi_to_qir_alu },
675 [TGSI_OPCODE_ADD] = { QOP_FADD, tgsi_to_qir_alu },
676 [TGSI_OPCODE_SUB] = { QOP_FSUB, tgsi_to_qir_alu },
677 [TGSI_OPCODE_MIN] = { QOP_FMIN, tgsi_to_qir_alu },
678 [TGSI_OPCODE_MAX] = { QOP_FMAX, tgsi_to_qir_alu },
679 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_alu },
680 [TGSI_OPCODE_SEQ] = { QOP_SEQ, tgsi_to_qir_alu },
681 [TGSI_OPCODE_SNE] = { QOP_SNE, tgsi_to_qir_alu },
682 [TGSI_OPCODE_SGE] = { QOP_SGE, tgsi_to_qir_alu },
683 [TGSI_OPCODE_SLT] = { QOP_SLT, tgsi_to_qir_alu },
684 [TGSI_OPCODE_CMP] = { QOP_CMP, tgsi_to_qir_alu },
685 [TGSI_OPCODE_MAD] = { 0, tgsi_to_qir_mad },
686 [TGSI_OPCODE_DP2] = { 0, tgsi_to_qir_dp2 },
687 [TGSI_OPCODE_DP3] = { 0, tgsi_to_qir_dp3 },
688 [TGSI_OPCODE_DP4] = { 0, tgsi_to_qir_dp4 },
689 [TGSI_OPCODE_RCP] = { QOP_RCP, tgsi_to_qir_alu },
690 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_alu },
691 [TGSI_OPCODE_EX2] = { QOP_EXP2, tgsi_to_qir_alu },
692 [TGSI_OPCODE_LG2] = { QOP_LOG2, tgsi_to_qir_alu },
693 [TGSI_OPCODE_LIT] = { 0, tgsi_to_qir_lit },
694 [TGSI_OPCODE_LRP] = { 0, tgsi_to_qir_lrp },
695 [TGSI_OPCODE_POW] = { 0, tgsi_to_qir_pow },
696 [TGSI_OPCODE_TRUNC] = { 0, tgsi_to_qir_trunc },
697 [TGSI_OPCODE_FRC] = { 0, tgsi_to_qir_frc },
698 [TGSI_OPCODE_FLR] = { 0, tgsi_to_qir_flr },
699 [TGSI_OPCODE_SIN] = { 0, tgsi_to_qir_sin },
700 [TGSI_OPCODE_COS] = { 0, tgsi_to_qir_cos },
701 };
702 static int asdf = 0;
703 uint32_t tgsi_op = tgsi_inst->Instruction.Opcode;
704
705 if (tgsi_op == TGSI_OPCODE_END)
706 return;
707
708 struct qreg src_regs[12];
709 for (int s = 0; s < 3; s++) {
710 for (int i = 0; i < 4; i++) {
711 src_regs[4 * s + i] =
712 get_src(trans, &tgsi_inst->Src[s].Register, i);
713 }
714 }
715
716 switch (tgsi_op) {
717 case TGSI_OPCODE_TEX:
718 case TGSI_OPCODE_TXP:
719 case TGSI_OPCODE_TXB:
720 tgsi_to_qir_tex(trans, tgsi_inst,
721 op_trans[tgsi_op].op, src_regs);
722 return;
723 default:
724 break;
725 }
726
727 if (tgsi_op > ARRAY_SIZE(op_trans) || !(op_trans[tgsi_op].func)) {
728 fprintf(stderr, "unknown tgsi inst: ");
729 tgsi_dump_instruction(tgsi_inst, asdf++);
730 fprintf(stderr, "\n");
731 abort();
732 }
733
734 for (int i = 0; i < 4; i++) {
735 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
736 continue;
737
738 struct qreg result;
739
740 result = op_trans[tgsi_op].func(trans, tgsi_inst,
741 op_trans[tgsi_op].op,
742 src_regs, i);
743
744 if (tgsi_inst->Instruction.Saturate) {
745 float low = (tgsi_inst->Instruction.Saturate ==
746 TGSI_SAT_MINUS_PLUS_ONE ? -1.0 : 0.0);
747 result = qir_FMAX(c,
748 qir_FMIN(c,
749 result,
750 qir_uniform_f(trans, 1.0)),
751 qir_uniform_f(trans, low));
752 }
753
754 update_dst(trans, tgsi_inst, i, result);
755 }
756 }
757
758 static void
759 parse_tgsi_immediate(struct tgsi_to_qir *trans, struct tgsi_full_immediate *imm)
760 {
761 for (int i = 0; i < 4; i++) {
762 unsigned n = trans->num_consts++;
763 trans->consts[n] = qir_uniform_ui(trans, imm->u[i].Uint);
764 }
765 }
766
767 static struct qreg
768 vc4_blend_channel(struct tgsi_to_qir *trans,
769 struct qreg *dst,
770 struct qreg *src,
771 struct qreg val,
772 unsigned factor,
773 int channel)
774 {
775 struct qcompile *c = trans->c;
776
777 switch(factor) {
778 case PIPE_BLENDFACTOR_ONE:
779 return val;
780 case PIPE_BLENDFACTOR_SRC_COLOR:
781 return qir_FMUL(c, val, src[channel]);
782 case PIPE_BLENDFACTOR_SRC_ALPHA:
783 return qir_FMUL(c, val, src[3]);
784 case PIPE_BLENDFACTOR_DST_ALPHA:
785 return qir_FMUL(c, val, dst[3]);
786 case PIPE_BLENDFACTOR_DST_COLOR:
787 return qir_FMUL(c, val, dst[channel]);
788 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
789 return qir_FMIN(c, src[3], qir_FSUB(c,
790 qir_uniform_f(trans, 1.0),
791 dst[3]));
792 case PIPE_BLENDFACTOR_CONST_COLOR:
793 return qir_FMUL(c, val,
794 get_temp_for_uniform(trans,
795 QUNIFORM_BLEND_CONST_COLOR,
796 channel));
797 case PIPE_BLENDFACTOR_CONST_ALPHA:
798 return qir_FMUL(c, val,
799 get_temp_for_uniform(trans,
800 QUNIFORM_BLEND_CONST_COLOR,
801 3));
802 case PIPE_BLENDFACTOR_ZERO:
803 return qir_uniform_f(trans, 0.0);
804 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
805 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(trans, 1.0),
806 src[channel]));
807 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
808 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(trans, 1.0),
809 src[3]));
810 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
811 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(trans, 1.0),
812 dst[3]));
813 case PIPE_BLENDFACTOR_INV_DST_COLOR:
814 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(trans, 1.0),
815 dst[channel]));
816 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
817 return qir_FMUL(c, val,
818 qir_FSUB(c, qir_uniform_f(trans, 1.0),
819 get_temp_for_uniform(trans,
820 QUNIFORM_BLEND_CONST_COLOR,
821 channel)));
822 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
823 return qir_FMUL(c, val,
824 qir_FSUB(c, qir_uniform_f(trans, 1.0),
825 get_temp_for_uniform(trans,
826 QUNIFORM_BLEND_CONST_COLOR,
827 3)));
828
829 default:
830 case PIPE_BLENDFACTOR_SRC1_COLOR:
831 case PIPE_BLENDFACTOR_SRC1_ALPHA:
832 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
833 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
834 /* Unsupported. */
835 fprintf(stderr, "Unknown blend factor %d\n", factor);
836 return val;
837 }
838 }
839
840 static struct qreg
841 vc4_blend_func(struct tgsi_to_qir *trans,
842 struct qreg src, struct qreg dst,
843 unsigned func)
844 {
845 struct qcompile *c = trans->c;
846
847 switch (func) {
848 case PIPE_BLEND_ADD:
849 return qir_FADD(c, src, dst);
850 case PIPE_BLEND_SUBTRACT:
851 return qir_FSUB(c, src, dst);
852 case PIPE_BLEND_REVERSE_SUBTRACT:
853 return qir_FSUB(c, dst, src);
854 case PIPE_BLEND_MIN:
855 return qir_FMIN(c, src, dst);
856 case PIPE_BLEND_MAX:
857 return qir_FMAX(c, src, dst);
858
859 default:
860 /* Unsupported. */
861 fprintf(stderr, "Unknown blend func %d\n", func);
862 return src;
863
864 }
865 }
866
867 /**
868 * Implements fixed function blending in shader code.
869 *
870 * VC4 doesn't have any hardware support for blending. Instead, you read the
871 * current contents of the destination from the tile buffer after having
872 * waited for the scoreboard (which is handled by vc4_qpu_emit.c), then do
873 * math using your output color and that destination value, and update the
874 * output color appropriately.
875 */
876 static void
877 vc4_blend(struct tgsi_to_qir *trans, struct qreg *result,
878 struct qreg *src_color)
879 {
880 struct qcompile *c = trans->c;
881 struct pipe_rt_blend_state *blend = &trans->fs_key->blend;
882
883 if (!blend->blend_enable) {
884 for (int i = 0; i < 4; i++)
885 result[i] = src_color[i];
886 return;
887 }
888
889 qir_emit(c, qir_inst(QOP_TLB_COLOR_READ, c->undef,
890 c->undef, c->undef));
891 struct qreg dst_color[4];
892 for (int i = 0; i < 4; i++) {
893 dst_color[i] = qir_get_temp(c);
894 qir_emit(c, qir_inst(QOP_R4_UNPACK_A + i,
895 dst_color[i],
896 c->undef, c->undef));
897 /* XXX: Swizzles? */
898 }
899
900 struct qreg src_blend[4], dst_blend[4];
901 for (int i = 0; i < 3; i++) {
902 src_blend[i] = vc4_blend_channel(trans,
903 dst_color, src_color,
904 src_color[i],
905 blend->rgb_src_factor, i);
906 dst_blend[i] = vc4_blend_channel(trans,
907 dst_color, src_color,
908 dst_color[i],
909 blend->rgb_dst_factor, i);
910 }
911 src_blend[3] = vc4_blend_channel(trans,
912 dst_color, src_color,
913 src_color[3],
914 blend->alpha_src_factor, 3);
915 dst_blend[3] = vc4_blend_channel(trans,
916 dst_color, src_color,
917 dst_color[3],
918 blend->alpha_dst_factor, 3);
919
920 for (int i = 0; i < 3; i++) {
921 result[i] = vc4_blend_func(trans,
922 src_blend[i], dst_blend[i],
923 blend->rgb_func);
924 }
925 result[3] = vc4_blend_func(trans,
926 src_blend[3], dst_blend[3],
927 blend->alpha_func);
928 }
929
930 static void
931 emit_frag_end(struct tgsi_to_qir *trans)
932 {
933 struct qcompile *c = trans->c;
934
935 struct qreg t = qir_get_temp(c);
936
937 const struct util_format_description *format_desc =
938 util_format_description(trans->fs_key->color_format);
939
940 struct qreg output_color[4] = {
941 trans->outputs[0], trans->outputs[1],
942 trans->outputs[2], trans->outputs[3],
943 };
944
945 struct qreg blend_color[4];
946 vc4_blend(trans, blend_color, output_color);
947
948 /* Debug: Sometimes you're getting a black output and just want to see
949 * if the FS is getting executed at all. Spam magenta into the color
950 * output.
951 */
952 if (0) {
953 blend_color[0] = qir_uniform_f(trans, 1.0);
954 blend_color[1] = qir_uniform_f(trans, 0.0);
955 blend_color[2] = qir_uniform_f(trans, 1.0);
956 blend_color[3] = qir_uniform_f(trans, 0.5);
957 }
958
959 struct qreg swizzled_outputs[4] = {
960 blend_color[format_desc->swizzle[0]],
961 blend_color[format_desc->swizzle[1]],
962 blend_color[format_desc->swizzle[2]],
963 blend_color[format_desc->swizzle[3]],
964 };
965
966 if (trans->fs_key->depth_enabled) {
967 qir_emit(c, qir_inst(QOP_TLB_PASSTHROUGH_Z_WRITE, c->undef,
968 c->undef, c->undef));
969 }
970
971 qir_emit(c, qir_inst4(QOP_PACK_COLORS, t,
972 swizzled_outputs[0],
973 swizzled_outputs[1],
974 swizzled_outputs[2],
975 swizzled_outputs[3]));
976 qir_emit(c, qir_inst(QOP_TLB_COLOR_WRITE, c->undef,
977 t, c->undef));
978 }
979
980 static void
981 emit_scaled_viewport_write(struct tgsi_to_qir *trans, struct qreg rcp_w)
982 {
983 struct qcompile *c = trans->c;
984 struct qreg xyi[2];
985
986 for (int i = 0; i < 2; i++) {
987 struct qreg scale =
988 add_uniform(trans, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
989
990 xyi[i] = qir_FTOI(c, qir_FMUL(c,
991 qir_FMUL(c,
992 trans->outputs[i],
993 scale),
994 rcp_w));
995 }
996
997 qir_VPM_WRITE(c, qir_PACK_SCALED(c, xyi[0], xyi[1]));
998 }
999
1000 static void
1001 emit_zs_write(struct tgsi_to_qir *trans, struct qreg rcp_w)
1002 {
1003 struct qcompile *c = trans->c;
1004
1005 struct qreg zscale = add_uniform(trans, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1006 struct qreg zoffset = add_uniform(trans, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1007
1008 qir_VPM_WRITE(c, qir_FMUL(c, qir_FADD(c, qir_FMUL(c,
1009 trans->outputs[2],
1010 zscale),
1011 zoffset),
1012 rcp_w));
1013 }
1014
1015 static void
1016 emit_rcp_wc_write(struct tgsi_to_qir *trans, struct qreg rcp_w)
1017 {
1018 struct qcompile *c = trans->c;
1019
1020 qir_VPM_WRITE(c, rcp_w);
1021 }
1022
1023 static void
1024 emit_vert_end(struct tgsi_to_qir *trans)
1025 {
1026 struct qcompile *c = trans->c;
1027
1028 struct qreg rcp_w = qir_RCP(c, trans->outputs[3]);
1029
1030 emit_scaled_viewport_write(trans, rcp_w);
1031 emit_zs_write(trans, rcp_w);
1032 emit_rcp_wc_write(trans, rcp_w);
1033
1034 for (int i = 4; i < trans->num_outputs; i++) {
1035 qir_VPM_WRITE(c, trans->outputs[i]);
1036 }
1037 }
1038
1039 static void
1040 emit_coord_end(struct tgsi_to_qir *trans)
1041 {
1042 struct qcompile *c = trans->c;
1043
1044 struct qreg rcp_w = qir_RCP(c, trans->outputs[3]);
1045
1046 for (int i = 0; i < 4; i++)
1047 qir_VPM_WRITE(c, trans->outputs[i]);
1048
1049 emit_scaled_viewport_write(trans, rcp_w);
1050 emit_zs_write(trans, rcp_w);
1051 emit_rcp_wc_write(trans, rcp_w);
1052 }
1053
1054 static struct tgsi_to_qir *
1055 vc4_shader_tgsi_to_qir(struct vc4_compiled_shader *shader, enum qstage stage,
1056 struct vc4_key *key)
1057 {
1058 struct tgsi_to_qir *trans = CALLOC_STRUCT(tgsi_to_qir);
1059 struct qcompile *c;
1060 int ret;
1061
1062 c = qir_compile_init();
1063 c->stage = stage;
1064
1065 memset(trans, 0, sizeof(*trans));
1066 /* XXX sizing */
1067 trans->temps = calloc(sizeof(struct qreg), 1024);
1068 trans->inputs = calloc(sizeof(struct qreg), 8 * 4);
1069 trans->outputs = calloc(sizeof(struct qreg), 1024);
1070 trans->uniforms = calloc(sizeof(struct qreg), 1024);
1071 trans->consts = calloc(sizeof(struct qreg), 1024);
1072
1073 trans->uniform_data = calloc(sizeof(uint32_t), 1024);
1074 trans->uniform_contents = calloc(sizeof(enum quniform_contents), 1024);
1075
1076 trans->shader_state = key->shader_state;
1077 trans->c = c;
1078 ret = tgsi_parse_init(&trans->parser, trans->shader_state->tokens);
1079 assert(ret == TGSI_PARSE_OK);
1080
1081 if (vc4_debug & VC4_DEBUG_TGSI) {
1082 fprintf(stderr, "TGSI:\n");
1083 tgsi_dump(trans->shader_state->tokens, 0);
1084 }
1085
1086 switch (stage) {
1087 case QSTAGE_FRAG:
1088 trans->fs_key = (struct vc4_fs_key *)key;
1089 if (trans->fs_key->is_points) {
1090 trans->point_x = emit_fragment_varying(trans, 0);
1091 trans->point_y = emit_fragment_varying(trans, 0);
1092 } else if (trans->fs_key->is_lines) {
1093 trans->line_x = emit_fragment_varying(trans, 0);
1094 }
1095 break;
1096 case QSTAGE_VERT:
1097 trans->vs_key = (struct vc4_vs_key *)key;
1098 break;
1099 case QSTAGE_COORD:
1100 trans->vs_key = (struct vc4_vs_key *)key;
1101 break;
1102 }
1103
1104 while (!tgsi_parse_end_of_tokens(&trans->parser)) {
1105 tgsi_parse_token(&trans->parser);
1106
1107 switch (trans->parser.FullToken.Token.Type) {
1108 case TGSI_TOKEN_TYPE_DECLARATION:
1109 emit_tgsi_declaration(trans,
1110 &trans->parser.FullToken.FullDeclaration);
1111 break;
1112
1113 case TGSI_TOKEN_TYPE_INSTRUCTION:
1114 emit_tgsi_instruction(trans,
1115 &trans->parser.FullToken.FullInstruction);
1116 break;
1117
1118 case TGSI_TOKEN_TYPE_IMMEDIATE:
1119 parse_tgsi_immediate(trans,
1120 &trans->parser.FullToken.FullImmediate);
1121 break;
1122 }
1123 }
1124
1125 switch (stage) {
1126 case QSTAGE_FRAG:
1127 emit_frag_end(trans);
1128 break;
1129 case QSTAGE_VERT:
1130 emit_vert_end(trans);
1131 break;
1132 case QSTAGE_COORD:
1133 emit_coord_end(trans);
1134 break;
1135 }
1136
1137 tgsi_parse_free(&trans->parser);
1138 free(trans->temps);
1139
1140 qir_optimize(c);
1141
1142 if (vc4_debug & VC4_DEBUG_QIR) {
1143 fprintf(stderr, "QIR:\n");
1144 qir_dump(c);
1145 }
1146 vc4_generate_code(c);
1147
1148 if (vc4_debug & VC4_DEBUG_SHADERDB) {
1149 fprintf(stderr, "SHADER-DB: %s: %d instructions\n",
1150 qir_get_stage_name(c->stage), c->qpu_inst_count);
1151 fprintf(stderr, "SHADER-DB: %s: %d uniforms\n",
1152 qir_get_stage_name(c->stage), trans->num_uniforms);
1153 }
1154
1155 return trans;
1156 }
1157
1158 static void *
1159 vc4_shader_state_create(struct pipe_context *pctx,
1160 const struct pipe_shader_state *cso)
1161 {
1162 struct pipe_shader_state *so = CALLOC_STRUCT(pipe_shader_state);
1163 if (!so)
1164 return NULL;
1165
1166 so->tokens = tgsi_dup_tokens(cso->tokens);
1167
1168 return so;
1169 }
1170
1171 static void
1172 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
1173 int shader_index,
1174 struct tgsi_to_qir *trans)
1175 {
1176 int count = trans->num_uniforms;
1177 struct vc4_shader_uniform_info *uinfo = &shader->uniforms[shader_index];
1178
1179 uinfo->count = count;
1180 uinfo->data = malloc(count * sizeof(*uinfo->data));
1181 memcpy(uinfo->data, trans->uniform_data,
1182 count * sizeof(*uinfo->data));
1183 uinfo->contents = malloc(count * sizeof(*uinfo->contents));
1184 memcpy(uinfo->contents, trans->uniform_contents,
1185 count * sizeof(*uinfo->contents));
1186 uinfo->num_texture_samples = trans->num_texture_samples;
1187 }
1188
1189 static void
1190 vc4_fs_compile(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1191 struct vc4_fs_key *key)
1192 {
1193 struct tgsi_to_qir *trans = vc4_shader_tgsi_to_qir(shader, QSTAGE_FRAG,
1194 &key->base);
1195 shader->num_inputs = trans->c->num_inputs;
1196 copy_uniform_state_to_shader(shader, 0, trans);
1197 shader->bo = vc4_bo_alloc_mem(vc4->screen, trans->c->qpu_insts,
1198 trans->c->qpu_inst_count * sizeof(uint64_t),
1199 "fs_code");
1200
1201 qir_compile_destroy(trans->c);
1202 free(trans);
1203 }
1204
1205 static void
1206 vc4_vs_compile(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1207 struct vc4_vs_key *key)
1208 {
1209 struct tgsi_to_qir *vs_trans = vc4_shader_tgsi_to_qir(shader,
1210 QSTAGE_VERT,
1211 &key->base);
1212 copy_uniform_state_to_shader(shader, 0, vs_trans);
1213
1214 struct tgsi_to_qir *cs_trans = vc4_shader_tgsi_to_qir(shader,
1215 QSTAGE_COORD,
1216 &key->base);
1217 copy_uniform_state_to_shader(shader, 1, cs_trans);
1218
1219 uint32_t vs_size = vs_trans->c->qpu_inst_count * sizeof(uint64_t);
1220 uint32_t cs_size = cs_trans->c->qpu_inst_count * sizeof(uint64_t);
1221 shader->coord_shader_offset = vs_size; /* XXX: alignment? */
1222 shader->bo = vc4_bo_alloc(vc4->screen,
1223 shader->coord_shader_offset + cs_size,
1224 "vs_code");
1225
1226 void *map = vc4_bo_map(shader->bo);
1227 memcpy(map, vs_trans->c->qpu_insts, vs_size);
1228 memcpy(map + shader->coord_shader_offset,
1229 cs_trans->c->qpu_insts, cs_size);
1230
1231 qir_compile_destroy(vs_trans->c);
1232 qir_compile_destroy(cs_trans->c);
1233 }
1234
1235 static void
1236 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
1237 {
1238 struct vc4_fs_key local_key;
1239 struct vc4_fs_key *key = &local_key;
1240
1241 memset(key, 0, sizeof(*key));
1242 key->base.shader_state = vc4->prog.bind_fs;
1243 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
1244 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
1245 prim_mode <= PIPE_PRIM_LINE_STRIP);
1246 key->blend = vc4->blend->rt[0];
1247
1248 if (vc4->framebuffer.cbufs[0])
1249 key->color_format = vc4->framebuffer.cbufs[0]->format;
1250
1251 key->depth_enabled = vc4->zsa->base.depth.enabled;
1252
1253 vc4->prog.fs = util_hash_table_get(vc4->fs_cache, key);
1254 if (vc4->prog.fs)
1255 return;
1256
1257 key = malloc(sizeof(*key));
1258 memcpy(key, &local_key, sizeof(*key));
1259
1260 struct vc4_compiled_shader *shader = CALLOC_STRUCT(vc4_compiled_shader);
1261 vc4_fs_compile(vc4, shader, key);
1262 util_hash_table_set(vc4->fs_cache, key, shader);
1263
1264 vc4->prog.fs = shader;
1265 }
1266
1267 static void
1268 vc4_update_compiled_vs(struct vc4_context *vc4)
1269 {
1270 struct vc4_vs_key local_key;
1271 struct vc4_vs_key *key = &local_key;
1272
1273 memset(key, 0, sizeof(*key));
1274 key->base.shader_state = vc4->prog.bind_vs;
1275
1276 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
1277 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
1278
1279 vc4->prog.vs = util_hash_table_get(vc4->vs_cache, key);
1280 if (vc4->prog.vs)
1281 return;
1282
1283 key = malloc(sizeof(*key));
1284 memcpy(key, &local_key, sizeof(*key));
1285
1286 struct vc4_compiled_shader *shader = CALLOC_STRUCT(vc4_compiled_shader);
1287 vc4_vs_compile(vc4, shader, key);
1288 util_hash_table_set(vc4->vs_cache, key, shader);
1289
1290 vc4->prog.vs = shader;
1291 }
1292
1293 void
1294 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
1295 {
1296 vc4_update_compiled_fs(vc4, prim_mode);
1297 vc4_update_compiled_vs(vc4);
1298 }
1299
1300 static unsigned
1301 fs_cache_hash(void *key)
1302 {
1303 return util_hash_crc32(key, sizeof(struct vc4_fs_key));
1304 }
1305
1306 static unsigned
1307 vs_cache_hash(void *key)
1308 {
1309 return util_hash_crc32(key, sizeof(struct vc4_vs_key));
1310 }
1311
1312 static int
1313 fs_cache_compare(void *key1, void *key2)
1314 {
1315 return memcmp(key1, key2, sizeof(struct vc4_fs_key));
1316 }
1317
1318 static int
1319 vs_cache_compare(void *key1, void *key2)
1320 {
1321 return memcmp(key1, key2, sizeof(struct vc4_vs_key));
1322 }
1323
1324 struct delete_state {
1325 struct vc4_context *vc4;
1326 struct pipe_shader_state *shader_state;
1327 };
1328
1329 static enum pipe_error
1330 fs_delete_from_cache(void *in_key, void *in_value, void *data)
1331 {
1332 struct delete_state *del = data;
1333 struct vc4_fs_key *key = in_key;
1334 struct vc4_compiled_shader *shader = in_value;
1335
1336 if (key->base.shader_state == data) {
1337 util_hash_table_remove(del->vc4->fs_cache, key);
1338 vc4_bo_unreference(&shader->bo);
1339 free(shader);
1340 }
1341
1342 return 0;
1343 }
1344
1345 static enum pipe_error
1346 vs_delete_from_cache(void *in_key, void *in_value, void *data)
1347 {
1348 struct delete_state *del = data;
1349 struct vc4_vs_key *key = in_key;
1350 struct vc4_compiled_shader *shader = in_value;
1351
1352 if (key->base.shader_state == data) {
1353 util_hash_table_remove(del->vc4->vs_cache, key);
1354 vc4_bo_unreference(&shader->bo);
1355 free(shader);
1356 }
1357
1358 return 0;
1359 }
1360
1361 static void
1362 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
1363 {
1364 struct vc4_context *vc4 = vc4_context(pctx);
1365 struct pipe_shader_state *so = hwcso;
1366 struct delete_state del;
1367
1368 del.vc4 = vc4;
1369 del.shader_state = so;
1370 util_hash_table_foreach(vc4->fs_cache, fs_delete_from_cache, &del);
1371 util_hash_table_foreach(vc4->vs_cache, vs_delete_from_cache, &del);
1372
1373 free((void *)so->tokens);
1374 free(so);
1375 }
1376
1377 static uint32_t translate_wrap(uint32_t p_wrap)
1378 {
1379 switch (p_wrap) {
1380 case PIPE_TEX_WRAP_REPEAT:
1381 return 0;
1382 case PIPE_TEX_WRAP_CLAMP:
1383 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1384 return 1;
1385 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1386 return 2;
1387 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1388 return 3;
1389 default:
1390 fprintf(stderr, "Unknown wrap mode %d\n", p_wrap);
1391 assert(!"not reached");
1392 return 0;
1393 }
1394 }
1395
1396 static void
1397 write_texture_p0(struct vc4_context *vc4,
1398 struct vc4_texture_stateobj *texstate,
1399 uint32_t tex_and_sampler)
1400 {
1401 uint32_t texi = (tex_and_sampler >> 0) & 0xff;
1402 struct pipe_sampler_view *texture = texstate->textures[texi];
1403 struct vc4_resource *rsc = vc4_resource(texture->texture);
1404
1405 cl_reloc(vc4, &vc4->uniforms, rsc->bo,
1406 texture->u.tex.last_level);
1407 }
1408
1409 static void
1410 write_texture_p1(struct vc4_context *vc4,
1411 struct vc4_texture_stateobj *texstate,
1412 uint32_t tex_and_sampler)
1413 {
1414 uint32_t texi = (tex_and_sampler >> 0) & 0xff;
1415 uint32_t sampi = (tex_and_sampler >> 8) & 0xff;
1416 struct pipe_sampler_view *texture = texstate->textures[texi];
1417 struct pipe_sampler_state *sampler = texstate->samplers[sampi];
1418 static const uint32_t mipfilter_map[] = {
1419 [PIPE_TEX_MIPFILTER_NEAREST] = 2,
1420 [PIPE_TEX_MIPFILTER_LINEAR] = 4,
1421 [PIPE_TEX_MIPFILTER_NONE] = 0
1422 };
1423 static const uint32_t imgfilter_map[] = {
1424 [PIPE_TEX_FILTER_NEAREST] = 1,
1425 [PIPE_TEX_FILTER_LINEAR] = 0,
1426 };
1427
1428 cl_u32(&vc4->uniforms,
1429 (1 << 31) /* XXX: data type */|
1430 (texture->texture->height0 << 20) |
1431 (texture->texture->width0 << 8) |
1432 (imgfilter_map[sampler->mag_img_filter] << 7) |
1433 ((imgfilter_map[sampler->min_img_filter] +
1434 mipfilter_map[sampler->min_mip_filter]) << 4) |
1435 (translate_wrap(sampler->wrap_t) << 2) |
1436 (translate_wrap(sampler->wrap_s) << 0));
1437 }
1438
1439 static uint32_t
1440 get_texrect_scale(struct vc4_texture_stateobj *texstate,
1441 enum quniform_contents contents,
1442 uint32_t data)
1443 {
1444 struct pipe_sampler_view *texture = texstate->textures[data];
1445 uint32_t dim;
1446
1447 if (contents == QUNIFORM_TEXRECT_SCALE_X)
1448 dim = texture->texture->width0;
1449 else
1450 dim = texture->texture->height0;
1451
1452 return fui(1.0f / dim);
1453 }
1454
1455 void
1456 vc4_write_uniforms(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1457 struct vc4_constbuf_stateobj *cb,
1458 struct vc4_texture_stateobj *texstate,
1459 int shader_index)
1460 {
1461 struct vc4_shader_uniform_info *uinfo = &shader->uniforms[shader_index];
1462 const uint32_t *gallium_uniforms = cb->cb[0].user_buffer;
1463
1464 cl_start_shader_reloc(&vc4->uniforms, uinfo->num_texture_samples);
1465
1466 for (int i = 0; i < uinfo->count; i++) {
1467
1468 switch (uinfo->contents[i]) {
1469 case QUNIFORM_CONSTANT:
1470 cl_u32(&vc4->uniforms, uinfo->data[i]);
1471 break;
1472 case QUNIFORM_UNIFORM:
1473 cl_u32(&vc4->uniforms,
1474 gallium_uniforms[uinfo->data[i]]);
1475 break;
1476 case QUNIFORM_VIEWPORT_X_SCALE:
1477 cl_f(&vc4->uniforms, vc4->viewport.scale[0] * 16.0f);
1478 break;
1479 case QUNIFORM_VIEWPORT_Y_SCALE:
1480 cl_f(&vc4->uniforms, vc4->viewport.scale[1] * 16.0f);
1481 break;
1482
1483 case QUNIFORM_VIEWPORT_Z_OFFSET:
1484 cl_f(&vc4->uniforms, vc4->viewport.translate[2]);
1485 break;
1486 case QUNIFORM_VIEWPORT_Z_SCALE:
1487 cl_f(&vc4->uniforms, vc4->viewport.scale[2]);
1488 break;
1489
1490 case QUNIFORM_TEXTURE_CONFIG_P0:
1491 write_texture_p0(vc4, texstate, uinfo->data[i]);
1492 break;
1493
1494 case QUNIFORM_TEXTURE_CONFIG_P1:
1495 write_texture_p1(vc4, texstate, uinfo->data[i]);
1496 break;
1497
1498 case QUNIFORM_TEXRECT_SCALE_X:
1499 case QUNIFORM_TEXRECT_SCALE_Y:
1500 cl_u32(&vc4->uniforms,
1501 get_texrect_scale(texstate,
1502 uinfo->contents[i],
1503 uinfo->data[i]));
1504 break;
1505
1506 case QUNIFORM_BLEND_CONST_COLOR:
1507 cl_f(&vc4->uniforms,
1508 vc4->blend_color.color[uinfo->data[i]]);
1509 break;
1510 }
1511 #if 0
1512 uint32_t written_val = *(uint32_t *)(vc4->uniforms.next - 4);
1513 fprintf(stderr, "%p/%d: %d: 0x%08x (%f)\n",
1514 shader, shader_index, i, written_val, uif(written_val));
1515 #endif
1516 }
1517 }
1518
1519 static void
1520 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
1521 {
1522 struct vc4_context *vc4 = vc4_context(pctx);
1523 vc4->prog.bind_fs = hwcso;
1524 vc4->prog.dirty |= VC4_SHADER_DIRTY_FP;
1525 vc4->dirty |= VC4_DIRTY_PROG;
1526 }
1527
1528 static void
1529 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
1530 {
1531 struct vc4_context *vc4 = vc4_context(pctx);
1532 vc4->prog.bind_vs = hwcso;
1533 vc4->prog.dirty |= VC4_SHADER_DIRTY_VP;
1534 vc4->dirty |= VC4_DIRTY_PROG;
1535 }
1536
1537 void
1538 vc4_program_init(struct pipe_context *pctx)
1539 {
1540 struct vc4_context *vc4 = vc4_context(pctx);
1541
1542 pctx->create_vs_state = vc4_shader_state_create;
1543 pctx->delete_vs_state = vc4_shader_state_delete;
1544
1545 pctx->create_fs_state = vc4_shader_state_create;
1546 pctx->delete_fs_state = vc4_shader_state_delete;
1547
1548 pctx->bind_fs_state = vc4_fp_state_bind;
1549 pctx->bind_vs_state = vc4_vp_state_bind;
1550
1551 vc4->fs_cache = util_hash_table_create(fs_cache_hash, fs_cache_compare);
1552 vc4->vs_cache = util_hash_table_create(vs_cache_hash, vs_cache_compare);
1553 }