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vc4: Avoid reusing a pointer from c->outputs[] after add_output().
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "pipe/p_state.h"
27 #include "util/u_format.h"
28 #include "util/u_hash_table.h"
29 #include "util/u_hash.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include "util/format_srgb.h"
33 #include "util/ralloc.h"
34 #include "util/hash_table.h"
35 #include "tgsi/tgsi_dump.h"
36 #include "tgsi/tgsi_info.h"
37 #include "tgsi/tgsi_lowering.h"
38
39 #include "vc4_context.h"
40 #include "vc4_qpu.h"
41 #include "vc4_qir.h"
42 #ifdef USE_VC4_SIMULATOR
43 #include "simpenrose/simpenrose.h"
44 #endif
45
46 struct vc4_key {
47 struct vc4_uncompiled_shader *shader_state;
48 struct {
49 enum pipe_format format;
50 unsigned compare_mode:1;
51 unsigned compare_func:3;
52 unsigned wrap_s:3;
53 unsigned wrap_t:3;
54 uint8_t swizzle[4];
55 } tex[VC4_MAX_TEXTURE_SAMPLERS];
56 uint8_t ucp_enables;
57 };
58
59 struct vc4_fs_key {
60 struct vc4_key base;
61 enum pipe_format color_format;
62 bool depth_enabled;
63 bool stencil_enabled;
64 bool stencil_twoside;
65 bool stencil_full_writemasks;
66 bool is_points;
67 bool is_lines;
68 bool alpha_test;
69 bool point_coord_upper_left;
70 bool light_twoside;
71 uint8_t alpha_test_func;
72 uint32_t point_sprite_mask;
73
74 struct pipe_rt_blend_state blend;
75 };
76
77 struct vc4_vs_key {
78 struct vc4_key base;
79
80 /**
81 * This is a proxy for the array of FS input semantics, which is
82 * larger than we would want to put in the key.
83 */
84 uint64_t compiled_fs_id;
85
86 enum pipe_format attr_formats[8];
87 bool is_coord;
88 bool per_vertex_point_size;
89 };
90
91 static void
92 resize_qreg_array(struct vc4_compile *c,
93 struct qreg **regs,
94 uint32_t *size,
95 uint32_t decl_size)
96 {
97 if (*size >= decl_size)
98 return;
99
100 uint32_t old_size = *size;
101 *size = MAX2(*size * 2, decl_size);
102 *regs = reralloc(c, *regs, struct qreg, *size);
103 if (!*regs) {
104 fprintf(stderr, "Malloc failure\n");
105 abort();
106 }
107
108 for (uint32_t i = old_size; i < *size; i++)
109 (*regs)[i] = c->undef;
110 }
111
112 static struct qreg
113 add_uniform(struct vc4_compile *c,
114 enum quniform_contents contents,
115 uint32_t data)
116 {
117 for (int i = 0; i < c->num_uniforms; i++) {
118 if (c->uniform_contents[i] == contents &&
119 c->uniform_data[i] == data) {
120 return (struct qreg) { QFILE_UNIF, i };
121 }
122 }
123
124 uint32_t uniform = c->num_uniforms++;
125 struct qreg u = { QFILE_UNIF, uniform };
126
127 if (uniform >= c->uniform_array_size) {
128 c->uniform_array_size = MAX2(MAX2(16, uniform + 1),
129 c->uniform_array_size * 2);
130
131 c->uniform_data = reralloc(c, c->uniform_data,
132 uint32_t,
133 c->uniform_array_size);
134 c->uniform_contents = reralloc(c, c->uniform_contents,
135 enum quniform_contents,
136 c->uniform_array_size);
137 }
138
139 c->uniform_contents[uniform] = contents;
140 c->uniform_data[uniform] = data;
141
142 return u;
143 }
144
145 static struct qreg
146 get_temp_for_uniform(struct vc4_compile *c, enum quniform_contents contents,
147 uint32_t data)
148 {
149 struct qreg u = add_uniform(c, contents, data);
150 struct qreg t = qir_MOV(c, u);
151 return t;
152 }
153
154 static struct qreg
155 qir_uniform_ui(struct vc4_compile *c, uint32_t ui)
156 {
157 return get_temp_for_uniform(c, QUNIFORM_CONSTANT, ui);
158 }
159
160 static struct qreg
161 qir_uniform_f(struct vc4_compile *c, float f)
162 {
163 return qir_uniform_ui(c, fui(f));
164 }
165
166 static struct qreg
167 indirect_uniform_load(struct vc4_compile *c,
168 struct tgsi_full_src_register *src, int swiz)
169 {
170 struct tgsi_ind_register *indirect = &src->Indirect;
171 struct vc4_compiler_ubo_range *range = &c->ubo_ranges[indirect->ArrayID];
172 if (!range->used) {
173 range->used = true;
174 range->dst_offset = c->next_ubo_dst_offset;
175 c->next_ubo_dst_offset += range->size;
176 c->num_ubo_ranges++;
177 };
178
179 assert(src->Register.Indirect);
180 assert(indirect->File == TGSI_FILE_ADDRESS);
181
182 struct qreg addr_val = c->addr[indirect->Swizzle];
183 struct qreg indirect_offset =
184 qir_ADD(c, addr_val, qir_uniform_ui(c,
185 range->dst_offset +
186 (src->Register.Index * 16)+
187 swiz * 4));
188 indirect_offset = qir_MIN(c, indirect_offset, qir_uniform_ui(c, (range->dst_offset +
189 range->size - 4)));
190
191 qir_TEX_DIRECT(c, indirect_offset, add_uniform(c, QUNIFORM_UBO_ADDR, 0));
192 struct qreg r4 = qir_TEX_RESULT(c);
193 c->num_texture_samples++;
194 return qir_MOV(c, r4);
195 }
196
197 static struct qreg
198 get_src(struct vc4_compile *c, unsigned tgsi_op,
199 struct tgsi_full_src_register *full_src, int i)
200 {
201 struct tgsi_src_register *src = &full_src->Register;
202 struct qreg r = c->undef;
203
204 uint32_t s = i;
205 switch (i) {
206 case TGSI_SWIZZLE_X:
207 s = src->SwizzleX;
208 break;
209 case TGSI_SWIZZLE_Y:
210 s = src->SwizzleY;
211 break;
212 case TGSI_SWIZZLE_Z:
213 s = src->SwizzleZ;
214 break;
215 case TGSI_SWIZZLE_W:
216 s = src->SwizzleW;
217 break;
218 default:
219 abort();
220 }
221
222 switch (src->File) {
223 case TGSI_FILE_NULL:
224 return r;
225 case TGSI_FILE_TEMPORARY:
226 r = c->temps[src->Index * 4 + s];
227 break;
228 case TGSI_FILE_IMMEDIATE:
229 r = c->consts[src->Index * 4 + s];
230 break;
231 case TGSI_FILE_CONSTANT:
232 if (src->Indirect) {
233 r = indirect_uniform_load(c, full_src, s);
234 } else {
235 r = get_temp_for_uniform(c, QUNIFORM_UNIFORM,
236 src->Index * 4 + s);
237 }
238 break;
239 case TGSI_FILE_INPUT:
240 r = c->inputs[src->Index * 4 + s];
241 break;
242 case TGSI_FILE_SAMPLER:
243 case TGSI_FILE_SAMPLER_VIEW:
244 r = c->undef;
245 break;
246 default:
247 fprintf(stderr, "unknown src file %d\n", src->File);
248 abort();
249 }
250
251 if (src->Absolute)
252 r = qir_FMAXABS(c, r, r);
253
254 if (src->Negate) {
255 switch (tgsi_opcode_infer_src_type(tgsi_op)) {
256 case TGSI_TYPE_SIGNED:
257 case TGSI_TYPE_UNSIGNED:
258 r = qir_SUB(c, qir_uniform_ui(c, 0), r);
259 break;
260 default:
261 r = qir_FSUB(c, qir_uniform_f(c, 0.0), r);
262 break;
263 }
264 }
265
266 return r;
267 };
268
269
270 static void
271 update_dst(struct vc4_compile *c, struct tgsi_full_instruction *tgsi_inst,
272 int i, struct qreg val)
273 {
274 struct tgsi_dst_register *tgsi_dst = &tgsi_inst->Dst[0].Register;
275
276 assert(!tgsi_dst->Indirect);
277
278 switch (tgsi_dst->File) {
279 case TGSI_FILE_TEMPORARY:
280 c->temps[tgsi_dst->Index * 4 + i] = val;
281 break;
282 case TGSI_FILE_OUTPUT:
283 c->outputs[tgsi_dst->Index * 4 + i] = val;
284 c->num_outputs = MAX2(c->num_outputs,
285 tgsi_dst->Index * 4 + i + 1);
286 break;
287 case TGSI_FILE_ADDRESS:
288 assert(tgsi_dst->Index == 0);
289 c->addr[i] = val;
290 break;
291 default:
292 fprintf(stderr, "unknown dst file %d\n", tgsi_dst->File);
293 abort();
294 }
295 };
296
297 static struct qreg
298 get_swizzled_channel(struct vc4_compile *c,
299 struct qreg *srcs, int swiz)
300 {
301 switch (swiz) {
302 default:
303 case UTIL_FORMAT_SWIZZLE_NONE:
304 fprintf(stderr, "warning: unknown swizzle\n");
305 /* FALLTHROUGH */
306 case UTIL_FORMAT_SWIZZLE_0:
307 return qir_uniform_f(c, 0.0);
308 case UTIL_FORMAT_SWIZZLE_1:
309 return qir_uniform_f(c, 1.0);
310 case UTIL_FORMAT_SWIZZLE_X:
311 case UTIL_FORMAT_SWIZZLE_Y:
312 case UTIL_FORMAT_SWIZZLE_Z:
313 case UTIL_FORMAT_SWIZZLE_W:
314 return srcs[swiz];
315 }
316 }
317
318 static struct qreg
319 tgsi_to_qir_alu(struct vc4_compile *c,
320 struct tgsi_full_instruction *tgsi_inst,
321 enum qop op, struct qreg *src, int i)
322 {
323 struct qreg dst = qir_get_temp(c);
324 qir_emit(c, qir_inst4(op, dst,
325 src[0 * 4 + i],
326 src[1 * 4 + i],
327 src[2 * 4 + i],
328 c->undef));
329 return dst;
330 }
331
332 static struct qreg
333 tgsi_to_qir_scalar(struct vc4_compile *c,
334 struct tgsi_full_instruction *tgsi_inst,
335 enum qop op, struct qreg *src, int i)
336 {
337 struct qreg dst = qir_get_temp(c);
338 qir_emit(c, qir_inst(op, dst,
339 src[0 * 4 + 0],
340 c->undef));
341 return dst;
342 }
343
344 static struct qreg
345 tgsi_to_qir_rcp(struct vc4_compile *c,
346 struct tgsi_full_instruction *tgsi_inst,
347 enum qop op, struct qreg *src, int i)
348 {
349 struct qreg x = src[0 * 4 + 0];
350 struct qreg r = qir_RCP(c, x);
351
352 /* Apply a Newton-Raphson step to improve the accuracy. */
353 r = qir_FMUL(c, r, qir_FSUB(c,
354 qir_uniform_f(c, 2.0),
355 qir_FMUL(c, x, r)));
356
357 return r;
358 }
359
360 static struct qreg
361 tgsi_to_qir_rsq(struct vc4_compile *c,
362 struct tgsi_full_instruction *tgsi_inst,
363 enum qop op, struct qreg *src, int i)
364 {
365 struct qreg x = src[0 * 4 + 0];
366 struct qreg r = qir_RSQ(c, x);
367
368 /* Apply a Newton-Raphson step to improve the accuracy. */
369 r = qir_FMUL(c, r, qir_FSUB(c,
370 qir_uniform_f(c, 1.5),
371 qir_FMUL(c,
372 qir_uniform_f(c, 0.5),
373 qir_FMUL(c, x,
374 qir_FMUL(c, r, r)))));
375
376 return r;
377 }
378
379 static struct qreg
380 qir_srgb_decode(struct vc4_compile *c, struct qreg srgb)
381 {
382 struct qreg low = qir_FMUL(c, srgb, qir_uniform_f(c, 1.0 / 12.92));
383 struct qreg high = qir_POW(c,
384 qir_FMUL(c,
385 qir_FADD(c,
386 srgb,
387 qir_uniform_f(c, 0.055)),
388 qir_uniform_f(c, 1.0 / 1.055)),
389 qir_uniform_f(c, 2.4));
390
391 qir_SF(c, qir_FSUB(c, srgb, qir_uniform_f(c, 0.04045)));
392 return qir_SEL_X_Y_NS(c, low, high);
393 }
394
395 static struct qreg
396 qir_srgb_encode(struct vc4_compile *c, struct qreg linear)
397 {
398 struct qreg low = qir_FMUL(c, linear, qir_uniform_f(c, 12.92));
399 struct qreg high = qir_FSUB(c,
400 qir_FMUL(c,
401 qir_uniform_f(c, 1.055),
402 qir_POW(c,
403 linear,
404 qir_uniform_f(c, 0.41666))),
405 qir_uniform_f(c, 0.055));
406
407 qir_SF(c, qir_FSUB(c, linear, qir_uniform_f(c, 0.0031308)));
408 return qir_SEL_X_Y_NS(c, low, high);
409 }
410
411 static struct qreg
412 tgsi_to_qir_umul(struct vc4_compile *c,
413 struct tgsi_full_instruction *tgsi_inst,
414 enum qop op, struct qreg *src, int i)
415 {
416 struct qreg src0_hi = qir_SHR(c, src[0 * 4 + i],
417 qir_uniform_ui(c, 16));
418 struct qreg src0_lo = qir_AND(c, src[0 * 4 + i],
419 qir_uniform_ui(c, 0xffff));
420 struct qreg src1_hi = qir_SHR(c, src[1 * 4 + i],
421 qir_uniform_ui(c, 16));
422 struct qreg src1_lo = qir_AND(c, src[1 * 4 + i],
423 qir_uniform_ui(c, 0xffff));
424
425 struct qreg hilo = qir_MUL24(c, src0_hi, src1_lo);
426 struct qreg lohi = qir_MUL24(c, src0_lo, src1_hi);
427 struct qreg lolo = qir_MUL24(c, src0_lo, src1_lo);
428
429 return qir_ADD(c, lolo, qir_SHL(c,
430 qir_ADD(c, hilo, lohi),
431 qir_uniform_ui(c, 16)));
432 }
433
434 static struct qreg
435 tgsi_to_qir_idiv(struct vc4_compile *c,
436 struct tgsi_full_instruction *tgsi_inst,
437 enum qop op, struct qreg *src, int i)
438 {
439 return qir_FTOI(c, qir_FMUL(c,
440 qir_ITOF(c, src[0 * 4 + i]),
441 qir_RCP(c, qir_ITOF(c, src[1 * 4 + i]))));
442 }
443
444 static struct qreg
445 tgsi_to_qir_ineg(struct vc4_compile *c,
446 struct tgsi_full_instruction *tgsi_inst,
447 enum qop op, struct qreg *src, int i)
448 {
449 return qir_SUB(c, qir_uniform_ui(c, 0), src[0 * 4 + i]);
450 }
451
452 static struct qreg
453 tgsi_to_qir_seq(struct vc4_compile *c,
454 struct tgsi_full_instruction *tgsi_inst,
455 enum qop op, struct qreg *src, int i)
456 {
457 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
458 return qir_SEL_X_0_ZS(c, qir_uniform_f(c, 1.0));
459 }
460
461 static struct qreg
462 tgsi_to_qir_sne(struct vc4_compile *c,
463 struct tgsi_full_instruction *tgsi_inst,
464 enum qop op, struct qreg *src, int i)
465 {
466 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
467 return qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0));
468 }
469
470 static struct qreg
471 tgsi_to_qir_slt(struct vc4_compile *c,
472 struct tgsi_full_instruction *tgsi_inst,
473 enum qop op, struct qreg *src, int i)
474 {
475 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
476 return qir_SEL_X_0_NS(c, qir_uniform_f(c, 1.0));
477 }
478
479 static struct qreg
480 tgsi_to_qir_sge(struct vc4_compile *c,
481 struct tgsi_full_instruction *tgsi_inst,
482 enum qop op, struct qreg *src, int i)
483 {
484 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
485 return qir_SEL_X_0_NC(c, qir_uniform_f(c, 1.0));
486 }
487
488 static struct qreg
489 tgsi_to_qir_fseq(struct vc4_compile *c,
490 struct tgsi_full_instruction *tgsi_inst,
491 enum qop op, struct qreg *src, int i)
492 {
493 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
494 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
495 }
496
497 static struct qreg
498 tgsi_to_qir_fsne(struct vc4_compile *c,
499 struct tgsi_full_instruction *tgsi_inst,
500 enum qop op, struct qreg *src, int i)
501 {
502 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
503 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
504 }
505
506 static struct qreg
507 tgsi_to_qir_fslt(struct vc4_compile *c,
508 struct tgsi_full_instruction *tgsi_inst,
509 enum qop op, struct qreg *src, int i)
510 {
511 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
512 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
513 }
514
515 static struct qreg
516 tgsi_to_qir_fsge(struct vc4_compile *c,
517 struct tgsi_full_instruction *tgsi_inst,
518 enum qop op, struct qreg *src, int i)
519 {
520 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
521 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
522 }
523
524 static struct qreg
525 tgsi_to_qir_useq(struct vc4_compile *c,
526 struct tgsi_full_instruction *tgsi_inst,
527 enum qop op, struct qreg *src, int i)
528 {
529 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
530 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
531 }
532
533 static struct qreg
534 tgsi_to_qir_usne(struct vc4_compile *c,
535 struct tgsi_full_instruction *tgsi_inst,
536 enum qop op, struct qreg *src, int i)
537 {
538 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
539 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
540 }
541
542 static struct qreg
543 tgsi_to_qir_islt(struct vc4_compile *c,
544 struct tgsi_full_instruction *tgsi_inst,
545 enum qop op, struct qreg *src, int i)
546 {
547 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
548 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
549 }
550
551 static struct qreg
552 tgsi_to_qir_isge(struct vc4_compile *c,
553 struct tgsi_full_instruction *tgsi_inst,
554 enum qop op, struct qreg *src, int i)
555 {
556 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
557 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
558 }
559
560 static struct qreg
561 tgsi_to_qir_cmp(struct vc4_compile *c,
562 struct tgsi_full_instruction *tgsi_inst,
563 enum qop op, struct qreg *src, int i)
564 {
565 qir_SF(c, src[0 * 4 + i]);
566 return qir_SEL_X_Y_NS(c,
567 src[1 * 4 + i],
568 src[2 * 4 + i]);
569 }
570
571 static struct qreg
572 tgsi_to_qir_mad(struct vc4_compile *c,
573 struct tgsi_full_instruction *tgsi_inst,
574 enum qop op, struct qreg *src, int i)
575 {
576 return qir_FADD(c,
577 qir_FMUL(c,
578 src[0 * 4 + i],
579 src[1 * 4 + i]),
580 src[2 * 4 + i]);
581 }
582
583 static struct qreg
584 tgsi_to_qir_lrp(struct vc4_compile *c,
585 struct tgsi_full_instruction *tgsi_inst,
586 enum qop op, struct qreg *src, int i)
587 {
588 struct qreg src0 = src[0 * 4 + i];
589 struct qreg src1 = src[1 * 4 + i];
590 struct qreg src2 = src[2 * 4 + i];
591
592 /* LRP is:
593 * src0 * src1 + (1 - src0) * src2.
594 * -> src0 * src1 + src2 - src0 * src2
595 * -> src2 + src0 * (src1 - src2)
596 */
597 return qir_FADD(c, src2, qir_FMUL(c, src0, qir_FSUB(c, src1, src2)));
598
599 }
600
601 static void
602 tgsi_to_qir_tex(struct vc4_compile *c,
603 struct tgsi_full_instruction *tgsi_inst,
604 enum qop op, struct qreg *src)
605 {
606 assert(!tgsi_inst->Instruction.Saturate);
607
608 struct qreg s = src[0 * 4 + 0];
609 struct qreg t = src[0 * 4 + 1];
610 struct qreg r = src[0 * 4 + 2];
611 uint32_t unit = tgsi_inst->Src[1].Register.Index;
612 bool is_txl = tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL;
613
614 struct qreg proj = c->undef;
615 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
616 proj = qir_RCP(c, src[0 * 4 + 3]);
617 s = qir_FMUL(c, s, proj);
618 t = qir_FMUL(c, t, proj);
619 }
620
621 struct qreg texture_u[] = {
622 add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit),
623 add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
624 add_uniform(c, QUNIFORM_CONSTANT, 0),
625 add_uniform(c, QUNIFORM_CONSTANT, 0),
626 };
627 uint32_t next_texture_u = 0;
628
629 /* There is no native support for GL texture rectangle coordinates, so
630 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
631 * 1]).
632 */
633 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_RECT ||
634 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT) {
635 s = qir_FMUL(c, s,
636 get_temp_for_uniform(c,
637 QUNIFORM_TEXRECT_SCALE_X,
638 unit));
639 t = qir_FMUL(c, t,
640 get_temp_for_uniform(c,
641 QUNIFORM_TEXRECT_SCALE_Y,
642 unit));
643 }
644
645 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
646 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
647 is_txl) {
648 texture_u[2] = add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P2,
649 unit | (is_txl << 16));
650 }
651
652 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
653 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE) {
654 struct qreg ma = qir_FMAXABS(c, qir_FMAXABS(c, s, t), r);
655 struct qreg rcp_ma = qir_RCP(c, ma);
656 s = qir_FMUL(c, s, rcp_ma);
657 t = qir_FMUL(c, t, rcp_ma);
658 r = qir_FMUL(c, r, rcp_ma);
659
660 qir_TEX_R(c, r, texture_u[next_texture_u++]);
661 } else if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
662 c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP ||
663 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
664 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
665 qir_TEX_R(c, get_temp_for_uniform(c, QUNIFORM_TEXTURE_BORDER_COLOR, unit),
666 texture_u[next_texture_u++]);
667 }
668
669 if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP) {
670 s = qir_FMIN(c, qir_FMAX(c, s, qir_uniform_f(c, 0.0)),
671 qir_uniform_f(c, 1.0));
672 }
673
674 if (c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
675 t = qir_FMIN(c, qir_FMAX(c, t, qir_uniform_f(c, 0.0)),
676 qir_uniform_f(c, 1.0));
677 }
678
679 qir_TEX_T(c, t, texture_u[next_texture_u++]);
680
681 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
682 tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL)
683 qir_TEX_B(c, src[0 * 4 + 3], texture_u[next_texture_u++]);
684
685 qir_TEX_S(c, s, texture_u[next_texture_u++]);
686
687 c->num_texture_samples++;
688 struct qreg r4 = qir_TEX_RESULT(c);
689
690 enum pipe_format format = c->key->tex[unit].format;
691
692 struct qreg unpacked[4];
693 if (util_format_is_depth_or_stencil(format)) {
694 struct qreg depthf = qir_ITOF(c, qir_SHR(c, r4,
695 qir_uniform_ui(c, 8)));
696 struct qreg normalized = qir_FMUL(c, depthf,
697 qir_uniform_f(c, 1.0f/0xffffff));
698
699 struct qreg depth_output;
700
701 struct qreg one = qir_uniform_f(c, 1.0f);
702 if (c->key->tex[unit].compare_mode) {
703 struct qreg compare = src[0 * 4 + 2];
704
705 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP)
706 compare = qir_FMUL(c, compare, proj);
707
708 switch (c->key->tex[unit].compare_func) {
709 case PIPE_FUNC_NEVER:
710 depth_output = qir_uniform_f(c, 0.0f);
711 break;
712 case PIPE_FUNC_ALWAYS:
713 depth_output = one;
714 break;
715 case PIPE_FUNC_EQUAL:
716 qir_SF(c, qir_FSUB(c, compare, normalized));
717 depth_output = qir_SEL_X_0_ZS(c, one);
718 break;
719 case PIPE_FUNC_NOTEQUAL:
720 qir_SF(c, qir_FSUB(c, compare, normalized));
721 depth_output = qir_SEL_X_0_ZC(c, one);
722 break;
723 case PIPE_FUNC_GREATER:
724 qir_SF(c, qir_FSUB(c, compare, normalized));
725 depth_output = qir_SEL_X_0_NC(c, one);
726 break;
727 case PIPE_FUNC_GEQUAL:
728 qir_SF(c, qir_FSUB(c, normalized, compare));
729 depth_output = qir_SEL_X_0_NS(c, one);
730 break;
731 case PIPE_FUNC_LESS:
732 qir_SF(c, qir_FSUB(c, compare, normalized));
733 depth_output = qir_SEL_X_0_NS(c, one);
734 break;
735 case PIPE_FUNC_LEQUAL:
736 qir_SF(c, qir_FSUB(c, normalized, compare));
737 depth_output = qir_SEL_X_0_NC(c, one);
738 break;
739 }
740 } else {
741 depth_output = normalized;
742 }
743
744 for (int i = 0; i < 4; i++)
745 unpacked[i] = depth_output;
746 } else {
747 for (int i = 0; i < 4; i++)
748 unpacked[i] = qir_R4_UNPACK(c, r4, i);
749 }
750
751 const uint8_t *format_swiz = vc4_get_format_swizzle(format);
752 struct qreg texture_output[4];
753 for (int i = 0; i < 4; i++) {
754 texture_output[i] = get_swizzled_channel(c, unpacked,
755 format_swiz[i]);
756 }
757
758 if (util_format_is_srgb(format)) {
759 for (int i = 0; i < 3; i++)
760 texture_output[i] = qir_srgb_decode(c,
761 texture_output[i]);
762 }
763
764 for (int i = 0; i < 4; i++) {
765 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
766 continue;
767
768 update_dst(c, tgsi_inst, i,
769 get_swizzled_channel(c, texture_output,
770 c->key->tex[unit].swizzle[i]));
771 }
772 }
773
774 static struct qreg
775 tgsi_to_qir_trunc(struct vc4_compile *c,
776 struct tgsi_full_instruction *tgsi_inst,
777 enum qop op, struct qreg *src, int i)
778 {
779 return qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
780 }
781
782 /**
783 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
784 * to zero).
785 */
786 static struct qreg
787 tgsi_to_qir_frc(struct vc4_compile *c,
788 struct tgsi_full_instruction *tgsi_inst,
789 enum qop op, struct qreg *src, int i)
790 {
791 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
792 struct qreg diff = qir_FSUB(c, src[0 * 4 + i], trunc);
793 qir_SF(c, diff);
794 return qir_SEL_X_Y_NS(c,
795 qir_FADD(c, diff, qir_uniform_f(c, 1.0)),
796 diff);
797 }
798
799 /**
800 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
801 * zero).
802 */
803 static struct qreg
804 tgsi_to_qir_flr(struct vc4_compile *c,
805 struct tgsi_full_instruction *tgsi_inst,
806 enum qop op, struct qreg *src, int i)
807 {
808 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
809
810 /* This will be < 0 if we truncated and the truncation was of a value
811 * that was < 0 in the first place.
812 */
813 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], trunc));
814
815 return qir_SEL_X_Y_NS(c,
816 qir_FSUB(c, trunc, qir_uniform_f(c, 1.0)),
817 trunc);
818 }
819
820 /**
821 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
822 * zero).
823 */
824 static struct qreg
825 tgsi_to_qir_ceil(struct vc4_compile *c,
826 struct tgsi_full_instruction *tgsi_inst,
827 enum qop op, struct qreg *src, int i)
828 {
829 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
830
831 /* This will be < 0 if we truncated and the truncation was of a value
832 * that was > 0 in the first place.
833 */
834 qir_SF(c, qir_FSUB(c, trunc, src[0 * 4 + i]));
835
836 return qir_SEL_X_Y_NS(c,
837 qir_FADD(c, trunc, qir_uniform_f(c, 1.0)),
838 trunc);
839 }
840
841 static struct qreg
842 tgsi_to_qir_abs(struct vc4_compile *c,
843 struct tgsi_full_instruction *tgsi_inst,
844 enum qop op, struct qreg *src, int i)
845 {
846 struct qreg arg = src[0 * 4 + i];
847 return qir_FMAXABS(c, arg, arg);
848 }
849
850 /* Note that this instruction replicates its result from the x channel */
851 static struct qreg
852 tgsi_to_qir_sin(struct vc4_compile *c,
853 struct tgsi_full_instruction *tgsi_inst,
854 enum qop op, struct qreg *src, int i)
855 {
856 float coeff[] = {
857 -2.0 * M_PI,
858 pow(2.0 * M_PI, 3) / (3 * 2 * 1),
859 -pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
860 pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
861 -pow(2.0 * M_PI, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
862 };
863
864 struct qreg scaled_x =
865 qir_FMUL(c,
866 src[0 * 4 + 0],
867 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
868
869 struct qreg x = qir_FADD(c,
870 tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0),
871 qir_uniform_f(c, -0.5));
872 struct qreg x2 = qir_FMUL(c, x, x);
873 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
874 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
875 x = qir_FMUL(c, x, x2);
876 sum = qir_FADD(c,
877 sum,
878 qir_FMUL(c,
879 x,
880 qir_uniform_f(c, coeff[i])));
881 }
882 return sum;
883 }
884
885 /* Note that this instruction replicates its result from the x channel */
886 static struct qreg
887 tgsi_to_qir_cos(struct vc4_compile *c,
888 struct tgsi_full_instruction *tgsi_inst,
889 enum qop op, struct qreg *src, int i)
890 {
891 float coeff[] = {
892 -1.0f,
893 pow(2.0 * M_PI, 2) / (2 * 1),
894 -pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
895 pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
896 -pow(2.0 * M_PI, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
897 pow(2.0 * M_PI, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
898 };
899
900 struct qreg scaled_x =
901 qir_FMUL(c, src[0 * 4 + 0],
902 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
903 struct qreg x_frac = qir_FADD(c,
904 tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0),
905 qir_uniform_f(c, -0.5));
906
907 struct qreg sum = qir_uniform_f(c, coeff[0]);
908 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
909 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
910 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
911 if (i != 1)
912 x = qir_FMUL(c, x, x2);
913
914 struct qreg mul = qir_FMUL(c,
915 x,
916 qir_uniform_f(c, coeff[i]));
917 if (i == 0)
918 sum = mul;
919 else
920 sum = qir_FADD(c, sum, mul);
921 }
922 return sum;
923 }
924
925 static struct qreg
926 tgsi_to_qir_clamp(struct vc4_compile *c,
927 struct tgsi_full_instruction *tgsi_inst,
928 enum qop op, struct qreg *src, int i)
929 {
930 return qir_FMAX(c, qir_FMIN(c,
931 src[0 * 4 + i],
932 src[2 * 4 + i]),
933 src[1 * 4 + i]);
934 }
935
936 static struct qreg
937 tgsi_to_qir_ssg(struct vc4_compile *c,
938 struct tgsi_full_instruction *tgsi_inst,
939 enum qop op, struct qreg *src, int i)
940 {
941 qir_SF(c, src[0 * 4 + i]);
942 return qir_SEL_X_Y_NC(c,
943 qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0)),
944 qir_uniform_f(c, -1.0));
945 }
946
947 /* Compare to tgsi_to_qir_flr() for the floor logic. */
948 static struct qreg
949 tgsi_to_qir_arl(struct vc4_compile *c,
950 struct tgsi_full_instruction *tgsi_inst,
951 enum qop op, struct qreg *src, int i)
952 {
953 struct qreg trunc = qir_FTOI(c, src[0 * 4 + i]);
954 struct qreg scaled = qir_SHL(c, trunc, qir_uniform_ui(c, 4));
955
956 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], qir_ITOF(c, trunc)));
957
958 return qir_SEL_X_Y_NS(c, qir_SUB(c, scaled, qir_uniform_ui(c, 4)),
959 scaled);
960 }
961
962 static struct qreg
963 tgsi_to_qir_uarl(struct vc4_compile *c,
964 struct tgsi_full_instruction *tgsi_inst,
965 enum qop op, struct qreg *src, int i)
966 {
967 return qir_SHL(c, src[0 * 4 + i], qir_uniform_ui(c, 4));
968 }
969
970 static void
971 emit_vertex_input(struct vc4_compile *c, int attr)
972 {
973 enum pipe_format format = c->vs_key->attr_formats[attr];
974 struct qreg vpm_reads[4];
975
976 /* Right now, we're setting the VPM offsets to be 16 bytes wide every
977 * time, so we always read 4 32-bit VPM entries.
978 */
979 for (int i = 0; i < 4; i++) {
980 vpm_reads[i] = qir_get_temp(c);
981 qir_emit(c, qir_inst(QOP_VPM_READ,
982 vpm_reads[i],
983 c->undef,
984 c->undef));
985 c->num_inputs++;
986 }
987
988 bool format_warned = false;
989 const struct util_format_description *desc =
990 util_format_description(format);
991
992 for (int i = 0; i < 4; i++) {
993 uint8_t swiz = desc->swizzle[i];
994 struct qreg result;
995
996 if (swiz > UTIL_FORMAT_SWIZZLE_W)
997 result = get_swizzled_channel(c, vpm_reads, swiz);
998 else if (desc->channel[swiz].size == 32 &&
999 desc->channel[swiz].type == UTIL_FORMAT_TYPE_FLOAT) {
1000 result = get_swizzled_channel(c, vpm_reads, swiz);
1001 } else if (desc->channel[swiz].size == 8 &&
1002 (desc->channel[swiz].type == UTIL_FORMAT_TYPE_UNSIGNED ||
1003 desc->channel[swiz].type == UTIL_FORMAT_TYPE_SIGNED) &&
1004 desc->channel[swiz].normalized) {
1005 struct qreg vpm = vpm_reads[0];
1006 if (desc->channel[swiz].type == UTIL_FORMAT_TYPE_SIGNED)
1007 vpm = qir_XOR(c, vpm, qir_uniform_ui(c, 0x80808080));
1008 result = qir_UNPACK_8(c, vpm, swiz);
1009 } else {
1010 if (!format_warned) {
1011 fprintf(stderr,
1012 "vtx element %d unsupported type: %s\n",
1013 attr, util_format_name(format));
1014 format_warned = true;
1015 }
1016 result = qir_uniform_f(c, 0.0);
1017 }
1018
1019 if (desc->channel[swiz].normalized &&
1020 desc->channel[swiz].type == UTIL_FORMAT_TYPE_SIGNED) {
1021 result = qir_FSUB(c,
1022 qir_FMUL(c,
1023 result,
1024 qir_uniform_f(c, 2.0)),
1025 qir_uniform_f(c, 1.0));
1026 }
1027
1028 c->inputs[attr * 4 + i] = result;
1029 }
1030 }
1031
1032 static void
1033 tgsi_to_qir_kill_if(struct vc4_compile *c, struct qreg *src, int i)
1034 {
1035 if (c->discard.file == QFILE_NULL)
1036 c->discard = qir_uniform_f(c, 0.0);
1037 qir_SF(c, src[0 * 4 + i]);
1038 c->discard = qir_SEL_X_Y_NS(c, qir_uniform_f(c, 1.0),
1039 c->discard);
1040 }
1041
1042 static void
1043 emit_fragcoord_input(struct vc4_compile *c, int attr)
1044 {
1045 c->inputs[attr * 4 + 0] = qir_FRAG_X(c);
1046 c->inputs[attr * 4 + 1] = qir_FRAG_Y(c);
1047 c->inputs[attr * 4 + 2] =
1048 qir_FMUL(c,
1049 qir_ITOF(c, qir_FRAG_Z(c)),
1050 qir_uniform_f(c, 1.0 / 0xffffff));
1051 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
1052 }
1053
1054 static void
1055 emit_point_coord_input(struct vc4_compile *c, int attr)
1056 {
1057 if (c->point_x.file == QFILE_NULL) {
1058 c->point_x = qir_uniform_f(c, 0.0);
1059 c->point_y = qir_uniform_f(c, 0.0);
1060 }
1061
1062 c->inputs[attr * 4 + 0] = c->point_x;
1063 if (c->fs_key->point_coord_upper_left) {
1064 c->inputs[attr * 4 + 1] = qir_FSUB(c,
1065 qir_uniform_f(c, 1.0),
1066 c->point_y);
1067 } else {
1068 c->inputs[attr * 4 + 1] = c->point_y;
1069 }
1070 c->inputs[attr * 4 + 2] = qir_uniform_f(c, 0.0);
1071 c->inputs[attr * 4 + 3] = qir_uniform_f(c, 1.0);
1072 }
1073
1074 static struct qreg
1075 emit_fragment_varying(struct vc4_compile *c, uint8_t semantic,
1076 uint8_t index, uint8_t swizzle)
1077 {
1078 uint32_t i = c->num_input_semantics++;
1079 struct qreg vary = {
1080 QFILE_VARY,
1081 i
1082 };
1083
1084 if (c->num_input_semantics >= c->input_semantics_array_size) {
1085 c->input_semantics_array_size =
1086 MAX2(4, c->input_semantics_array_size * 2);
1087
1088 c->input_semantics = reralloc(c, c->input_semantics,
1089 struct vc4_varying_semantic,
1090 c->input_semantics_array_size);
1091 }
1092
1093 c->input_semantics[i].semantic = semantic;
1094 c->input_semantics[i].index = index;
1095 c->input_semantics[i].swizzle = swizzle;
1096
1097 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
1098 }
1099
1100 static void
1101 emit_fragment_input(struct vc4_compile *c, int attr,
1102 struct tgsi_full_declaration *decl)
1103 {
1104 for (int i = 0; i < 4; i++) {
1105 c->inputs[attr * 4 + i] =
1106 emit_fragment_varying(c,
1107 decl->Semantic.Name,
1108 decl->Semantic.Index,
1109 i);
1110 c->num_inputs++;
1111 }
1112 }
1113
1114 static void
1115 emit_face_input(struct vc4_compile *c, int attr)
1116 {
1117 c->inputs[attr * 4 + 0] = qir_FSUB(c,
1118 qir_uniform_f(c, 1.0),
1119 qir_FMUL(c,
1120 qir_ITOF(c, qir_FRAG_REV_FLAG(c)),
1121 qir_uniform_f(c, 2.0)));
1122 c->inputs[attr * 4 + 1] = qir_uniform_f(c, 0.0);
1123 c->inputs[attr * 4 + 2] = qir_uniform_f(c, 0.0);
1124 c->inputs[attr * 4 + 3] = qir_uniform_f(c, 1.0);
1125 }
1126
1127 static void
1128 add_output(struct vc4_compile *c,
1129 uint32_t decl_offset,
1130 uint8_t semantic_name,
1131 uint8_t semantic_index,
1132 uint8_t semantic_swizzle)
1133 {
1134 uint32_t old_array_size = c->outputs_array_size;
1135 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
1136 decl_offset + 1);
1137
1138 if (old_array_size != c->outputs_array_size) {
1139 c->output_semantics = reralloc(c,
1140 c->output_semantics,
1141 struct vc4_varying_semantic,
1142 c->outputs_array_size);
1143 }
1144
1145 c->output_semantics[decl_offset].semantic = semantic_name;
1146 c->output_semantics[decl_offset].index = semantic_index;
1147 c->output_semantics[decl_offset].swizzle = semantic_swizzle;
1148 }
1149
1150 static void
1151 add_array_info(struct vc4_compile *c, uint32_t array_id,
1152 uint32_t start, uint32_t size)
1153 {
1154 if (array_id >= c->ubo_ranges_array_size) {
1155 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
1156 array_id + 1);
1157 c->ubo_ranges = reralloc(c, c->ubo_ranges,
1158 struct vc4_compiler_ubo_range,
1159 c->ubo_ranges_array_size);
1160 }
1161
1162 c->ubo_ranges[array_id].dst_offset = 0;
1163 c->ubo_ranges[array_id].src_offset = start;
1164 c->ubo_ranges[array_id].size = size;
1165 c->ubo_ranges[array_id].used = false;
1166 }
1167
1168 static void
1169 emit_tgsi_declaration(struct vc4_compile *c,
1170 struct tgsi_full_declaration *decl)
1171 {
1172 switch (decl->Declaration.File) {
1173 case TGSI_FILE_TEMPORARY: {
1174 uint32_t old_size = c->temps_array_size;
1175 resize_qreg_array(c, &c->temps, &c->temps_array_size,
1176 (decl->Range.Last + 1) * 4);
1177
1178 for (int i = old_size; i < c->temps_array_size; i++)
1179 c->temps[i] = qir_uniform_ui(c, 0);
1180 break;
1181 }
1182
1183 case TGSI_FILE_INPUT:
1184 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1185 (decl->Range.Last + 1) * 4);
1186
1187 for (int i = decl->Range.First;
1188 i <= decl->Range.Last;
1189 i++) {
1190 if (c->stage == QSTAGE_FRAG) {
1191 if (decl->Semantic.Name ==
1192 TGSI_SEMANTIC_POSITION) {
1193 emit_fragcoord_input(c, i);
1194 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
1195 emit_face_input(c, i);
1196 } else if (decl->Semantic.Name == TGSI_SEMANTIC_GENERIC &&
1197 (c->fs_key->point_sprite_mask &
1198 (1 << decl->Semantic.Index))) {
1199 emit_point_coord_input(c, i);
1200 } else {
1201 emit_fragment_input(c, i, decl);
1202 }
1203 } else {
1204 emit_vertex_input(c, i);
1205 }
1206 }
1207 break;
1208
1209 case TGSI_FILE_OUTPUT: {
1210 for (int i = 0; i < 4; i++) {
1211 add_output(c,
1212 decl->Range.First * 4 + i,
1213 decl->Semantic.Name,
1214 decl->Semantic.Index,
1215 i);
1216 }
1217
1218 switch (decl->Semantic.Name) {
1219 case TGSI_SEMANTIC_POSITION:
1220 c->output_position_index = decl->Range.First * 4;
1221 break;
1222 case TGSI_SEMANTIC_CLIPVERTEX:
1223 c->output_clipvertex_index = decl->Range.First * 4;
1224 break;
1225 case TGSI_SEMANTIC_COLOR:
1226 c->output_color_index = decl->Range.First * 4;
1227 break;
1228 case TGSI_SEMANTIC_PSIZE:
1229 c->output_point_size_index = decl->Range.First * 4;
1230 break;
1231 }
1232
1233 break;
1234
1235 case TGSI_FILE_CONSTANT:
1236 add_array_info(c,
1237 decl->Array.ArrayID,
1238 decl->Range.First * 16,
1239 (decl->Range.Last -
1240 decl->Range.First + 1) * 16);
1241 break;
1242 }
1243 }
1244 }
1245
1246 static void
1247 emit_tgsi_instruction(struct vc4_compile *c,
1248 struct tgsi_full_instruction *tgsi_inst)
1249 {
1250 struct {
1251 enum qop op;
1252 struct qreg (*func)(struct vc4_compile *c,
1253 struct tgsi_full_instruction *tgsi_inst,
1254 enum qop op,
1255 struct qreg *src, int i);
1256 } op_trans[] = {
1257 [TGSI_OPCODE_MOV] = { QOP_MOV, tgsi_to_qir_alu },
1258 [TGSI_OPCODE_ABS] = { 0, tgsi_to_qir_abs },
1259 [TGSI_OPCODE_MUL] = { QOP_FMUL, tgsi_to_qir_alu },
1260 [TGSI_OPCODE_ADD] = { QOP_FADD, tgsi_to_qir_alu },
1261 [TGSI_OPCODE_SUB] = { QOP_FSUB, tgsi_to_qir_alu },
1262 [TGSI_OPCODE_MIN] = { QOP_FMIN, tgsi_to_qir_alu },
1263 [TGSI_OPCODE_MAX] = { QOP_FMAX, tgsi_to_qir_alu },
1264 [TGSI_OPCODE_F2I] = { QOP_FTOI, tgsi_to_qir_alu },
1265 [TGSI_OPCODE_I2F] = { QOP_ITOF, tgsi_to_qir_alu },
1266 [TGSI_OPCODE_UADD] = { QOP_ADD, tgsi_to_qir_alu },
1267 [TGSI_OPCODE_USHR] = { QOP_SHR, tgsi_to_qir_alu },
1268 [TGSI_OPCODE_ISHR] = { QOP_ASR, tgsi_to_qir_alu },
1269 [TGSI_OPCODE_SHL] = { QOP_SHL, tgsi_to_qir_alu },
1270 [TGSI_OPCODE_IMIN] = { QOP_MIN, tgsi_to_qir_alu },
1271 [TGSI_OPCODE_IMAX] = { QOP_MAX, tgsi_to_qir_alu },
1272 [TGSI_OPCODE_AND] = { QOP_AND, tgsi_to_qir_alu },
1273 [TGSI_OPCODE_OR] = { QOP_OR, tgsi_to_qir_alu },
1274 [TGSI_OPCODE_XOR] = { QOP_XOR, tgsi_to_qir_alu },
1275 [TGSI_OPCODE_NOT] = { QOP_NOT, tgsi_to_qir_alu },
1276
1277 [TGSI_OPCODE_UMUL] = { 0, tgsi_to_qir_umul },
1278 [TGSI_OPCODE_IDIV] = { 0, tgsi_to_qir_idiv },
1279 [TGSI_OPCODE_INEG] = { 0, tgsi_to_qir_ineg },
1280
1281 [TGSI_OPCODE_SEQ] = { 0, tgsi_to_qir_seq },
1282 [TGSI_OPCODE_SNE] = { 0, tgsi_to_qir_sne },
1283 [TGSI_OPCODE_SGE] = { 0, tgsi_to_qir_sge },
1284 [TGSI_OPCODE_SLT] = { 0, tgsi_to_qir_slt },
1285 [TGSI_OPCODE_FSEQ] = { 0, tgsi_to_qir_fseq },
1286 [TGSI_OPCODE_FSNE] = { 0, tgsi_to_qir_fsne },
1287 [TGSI_OPCODE_FSGE] = { 0, tgsi_to_qir_fsge },
1288 [TGSI_OPCODE_FSLT] = { 0, tgsi_to_qir_fslt },
1289 [TGSI_OPCODE_USEQ] = { 0, tgsi_to_qir_useq },
1290 [TGSI_OPCODE_USNE] = { 0, tgsi_to_qir_usne },
1291 [TGSI_OPCODE_ISGE] = { 0, tgsi_to_qir_isge },
1292 [TGSI_OPCODE_ISLT] = { 0, tgsi_to_qir_islt },
1293
1294 [TGSI_OPCODE_CMP] = { 0, tgsi_to_qir_cmp },
1295 [TGSI_OPCODE_MAD] = { 0, tgsi_to_qir_mad },
1296 [TGSI_OPCODE_RCP] = { QOP_RCP, tgsi_to_qir_rcp },
1297 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_rsq },
1298 [TGSI_OPCODE_EX2] = { QOP_EXP2, tgsi_to_qir_scalar },
1299 [TGSI_OPCODE_LG2] = { QOP_LOG2, tgsi_to_qir_scalar },
1300 [TGSI_OPCODE_LRP] = { 0, tgsi_to_qir_lrp },
1301 [TGSI_OPCODE_TRUNC] = { 0, tgsi_to_qir_trunc },
1302 [TGSI_OPCODE_CEIL] = { 0, tgsi_to_qir_ceil },
1303 [TGSI_OPCODE_FRC] = { 0, tgsi_to_qir_frc },
1304 [TGSI_OPCODE_FLR] = { 0, tgsi_to_qir_flr },
1305 [TGSI_OPCODE_SIN] = { 0, tgsi_to_qir_sin },
1306 [TGSI_OPCODE_COS] = { 0, tgsi_to_qir_cos },
1307 [TGSI_OPCODE_CLAMP] = { 0, tgsi_to_qir_clamp },
1308 [TGSI_OPCODE_SSG] = { 0, tgsi_to_qir_ssg },
1309 [TGSI_OPCODE_ARL] = { 0, tgsi_to_qir_arl },
1310 [TGSI_OPCODE_UARL] = { 0, tgsi_to_qir_uarl },
1311 };
1312 static int asdf = 0;
1313 uint32_t tgsi_op = tgsi_inst->Instruction.Opcode;
1314
1315 if (tgsi_op == TGSI_OPCODE_END)
1316 return;
1317
1318 struct qreg src_regs[12];
1319 for (int s = 0; s < 3; s++) {
1320 for (int i = 0; i < 4; i++) {
1321 src_regs[4 * s + i] =
1322 get_src(c, tgsi_inst->Instruction.Opcode,
1323 &tgsi_inst->Src[s], i);
1324 }
1325 }
1326
1327 switch (tgsi_op) {
1328 case TGSI_OPCODE_TEX:
1329 case TGSI_OPCODE_TXP:
1330 case TGSI_OPCODE_TXB:
1331 case TGSI_OPCODE_TXL:
1332 tgsi_to_qir_tex(c, tgsi_inst,
1333 op_trans[tgsi_op].op, src_regs);
1334 return;
1335 case TGSI_OPCODE_KILL:
1336 c->discard = qir_uniform_f(c, 1.0);
1337 return;
1338 case TGSI_OPCODE_KILL_IF:
1339 for (int i = 0; i < 4; i++)
1340 tgsi_to_qir_kill_if(c, src_regs, i);
1341 return;
1342 default:
1343 break;
1344 }
1345
1346 if (tgsi_op > ARRAY_SIZE(op_trans) || !(op_trans[tgsi_op].func)) {
1347 fprintf(stderr, "unknown tgsi inst: ");
1348 tgsi_dump_instruction(tgsi_inst, asdf++);
1349 fprintf(stderr, "\n");
1350 abort();
1351 }
1352
1353 for (int i = 0; i < 4; i++) {
1354 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
1355 continue;
1356
1357 struct qreg result;
1358
1359 result = op_trans[tgsi_op].func(c, tgsi_inst,
1360 op_trans[tgsi_op].op,
1361 src_regs, i);
1362
1363 if (tgsi_inst->Instruction.Saturate) {
1364 float low = (tgsi_inst->Instruction.Saturate ==
1365 TGSI_SAT_MINUS_PLUS_ONE ? -1.0 : 0.0);
1366 result = qir_FMAX(c,
1367 qir_FMIN(c,
1368 result,
1369 qir_uniform_f(c, 1.0)),
1370 qir_uniform_f(c, low));
1371 }
1372
1373 update_dst(c, tgsi_inst, i, result);
1374 }
1375 }
1376
1377 static void
1378 parse_tgsi_immediate(struct vc4_compile *c, struct tgsi_full_immediate *imm)
1379 {
1380 for (int i = 0; i < 4; i++) {
1381 unsigned n = c->num_consts++;
1382 resize_qreg_array(c, &c->consts, &c->consts_array_size, n + 1);
1383 c->consts[n] = qir_uniform_ui(c, imm->u[i].Uint);
1384 }
1385 }
1386
1387 static struct qreg
1388 vc4_blend_channel(struct vc4_compile *c,
1389 struct qreg *dst,
1390 struct qreg *src,
1391 struct qreg val,
1392 unsigned factor,
1393 int channel)
1394 {
1395 switch(factor) {
1396 case PIPE_BLENDFACTOR_ONE:
1397 return val;
1398 case PIPE_BLENDFACTOR_SRC_COLOR:
1399 return qir_FMUL(c, val, src[channel]);
1400 case PIPE_BLENDFACTOR_SRC_ALPHA:
1401 return qir_FMUL(c, val, src[3]);
1402 case PIPE_BLENDFACTOR_DST_ALPHA:
1403 return qir_FMUL(c, val, dst[3]);
1404 case PIPE_BLENDFACTOR_DST_COLOR:
1405 return qir_FMUL(c, val, dst[channel]);
1406 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
1407 if (channel != 3) {
1408 return qir_FMUL(c,
1409 val,
1410 qir_FMIN(c,
1411 src[3],
1412 qir_FSUB(c,
1413 qir_uniform_f(c, 1.0),
1414 dst[3])));
1415 } else {
1416 return val;
1417 }
1418 case PIPE_BLENDFACTOR_CONST_COLOR:
1419 return qir_FMUL(c, val,
1420 get_temp_for_uniform(c,
1421 QUNIFORM_BLEND_CONST_COLOR,
1422 channel));
1423 case PIPE_BLENDFACTOR_CONST_ALPHA:
1424 return qir_FMUL(c, val,
1425 get_temp_for_uniform(c,
1426 QUNIFORM_BLEND_CONST_COLOR,
1427 3));
1428 case PIPE_BLENDFACTOR_ZERO:
1429 return qir_uniform_f(c, 0.0);
1430 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
1431 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1432 src[channel]));
1433 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
1434 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1435 src[3]));
1436 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
1437 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1438 dst[3]));
1439 case PIPE_BLENDFACTOR_INV_DST_COLOR:
1440 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1441 dst[channel]));
1442 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
1443 return qir_FMUL(c, val,
1444 qir_FSUB(c, qir_uniform_f(c, 1.0),
1445 get_temp_for_uniform(c,
1446 QUNIFORM_BLEND_CONST_COLOR,
1447 channel)));
1448 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
1449 return qir_FMUL(c, val,
1450 qir_FSUB(c, qir_uniform_f(c, 1.0),
1451 get_temp_for_uniform(c,
1452 QUNIFORM_BLEND_CONST_COLOR,
1453 3)));
1454
1455 default:
1456 case PIPE_BLENDFACTOR_SRC1_COLOR:
1457 case PIPE_BLENDFACTOR_SRC1_ALPHA:
1458 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
1459 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
1460 /* Unsupported. */
1461 fprintf(stderr, "Unknown blend factor %d\n", factor);
1462 return val;
1463 }
1464 }
1465
1466 static struct qreg
1467 vc4_blend_func(struct vc4_compile *c,
1468 struct qreg src, struct qreg dst,
1469 unsigned func)
1470 {
1471 switch (func) {
1472 case PIPE_BLEND_ADD:
1473 return qir_FADD(c, src, dst);
1474 case PIPE_BLEND_SUBTRACT:
1475 return qir_FSUB(c, src, dst);
1476 case PIPE_BLEND_REVERSE_SUBTRACT:
1477 return qir_FSUB(c, dst, src);
1478 case PIPE_BLEND_MIN:
1479 return qir_FMIN(c, src, dst);
1480 case PIPE_BLEND_MAX:
1481 return qir_FMAX(c, src, dst);
1482
1483 default:
1484 /* Unsupported. */
1485 fprintf(stderr, "Unknown blend func %d\n", func);
1486 return src;
1487
1488 }
1489 }
1490
1491 /**
1492 * Implements fixed function blending in shader code.
1493 *
1494 * VC4 doesn't have any hardware support for blending. Instead, you read the
1495 * current contents of the destination from the tile buffer after having
1496 * waited for the scoreboard (which is handled by vc4_qpu_emit.c), then do
1497 * math using your output color and that destination value, and update the
1498 * output color appropriately.
1499 */
1500 static void
1501 vc4_blend(struct vc4_compile *c, struct qreg *result,
1502 struct qreg *dst_color, struct qreg *src_color)
1503 {
1504 struct pipe_rt_blend_state *blend = &c->fs_key->blend;
1505
1506 if (!blend->blend_enable) {
1507 for (int i = 0; i < 4; i++)
1508 result[i] = src_color[i];
1509 return;
1510 }
1511
1512 struct qreg src_blend[4], dst_blend[4];
1513 for (int i = 0; i < 3; i++) {
1514 src_blend[i] = vc4_blend_channel(c,
1515 dst_color, src_color,
1516 src_color[i],
1517 blend->rgb_src_factor, i);
1518 dst_blend[i] = vc4_blend_channel(c,
1519 dst_color, src_color,
1520 dst_color[i],
1521 blend->rgb_dst_factor, i);
1522 }
1523 src_blend[3] = vc4_blend_channel(c,
1524 dst_color, src_color,
1525 src_color[3],
1526 blend->alpha_src_factor, 3);
1527 dst_blend[3] = vc4_blend_channel(c,
1528 dst_color, src_color,
1529 dst_color[3],
1530 blend->alpha_dst_factor, 3);
1531
1532 for (int i = 0; i < 3; i++) {
1533 result[i] = vc4_blend_func(c,
1534 src_blend[i], dst_blend[i],
1535 blend->rgb_func);
1536 }
1537 result[3] = vc4_blend_func(c,
1538 src_blend[3], dst_blend[3],
1539 blend->alpha_func);
1540 }
1541
1542 static void
1543 clip_distance_discard(struct vc4_compile *c)
1544 {
1545 for (int i = 0; i < PIPE_MAX_CLIP_PLANES; i++) {
1546 if (!(c->key->ucp_enables & (1 << i)))
1547 continue;
1548
1549 struct qreg dist = emit_fragment_varying(c,
1550 TGSI_SEMANTIC_CLIPDIST,
1551 i,
1552 TGSI_SWIZZLE_X);
1553
1554 qir_SF(c, dist);
1555
1556 if (c->discard.file == QFILE_NULL)
1557 c->discard = qir_uniform_f(c, 0.0);
1558
1559 c->discard = qir_SEL_X_Y_NS(c, qir_uniform_f(c, 1.0),
1560 c->discard);
1561 }
1562 }
1563
1564 static void
1565 alpha_test_discard(struct vc4_compile *c)
1566 {
1567 struct qreg src_alpha;
1568 struct qreg alpha_ref = get_temp_for_uniform(c, QUNIFORM_ALPHA_REF, 0);
1569
1570 if (!c->fs_key->alpha_test)
1571 return;
1572
1573 if (c->output_color_index != -1)
1574 src_alpha = c->outputs[c->output_color_index + 3];
1575 else
1576 src_alpha = qir_uniform_f(c, 1.0);
1577
1578 if (c->discard.file == QFILE_NULL)
1579 c->discard = qir_uniform_f(c, 0.0);
1580
1581 switch (c->fs_key->alpha_test_func) {
1582 case PIPE_FUNC_NEVER:
1583 c->discard = qir_uniform_f(c, 1.0);
1584 break;
1585 case PIPE_FUNC_ALWAYS:
1586 break;
1587 case PIPE_FUNC_EQUAL:
1588 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1589 c->discard = qir_SEL_X_Y_ZS(c, c->discard,
1590 qir_uniform_f(c, 1.0));
1591 break;
1592 case PIPE_FUNC_NOTEQUAL:
1593 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1594 c->discard = qir_SEL_X_Y_ZC(c, c->discard,
1595 qir_uniform_f(c, 1.0));
1596 break;
1597 case PIPE_FUNC_GREATER:
1598 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1599 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1600 qir_uniform_f(c, 1.0));
1601 break;
1602 case PIPE_FUNC_GEQUAL:
1603 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1604 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1605 qir_uniform_f(c, 1.0));
1606 break;
1607 case PIPE_FUNC_LESS:
1608 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1609 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1610 qir_uniform_f(c, 1.0));
1611 break;
1612 case PIPE_FUNC_LEQUAL:
1613 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1614 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1615 qir_uniform_f(c, 1.0));
1616 break;
1617 }
1618 }
1619
1620 static void
1621 emit_frag_end(struct vc4_compile *c)
1622 {
1623 clip_distance_discard(c);
1624 alpha_test_discard(c);
1625
1626 enum pipe_format color_format = c->fs_key->color_format;
1627 const uint8_t *format_swiz = vc4_get_format_swizzle(color_format);
1628 struct qreg tlb_read_color[4] = { c->undef, c->undef, c->undef, c->undef };
1629 struct qreg dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1630 struct qreg linear_dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1631 if (c->fs_key->blend.blend_enable ||
1632 c->fs_key->blend.colormask != 0xf) {
1633 struct qreg r4 = qir_TLB_COLOR_READ(c);
1634 for (int i = 0; i < 4; i++)
1635 tlb_read_color[i] = qir_R4_UNPACK(c, r4, i);
1636 for (int i = 0; i < 4; i++) {
1637 dst_color[i] = get_swizzled_channel(c,
1638 tlb_read_color,
1639 format_swiz[i]);
1640 if (util_format_is_srgb(color_format) && i != 3) {
1641 linear_dst_color[i] =
1642 qir_srgb_decode(c, dst_color[i]);
1643 } else {
1644 linear_dst_color[i] = dst_color[i];
1645 }
1646 }
1647 }
1648
1649 struct qreg blend_color[4];
1650 struct qreg undef_array[4] = {
1651 c->undef, c->undef, c->undef, c->undef
1652 };
1653 vc4_blend(c, blend_color, linear_dst_color,
1654 (c->output_color_index != -1 ?
1655 c->outputs + c->output_color_index :
1656 undef_array));
1657
1658 if (util_format_is_srgb(color_format)) {
1659 for (int i = 0; i < 3; i++)
1660 blend_color[i] = qir_srgb_encode(c, blend_color[i]);
1661 }
1662
1663 /* If the bit isn't set in the color mask, then just return the
1664 * original dst color, instead.
1665 */
1666 for (int i = 0; i < 4; i++) {
1667 if (!(c->fs_key->blend.colormask & (1 << i))) {
1668 blend_color[i] = dst_color[i];
1669 }
1670 }
1671
1672 /* Debug: Sometimes you're getting a black output and just want to see
1673 * if the FS is getting executed at all. Spam magenta into the color
1674 * output.
1675 */
1676 if (0) {
1677 blend_color[0] = qir_uniform_f(c, 1.0);
1678 blend_color[1] = qir_uniform_f(c, 0.0);
1679 blend_color[2] = qir_uniform_f(c, 1.0);
1680 blend_color[3] = qir_uniform_f(c, 0.5);
1681 }
1682
1683 struct qreg swizzled_outputs[4];
1684 for (int i = 0; i < 4; i++) {
1685 swizzled_outputs[i] = get_swizzled_channel(c, blend_color,
1686 format_swiz[i]);
1687 }
1688
1689 if (c->discard.file != QFILE_NULL)
1690 qir_TLB_DISCARD_SETUP(c, c->discard);
1691
1692 if (c->fs_key->stencil_enabled) {
1693 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 0));
1694 if (c->fs_key->stencil_twoside) {
1695 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 1));
1696 }
1697 if (c->fs_key->stencil_full_writemasks) {
1698 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 2));
1699 }
1700 }
1701
1702 if (c->fs_key->depth_enabled) {
1703 struct qreg z;
1704 if (c->output_position_index != -1) {
1705 z = qir_FTOI(c, qir_FMUL(c, c->outputs[c->output_position_index + 2],
1706 qir_uniform_f(c, 0xffffff)));
1707 } else {
1708 z = qir_FRAG_Z(c);
1709 }
1710 qir_TLB_Z_WRITE(c, z);
1711 }
1712
1713 bool color_written = false;
1714 for (int i = 0; i < 4; i++) {
1715 if (swizzled_outputs[i].file != QFILE_NULL)
1716 color_written = true;
1717 }
1718
1719 struct qreg packed_color;
1720 if (color_written) {
1721 /* Fill in any undefined colors. The simulator will assertion
1722 * fail if we read something that wasn't written, and I don't
1723 * know what hardware does.
1724 */
1725 for (int i = 0; i < 4; i++) {
1726 if (swizzled_outputs[i].file == QFILE_NULL)
1727 swizzled_outputs[i] = qir_uniform_f(c, 0.0);
1728 }
1729 packed_color = qir_get_temp(c);
1730 qir_emit(c, qir_inst4(QOP_PACK_COLORS, packed_color,
1731 swizzled_outputs[0],
1732 swizzled_outputs[1],
1733 swizzled_outputs[2],
1734 swizzled_outputs[3]));
1735 } else {
1736 packed_color = qir_uniform_ui(c, 0);
1737 }
1738
1739 qir_emit(c, qir_inst(QOP_TLB_COLOR_WRITE, c->undef,
1740 packed_color, c->undef));
1741 }
1742
1743 static void
1744 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1745 {
1746 struct qreg xyi[2];
1747
1748 for (int i = 0; i < 2; i++) {
1749 struct qreg scale =
1750 add_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1751
1752 xyi[i] = qir_FTOI(c, qir_FMUL(c,
1753 qir_FMUL(c,
1754 c->outputs[c->output_position_index + i],
1755 scale),
1756 rcp_w));
1757 }
1758
1759 qir_VPM_WRITE(c, qir_PACK_SCALED(c, xyi[0], xyi[1]));
1760 }
1761
1762 static void
1763 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1764 {
1765 struct qreg zscale = add_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1766 struct qreg zoffset = add_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1767
1768 qir_VPM_WRITE(c, qir_FMUL(c, qir_FADD(c, qir_FMUL(c,
1769 c->outputs[c->output_position_index + 2],
1770 zscale),
1771 zoffset),
1772 rcp_w));
1773 }
1774
1775 static void
1776 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1777 {
1778 qir_VPM_WRITE(c, rcp_w);
1779 }
1780
1781 static void
1782 emit_point_size_write(struct vc4_compile *c)
1783 {
1784 struct qreg point_size;
1785
1786 if (c->output_point_size_index)
1787 point_size = c->outputs[c->output_point_size_index + 3];
1788 else
1789 point_size = qir_uniform_f(c, 1.0);
1790
1791 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1792 * BCM21553).
1793 */
1794 point_size = qir_FMAX(c, point_size, qir_uniform_f(c, .125));
1795
1796 qir_VPM_WRITE(c, point_size);
1797 }
1798
1799 /**
1800 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1801 *
1802 * The simulator insists that there be at least one vertex attribute, so
1803 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also
1804 * insists that all vertex attributes loaded get read by the VS/CS, so we have
1805 * to consume it here.
1806 */
1807 static void
1808 emit_stub_vpm_read(struct vc4_compile *c)
1809 {
1810 if (c->num_inputs)
1811 return;
1812
1813 for (int i = 0; i < 4; i++) {
1814 qir_emit(c, qir_inst(QOP_VPM_READ,
1815 qir_get_temp(c),
1816 c->undef,
1817 c->undef));
1818 c->num_inputs++;
1819 }
1820 }
1821
1822 static void
1823 emit_ucp_clipdistance(struct vc4_compile *c)
1824 {
1825 unsigned cv;
1826 if (c->output_clipvertex_index != -1)
1827 cv = c->output_clipvertex_index;
1828 else if (c->output_position_index != -1)
1829 cv = c->output_position_index;
1830 else
1831 return;
1832
1833 for (int plane = 0; plane < PIPE_MAX_CLIP_PLANES; plane++) {
1834 if (!(c->key->ucp_enables & (1 << plane)))
1835 continue;
1836
1837 /* Pick the next outputs[] that hasn't been written to, since
1838 * there are no other program writes left to be processed at
1839 * this point. If something had been declared but not written
1840 * (like a w component), we'll just smash over the top of it.
1841 */
1842 uint32_t output_index = c->num_outputs++;
1843 add_output(c, output_index,
1844 TGSI_SEMANTIC_CLIPDIST,
1845 plane,
1846 TGSI_SWIZZLE_X);
1847
1848
1849 struct qreg dist = qir_uniform_f(c, 0.0);
1850 for (int i = 0; i < 4; i++) {
1851 struct qreg pos_chan = c->outputs[cv + i];
1852 struct qreg ucp =
1853 add_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1854 plane * 4 + i);
1855 dist = qir_FADD(c, dist, qir_FMUL(c, pos_chan, ucp));
1856 }
1857
1858 c->outputs[output_index] = dist;
1859 }
1860 }
1861
1862 static void
1863 emit_vert_end(struct vc4_compile *c,
1864 struct vc4_varying_semantic *fs_inputs,
1865 uint32_t num_fs_inputs)
1866 {
1867 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1868
1869 emit_stub_vpm_read(c);
1870 emit_ucp_clipdistance(c);
1871
1872 emit_scaled_viewport_write(c, rcp_w);
1873 emit_zs_write(c, rcp_w);
1874 emit_rcp_wc_write(c, rcp_w);
1875 if (c->vs_key->per_vertex_point_size)
1876 emit_point_size_write(c);
1877
1878 for (int i = 0; i < num_fs_inputs; i++) {
1879 struct vc4_varying_semantic *input = &fs_inputs[i];
1880 int j;
1881
1882 for (j = 0; j < c->num_outputs; j++) {
1883 struct vc4_varying_semantic *output =
1884 &c->output_semantics[j];
1885
1886 if (input->semantic == output->semantic &&
1887 input->index == output->index &&
1888 input->swizzle == output->swizzle) {
1889 qir_VPM_WRITE(c, c->outputs[j]);
1890 break;
1891 }
1892 }
1893 /* Emit padding if we didn't find a declared VS output for
1894 * this FS input.
1895 */
1896 if (j == c->num_outputs)
1897 qir_VPM_WRITE(c, qir_uniform_f(c, 0.0));
1898 }
1899 }
1900
1901 static void
1902 emit_coord_end(struct vc4_compile *c)
1903 {
1904 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1905
1906 emit_stub_vpm_read(c);
1907
1908 for (int i = 0; i < 4; i++)
1909 qir_VPM_WRITE(c, c->outputs[c->output_position_index + i]);
1910
1911 emit_scaled_viewport_write(c, rcp_w);
1912 emit_zs_write(c, rcp_w);
1913 emit_rcp_wc_write(c, rcp_w);
1914 if (c->vs_key->per_vertex_point_size)
1915 emit_point_size_write(c);
1916 }
1917
1918 static struct vc4_compile *
1919 vc4_shader_tgsi_to_qir(struct vc4_context *vc4, enum qstage stage,
1920 struct vc4_key *key)
1921 {
1922 struct vc4_compile *c = qir_compile_init();
1923 int ret;
1924
1925 c->stage = stage;
1926 for (int i = 0; i < 4; i++)
1927 c->addr[i] = qir_uniform_f(c, 0.0);
1928
1929 c->shader_state = &key->shader_state->base;
1930 c->program_id = key->shader_state->program_id;
1931 c->variant_id = key->shader_state->compiled_variant_count++;
1932
1933 c->key = key;
1934 switch (stage) {
1935 case QSTAGE_FRAG:
1936 c->fs_key = (struct vc4_fs_key *)key;
1937 if (c->fs_key->is_points) {
1938 c->point_x = emit_fragment_varying(c, ~0, ~0, 0);
1939 c->point_y = emit_fragment_varying(c, ~0, ~0, 0);
1940 } else if (c->fs_key->is_lines) {
1941 c->line_x = emit_fragment_varying(c, ~0, ~0, 0);
1942 }
1943 break;
1944 case QSTAGE_VERT:
1945 c->vs_key = (struct vc4_vs_key *)key;
1946 break;
1947 case QSTAGE_COORD:
1948 c->vs_key = (struct vc4_vs_key *)key;
1949 break;
1950 }
1951
1952 const struct tgsi_token *tokens = key->shader_state->base.tokens;
1953 if (c->fs_key && c->fs_key->light_twoside) {
1954 if (!key->shader_state->twoside_tokens) {
1955 const struct tgsi_lowering_config lowering_config = {
1956 .color_two_side = true,
1957 };
1958 struct tgsi_shader_info info;
1959 key->shader_state->twoside_tokens =
1960 tgsi_transform_lowering(&lowering_config,
1961 key->shader_state->base.tokens,
1962 &info);
1963
1964 /* If no transformation occurred, then NULL is
1965 * returned and we just use our original tokens.
1966 */
1967 if (!key->shader_state->twoside_tokens) {
1968 key->shader_state->twoside_tokens =
1969 key->shader_state->base.tokens;
1970 }
1971 }
1972 tokens = key->shader_state->twoside_tokens;
1973 }
1974
1975 ret = tgsi_parse_init(&c->parser, tokens);
1976 assert(ret == TGSI_PARSE_OK);
1977
1978 if (vc4_debug & VC4_DEBUG_TGSI) {
1979 fprintf(stderr, "%s prog %d/%d TGSI:\n",
1980 qir_get_stage_name(c->stage),
1981 c->program_id, c->variant_id);
1982 tgsi_dump(tokens, 0);
1983 }
1984
1985 while (!tgsi_parse_end_of_tokens(&c->parser)) {
1986 tgsi_parse_token(&c->parser);
1987
1988 switch (c->parser.FullToken.Token.Type) {
1989 case TGSI_TOKEN_TYPE_DECLARATION:
1990 emit_tgsi_declaration(c,
1991 &c->parser.FullToken.FullDeclaration);
1992 break;
1993
1994 case TGSI_TOKEN_TYPE_INSTRUCTION:
1995 emit_tgsi_instruction(c,
1996 &c->parser.FullToken.FullInstruction);
1997 break;
1998
1999 case TGSI_TOKEN_TYPE_IMMEDIATE:
2000 parse_tgsi_immediate(c,
2001 &c->parser.FullToken.FullImmediate);
2002 break;
2003 }
2004 }
2005
2006 switch (stage) {
2007 case QSTAGE_FRAG:
2008 emit_frag_end(c);
2009 break;
2010 case QSTAGE_VERT:
2011 emit_vert_end(c,
2012 vc4->prog.fs->input_semantics,
2013 vc4->prog.fs->num_inputs);
2014 break;
2015 case QSTAGE_COORD:
2016 emit_coord_end(c);
2017 break;
2018 }
2019
2020 tgsi_parse_free(&c->parser);
2021
2022 qir_optimize(c);
2023
2024 if (vc4_debug & VC4_DEBUG_QIR) {
2025 fprintf(stderr, "%s prog %d/%d QIR:\n",
2026 qir_get_stage_name(c->stage),
2027 c->program_id, c->variant_id);
2028 qir_dump(c);
2029 }
2030 qir_reorder_uniforms(c);
2031 vc4_generate_code(vc4, c);
2032
2033 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2034 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d instructions\n",
2035 qir_get_stage_name(c->stage),
2036 c->program_id, c->variant_id,
2037 c->qpu_inst_count);
2038 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d uniforms\n",
2039 qir_get_stage_name(c->stage),
2040 c->program_id, c->variant_id,
2041 c->num_uniforms);
2042 }
2043
2044 return c;
2045 }
2046
2047 static void *
2048 vc4_shader_state_create(struct pipe_context *pctx,
2049 const struct pipe_shader_state *cso)
2050 {
2051 struct vc4_context *vc4 = vc4_context(pctx);
2052 struct vc4_uncompiled_shader *so = CALLOC_STRUCT(vc4_uncompiled_shader);
2053 if (!so)
2054 return NULL;
2055
2056 const struct tgsi_lowering_config lowering_config = {
2057 .lower_DST = true,
2058 .lower_XPD = true,
2059 .lower_SCS = true,
2060 .lower_POW = true,
2061 .lower_LIT = true,
2062 .lower_EXP = true,
2063 .lower_LOG = true,
2064 .lower_DP4 = true,
2065 .lower_DP3 = true,
2066 .lower_DPH = true,
2067 .lower_DP2 = true,
2068 .lower_DP2A = true,
2069 };
2070
2071 struct tgsi_shader_info info;
2072 so->base.tokens = tgsi_transform_lowering(&lowering_config, cso->tokens, &info);
2073 if (!so->base.tokens)
2074 so->base.tokens = tgsi_dup_tokens(cso->tokens);
2075 so->program_id = vc4->next_uncompiled_program_id++;
2076
2077 return so;
2078 }
2079
2080 static void
2081 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
2082 struct vc4_compile *c)
2083 {
2084 int count = c->num_uniforms;
2085 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
2086
2087 uinfo->count = count;
2088 uinfo->data = ralloc_array(shader, uint32_t, count);
2089 memcpy(uinfo->data, c->uniform_data,
2090 count * sizeof(*uinfo->data));
2091 uinfo->contents = ralloc_array(shader, enum quniform_contents, count);
2092 memcpy(uinfo->contents, c->uniform_contents,
2093 count * sizeof(*uinfo->contents));
2094 uinfo->num_texture_samples = c->num_texture_samples;
2095 }
2096
2097 static struct vc4_compiled_shader *
2098 vc4_get_compiled_shader(struct vc4_context *vc4, enum qstage stage,
2099 struct vc4_key *key)
2100 {
2101 struct util_hash_table *ht;
2102 uint32_t key_size;
2103 if (stage == QSTAGE_FRAG) {
2104 ht = vc4->fs_cache;
2105 key_size = sizeof(struct vc4_fs_key);
2106 } else {
2107 ht = vc4->vs_cache;
2108 key_size = sizeof(struct vc4_vs_key);
2109 }
2110
2111 struct vc4_compiled_shader *shader;
2112 shader = util_hash_table_get(ht, key);
2113 if (shader)
2114 return shader;
2115
2116 struct vc4_compile *c = vc4_shader_tgsi_to_qir(vc4, stage, key);
2117 shader = rzalloc(NULL, struct vc4_compiled_shader);
2118
2119 shader->program_id = vc4->next_compiled_program_id++;
2120 if (stage == QSTAGE_FRAG) {
2121 bool input_live[c->num_input_semantics];
2122 struct simple_node *node;
2123
2124 memset(input_live, 0, sizeof(input_live));
2125 foreach(node, &c->instructions) {
2126 struct qinst *inst = (struct qinst *)node;
2127 for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) {
2128 if (inst->src[i].file == QFILE_VARY)
2129 input_live[inst->src[i].index] = true;
2130 }
2131 }
2132
2133 shader->input_semantics = ralloc_array(shader,
2134 struct vc4_varying_semantic,
2135 c->num_input_semantics);
2136
2137 for (int i = 0; i < c->num_input_semantics; i++) {
2138 struct vc4_varying_semantic *sem = &c->input_semantics[i];
2139
2140 if (!input_live[i])
2141 continue;
2142
2143 /* Skip non-VS-output inputs. */
2144 if (sem->semantic == (uint8_t)~0)
2145 continue;
2146
2147 if (sem->semantic == TGSI_SEMANTIC_COLOR)
2148 shader->color_inputs |= (1 << shader->num_inputs);
2149 shader->input_semantics[shader->num_inputs] = *sem;
2150 shader->num_inputs++;
2151 }
2152 } else {
2153 shader->num_inputs = c->num_inputs;
2154 }
2155
2156 copy_uniform_state_to_shader(shader, c);
2157 shader->bo = vc4_bo_alloc_mem(vc4->screen, c->qpu_insts,
2158 c->qpu_inst_count * sizeof(uint64_t),
2159 "code");
2160
2161 /* Copy the compiler UBO range state to the compiled shader, dropping
2162 * out arrays that were never referenced by an indirect load.
2163 *
2164 * (Note that QIR dead code elimination of an array access still
2165 * leaves that array alive, though)
2166 */
2167 if (c->num_ubo_ranges) {
2168 shader->num_ubo_ranges = c->num_ubo_ranges;
2169 shader->ubo_ranges = ralloc_array(shader, struct vc4_ubo_range,
2170 c->num_ubo_ranges);
2171 uint32_t j = 0;
2172 for (int i = 0; i < c->ubo_ranges_array_size; i++) {
2173 struct vc4_compiler_ubo_range *range =
2174 &c->ubo_ranges[i];
2175 if (!range->used)
2176 continue;
2177
2178 shader->ubo_ranges[j].dst_offset = range->dst_offset;
2179 shader->ubo_ranges[j].src_offset = range->src_offset;
2180 shader->ubo_ranges[j].size = range->size;
2181 shader->ubo_size += c->ubo_ranges[i].size;
2182 j++;
2183 }
2184 }
2185
2186 qir_compile_destroy(c);
2187
2188 struct vc4_key *dup_key;
2189 dup_key = malloc(key_size);
2190 memcpy(dup_key, key, key_size);
2191 util_hash_table_set(ht, dup_key, shader);
2192
2193 return shader;
2194 }
2195
2196 static void
2197 vc4_setup_shared_key(struct vc4_context *vc4, struct vc4_key *key,
2198 struct vc4_texture_stateobj *texstate)
2199 {
2200 for (int i = 0; i < texstate->num_textures; i++) {
2201 struct pipe_sampler_view *sampler = texstate->textures[i];
2202 struct pipe_sampler_state *sampler_state =
2203 texstate->samplers[i];
2204
2205 if (sampler) {
2206 key->tex[i].format = sampler->format;
2207 key->tex[i].swizzle[0] = sampler->swizzle_r;
2208 key->tex[i].swizzle[1] = sampler->swizzle_g;
2209 key->tex[i].swizzle[2] = sampler->swizzle_b;
2210 key->tex[i].swizzle[3] = sampler->swizzle_a;
2211 key->tex[i].compare_mode = sampler_state->compare_mode;
2212 key->tex[i].compare_func = sampler_state->compare_func;
2213 key->tex[i].wrap_s = sampler_state->wrap_s;
2214 key->tex[i].wrap_t = sampler_state->wrap_t;
2215 }
2216 }
2217
2218 key->ucp_enables = vc4->rasterizer->base.clip_plane_enable;
2219 }
2220
2221 static void
2222 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
2223 {
2224 struct vc4_fs_key local_key;
2225 struct vc4_fs_key *key = &local_key;
2226
2227 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2228 VC4_DIRTY_BLEND |
2229 VC4_DIRTY_FRAMEBUFFER |
2230 VC4_DIRTY_ZSA |
2231 VC4_DIRTY_RASTERIZER |
2232 VC4_DIRTY_FRAGTEX |
2233 VC4_DIRTY_TEXSTATE |
2234 VC4_DIRTY_PROG))) {
2235 return;
2236 }
2237
2238 memset(key, 0, sizeof(*key));
2239 vc4_setup_shared_key(vc4, &key->base, &vc4->fragtex);
2240 key->base.shader_state = vc4->prog.bind_fs;
2241 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
2242 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
2243 prim_mode <= PIPE_PRIM_LINE_STRIP);
2244 key->blend = vc4->blend->rt[0];
2245
2246 if (vc4->framebuffer.cbufs[0])
2247 key->color_format = vc4->framebuffer.cbufs[0]->format;
2248
2249 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
2250 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
2251 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
2252 key->depth_enabled = (vc4->zsa->base.depth.enabled ||
2253 key->stencil_enabled);
2254 if (vc4->zsa->base.alpha.enabled) {
2255 key->alpha_test = true;
2256 key->alpha_test_func = vc4->zsa->base.alpha.func;
2257 }
2258
2259 if (key->is_points) {
2260 key->point_sprite_mask =
2261 vc4->rasterizer->base.sprite_coord_enable;
2262 key->point_coord_upper_left =
2263 (vc4->rasterizer->base.sprite_coord_mode ==
2264 PIPE_SPRITE_COORD_UPPER_LEFT);
2265 }
2266
2267 key->light_twoside = vc4->rasterizer->base.light_twoside;
2268
2269 struct vc4_compiled_shader *old_fs = vc4->prog.fs;
2270 vc4->prog.fs = vc4_get_compiled_shader(vc4, QSTAGE_FRAG, &key->base);
2271 if (vc4->prog.fs == old_fs)
2272 return;
2273
2274 if (vc4->rasterizer->base.flatshade &&
2275 old_fs && vc4->prog.fs->color_inputs != old_fs->color_inputs) {
2276 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
2277 }
2278 }
2279
2280 static void
2281 vc4_update_compiled_vs(struct vc4_context *vc4, uint8_t prim_mode)
2282 {
2283 struct vc4_vs_key local_key;
2284 struct vc4_vs_key *key = &local_key;
2285
2286 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2287 VC4_DIRTY_RASTERIZER |
2288 VC4_DIRTY_VERTTEX |
2289 VC4_DIRTY_TEXSTATE |
2290 VC4_DIRTY_VTXSTATE |
2291 VC4_DIRTY_PROG))) {
2292 return;
2293 }
2294
2295 memset(key, 0, sizeof(*key));
2296 vc4_setup_shared_key(vc4, &key->base, &vc4->verttex);
2297 key->base.shader_state = vc4->prog.bind_vs;
2298 key->compiled_fs_id = vc4->prog.fs->program_id;
2299
2300 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
2301 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
2302
2303 key->per_vertex_point_size =
2304 (prim_mode == PIPE_PRIM_POINTS &&
2305 vc4->rasterizer->base.point_size_per_vertex);
2306
2307 vc4->prog.vs = vc4_get_compiled_shader(vc4, QSTAGE_VERT, &key->base);
2308 key->is_coord = true;
2309 vc4->prog.cs = vc4_get_compiled_shader(vc4, QSTAGE_COORD, &key->base);
2310 }
2311
2312 void
2313 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
2314 {
2315 vc4_update_compiled_fs(vc4, prim_mode);
2316 vc4_update_compiled_vs(vc4, prim_mode);
2317 }
2318
2319 static unsigned
2320 fs_cache_hash(void *key)
2321 {
2322 return _mesa_hash_data(key, sizeof(struct vc4_fs_key));
2323 }
2324
2325 static unsigned
2326 vs_cache_hash(void *key)
2327 {
2328 return _mesa_hash_data(key, sizeof(struct vc4_vs_key));
2329 }
2330
2331 static int
2332 fs_cache_compare(void *key1, void *key2)
2333 {
2334 return memcmp(key1, key2, sizeof(struct vc4_fs_key));
2335 }
2336
2337 static int
2338 vs_cache_compare(void *key1, void *key2)
2339 {
2340 return memcmp(key1, key2, sizeof(struct vc4_vs_key));
2341 }
2342
2343 struct delete_state {
2344 struct vc4_context *vc4;
2345 struct vc4_uncompiled_shader *shader_state;
2346 };
2347
2348 static enum pipe_error
2349 fs_delete_from_cache(void *in_key, void *in_value, void *data)
2350 {
2351 struct delete_state *del = data;
2352 struct vc4_fs_key *key = in_key;
2353 struct vc4_compiled_shader *shader = in_value;
2354
2355 if (key->base.shader_state == data) {
2356 util_hash_table_remove(del->vc4->fs_cache, key);
2357 vc4_bo_unreference(&shader->bo);
2358 ralloc_free(shader);
2359 }
2360
2361 return 0;
2362 }
2363
2364 static enum pipe_error
2365 vs_delete_from_cache(void *in_key, void *in_value, void *data)
2366 {
2367 struct delete_state *del = data;
2368 struct vc4_vs_key *key = in_key;
2369 struct vc4_compiled_shader *shader = in_value;
2370
2371 if (key->base.shader_state == data) {
2372 util_hash_table_remove(del->vc4->vs_cache, key);
2373 vc4_bo_unreference(&shader->bo);
2374 ralloc_free(shader);
2375 }
2376
2377 return 0;
2378 }
2379
2380 static void
2381 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
2382 {
2383 struct vc4_context *vc4 = vc4_context(pctx);
2384 struct vc4_uncompiled_shader *so = hwcso;
2385 struct delete_state del;
2386
2387 del.vc4 = vc4;
2388 del.shader_state = so;
2389 util_hash_table_foreach(vc4->fs_cache, fs_delete_from_cache, &del);
2390 util_hash_table_foreach(vc4->vs_cache, vs_delete_from_cache, &del);
2391
2392 if (so->twoside_tokens != so->base.tokens)
2393 free((void *)so->twoside_tokens);
2394 free((void *)so->base.tokens);
2395 free(so);
2396 }
2397
2398 static uint32_t translate_wrap(uint32_t p_wrap, bool using_nearest)
2399 {
2400 switch (p_wrap) {
2401 case PIPE_TEX_WRAP_REPEAT:
2402 return 0;
2403 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
2404 return 1;
2405 case PIPE_TEX_WRAP_MIRROR_REPEAT:
2406 return 2;
2407 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
2408 return 3;
2409 case PIPE_TEX_WRAP_CLAMP:
2410 return (using_nearest ? 1 : 3);
2411 default:
2412 fprintf(stderr, "Unknown wrap mode %d\n", p_wrap);
2413 assert(!"not reached");
2414 return 0;
2415 }
2416 }
2417
2418 static void
2419 write_texture_p0(struct vc4_context *vc4,
2420 struct vc4_texture_stateobj *texstate,
2421 uint32_t unit)
2422 {
2423 struct pipe_sampler_view *texture = texstate->textures[unit];
2424 struct vc4_resource *rsc = vc4_resource(texture->texture);
2425
2426 cl_reloc(vc4, &vc4->uniforms, rsc->bo,
2427 VC4_SET_FIELD(rsc->slices[0].offset >> 12, VC4_TEX_P0_OFFSET) |
2428 VC4_SET_FIELD(texture->u.tex.last_level -
2429 texture->u.tex.first_level, VC4_TEX_P0_MIPLVLS) |
2430 VC4_SET_FIELD(texture->target == PIPE_TEXTURE_CUBE,
2431 VC4_TEX_P0_CMMODE) |
2432 VC4_SET_FIELD(rsc->vc4_format & 7, VC4_TEX_P0_TYPE));
2433 }
2434
2435 static void
2436 write_texture_p1(struct vc4_context *vc4,
2437 struct vc4_texture_stateobj *texstate,
2438 uint32_t unit)
2439 {
2440 struct pipe_sampler_view *texture = texstate->textures[unit];
2441 struct vc4_resource *rsc = vc4_resource(texture->texture);
2442 struct pipe_sampler_state *sampler = texstate->samplers[unit];
2443 static const uint8_t minfilter_map[6] = {
2444 VC4_TEX_P1_MINFILT_NEAR_MIP_NEAR,
2445 VC4_TEX_P1_MINFILT_LIN_MIP_NEAR,
2446 VC4_TEX_P1_MINFILT_NEAR_MIP_LIN,
2447 VC4_TEX_P1_MINFILT_LIN_MIP_LIN,
2448 VC4_TEX_P1_MINFILT_NEAREST,
2449 VC4_TEX_P1_MINFILT_LINEAR,
2450 };
2451 static const uint32_t magfilter_map[] = {
2452 [PIPE_TEX_FILTER_NEAREST] = VC4_TEX_P1_MAGFILT_NEAREST,
2453 [PIPE_TEX_FILTER_LINEAR] = VC4_TEX_P1_MAGFILT_LINEAR,
2454 };
2455
2456 bool either_nearest =
2457 (sampler->mag_img_filter == PIPE_TEX_MIPFILTER_NEAREST ||
2458 sampler->min_img_filter == PIPE_TEX_MIPFILTER_NEAREST);
2459
2460 cl_u32(&vc4->uniforms,
2461 VC4_SET_FIELD(rsc->vc4_format >> 4, VC4_TEX_P1_TYPE4) |
2462 VC4_SET_FIELD(texture->texture->height0 & 2047,
2463 VC4_TEX_P1_HEIGHT) |
2464 VC4_SET_FIELD(texture->texture->width0 & 2047,
2465 VC4_TEX_P1_WIDTH) |
2466 VC4_SET_FIELD(magfilter_map[sampler->mag_img_filter],
2467 VC4_TEX_P1_MAGFILT) |
2468 VC4_SET_FIELD(minfilter_map[sampler->min_mip_filter * 2 +
2469 sampler->min_img_filter],
2470 VC4_TEX_P1_MINFILT) |
2471 VC4_SET_FIELD(translate_wrap(sampler->wrap_s, either_nearest),
2472 VC4_TEX_P1_WRAP_S) |
2473 VC4_SET_FIELD(translate_wrap(sampler->wrap_t, either_nearest),
2474 VC4_TEX_P1_WRAP_T));
2475 }
2476
2477 static void
2478 write_texture_p2(struct vc4_context *vc4,
2479 struct vc4_texture_stateobj *texstate,
2480 uint32_t data)
2481 {
2482 uint32_t unit = data & 0xffff;
2483 struct pipe_sampler_view *texture = texstate->textures[unit];
2484 struct vc4_resource *rsc = vc4_resource(texture->texture);
2485
2486 cl_u32(&vc4->uniforms,
2487 VC4_SET_FIELD(VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE,
2488 VC4_TEX_P2_PTYPE) |
2489 VC4_SET_FIELD(rsc->cube_map_stride >> 12, VC4_TEX_P2_CMST) |
2490 VC4_SET_FIELD((data >> 16) & 1, VC4_TEX_P2_BSLOD));
2491 }
2492
2493
2494 #define SWIZ(x,y,z,w) { \
2495 UTIL_FORMAT_SWIZZLE_##x, \
2496 UTIL_FORMAT_SWIZZLE_##y, \
2497 UTIL_FORMAT_SWIZZLE_##z, \
2498 UTIL_FORMAT_SWIZZLE_##w \
2499 }
2500
2501 static void
2502 write_texture_border_color(struct vc4_context *vc4,
2503 struct vc4_texture_stateobj *texstate,
2504 uint32_t unit)
2505 {
2506 struct pipe_sampler_state *sampler = texstate->samplers[unit];
2507 struct pipe_sampler_view *texture = texstate->textures[unit];
2508 struct vc4_resource *rsc = vc4_resource(texture->texture);
2509 union util_color uc;
2510
2511 const struct util_format_description *tex_format_desc =
2512 util_format_description(texture->format);
2513
2514 float border_color[4];
2515 for (int i = 0; i < 4; i++)
2516 border_color[i] = sampler->border_color.f[i];
2517 if (util_format_is_srgb(texture->format)) {
2518 for (int i = 0; i < 3; i++)
2519 border_color[i] =
2520 util_format_linear_to_srgb_float(border_color[i]);
2521 }
2522
2523 /* Turn the border color into the layout of channels that it would
2524 * have when stored as texture contents.
2525 */
2526 float storage_color[4];
2527 util_format_unswizzle_4f(storage_color,
2528 border_color,
2529 tex_format_desc->swizzle);
2530
2531 /* Now, pack so that when the vc4_format-sampled texture contents are
2532 * replaced with our border color, the vc4_get_format_swizzle()
2533 * swizzling will get the right channels.
2534 */
2535 if (util_format_is_depth_or_stencil(texture->format)) {
2536 uc.ui[0] = util_pack_z(PIPE_FORMAT_Z24X8_UNORM,
2537 sampler->border_color.f[0]) << 8;
2538 } else {
2539 switch (rsc->vc4_format) {
2540 default:
2541 case VC4_TEXTURE_TYPE_RGBA8888:
2542 util_pack_color(storage_color,
2543 PIPE_FORMAT_R8G8B8A8_UNORM, &uc);
2544 break;
2545 case VC4_TEXTURE_TYPE_RGBA4444:
2546 util_pack_color(storage_color,
2547 PIPE_FORMAT_A8B8G8R8_UNORM, &uc);
2548 break;
2549 case VC4_TEXTURE_TYPE_RGB565:
2550 util_pack_color(storage_color,
2551 PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
2552 break;
2553 case VC4_TEXTURE_TYPE_ALPHA:
2554 uc.ui[0] = float_to_ubyte(storage_color[0]) << 24;
2555 break;
2556 case VC4_TEXTURE_TYPE_LUMALPHA:
2557 uc.ui[0] = ((float_to_ubyte(storage_color[1]) << 24) |
2558 (float_to_ubyte(storage_color[0]) << 0));
2559 break;
2560 }
2561 }
2562
2563 cl_u32(&vc4->uniforms, uc.ui[0]);
2564 }
2565
2566 static uint32_t
2567 get_texrect_scale(struct vc4_texture_stateobj *texstate,
2568 enum quniform_contents contents,
2569 uint32_t data)
2570 {
2571 struct pipe_sampler_view *texture = texstate->textures[data];
2572 uint32_t dim;
2573
2574 if (contents == QUNIFORM_TEXRECT_SCALE_X)
2575 dim = texture->texture->width0;
2576 else
2577 dim = texture->texture->height0;
2578
2579 return fui(1.0f / dim);
2580 }
2581
2582 static struct vc4_bo *
2583 vc4_upload_ubo(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
2584 const uint32_t *gallium_uniforms)
2585 {
2586 if (!shader->ubo_size)
2587 return NULL;
2588
2589 struct vc4_bo *ubo = vc4_bo_alloc(vc4->screen, shader->ubo_size, "ubo");
2590 uint32_t *data = vc4_bo_map(ubo);
2591 for (uint32_t i = 0; i < shader->num_ubo_ranges; i++) {
2592 memcpy(data + shader->ubo_ranges[i].dst_offset,
2593 gallium_uniforms + shader->ubo_ranges[i].src_offset,
2594 shader->ubo_ranges[i].size);
2595 }
2596
2597 return ubo;
2598 }
2599
2600 void
2601 vc4_write_uniforms(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
2602 struct vc4_constbuf_stateobj *cb,
2603 struct vc4_texture_stateobj *texstate)
2604 {
2605 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
2606 const uint32_t *gallium_uniforms = cb->cb[0].user_buffer;
2607 struct vc4_bo *ubo = vc4_upload_ubo(vc4, shader, gallium_uniforms);
2608
2609 cl_start_shader_reloc(&vc4->uniforms, uinfo->num_texture_samples);
2610
2611 for (int i = 0; i < uinfo->count; i++) {
2612
2613 switch (uinfo->contents[i]) {
2614 case QUNIFORM_CONSTANT:
2615 cl_u32(&vc4->uniforms, uinfo->data[i]);
2616 break;
2617 case QUNIFORM_UNIFORM:
2618 cl_u32(&vc4->uniforms,
2619 gallium_uniforms[uinfo->data[i]]);
2620 break;
2621 case QUNIFORM_VIEWPORT_X_SCALE:
2622 cl_f(&vc4->uniforms, vc4->viewport.scale[0] * 16.0f);
2623 break;
2624 case QUNIFORM_VIEWPORT_Y_SCALE:
2625 cl_f(&vc4->uniforms, vc4->viewport.scale[1] * 16.0f);
2626 break;
2627
2628 case QUNIFORM_VIEWPORT_Z_OFFSET:
2629 cl_f(&vc4->uniforms, vc4->viewport.translate[2]);
2630 break;
2631 case QUNIFORM_VIEWPORT_Z_SCALE:
2632 cl_f(&vc4->uniforms, vc4->viewport.scale[2]);
2633 break;
2634
2635 case QUNIFORM_USER_CLIP_PLANE:
2636 cl_f(&vc4->uniforms,
2637 vc4->clip.ucp[uinfo->data[i] / 4][uinfo->data[i] % 4]);
2638 break;
2639
2640 case QUNIFORM_TEXTURE_CONFIG_P0:
2641 write_texture_p0(vc4, texstate, uinfo->data[i]);
2642 break;
2643
2644 case QUNIFORM_TEXTURE_CONFIG_P1:
2645 write_texture_p1(vc4, texstate, uinfo->data[i]);
2646 break;
2647
2648 case QUNIFORM_TEXTURE_CONFIG_P2:
2649 write_texture_p2(vc4, texstate, uinfo->data[i]);
2650 break;
2651
2652 case QUNIFORM_UBO_ADDR:
2653 cl_reloc(vc4, &vc4->uniforms, ubo, 0);
2654 break;
2655
2656 case QUNIFORM_TEXTURE_BORDER_COLOR:
2657 write_texture_border_color(vc4, texstate, uinfo->data[i]);
2658 break;
2659
2660 case QUNIFORM_TEXRECT_SCALE_X:
2661 case QUNIFORM_TEXRECT_SCALE_Y:
2662 cl_u32(&vc4->uniforms,
2663 get_texrect_scale(texstate,
2664 uinfo->contents[i],
2665 uinfo->data[i]));
2666 break;
2667
2668 case QUNIFORM_BLEND_CONST_COLOR:
2669 cl_f(&vc4->uniforms,
2670 vc4->blend_color.color[uinfo->data[i]]);
2671 break;
2672
2673 case QUNIFORM_STENCIL:
2674 cl_u32(&vc4->uniforms,
2675 vc4->zsa->stencil_uniforms[uinfo->data[i]] |
2676 (uinfo->data[i] <= 1 ?
2677 (vc4->stencil_ref.ref_value[uinfo->data[i]] << 8) :
2678 0));
2679 break;
2680
2681 case QUNIFORM_ALPHA_REF:
2682 cl_f(&vc4->uniforms, vc4->zsa->base.alpha.ref_value);
2683 break;
2684 }
2685 #if 0
2686 uint32_t written_val = *(uint32_t *)(vc4->uniforms.next - 4);
2687 fprintf(stderr, "%p: %d / 0x%08x (%f)\n",
2688 shader, i, written_val, uif(written_val));
2689 #endif
2690 }
2691 }
2692
2693 static void
2694 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
2695 {
2696 struct vc4_context *vc4 = vc4_context(pctx);
2697 vc4->prog.bind_fs = hwcso;
2698 vc4->prog.dirty |= VC4_SHADER_DIRTY_FP;
2699 vc4->dirty |= VC4_DIRTY_PROG;
2700 }
2701
2702 static void
2703 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
2704 {
2705 struct vc4_context *vc4 = vc4_context(pctx);
2706 vc4->prog.bind_vs = hwcso;
2707 vc4->prog.dirty |= VC4_SHADER_DIRTY_VP;
2708 vc4->dirty |= VC4_DIRTY_PROG;
2709 }
2710
2711 void
2712 vc4_program_init(struct pipe_context *pctx)
2713 {
2714 struct vc4_context *vc4 = vc4_context(pctx);
2715
2716 pctx->create_vs_state = vc4_shader_state_create;
2717 pctx->delete_vs_state = vc4_shader_state_delete;
2718
2719 pctx->create_fs_state = vc4_shader_state_create;
2720 pctx->delete_fs_state = vc4_shader_state_delete;
2721
2722 pctx->bind_fs_state = vc4_fp_state_bind;
2723 pctx->bind_vs_state = vc4_vp_state_bind;
2724
2725 vc4->fs_cache = util_hash_table_create(fs_cache_hash, fs_cache_compare);
2726 vc4->vs_cache = util_hash_table_create(vs_cache_hash, vs_cache_compare);
2727 }