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vc4: Avoid a null-deref if a sampler index isn't used.
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <stdio.h>
26 #include <inttypes.h>
27 #include "pipe/p_state.h"
28 #include "util/u_format.h"
29 #include "util/u_hash_table.h"
30 #include "util/u_hash.h"
31 #include "util/u_memory.h"
32 #include "tgsi/tgsi_parse.h"
33 #include "tgsi/tgsi_dump.h"
34
35 #include "vc4_context.h"
36 #include "vc4_qpu.h"
37 #include "vc4_qir.h"
38 #ifdef USE_VC4_SIMULATOR
39 #include "simpenrose/simpenrose.h"
40 #endif
41
42 struct tgsi_to_qir {
43 struct tgsi_parse_context parser;
44 struct qcompile *c;
45 struct qreg *temps;
46 struct qreg *inputs;
47 struct qreg *outputs;
48 struct qreg *uniforms;
49 struct qreg *consts;
50 struct qreg line_x, point_x, point_y;
51
52 uint32_t num_consts;
53
54 struct pipe_shader_state *shader_state;
55 struct vc4_key *key;
56 struct vc4_fs_key *fs_key;
57 struct vc4_vs_key *vs_key;
58
59 uint32_t *uniform_data;
60 enum quniform_contents *uniform_contents;
61 uint32_t num_uniforms;
62 uint32_t num_outputs;
63 uint32_t num_texture_samples;
64 };
65
66 struct vc4_key {
67 struct pipe_shader_state *shader_state;
68 enum pipe_format tex_format[VC4_MAX_TEXTURE_SAMPLERS];
69 };
70
71 struct vc4_fs_key {
72 struct vc4_key base;
73 enum pipe_format color_format;
74 bool depth_enabled;
75 bool is_points;
76 bool is_lines;
77
78 struct pipe_rt_blend_state blend;
79 };
80
81 struct vc4_vs_key {
82 struct vc4_key base;
83 enum pipe_format attr_formats[8];
84 };
85
86 static struct qreg
87 add_uniform(struct tgsi_to_qir *trans,
88 enum quniform_contents contents,
89 uint32_t data)
90 {
91 uint32_t uniform = trans->num_uniforms++;
92 struct qreg u = { QFILE_UNIF, uniform };
93
94 trans->uniform_contents[uniform] = contents;
95 trans->uniform_data[uniform] = data;
96
97 return u;
98 }
99
100 static struct qreg
101 get_temp_for_uniform(struct tgsi_to_qir *trans, enum quniform_contents contents,
102 uint32_t data)
103 {
104 struct qcompile *c = trans->c;
105
106 for (int i = 0; i < trans->num_uniforms; i++) {
107 if (trans->uniform_contents[i] == contents &&
108 trans->uniform_data[i] == data)
109 return trans->uniforms[i];
110 }
111
112 struct qreg u = add_uniform(trans, contents, data);
113 struct qreg t = qir_MOV(c, u);
114
115 trans->uniforms[u.index] = t;
116 return t;
117 }
118
119 static struct qreg
120 qir_uniform_ui(struct tgsi_to_qir *trans, uint32_t ui)
121 {
122 return get_temp_for_uniform(trans, QUNIFORM_CONSTANT, ui);
123 }
124
125 static struct qreg
126 qir_uniform_f(struct tgsi_to_qir *trans, float f)
127 {
128 return qir_uniform_ui(trans, fui(f));
129 }
130
131 static struct qreg
132 get_src(struct tgsi_to_qir *trans, struct tgsi_src_register *src, int i)
133 {
134 struct qcompile *c = trans->c;
135 struct qreg r = c->undef;
136
137 uint32_t s = i;
138 switch (i) {
139 case TGSI_SWIZZLE_X:
140 s = src->SwizzleX;
141 break;
142 case TGSI_SWIZZLE_Y:
143 s = src->SwizzleY;
144 break;
145 case TGSI_SWIZZLE_Z:
146 s = src->SwizzleZ;
147 break;
148 case TGSI_SWIZZLE_W:
149 s = src->SwizzleW;
150 break;
151 default:
152 abort();
153 }
154
155 assert(!src->Indirect);
156
157 switch (src->File) {
158 case TGSI_FILE_NULL:
159 return r;
160 case TGSI_FILE_TEMPORARY:
161 r = trans->temps[src->Index * 4 + s];
162 break;
163 case TGSI_FILE_IMMEDIATE:
164 r = trans->consts[src->Index * 4 + s];
165 break;
166 case TGSI_FILE_CONSTANT:
167 r = get_temp_for_uniform(trans, QUNIFORM_UNIFORM,
168 src->Index * 4 + s);
169 break;
170 case TGSI_FILE_INPUT:
171 r = trans->inputs[src->Index * 4 + s];
172 break;
173 case TGSI_FILE_SAMPLER:
174 case TGSI_FILE_SAMPLER_VIEW:
175 r = c->undef;
176 break;
177 default:
178 fprintf(stderr, "unknown src file %d\n", src->File);
179 abort();
180 }
181
182 if (src->Absolute)
183 r = qir_FMAXABS(c, r, r);
184
185 if (src->Negate)
186 r = qir_FSUB(c, qir_uniform_f(trans, 0), r);
187
188 return r;
189 };
190
191
192 static void
193 update_dst(struct tgsi_to_qir *trans, struct tgsi_full_instruction *tgsi_inst,
194 int i, struct qreg val)
195 {
196 struct tgsi_dst_register *tgsi_dst = &tgsi_inst->Dst[0].Register;
197
198 assert(!tgsi_dst->Indirect);
199
200 switch (tgsi_dst->File) {
201 case TGSI_FILE_TEMPORARY:
202 trans->temps[tgsi_dst->Index * 4 + i] = val;
203 break;
204 case TGSI_FILE_OUTPUT:
205 trans->outputs[tgsi_dst->Index * 4 + i] = val;
206 trans->num_outputs = MAX2(trans->num_outputs,
207 tgsi_dst->Index * 4 + i + 1);
208 break;
209 default:
210 fprintf(stderr, "unknown dst file %d\n", tgsi_dst->File);
211 abort();
212 }
213 };
214
215 static struct qreg
216 get_swizzled_channel(struct tgsi_to_qir *trans,
217 struct qreg *srcs, int swiz)
218 {
219 switch (swiz) {
220 default:
221 case UTIL_FORMAT_SWIZZLE_NONE:
222 fprintf(stderr, "warning: unknown swizzle\n");
223 /* FALLTHROUGH */
224 case UTIL_FORMAT_SWIZZLE_0:
225 return qir_uniform_f(trans, 0.0);
226 case UTIL_FORMAT_SWIZZLE_1:
227 return qir_uniform_f(trans, 1.0);
228 case UTIL_FORMAT_SWIZZLE_X:
229 case UTIL_FORMAT_SWIZZLE_Y:
230 case UTIL_FORMAT_SWIZZLE_Z:
231 case UTIL_FORMAT_SWIZZLE_W:
232 return srcs[swiz];
233 }
234 }
235
236 static struct qreg
237 tgsi_to_qir_alu(struct tgsi_to_qir *trans,
238 struct tgsi_full_instruction *tgsi_inst,
239 enum qop op, struct qreg *src, int i)
240 {
241 struct qcompile *c = trans->c;
242 struct qreg dst = qir_get_temp(c);
243 qir_emit(c, qir_inst4(op, dst,
244 src[0 * 4 + i],
245 src[1 * 4 + i],
246 src[2 * 4 + i],
247 c->undef));
248 return dst;
249 }
250
251 static struct qreg
252 tgsi_to_qir_mad(struct tgsi_to_qir *trans,
253 struct tgsi_full_instruction *tgsi_inst,
254 enum qop op, struct qreg *src, int i)
255 {
256 struct qcompile *c = trans->c;
257 return qir_FADD(c,
258 qir_FMUL(c,
259 src[0 * 4 + i],
260 src[1 * 4 + i]),
261 src[2 * 4 + i]);
262 }
263
264 static struct qreg
265 tgsi_to_qir_lit(struct tgsi_to_qir *trans,
266 struct tgsi_full_instruction *tgsi_inst,
267 enum qop op, struct qreg *src, int i)
268 {
269 struct qcompile *c = trans->c;
270 struct qreg x = src[0 * 4 + 0];
271 struct qreg y = src[0 * 4 + 1];
272 struct qreg w = src[0 * 4 + 3];
273
274 switch (i) {
275 case 0:
276 case 3:
277 return qir_uniform_f(trans, 1.0);
278 case 1:
279 return qir_FMAX(c, src[0 * 4 + 0], qir_uniform_f(trans, 0.0));
280 case 2: {
281 struct qreg zero = qir_uniform_f(trans, 0.0);
282
283 /* XXX: Clamp w to -128..128 */
284 return qir_CMP(c,
285 x,
286 zero,
287 qir_EXP2(c, qir_FMUL(c,
288 w,
289 qir_LOG2(c,
290 qir_FMAX(c,
291 y,
292 zero)))));
293 }
294 default:
295 assert(!"not reached");
296 return c->undef;
297 }
298 }
299
300 static struct qreg
301 tgsi_to_qir_lrp(struct tgsi_to_qir *trans,
302 struct tgsi_full_instruction *tgsi_inst,
303 enum qop op, struct qreg *src, int i)
304 {
305 struct qcompile *c = trans->c;
306 struct qreg src0 = src[0 * 4 + i];
307 struct qreg src1 = src[1 * 4 + i];
308 struct qreg src2 = src[2 * 4 + i];
309
310 /* LRP is:
311 * src0 * src1 + (1 - src0) * src2.
312 * -> src0 * src1 + src2 - src0 * src2
313 * -> src2 + src0 * (src1 - src2)
314 */
315 return qir_FADD(c, src2, qir_FMUL(c, src0, qir_FSUB(c, src1, src2)));
316
317 }
318
319 static void
320 tgsi_to_qir_tex(struct tgsi_to_qir *trans,
321 struct tgsi_full_instruction *tgsi_inst,
322 enum qop op, struct qreg *src)
323 {
324 struct qcompile *c = trans->c;
325
326 assert(!tgsi_inst->Instruction.Saturate);
327
328 struct qreg s = src[0 * 4 + 0];
329 struct qreg t = src[0 * 4 + 1];
330 uint32_t sampler = 0; /* XXX */
331
332 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
333 struct qreg proj = qir_RCP(c, src[0 * 4 + 3]);
334 s = qir_FMUL(c, s, proj);
335 t = qir_FMUL(c, t, proj);
336 }
337
338 /* There is no native support for GL texture rectangle coordinates, so
339 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
340 * 1]).
341 */
342 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_RECT) {
343 s = qir_FMUL(c, s,
344 get_temp_for_uniform(trans,
345 QUNIFORM_TEXRECT_SCALE_X,
346 sampler));
347 t = qir_FMUL(c, t,
348 get_temp_for_uniform(trans,
349 QUNIFORM_TEXRECT_SCALE_Y,
350 sampler));
351 }
352
353 uint32_t tex_and_sampler = 0; /* XXX */
354 qir_TEX_T(c, t, add_uniform(trans, QUNIFORM_TEXTURE_CONFIG_P0,
355 tex_and_sampler));
356
357 struct qreg sampler_p1 = add_uniform(trans, QUNIFORM_TEXTURE_CONFIG_P1,
358 tex_and_sampler);
359 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB) {
360 qir_TEX_B(c, src[0 * 4 + 3], sampler_p1);
361 qir_TEX_S(c, s, add_uniform(trans, QUNIFORM_CONSTANT, 0));
362 } else {
363 qir_TEX_S(c, s, sampler_p1);
364 }
365
366 trans->num_texture_samples++;
367 qir_emit(c, qir_inst(QOP_TEX_RESULT, c->undef, c->undef, c->undef));
368
369 struct qreg unpacked[4];
370 for (int i = 0; i < 4; i++)
371 unpacked[i] = qir_R4_UNPACK(c, i);
372
373 bool format_warned = false;
374 for (int i = 0; i < 4; i++) {
375 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
376 continue;
377
378 enum pipe_format format = trans->key->tex_format[sampler];
379 const struct util_format_description *desc =
380 util_format_description(format);
381
382 uint8_t swiz = desc->swizzle[i];
383 if (!format_warned &&
384 swiz <= UTIL_FORMAT_SWIZZLE_W &&
385 (desc->channel[swiz].type != UTIL_FORMAT_TYPE_UNSIGNED ||
386 desc->channel[swiz].size != 8)) {
387 fprintf(stderr,
388 "tex channel %d unsupported type: %s\n",
389 i, util_format_name(format));
390 format_warned = true;
391 }
392
393 update_dst(trans, tgsi_inst, i,
394 get_swizzled_channel(trans, unpacked, swiz));
395 }
396 }
397
398 static struct qreg
399 tgsi_to_qir_pow(struct tgsi_to_qir *trans,
400 struct tgsi_full_instruction *tgsi_inst,
401 enum qop op, struct qreg *src, int i)
402 {
403 struct qcompile *c = trans->c;
404
405 /* Note that this instruction replicates its result from the x channel
406 */
407 return qir_EXP2(c, qir_FMUL(c,
408 src[1 * 4 + 0],
409 qir_LOG2(c, src[0 * 4 + 0])));
410 }
411
412 static struct qreg
413 tgsi_to_qir_trunc(struct tgsi_to_qir *trans,
414 struct tgsi_full_instruction *tgsi_inst,
415 enum qop op, struct qreg *src, int i)
416 {
417 struct qcompile *c = trans->c;
418 return qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
419 }
420
421 /**
422 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
423 * to zero).
424 */
425 static struct qreg
426 tgsi_to_qir_frc(struct tgsi_to_qir *trans,
427 struct tgsi_full_instruction *tgsi_inst,
428 enum qop op, struct qreg *src, int i)
429 {
430 struct qcompile *c = trans->c;
431 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
432 struct qreg diff = qir_FSUB(c, src[0 * 4 + i], trunc);
433 return qir_CMP(c,
434 diff,
435 qir_FADD(c, diff, qir_uniform_f(trans, 1.0)),
436 diff);
437 }
438
439 /**
440 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
441 * zero).
442 */
443 static struct qreg
444 tgsi_to_qir_flr(struct tgsi_to_qir *trans,
445 struct tgsi_full_instruction *tgsi_inst,
446 enum qop op, struct qreg *src, int i)
447 {
448 struct qcompile *c = trans->c;
449 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
450 return qir_CMP(c,
451 src[0 * 4 + i],
452 qir_FSUB(c, trunc, qir_uniform_f(trans, 1.0)),
453 trunc);
454 }
455
456 static struct qreg
457 tgsi_to_qir_dp(struct tgsi_to_qir *trans,
458 struct tgsi_full_instruction *tgsi_inst,
459 int num, struct qreg *src, int i)
460 {
461 struct qcompile *c = trans->c;
462
463 struct qreg sum = qir_FMUL(c, src[0 * 4 + 0], src[1 * 4 + 0]);
464 for (int j = 1; j < num; j++) {
465 sum = qir_FADD(c, sum, qir_FMUL(c,
466 src[0 * 4 + j],
467 src[1 * 4 + j]));
468 }
469 return sum;
470 }
471
472 static struct qreg
473 tgsi_to_qir_dp2(struct tgsi_to_qir *trans,
474 struct tgsi_full_instruction *tgsi_inst,
475 enum qop op, struct qreg *src, int i)
476 {
477 return tgsi_to_qir_dp(trans, tgsi_inst, 2, src, i);
478 }
479
480 static struct qreg
481 tgsi_to_qir_dp3(struct tgsi_to_qir *trans,
482 struct tgsi_full_instruction *tgsi_inst,
483 enum qop op, struct qreg *src, int i)
484 {
485 return tgsi_to_qir_dp(trans, tgsi_inst, 3, src, i);
486 }
487
488 static struct qreg
489 tgsi_to_qir_dp4(struct tgsi_to_qir *trans,
490 struct tgsi_full_instruction *tgsi_inst,
491 enum qop op, struct qreg *src, int i)
492 {
493 return tgsi_to_qir_dp(trans, tgsi_inst, 4, src, i);
494 }
495
496 static struct qreg
497 tgsi_to_qir_abs(struct tgsi_to_qir *trans,
498 struct tgsi_full_instruction *tgsi_inst,
499 enum qop op, struct qreg *src, int i)
500 {
501 struct qcompile *c = trans->c;
502 struct qreg arg = src[0 * 4 + i];
503 return qir_FMAXABS(c, arg, arg);
504 }
505
506 /* Note that this instruction replicates its result from the x channel */
507 static struct qreg
508 tgsi_to_qir_sin(struct tgsi_to_qir *trans,
509 struct tgsi_full_instruction *tgsi_inst,
510 enum qop op, struct qreg *src, int i)
511 {
512 struct qcompile *c = trans->c;
513 float coeff[] = {
514 2.0 * M_PI,
515 -pow(2.0 * M_PI, 3) / (3 * 2 * 1),
516 pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
517 -pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
518 };
519
520 struct qreg scaled_x =
521 qir_FMUL(c,
522 src[0 * 4 + 0],
523 qir_uniform_f(trans, 1.0f / (M_PI * 2.0f)));
524
525
526 struct qreg x = tgsi_to_qir_frc(trans, NULL, 0, &scaled_x, 0);
527 struct qreg x2 = qir_FMUL(c, x, x);
528 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(trans, coeff[0]));
529 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
530 x = qir_FMUL(c, x, x2);
531 sum = qir_FADD(c,
532 sum,
533 qir_FMUL(c,
534 x,
535 qir_uniform_f(trans, coeff[i])));
536 }
537 return sum;
538 }
539
540 /* Note that this instruction replicates its result from the x channel */
541 static struct qreg
542 tgsi_to_qir_cos(struct tgsi_to_qir *trans,
543 struct tgsi_full_instruction *tgsi_inst,
544 enum qop op, struct qreg *src, int i)
545 {
546 struct qcompile *c = trans->c;
547 float coeff[] = {
548 1.0f,
549 -pow(2.0 * M_PI, 2) / (2 * 1),
550 pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
551 -pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
552 };
553
554 struct qreg scaled_x =
555 qir_FMUL(c, src[0 * 4 + 0],
556 qir_uniform_f(trans, 1.0f / (M_PI * 2.0f)));
557 struct qreg x_frac = tgsi_to_qir_frc(trans, NULL, 0, &scaled_x, 0);
558
559 struct qreg sum = qir_uniform_f(trans, coeff[0]);
560 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
561 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
562 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
563 if (i != 1)
564 x = qir_FMUL(c, x, x2);
565
566 struct qreg mul = qir_FMUL(c,
567 x,
568 qir_uniform_f(trans, coeff[i]));
569 if (i == 0)
570 sum = mul;
571 else
572 sum = qir_FADD(c, sum, mul);
573 }
574 return sum;
575 }
576
577 static void
578 emit_vertex_input(struct tgsi_to_qir *trans, int attr)
579 {
580 enum pipe_format format = trans->vs_key->attr_formats[attr];
581 struct qcompile *c = trans->c;
582 struct qreg vpm_reads[4];
583
584 /* Right now, we're setting the VPM offsets to be 16 bytes wide every
585 * time, so we always read 4 32-bit VPM entries.
586 */
587 for (int i = 0; i < 4; i++) {
588 vpm_reads[i] = qir_get_temp(c);
589 qir_emit(c, qir_inst(QOP_VPM_READ,
590 vpm_reads[i],
591 c->undef,
592 c->undef));
593 c->num_inputs++;
594 }
595
596 bool format_warned = false;
597 const struct util_format_description *desc =
598 util_format_description(format);
599
600 for (int i = 0; i < 4; i++) {
601 uint8_t swiz = desc->swizzle[i];
602
603 if (swiz <= UTIL_FORMAT_SWIZZLE_W &&
604 !format_warned &&
605 (desc->channel[swiz].type != UTIL_FORMAT_TYPE_FLOAT ||
606 desc->channel[swiz].size != 32)) {
607 fprintf(stderr,
608 "vtx element %d unsupported type: %s\n",
609 attr, util_format_name(format));
610 format_warned = true;
611 }
612
613 trans->inputs[attr * 4 + i] =
614 get_swizzled_channel(trans, vpm_reads, swiz);
615 }
616 }
617
618 static void
619 emit_fragcoord_input(struct tgsi_to_qir *trans, int attr)
620 {
621 struct qcompile *c = trans->c;
622
623 trans->inputs[attr * 4 + 0] = qir_FRAG_X(c);
624 trans->inputs[attr * 4 + 1] = qir_FRAG_Y(c);
625 trans->inputs[attr * 4 + 2] =
626 qir_FMUL(c,
627 qir_FRAG_Z(c),
628 qir_uniform_f(trans, 1.0 / 0xffffff));
629 trans->inputs[attr * 4 + 3] = qir_FRAG_RCP_W(c);
630 }
631
632 static struct qreg
633 emit_fragment_varying(struct tgsi_to_qir *trans, int index)
634 {
635 struct qcompile *c = trans->c;
636
637 struct qreg vary = {
638 QFILE_VARY,
639 index
640 };
641
642 /* XXX: multiply by W */
643 return qir_VARY_ADD_C(c, qir_MOV(c, vary));
644 }
645
646 static void
647 emit_fragment_input(struct tgsi_to_qir *trans, int attr)
648 {
649 struct qcompile *c = trans->c;
650
651 for (int i = 0; i < 4; i++) {
652 trans->inputs[attr * 4 + i] =
653 emit_fragment_varying(trans, attr * 4 + i);
654 c->num_inputs++;
655 }
656 }
657
658 static void
659 emit_tgsi_declaration(struct tgsi_to_qir *trans,
660 struct tgsi_full_declaration *decl)
661 {
662 struct qcompile *c = trans->c;
663
664 switch (decl->Declaration.File) {
665 case TGSI_FILE_INPUT:
666 for (int i = decl->Range.First;
667 i <= decl->Range.Last;
668 i++) {
669 if (c->stage == QSTAGE_FRAG) {
670 if (decl->Semantic.Name ==
671 TGSI_SEMANTIC_POSITION) {
672 emit_fragcoord_input(trans, i);
673 } else {
674 emit_fragment_input(trans, i);
675 }
676 } else {
677 emit_vertex_input(trans, i);
678 }
679 }
680 break;
681 }
682 }
683
684 static void
685 emit_tgsi_instruction(struct tgsi_to_qir *trans,
686 struct tgsi_full_instruction *tgsi_inst)
687 {
688 struct qcompile *c = trans->c;
689 struct {
690 enum qop op;
691 struct qreg (*func)(struct tgsi_to_qir *trans,
692 struct tgsi_full_instruction *tgsi_inst,
693 enum qop op,
694 struct qreg *src, int i);
695 } op_trans[] = {
696 [TGSI_OPCODE_MOV] = { QOP_MOV, tgsi_to_qir_alu },
697 [TGSI_OPCODE_ABS] = { 0, tgsi_to_qir_abs },
698 [TGSI_OPCODE_MUL] = { QOP_FMUL, tgsi_to_qir_alu },
699 [TGSI_OPCODE_ADD] = { QOP_FADD, tgsi_to_qir_alu },
700 [TGSI_OPCODE_SUB] = { QOP_FSUB, tgsi_to_qir_alu },
701 [TGSI_OPCODE_MIN] = { QOP_FMIN, tgsi_to_qir_alu },
702 [TGSI_OPCODE_MAX] = { QOP_FMAX, tgsi_to_qir_alu },
703 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_alu },
704 [TGSI_OPCODE_SEQ] = { QOP_SEQ, tgsi_to_qir_alu },
705 [TGSI_OPCODE_SNE] = { QOP_SNE, tgsi_to_qir_alu },
706 [TGSI_OPCODE_SGE] = { QOP_SGE, tgsi_to_qir_alu },
707 [TGSI_OPCODE_SLT] = { QOP_SLT, tgsi_to_qir_alu },
708 [TGSI_OPCODE_CMP] = { QOP_CMP, tgsi_to_qir_alu },
709 [TGSI_OPCODE_MAD] = { 0, tgsi_to_qir_mad },
710 [TGSI_OPCODE_DP2] = { 0, tgsi_to_qir_dp2 },
711 [TGSI_OPCODE_DP3] = { 0, tgsi_to_qir_dp3 },
712 [TGSI_OPCODE_DP4] = { 0, tgsi_to_qir_dp4 },
713 [TGSI_OPCODE_RCP] = { QOP_RCP, tgsi_to_qir_alu },
714 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_alu },
715 [TGSI_OPCODE_EX2] = { QOP_EXP2, tgsi_to_qir_alu },
716 [TGSI_OPCODE_LG2] = { QOP_LOG2, tgsi_to_qir_alu },
717 [TGSI_OPCODE_LIT] = { 0, tgsi_to_qir_lit },
718 [TGSI_OPCODE_LRP] = { 0, tgsi_to_qir_lrp },
719 [TGSI_OPCODE_POW] = { 0, tgsi_to_qir_pow },
720 [TGSI_OPCODE_TRUNC] = { 0, tgsi_to_qir_trunc },
721 [TGSI_OPCODE_FRC] = { 0, tgsi_to_qir_frc },
722 [TGSI_OPCODE_FLR] = { 0, tgsi_to_qir_flr },
723 [TGSI_OPCODE_SIN] = { 0, tgsi_to_qir_sin },
724 [TGSI_OPCODE_COS] = { 0, tgsi_to_qir_cos },
725 };
726 static int asdf = 0;
727 uint32_t tgsi_op = tgsi_inst->Instruction.Opcode;
728
729 if (tgsi_op == TGSI_OPCODE_END)
730 return;
731
732 struct qreg src_regs[12];
733 for (int s = 0; s < 3; s++) {
734 for (int i = 0; i < 4; i++) {
735 src_regs[4 * s + i] =
736 get_src(trans, &tgsi_inst->Src[s].Register, i);
737 }
738 }
739
740 switch (tgsi_op) {
741 case TGSI_OPCODE_TEX:
742 case TGSI_OPCODE_TXP:
743 case TGSI_OPCODE_TXB:
744 tgsi_to_qir_tex(trans, tgsi_inst,
745 op_trans[tgsi_op].op, src_regs);
746 return;
747 default:
748 break;
749 }
750
751 if (tgsi_op > ARRAY_SIZE(op_trans) || !(op_trans[tgsi_op].func)) {
752 fprintf(stderr, "unknown tgsi inst: ");
753 tgsi_dump_instruction(tgsi_inst, asdf++);
754 fprintf(stderr, "\n");
755 abort();
756 }
757
758 for (int i = 0; i < 4; i++) {
759 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
760 continue;
761
762 struct qreg result;
763
764 result = op_trans[tgsi_op].func(trans, tgsi_inst,
765 op_trans[tgsi_op].op,
766 src_regs, i);
767
768 if (tgsi_inst->Instruction.Saturate) {
769 float low = (tgsi_inst->Instruction.Saturate ==
770 TGSI_SAT_MINUS_PLUS_ONE ? -1.0 : 0.0);
771 result = qir_FMAX(c,
772 qir_FMIN(c,
773 result,
774 qir_uniform_f(trans, 1.0)),
775 qir_uniform_f(trans, low));
776 }
777
778 update_dst(trans, tgsi_inst, i, result);
779 }
780 }
781
782 static void
783 parse_tgsi_immediate(struct tgsi_to_qir *trans, struct tgsi_full_immediate *imm)
784 {
785 for (int i = 0; i < 4; i++) {
786 unsigned n = trans->num_consts++;
787 trans->consts[n] = qir_uniform_ui(trans, imm->u[i].Uint);
788 }
789 }
790
791 static struct qreg
792 vc4_blend_channel(struct tgsi_to_qir *trans,
793 struct qreg *dst,
794 struct qreg *src,
795 struct qreg val,
796 unsigned factor,
797 int channel)
798 {
799 struct qcompile *c = trans->c;
800
801 switch(factor) {
802 case PIPE_BLENDFACTOR_ONE:
803 return val;
804 case PIPE_BLENDFACTOR_SRC_COLOR:
805 return qir_FMUL(c, val, src[channel]);
806 case PIPE_BLENDFACTOR_SRC_ALPHA:
807 return qir_FMUL(c, val, src[3]);
808 case PIPE_BLENDFACTOR_DST_ALPHA:
809 return qir_FMUL(c, val, dst[3]);
810 case PIPE_BLENDFACTOR_DST_COLOR:
811 return qir_FMUL(c, val, dst[channel]);
812 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
813 return qir_FMIN(c, src[3], qir_FSUB(c,
814 qir_uniform_f(trans, 1.0),
815 dst[3]));
816 case PIPE_BLENDFACTOR_CONST_COLOR:
817 return qir_FMUL(c, val,
818 get_temp_for_uniform(trans,
819 QUNIFORM_BLEND_CONST_COLOR,
820 channel));
821 case PIPE_BLENDFACTOR_CONST_ALPHA:
822 return qir_FMUL(c, val,
823 get_temp_for_uniform(trans,
824 QUNIFORM_BLEND_CONST_COLOR,
825 3));
826 case PIPE_BLENDFACTOR_ZERO:
827 return qir_uniform_f(trans, 0.0);
828 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
829 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(trans, 1.0),
830 src[channel]));
831 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
832 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(trans, 1.0),
833 src[3]));
834 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
835 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(trans, 1.0),
836 dst[3]));
837 case PIPE_BLENDFACTOR_INV_DST_COLOR:
838 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(trans, 1.0),
839 dst[channel]));
840 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
841 return qir_FMUL(c, val,
842 qir_FSUB(c, qir_uniform_f(trans, 1.0),
843 get_temp_for_uniform(trans,
844 QUNIFORM_BLEND_CONST_COLOR,
845 channel)));
846 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
847 return qir_FMUL(c, val,
848 qir_FSUB(c, qir_uniform_f(trans, 1.0),
849 get_temp_for_uniform(trans,
850 QUNIFORM_BLEND_CONST_COLOR,
851 3)));
852
853 default:
854 case PIPE_BLENDFACTOR_SRC1_COLOR:
855 case PIPE_BLENDFACTOR_SRC1_ALPHA:
856 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
857 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
858 /* Unsupported. */
859 fprintf(stderr, "Unknown blend factor %d\n", factor);
860 return val;
861 }
862 }
863
864 static struct qreg
865 vc4_blend_func(struct tgsi_to_qir *trans,
866 struct qreg src, struct qreg dst,
867 unsigned func)
868 {
869 struct qcompile *c = trans->c;
870
871 switch (func) {
872 case PIPE_BLEND_ADD:
873 return qir_FADD(c, src, dst);
874 case PIPE_BLEND_SUBTRACT:
875 return qir_FSUB(c, src, dst);
876 case PIPE_BLEND_REVERSE_SUBTRACT:
877 return qir_FSUB(c, dst, src);
878 case PIPE_BLEND_MIN:
879 return qir_FMIN(c, src, dst);
880 case PIPE_BLEND_MAX:
881 return qir_FMAX(c, src, dst);
882
883 default:
884 /* Unsupported. */
885 fprintf(stderr, "Unknown blend func %d\n", func);
886 return src;
887
888 }
889 }
890
891 /**
892 * Implements fixed function blending in shader code.
893 *
894 * VC4 doesn't have any hardware support for blending. Instead, you read the
895 * current contents of the destination from the tile buffer after having
896 * waited for the scoreboard (which is handled by vc4_qpu_emit.c), then do
897 * math using your output color and that destination value, and update the
898 * output color appropriately.
899 */
900 static void
901 vc4_blend(struct tgsi_to_qir *trans, struct qreg *result,
902 struct qreg *dst_color, struct qreg *src_color)
903 {
904 struct pipe_rt_blend_state *blend = &trans->fs_key->blend;
905
906 if (!blend->blend_enable) {
907 for (int i = 0; i < 4; i++)
908 result[i] = src_color[i];
909 return;
910 }
911
912 struct qreg src_blend[4], dst_blend[4];
913 for (int i = 0; i < 3; i++) {
914 src_blend[i] = vc4_blend_channel(trans,
915 dst_color, src_color,
916 src_color[i],
917 blend->rgb_src_factor, i);
918 dst_blend[i] = vc4_blend_channel(trans,
919 dst_color, src_color,
920 dst_color[i],
921 blend->rgb_dst_factor, i);
922 }
923 src_blend[3] = vc4_blend_channel(trans,
924 dst_color, src_color,
925 src_color[3],
926 blend->alpha_src_factor, 3);
927 dst_blend[3] = vc4_blend_channel(trans,
928 dst_color, src_color,
929 dst_color[3],
930 blend->alpha_dst_factor, 3);
931
932 for (int i = 0; i < 3; i++) {
933 result[i] = vc4_blend_func(trans,
934 src_blend[i], dst_blend[i],
935 blend->rgb_func);
936 }
937 result[3] = vc4_blend_func(trans,
938 src_blend[3], dst_blend[3],
939 blend->alpha_func);
940 }
941
942 static void
943 emit_frag_end(struct tgsi_to_qir *trans)
944 {
945 struct qcompile *c = trans->c;
946
947 struct qreg t = qir_get_temp(c);
948
949 const struct util_format_description *format_desc =
950 util_format_description(trans->fs_key->color_format);
951
952 struct qreg src_color[4] = {
953 trans->outputs[0], trans->outputs[1],
954 trans->outputs[2], trans->outputs[3],
955 };
956
957 struct qreg dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
958 if (trans->fs_key->blend.blend_enable ||
959 trans->fs_key->blend.colormask != 0xf) {
960 qir_emit(c, qir_inst(QOP_TLB_COLOR_READ, c->undef,
961 c->undef, c->undef));
962 for (int i = 0; i < 4; i++) {
963 dst_color[i] = qir_R4_UNPACK(c, i);
964
965 /* XXX: Swizzles? */
966 }
967 }
968
969 struct qreg blend_color[4];
970 vc4_blend(trans, blend_color, dst_color, src_color);
971
972 /* If the bit isn't set in the color mask, then just return the
973 * original dst color, instead.
974 */
975 for (int i = 0; i < 4; i++) {
976 if (!(trans->fs_key->blend.colormask & (1 << i))) {
977 blend_color[i] = dst_color[i];
978 }
979 }
980
981 /* Debug: Sometimes you're getting a black output and just want to see
982 * if the FS is getting executed at all. Spam magenta into the color
983 * output.
984 */
985 if (0) {
986 blend_color[0] = qir_uniform_f(trans, 1.0);
987 blend_color[1] = qir_uniform_f(trans, 0.0);
988 blend_color[2] = qir_uniform_f(trans, 1.0);
989 blend_color[3] = qir_uniform_f(trans, 0.5);
990 }
991
992 struct qreg swizzled_outputs[4];
993 for (int i = 0; i < 4; i++) {
994 swizzled_outputs[i] =
995 get_swizzled_channel(trans, blend_color,
996 format_desc->swizzle[i]);
997 }
998
999 if (trans->fs_key->depth_enabled) {
1000 qir_emit(c, qir_inst(QOP_TLB_PASSTHROUGH_Z_WRITE, c->undef,
1001 c->undef, c->undef));
1002 }
1003
1004 qir_emit(c, qir_inst4(QOP_PACK_COLORS, t,
1005 swizzled_outputs[0],
1006 swizzled_outputs[1],
1007 swizzled_outputs[2],
1008 swizzled_outputs[3]));
1009 qir_emit(c, qir_inst(QOP_TLB_COLOR_WRITE, c->undef,
1010 t, c->undef));
1011 }
1012
1013 static void
1014 emit_scaled_viewport_write(struct tgsi_to_qir *trans, struct qreg rcp_w)
1015 {
1016 struct qcompile *c = trans->c;
1017 struct qreg xyi[2];
1018
1019 for (int i = 0; i < 2; i++) {
1020 struct qreg scale =
1021 add_uniform(trans, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1022
1023 xyi[i] = qir_FTOI(c, qir_FMUL(c,
1024 qir_FMUL(c,
1025 trans->outputs[i],
1026 scale),
1027 rcp_w));
1028 }
1029
1030 qir_VPM_WRITE(c, qir_PACK_SCALED(c, xyi[0], xyi[1]));
1031 }
1032
1033 static void
1034 emit_zs_write(struct tgsi_to_qir *trans, struct qreg rcp_w)
1035 {
1036 struct qcompile *c = trans->c;
1037
1038 struct qreg zscale = add_uniform(trans, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1039 struct qreg zoffset = add_uniform(trans, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1040
1041 qir_VPM_WRITE(c, qir_FMUL(c, qir_FADD(c, qir_FMUL(c,
1042 trans->outputs[2],
1043 zscale),
1044 zoffset),
1045 rcp_w));
1046 }
1047
1048 static void
1049 emit_rcp_wc_write(struct tgsi_to_qir *trans, struct qreg rcp_w)
1050 {
1051 struct qcompile *c = trans->c;
1052
1053 qir_VPM_WRITE(c, rcp_w);
1054 }
1055
1056 static void
1057 emit_vert_end(struct tgsi_to_qir *trans)
1058 {
1059 struct qcompile *c = trans->c;
1060
1061 struct qreg rcp_w = qir_RCP(c, trans->outputs[3]);
1062
1063 emit_scaled_viewport_write(trans, rcp_w);
1064 emit_zs_write(trans, rcp_w);
1065 emit_rcp_wc_write(trans, rcp_w);
1066
1067 for (int i = 4; i < trans->num_outputs; i++) {
1068 qir_VPM_WRITE(c, trans->outputs[i]);
1069 }
1070 }
1071
1072 static void
1073 emit_coord_end(struct tgsi_to_qir *trans)
1074 {
1075 struct qcompile *c = trans->c;
1076
1077 struct qreg rcp_w = qir_RCP(c, trans->outputs[3]);
1078
1079 for (int i = 0; i < 4; i++)
1080 qir_VPM_WRITE(c, trans->outputs[i]);
1081
1082 emit_scaled_viewport_write(trans, rcp_w);
1083 emit_zs_write(trans, rcp_w);
1084 emit_rcp_wc_write(trans, rcp_w);
1085 }
1086
1087 static struct tgsi_to_qir *
1088 vc4_shader_tgsi_to_qir(struct vc4_compiled_shader *shader, enum qstage stage,
1089 struct vc4_key *key)
1090 {
1091 struct tgsi_to_qir *trans = CALLOC_STRUCT(tgsi_to_qir);
1092 struct qcompile *c;
1093 int ret;
1094
1095 c = qir_compile_init();
1096 c->stage = stage;
1097
1098 memset(trans, 0, sizeof(*trans));
1099 /* XXX sizing */
1100 trans->temps = calloc(sizeof(struct qreg), 1024);
1101 trans->inputs = calloc(sizeof(struct qreg), 8 * 4);
1102 trans->outputs = calloc(sizeof(struct qreg), 1024);
1103 trans->uniforms = calloc(sizeof(struct qreg), 1024);
1104 trans->consts = calloc(sizeof(struct qreg), 1024);
1105
1106 trans->uniform_data = calloc(sizeof(uint32_t), 1024);
1107 trans->uniform_contents = calloc(sizeof(enum quniform_contents), 1024);
1108
1109 trans->shader_state = key->shader_state;
1110 trans->c = c;
1111 ret = tgsi_parse_init(&trans->parser, trans->shader_state->tokens);
1112 assert(ret == TGSI_PARSE_OK);
1113
1114 if (vc4_debug & VC4_DEBUG_TGSI) {
1115 fprintf(stderr, "TGSI:\n");
1116 tgsi_dump(trans->shader_state->tokens, 0);
1117 }
1118
1119 trans->key = key;
1120 switch (stage) {
1121 case QSTAGE_FRAG:
1122 trans->fs_key = (struct vc4_fs_key *)key;
1123 if (trans->fs_key->is_points) {
1124 trans->point_x = emit_fragment_varying(trans, 0);
1125 trans->point_y = emit_fragment_varying(trans, 0);
1126 } else if (trans->fs_key->is_lines) {
1127 trans->line_x = emit_fragment_varying(trans, 0);
1128 }
1129 break;
1130 case QSTAGE_VERT:
1131 trans->vs_key = (struct vc4_vs_key *)key;
1132 break;
1133 case QSTAGE_COORD:
1134 trans->vs_key = (struct vc4_vs_key *)key;
1135 break;
1136 }
1137
1138 while (!tgsi_parse_end_of_tokens(&trans->parser)) {
1139 tgsi_parse_token(&trans->parser);
1140
1141 switch (trans->parser.FullToken.Token.Type) {
1142 case TGSI_TOKEN_TYPE_DECLARATION:
1143 emit_tgsi_declaration(trans,
1144 &trans->parser.FullToken.FullDeclaration);
1145 break;
1146
1147 case TGSI_TOKEN_TYPE_INSTRUCTION:
1148 emit_tgsi_instruction(trans,
1149 &trans->parser.FullToken.FullInstruction);
1150 break;
1151
1152 case TGSI_TOKEN_TYPE_IMMEDIATE:
1153 parse_tgsi_immediate(trans,
1154 &trans->parser.FullToken.FullImmediate);
1155 break;
1156 }
1157 }
1158
1159 switch (stage) {
1160 case QSTAGE_FRAG:
1161 emit_frag_end(trans);
1162 break;
1163 case QSTAGE_VERT:
1164 emit_vert_end(trans);
1165 break;
1166 case QSTAGE_COORD:
1167 emit_coord_end(trans);
1168 break;
1169 }
1170
1171 tgsi_parse_free(&trans->parser);
1172 free(trans->temps);
1173
1174 qir_optimize(c);
1175
1176 if (vc4_debug & VC4_DEBUG_QIR) {
1177 fprintf(stderr, "QIR:\n");
1178 qir_dump(c);
1179 }
1180 vc4_generate_code(c);
1181
1182 if (vc4_debug & VC4_DEBUG_SHADERDB) {
1183 fprintf(stderr, "SHADER-DB: %s: %d instructions\n",
1184 qir_get_stage_name(c->stage), c->qpu_inst_count);
1185 fprintf(stderr, "SHADER-DB: %s: %d uniforms\n",
1186 qir_get_stage_name(c->stage), trans->num_uniforms);
1187 }
1188
1189 return trans;
1190 }
1191
1192 static void *
1193 vc4_shader_state_create(struct pipe_context *pctx,
1194 const struct pipe_shader_state *cso)
1195 {
1196 struct pipe_shader_state *so = CALLOC_STRUCT(pipe_shader_state);
1197 if (!so)
1198 return NULL;
1199
1200 so->tokens = tgsi_dup_tokens(cso->tokens);
1201
1202 return so;
1203 }
1204
1205 static void
1206 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
1207 int shader_index,
1208 struct tgsi_to_qir *trans)
1209 {
1210 int count = trans->num_uniforms;
1211 struct vc4_shader_uniform_info *uinfo = &shader->uniforms[shader_index];
1212
1213 uinfo->count = count;
1214 uinfo->data = malloc(count * sizeof(*uinfo->data));
1215 memcpy(uinfo->data, trans->uniform_data,
1216 count * sizeof(*uinfo->data));
1217 uinfo->contents = malloc(count * sizeof(*uinfo->contents));
1218 memcpy(uinfo->contents, trans->uniform_contents,
1219 count * sizeof(*uinfo->contents));
1220 uinfo->num_texture_samples = trans->num_texture_samples;
1221 }
1222
1223 static void
1224 vc4_fs_compile(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1225 struct vc4_fs_key *key)
1226 {
1227 struct tgsi_to_qir *trans = vc4_shader_tgsi_to_qir(shader, QSTAGE_FRAG,
1228 &key->base);
1229 shader->num_inputs = trans->c->num_inputs;
1230 copy_uniform_state_to_shader(shader, 0, trans);
1231 shader->bo = vc4_bo_alloc_mem(vc4->screen, trans->c->qpu_insts,
1232 trans->c->qpu_inst_count * sizeof(uint64_t),
1233 "fs_code");
1234
1235 qir_compile_destroy(trans->c);
1236 free(trans);
1237 }
1238
1239 static void
1240 vc4_vs_compile(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1241 struct vc4_vs_key *key)
1242 {
1243 struct tgsi_to_qir *vs_trans = vc4_shader_tgsi_to_qir(shader,
1244 QSTAGE_VERT,
1245 &key->base);
1246 copy_uniform_state_to_shader(shader, 0, vs_trans);
1247
1248 struct tgsi_to_qir *cs_trans = vc4_shader_tgsi_to_qir(shader,
1249 QSTAGE_COORD,
1250 &key->base);
1251 copy_uniform_state_to_shader(shader, 1, cs_trans);
1252
1253 uint32_t vs_size = vs_trans->c->qpu_inst_count * sizeof(uint64_t);
1254 uint32_t cs_size = cs_trans->c->qpu_inst_count * sizeof(uint64_t);
1255 shader->coord_shader_offset = vs_size; /* XXX: alignment? */
1256 shader->bo = vc4_bo_alloc(vc4->screen,
1257 shader->coord_shader_offset + cs_size,
1258 "vs_code");
1259
1260 void *map = vc4_bo_map(shader->bo);
1261 memcpy(map, vs_trans->c->qpu_insts, vs_size);
1262 memcpy(map + shader->coord_shader_offset,
1263 cs_trans->c->qpu_insts, cs_size);
1264
1265 qir_compile_destroy(vs_trans->c);
1266 qir_compile_destroy(cs_trans->c);
1267 }
1268
1269 static void
1270 vc4_setup_shared_key(struct vc4_key *key, struct vc4_texture_stateobj *texstate)
1271 {
1272 for (int i = 0; i < texstate->num_textures; i++) {
1273 struct pipe_sampler_view *sampler = texstate->textures[i];
1274 if (sampler) {
1275 struct pipe_resource *prsc = sampler->texture;
1276 key->tex_format[i] = prsc->format;
1277 }
1278 }
1279 }
1280
1281 static void
1282 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
1283 {
1284 struct vc4_fs_key local_key;
1285 struct vc4_fs_key *key = &local_key;
1286
1287 memset(key, 0, sizeof(*key));
1288 vc4_setup_shared_key(&key->base, &vc4->fragtex);
1289 key->base.shader_state = vc4->prog.bind_fs;
1290 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
1291 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
1292 prim_mode <= PIPE_PRIM_LINE_STRIP);
1293 key->blend = vc4->blend->rt[0];
1294
1295 if (vc4->framebuffer.cbufs[0])
1296 key->color_format = vc4->framebuffer.cbufs[0]->format;
1297
1298 key->depth_enabled = vc4->zsa->base.depth.enabled;
1299
1300 vc4->prog.fs = util_hash_table_get(vc4->fs_cache, key);
1301 if (vc4->prog.fs)
1302 return;
1303
1304 key = malloc(sizeof(*key));
1305 memcpy(key, &local_key, sizeof(*key));
1306
1307 struct vc4_compiled_shader *shader = CALLOC_STRUCT(vc4_compiled_shader);
1308 vc4_fs_compile(vc4, shader, key);
1309 util_hash_table_set(vc4->fs_cache, key, shader);
1310
1311 vc4->prog.fs = shader;
1312 }
1313
1314 static void
1315 vc4_update_compiled_vs(struct vc4_context *vc4)
1316 {
1317 struct vc4_vs_key local_key;
1318 struct vc4_vs_key *key = &local_key;
1319
1320 memset(key, 0, sizeof(*key));
1321 vc4_setup_shared_key(&key->base, &vc4->verttex);
1322 key->base.shader_state = vc4->prog.bind_vs;
1323
1324 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
1325 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
1326
1327 vc4->prog.vs = util_hash_table_get(vc4->vs_cache, key);
1328 if (vc4->prog.vs)
1329 return;
1330
1331 key = malloc(sizeof(*key));
1332 memcpy(key, &local_key, sizeof(*key));
1333
1334 struct vc4_compiled_shader *shader = CALLOC_STRUCT(vc4_compiled_shader);
1335 vc4_vs_compile(vc4, shader, key);
1336 util_hash_table_set(vc4->vs_cache, key, shader);
1337
1338 vc4->prog.vs = shader;
1339 }
1340
1341 void
1342 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
1343 {
1344 vc4_update_compiled_fs(vc4, prim_mode);
1345 vc4_update_compiled_vs(vc4);
1346 }
1347
1348 static unsigned
1349 fs_cache_hash(void *key)
1350 {
1351 return util_hash_crc32(key, sizeof(struct vc4_fs_key));
1352 }
1353
1354 static unsigned
1355 vs_cache_hash(void *key)
1356 {
1357 return util_hash_crc32(key, sizeof(struct vc4_vs_key));
1358 }
1359
1360 static int
1361 fs_cache_compare(void *key1, void *key2)
1362 {
1363 return memcmp(key1, key2, sizeof(struct vc4_fs_key));
1364 }
1365
1366 static int
1367 vs_cache_compare(void *key1, void *key2)
1368 {
1369 return memcmp(key1, key2, sizeof(struct vc4_vs_key));
1370 }
1371
1372 struct delete_state {
1373 struct vc4_context *vc4;
1374 struct pipe_shader_state *shader_state;
1375 };
1376
1377 static enum pipe_error
1378 fs_delete_from_cache(void *in_key, void *in_value, void *data)
1379 {
1380 struct delete_state *del = data;
1381 struct vc4_fs_key *key = in_key;
1382 struct vc4_compiled_shader *shader = in_value;
1383
1384 if (key->base.shader_state == data) {
1385 util_hash_table_remove(del->vc4->fs_cache, key);
1386 vc4_bo_unreference(&shader->bo);
1387 free(shader);
1388 }
1389
1390 return 0;
1391 }
1392
1393 static enum pipe_error
1394 vs_delete_from_cache(void *in_key, void *in_value, void *data)
1395 {
1396 struct delete_state *del = data;
1397 struct vc4_vs_key *key = in_key;
1398 struct vc4_compiled_shader *shader = in_value;
1399
1400 if (key->base.shader_state == data) {
1401 util_hash_table_remove(del->vc4->vs_cache, key);
1402 vc4_bo_unreference(&shader->bo);
1403 free(shader);
1404 }
1405
1406 return 0;
1407 }
1408
1409 static void
1410 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
1411 {
1412 struct vc4_context *vc4 = vc4_context(pctx);
1413 struct pipe_shader_state *so = hwcso;
1414 struct delete_state del;
1415
1416 del.vc4 = vc4;
1417 del.shader_state = so;
1418 util_hash_table_foreach(vc4->fs_cache, fs_delete_from_cache, &del);
1419 util_hash_table_foreach(vc4->vs_cache, vs_delete_from_cache, &del);
1420
1421 free((void *)so->tokens);
1422 free(so);
1423 }
1424
1425 static uint32_t translate_wrap(uint32_t p_wrap)
1426 {
1427 switch (p_wrap) {
1428 case PIPE_TEX_WRAP_REPEAT:
1429 return 0;
1430 case PIPE_TEX_WRAP_CLAMP:
1431 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1432 return 1;
1433 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1434 return 2;
1435 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1436 return 3;
1437 default:
1438 fprintf(stderr, "Unknown wrap mode %d\n", p_wrap);
1439 assert(!"not reached");
1440 return 0;
1441 }
1442 }
1443
1444 static void
1445 write_texture_p0(struct vc4_context *vc4,
1446 struct vc4_texture_stateobj *texstate,
1447 uint32_t tex_and_sampler)
1448 {
1449 uint32_t texi = (tex_and_sampler >> 0) & 0xff;
1450 struct pipe_sampler_view *texture = texstate->textures[texi];
1451 struct vc4_resource *rsc = vc4_resource(texture->texture);
1452
1453 cl_reloc(vc4, &vc4->uniforms, rsc->bo,
1454 rsc->slices[0].offset | texture->u.tex.last_level);
1455 }
1456
1457 static void
1458 write_texture_p1(struct vc4_context *vc4,
1459 struct vc4_texture_stateobj *texstate,
1460 uint32_t tex_and_sampler)
1461 {
1462 uint32_t texi = (tex_and_sampler >> 0) & 0xff;
1463 uint32_t sampi = (tex_and_sampler >> 8) & 0xff;
1464 struct pipe_sampler_view *texture = texstate->textures[texi];
1465 struct pipe_sampler_state *sampler = texstate->samplers[sampi];
1466 static const uint32_t mipfilter_map[] = {
1467 [PIPE_TEX_MIPFILTER_NEAREST] = 2,
1468 [PIPE_TEX_MIPFILTER_LINEAR] = 4,
1469 [PIPE_TEX_MIPFILTER_NONE] = 0
1470 };
1471 static const uint32_t imgfilter_map[] = {
1472 [PIPE_TEX_FILTER_NEAREST] = 1,
1473 [PIPE_TEX_FILTER_LINEAR] = 0,
1474 };
1475
1476 cl_u32(&vc4->uniforms,
1477 (1 << 31) /* XXX: data type */|
1478 (texture->texture->height0 << 20) |
1479 (texture->texture->width0 << 8) |
1480 (imgfilter_map[sampler->mag_img_filter] << 7) |
1481 ((imgfilter_map[sampler->min_img_filter] +
1482 mipfilter_map[sampler->min_mip_filter]) << 4) |
1483 (translate_wrap(sampler->wrap_t) << 2) |
1484 (translate_wrap(sampler->wrap_s) << 0));
1485 }
1486
1487 static uint32_t
1488 get_texrect_scale(struct vc4_texture_stateobj *texstate,
1489 enum quniform_contents contents,
1490 uint32_t data)
1491 {
1492 struct pipe_sampler_view *texture = texstate->textures[data];
1493 uint32_t dim;
1494
1495 if (contents == QUNIFORM_TEXRECT_SCALE_X)
1496 dim = texture->texture->width0;
1497 else
1498 dim = texture->texture->height0;
1499
1500 return fui(1.0f / dim);
1501 }
1502
1503 void
1504 vc4_write_uniforms(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1505 struct vc4_constbuf_stateobj *cb,
1506 struct vc4_texture_stateobj *texstate,
1507 int shader_index)
1508 {
1509 struct vc4_shader_uniform_info *uinfo = &shader->uniforms[shader_index];
1510 const uint32_t *gallium_uniforms = cb->cb[0].user_buffer;
1511
1512 cl_start_shader_reloc(&vc4->uniforms, uinfo->num_texture_samples);
1513
1514 for (int i = 0; i < uinfo->count; i++) {
1515
1516 switch (uinfo->contents[i]) {
1517 case QUNIFORM_CONSTANT:
1518 cl_u32(&vc4->uniforms, uinfo->data[i]);
1519 break;
1520 case QUNIFORM_UNIFORM:
1521 cl_u32(&vc4->uniforms,
1522 gallium_uniforms[uinfo->data[i]]);
1523 break;
1524 case QUNIFORM_VIEWPORT_X_SCALE:
1525 cl_f(&vc4->uniforms, vc4->viewport.scale[0] * 16.0f);
1526 break;
1527 case QUNIFORM_VIEWPORT_Y_SCALE:
1528 cl_f(&vc4->uniforms, vc4->viewport.scale[1] * 16.0f);
1529 break;
1530
1531 case QUNIFORM_VIEWPORT_Z_OFFSET:
1532 cl_f(&vc4->uniforms, vc4->viewport.translate[2]);
1533 break;
1534 case QUNIFORM_VIEWPORT_Z_SCALE:
1535 cl_f(&vc4->uniforms, vc4->viewport.scale[2]);
1536 break;
1537
1538 case QUNIFORM_TEXTURE_CONFIG_P0:
1539 write_texture_p0(vc4, texstate, uinfo->data[i]);
1540 break;
1541
1542 case QUNIFORM_TEXTURE_CONFIG_P1:
1543 write_texture_p1(vc4, texstate, uinfo->data[i]);
1544 break;
1545
1546 case QUNIFORM_TEXRECT_SCALE_X:
1547 case QUNIFORM_TEXRECT_SCALE_Y:
1548 cl_u32(&vc4->uniforms,
1549 get_texrect_scale(texstate,
1550 uinfo->contents[i],
1551 uinfo->data[i]));
1552 break;
1553
1554 case QUNIFORM_BLEND_CONST_COLOR:
1555 cl_f(&vc4->uniforms,
1556 vc4->blend_color.color[uinfo->data[i]]);
1557 break;
1558 }
1559 #if 0
1560 uint32_t written_val = *(uint32_t *)(vc4->uniforms.next - 4);
1561 fprintf(stderr, "%p/%d: %d: 0x%08x (%f)\n",
1562 shader, shader_index, i, written_val, uif(written_val));
1563 #endif
1564 }
1565 }
1566
1567 static void
1568 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
1569 {
1570 struct vc4_context *vc4 = vc4_context(pctx);
1571 vc4->prog.bind_fs = hwcso;
1572 vc4->prog.dirty |= VC4_SHADER_DIRTY_FP;
1573 vc4->dirty |= VC4_DIRTY_PROG;
1574 }
1575
1576 static void
1577 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
1578 {
1579 struct vc4_context *vc4 = vc4_context(pctx);
1580 vc4->prog.bind_vs = hwcso;
1581 vc4->prog.dirty |= VC4_SHADER_DIRTY_VP;
1582 vc4->dirty |= VC4_DIRTY_PROG;
1583 }
1584
1585 void
1586 vc4_program_init(struct pipe_context *pctx)
1587 {
1588 struct vc4_context *vc4 = vc4_context(pctx);
1589
1590 pctx->create_vs_state = vc4_shader_state_create;
1591 pctx->delete_vs_state = vc4_shader_state_delete;
1592
1593 pctx->create_fs_state = vc4_shader_state_create;
1594 pctx->delete_fs_state = vc4_shader_state_delete;
1595
1596 pctx->bind_fs_state = vc4_fp_state_bind;
1597 pctx->bind_vs_state = vc4_vp_state_bind;
1598
1599 vc4->fs_cache = util_hash_table_create(fs_cache_hash, fs_cache_compare);
1600 vc4->vs_cache = util_hash_table_create(vs_cache_hash, vs_cache_compare);
1601 }