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vc4: Don't look up the compiled shaders unless state has changed.
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "pipe/p_state.h"
27 #include "util/u_format.h"
28 #include "util/u_hash_table.h"
29 #include "util/u_hash.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include "util/format_srgb.h"
33 #include "util/ralloc.h"
34 #include "tgsi/tgsi_dump.h"
35 #include "tgsi/tgsi_info.h"
36 #include "tgsi/tgsi_lowering.h"
37
38 #include "vc4_context.h"
39 #include "vc4_qpu.h"
40 #include "vc4_qir.h"
41 #ifdef USE_VC4_SIMULATOR
42 #include "simpenrose/simpenrose.h"
43 #endif
44
45 struct vc4_key {
46 struct vc4_uncompiled_shader *shader_state;
47 struct {
48 enum pipe_format format;
49 unsigned compare_mode:1;
50 unsigned compare_func:3;
51 unsigned wrap_s:3;
52 unsigned wrap_t:3;
53 uint8_t swizzle[4];
54 } tex[VC4_MAX_TEXTURE_SAMPLERS];
55 };
56
57 struct vc4_fs_key {
58 struct vc4_key base;
59 enum pipe_format color_format;
60 bool depth_enabled;
61 bool stencil_enabled;
62 bool stencil_twoside;
63 bool stencil_full_writemasks;
64 bool is_points;
65 bool is_lines;
66 bool alpha_test;
67 bool point_coord_upper_left;
68 bool light_twoside;
69 uint8_t alpha_test_func;
70 uint32_t point_sprite_mask;
71
72 struct pipe_rt_blend_state blend;
73 };
74
75 struct vc4_vs_key {
76 struct vc4_key base;
77 enum pipe_format attr_formats[8];
78 bool is_coord;
79 bool per_vertex_point_size;
80 };
81
82 static void
83 resize_qreg_array(struct vc4_compile *c,
84 struct qreg **regs,
85 uint32_t *size,
86 uint32_t decl_size)
87 {
88 if (*size >= decl_size)
89 return;
90
91 uint32_t old_size = *size;
92 *size = MAX2(*size * 2, decl_size);
93 *regs = reralloc(c, *regs, struct qreg, *size);
94 if (!*regs) {
95 fprintf(stderr, "Malloc failure\n");
96 abort();
97 }
98
99 for (uint32_t i = old_size; i < *size; i++)
100 (*regs)[i] = c->undef;
101 }
102
103 static struct qreg
104 add_uniform(struct vc4_compile *c,
105 enum quniform_contents contents,
106 uint32_t data)
107 {
108 uint32_t uniform = c->num_uniforms++;
109 struct qreg u = { QFILE_UNIF, uniform };
110
111 if (uniform >= c->uniform_array_size) {
112 c->uniform_array_size = MAX2(MAX2(16, uniform + 1),
113 c->uniform_array_size * 2);
114
115 c->uniform_data = reralloc(c, c->uniform_data,
116 uint32_t,
117 c->uniform_array_size);
118 c->uniform_contents = reralloc(c, c->uniform_contents,
119 enum quniform_contents,
120 c->uniform_array_size);
121 }
122
123 c->uniform_contents[uniform] = contents;
124 c->uniform_data[uniform] = data;
125
126 return u;
127 }
128
129 static struct qreg
130 get_temp_for_uniform(struct vc4_compile *c, enum quniform_contents contents,
131 uint32_t data)
132 {
133 struct qreg u = add_uniform(c, contents, data);
134 struct qreg t = qir_MOV(c, u);
135 return t;
136 }
137
138 static struct qreg
139 qir_uniform_ui(struct vc4_compile *c, uint32_t ui)
140 {
141 return get_temp_for_uniform(c, QUNIFORM_CONSTANT, ui);
142 }
143
144 static struct qreg
145 qir_uniform_f(struct vc4_compile *c, float f)
146 {
147 return qir_uniform_ui(c, fui(f));
148 }
149
150 static struct qreg
151 get_src(struct vc4_compile *c, unsigned tgsi_op,
152 struct tgsi_src_register *src, int i)
153 {
154 struct qreg r = c->undef;
155
156 uint32_t s = i;
157 switch (i) {
158 case TGSI_SWIZZLE_X:
159 s = src->SwizzleX;
160 break;
161 case TGSI_SWIZZLE_Y:
162 s = src->SwizzleY;
163 break;
164 case TGSI_SWIZZLE_Z:
165 s = src->SwizzleZ;
166 break;
167 case TGSI_SWIZZLE_W:
168 s = src->SwizzleW;
169 break;
170 default:
171 abort();
172 }
173
174 assert(!src->Indirect);
175
176 switch (src->File) {
177 case TGSI_FILE_NULL:
178 return r;
179 case TGSI_FILE_TEMPORARY:
180 r = c->temps[src->Index * 4 + s];
181 break;
182 case TGSI_FILE_IMMEDIATE:
183 r = c->consts[src->Index * 4 + s];
184 break;
185 case TGSI_FILE_CONSTANT:
186 r = get_temp_for_uniform(c, QUNIFORM_UNIFORM,
187 src->Index * 4 + s);
188 break;
189 case TGSI_FILE_INPUT:
190 r = c->inputs[src->Index * 4 + s];
191 break;
192 case TGSI_FILE_SAMPLER:
193 case TGSI_FILE_SAMPLER_VIEW:
194 r = c->undef;
195 break;
196 default:
197 fprintf(stderr, "unknown src file %d\n", src->File);
198 abort();
199 }
200
201 if (src->Absolute)
202 r = qir_FMAXABS(c, r, r);
203
204 if (src->Negate) {
205 switch (tgsi_opcode_infer_src_type(tgsi_op)) {
206 case TGSI_TYPE_SIGNED:
207 case TGSI_TYPE_UNSIGNED:
208 r = qir_SUB(c, qir_uniform_ui(c, 0), r);
209 break;
210 default:
211 r = qir_FSUB(c, qir_uniform_f(c, 0.0), r);
212 break;
213 }
214 }
215
216 return r;
217 };
218
219
220 static void
221 update_dst(struct vc4_compile *c, struct tgsi_full_instruction *tgsi_inst,
222 int i, struct qreg val)
223 {
224 struct tgsi_dst_register *tgsi_dst = &tgsi_inst->Dst[0].Register;
225
226 assert(!tgsi_dst->Indirect);
227
228 switch (tgsi_dst->File) {
229 case TGSI_FILE_TEMPORARY:
230 c->temps[tgsi_dst->Index * 4 + i] = val;
231 break;
232 case TGSI_FILE_OUTPUT:
233 c->outputs[tgsi_dst->Index * 4 + i] = val;
234 c->num_outputs = MAX2(c->num_outputs,
235 tgsi_dst->Index * 4 + i + 1);
236 break;
237 default:
238 fprintf(stderr, "unknown dst file %d\n", tgsi_dst->File);
239 abort();
240 }
241 };
242
243 static struct qreg
244 get_swizzled_channel(struct vc4_compile *c,
245 struct qreg *srcs, int swiz)
246 {
247 switch (swiz) {
248 default:
249 case UTIL_FORMAT_SWIZZLE_NONE:
250 fprintf(stderr, "warning: unknown swizzle\n");
251 /* FALLTHROUGH */
252 case UTIL_FORMAT_SWIZZLE_0:
253 return qir_uniform_f(c, 0.0);
254 case UTIL_FORMAT_SWIZZLE_1:
255 return qir_uniform_f(c, 1.0);
256 case UTIL_FORMAT_SWIZZLE_X:
257 case UTIL_FORMAT_SWIZZLE_Y:
258 case UTIL_FORMAT_SWIZZLE_Z:
259 case UTIL_FORMAT_SWIZZLE_W:
260 return srcs[swiz];
261 }
262 }
263
264 static struct qreg
265 tgsi_to_qir_alu(struct vc4_compile *c,
266 struct tgsi_full_instruction *tgsi_inst,
267 enum qop op, struct qreg *src, int i)
268 {
269 struct qreg dst = qir_get_temp(c);
270 qir_emit(c, qir_inst4(op, dst,
271 src[0 * 4 + i],
272 src[1 * 4 + i],
273 src[2 * 4 + i],
274 c->undef));
275 return dst;
276 }
277
278 static struct qreg
279 tgsi_to_qir_scalar(struct vc4_compile *c,
280 struct tgsi_full_instruction *tgsi_inst,
281 enum qop op, struct qreg *src, int i)
282 {
283 struct qreg dst = qir_get_temp(c);
284 qir_emit(c, qir_inst(op, dst,
285 src[0 * 4 + 0],
286 c->undef));
287 return dst;
288 }
289
290 static struct qreg
291 qir_srgb_decode(struct vc4_compile *c, struct qreg srgb)
292 {
293 struct qreg low = qir_FMUL(c, srgb, qir_uniform_f(c, 1.0 / 12.92));
294 struct qreg high = qir_POW(c,
295 qir_FMUL(c,
296 qir_FADD(c,
297 srgb,
298 qir_uniform_f(c, 0.055)),
299 qir_uniform_f(c, 1.0 / 1.055)),
300 qir_uniform_f(c, 2.4));
301
302 qir_SF(c, qir_FSUB(c, srgb, qir_uniform_f(c, 0.04045)));
303 return qir_SEL_X_Y_NS(c, low, high);
304 }
305
306 static struct qreg
307 qir_srgb_encode(struct vc4_compile *c, struct qreg linear)
308 {
309 struct qreg low = qir_FMUL(c, linear, qir_uniform_f(c, 12.92));
310 struct qreg high = qir_FSUB(c,
311 qir_FMUL(c,
312 qir_uniform_f(c, 1.055),
313 qir_POW(c,
314 linear,
315 qir_uniform_f(c, 0.41666))),
316 qir_uniform_f(c, 0.055));
317
318 qir_SF(c, qir_FSUB(c, linear, qir_uniform_f(c, 0.0031308)));
319 return qir_SEL_X_Y_NS(c, low, high);
320 }
321
322 static struct qreg
323 tgsi_to_qir_umul(struct vc4_compile *c,
324 struct tgsi_full_instruction *tgsi_inst,
325 enum qop op, struct qreg *src, int i)
326 {
327 struct qreg src0_hi = qir_SHR(c, src[0 * 4 + i],
328 qir_uniform_ui(c, 16));
329 struct qreg src0_lo = qir_AND(c, src[0 * 4 + i],
330 qir_uniform_ui(c, 0xffff));
331 struct qreg src1_hi = qir_SHR(c, src[1 * 4 + i],
332 qir_uniform_ui(c, 16));
333 struct qreg src1_lo = qir_AND(c, src[1 * 4 + i],
334 qir_uniform_ui(c, 0xffff));
335
336 struct qreg hilo = qir_MUL24(c, src0_hi, src1_lo);
337 struct qreg lohi = qir_MUL24(c, src0_lo, src1_hi);
338 struct qreg lolo = qir_MUL24(c, src0_lo, src1_lo);
339
340 return qir_ADD(c, lolo, qir_SHL(c,
341 qir_ADD(c, hilo, lohi),
342 qir_uniform_ui(c, 16)));
343 }
344
345 static struct qreg
346 tgsi_to_qir_idiv(struct vc4_compile *c,
347 struct tgsi_full_instruction *tgsi_inst,
348 enum qop op, struct qreg *src, int i)
349 {
350 return qir_FTOI(c, qir_FMUL(c,
351 qir_ITOF(c, src[0 * 4 + i]),
352 qir_RCP(c, qir_ITOF(c, src[1 * 4 + i]))));
353 }
354
355 static struct qreg
356 tgsi_to_qir_ineg(struct vc4_compile *c,
357 struct tgsi_full_instruction *tgsi_inst,
358 enum qop op, struct qreg *src, int i)
359 {
360 return qir_SUB(c, qir_uniform_ui(c, 0), src[0 * 4 + i]);
361 }
362
363 static struct qreg
364 tgsi_to_qir_seq(struct vc4_compile *c,
365 struct tgsi_full_instruction *tgsi_inst,
366 enum qop op, struct qreg *src, int i)
367 {
368 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
369 return qir_SEL_X_0_ZS(c, qir_uniform_f(c, 1.0));
370 }
371
372 static struct qreg
373 tgsi_to_qir_sne(struct vc4_compile *c,
374 struct tgsi_full_instruction *tgsi_inst,
375 enum qop op, struct qreg *src, int i)
376 {
377 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
378 return qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0));
379 }
380
381 static struct qreg
382 tgsi_to_qir_slt(struct vc4_compile *c,
383 struct tgsi_full_instruction *tgsi_inst,
384 enum qop op, struct qreg *src, int i)
385 {
386 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
387 return qir_SEL_X_0_NS(c, qir_uniform_f(c, 1.0));
388 }
389
390 static struct qreg
391 tgsi_to_qir_sge(struct vc4_compile *c,
392 struct tgsi_full_instruction *tgsi_inst,
393 enum qop op, struct qreg *src, int i)
394 {
395 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
396 return qir_SEL_X_0_NC(c, qir_uniform_f(c, 1.0));
397 }
398
399 static struct qreg
400 tgsi_to_qir_fseq(struct vc4_compile *c,
401 struct tgsi_full_instruction *tgsi_inst,
402 enum qop op, struct qreg *src, int i)
403 {
404 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
405 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
406 }
407
408 static struct qreg
409 tgsi_to_qir_fsne(struct vc4_compile *c,
410 struct tgsi_full_instruction *tgsi_inst,
411 enum qop op, struct qreg *src, int i)
412 {
413 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
414 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
415 }
416
417 static struct qreg
418 tgsi_to_qir_fslt(struct vc4_compile *c,
419 struct tgsi_full_instruction *tgsi_inst,
420 enum qop op, struct qreg *src, int i)
421 {
422 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
423 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
424 }
425
426 static struct qreg
427 tgsi_to_qir_fsge(struct vc4_compile *c,
428 struct tgsi_full_instruction *tgsi_inst,
429 enum qop op, struct qreg *src, int i)
430 {
431 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
432 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
433 }
434
435 static struct qreg
436 tgsi_to_qir_useq(struct vc4_compile *c,
437 struct tgsi_full_instruction *tgsi_inst,
438 enum qop op, struct qreg *src, int i)
439 {
440 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
441 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
442 }
443
444 static struct qreg
445 tgsi_to_qir_usne(struct vc4_compile *c,
446 struct tgsi_full_instruction *tgsi_inst,
447 enum qop op, struct qreg *src, int i)
448 {
449 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
450 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
451 }
452
453 static struct qreg
454 tgsi_to_qir_islt(struct vc4_compile *c,
455 struct tgsi_full_instruction *tgsi_inst,
456 enum qop op, struct qreg *src, int i)
457 {
458 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
459 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
460 }
461
462 static struct qreg
463 tgsi_to_qir_isge(struct vc4_compile *c,
464 struct tgsi_full_instruction *tgsi_inst,
465 enum qop op, struct qreg *src, int i)
466 {
467 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
468 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
469 }
470
471 static struct qreg
472 tgsi_to_qir_cmp(struct vc4_compile *c,
473 struct tgsi_full_instruction *tgsi_inst,
474 enum qop op, struct qreg *src, int i)
475 {
476 qir_SF(c, src[0 * 4 + i]);
477 return qir_SEL_X_Y_NS(c,
478 src[1 * 4 + i],
479 src[2 * 4 + i]);
480 }
481
482 static struct qreg
483 tgsi_to_qir_mad(struct vc4_compile *c,
484 struct tgsi_full_instruction *tgsi_inst,
485 enum qop op, struct qreg *src, int i)
486 {
487 return qir_FADD(c,
488 qir_FMUL(c,
489 src[0 * 4 + i],
490 src[1 * 4 + i]),
491 src[2 * 4 + i]);
492 }
493
494 static struct qreg
495 tgsi_to_qir_lrp(struct vc4_compile *c,
496 struct tgsi_full_instruction *tgsi_inst,
497 enum qop op, struct qreg *src, int i)
498 {
499 struct qreg src0 = src[0 * 4 + i];
500 struct qreg src1 = src[1 * 4 + i];
501 struct qreg src2 = src[2 * 4 + i];
502
503 /* LRP is:
504 * src0 * src1 + (1 - src0) * src2.
505 * -> src0 * src1 + src2 - src0 * src2
506 * -> src2 + src0 * (src1 - src2)
507 */
508 return qir_FADD(c, src2, qir_FMUL(c, src0, qir_FSUB(c, src1, src2)));
509
510 }
511
512 static void
513 tgsi_to_qir_tex(struct vc4_compile *c,
514 struct tgsi_full_instruction *tgsi_inst,
515 enum qop op, struct qreg *src)
516 {
517 assert(!tgsi_inst->Instruction.Saturate);
518
519 struct qreg s = src[0 * 4 + 0];
520 struct qreg t = src[0 * 4 + 1];
521 struct qreg r = src[0 * 4 + 2];
522 uint32_t unit = tgsi_inst->Src[1].Register.Index;
523
524 struct qreg proj = c->undef;
525 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
526 proj = qir_RCP(c, src[0 * 4 + 3]);
527 s = qir_FMUL(c, s, proj);
528 t = qir_FMUL(c, t, proj);
529 }
530
531 struct qreg texture_u[] = {
532 add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit),
533 add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
534 add_uniform(c, QUNIFORM_CONSTANT, 0),
535 add_uniform(c, QUNIFORM_CONSTANT, 0),
536 };
537 uint32_t next_texture_u = 0;
538
539 /* There is no native support for GL texture rectangle coordinates, so
540 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
541 * 1]).
542 */
543 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_RECT ||
544 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT) {
545 s = qir_FMUL(c, s,
546 get_temp_for_uniform(c,
547 QUNIFORM_TEXRECT_SCALE_X,
548 unit));
549 t = qir_FMUL(c, t,
550 get_temp_for_uniform(c,
551 QUNIFORM_TEXRECT_SCALE_Y,
552 unit));
553 }
554
555 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
556 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE) {
557 struct qreg ma = qir_FMAXABS(c, qir_FMAXABS(c, s, t), r);
558 struct qreg rcp_ma = qir_RCP(c, ma);
559 s = qir_FMUL(c, s, rcp_ma);
560 t = qir_FMUL(c, t, rcp_ma);
561 r = qir_FMUL(c, r, rcp_ma);
562
563 texture_u[2] = add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P2, unit);
564
565 qir_TEX_R(c, r, texture_u[next_texture_u++]);
566 } else if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
567 c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP ||
568 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
569 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
570 qir_TEX_R(c, get_temp_for_uniform(c, QUNIFORM_TEXTURE_BORDER_COLOR, unit),
571 texture_u[next_texture_u++]);
572 }
573
574 if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP) {
575 s = qir_FMIN(c, qir_FMAX(c, s, qir_uniform_f(c, 0.0)),
576 qir_uniform_f(c, 1.0));
577 }
578
579 if (c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
580 t = qir_FMIN(c, qir_FMAX(c, t, qir_uniform_f(c, 0.0)),
581 qir_uniform_f(c, 1.0));
582 }
583
584 qir_TEX_T(c, t, texture_u[next_texture_u++]);
585
586 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB)
587 qir_TEX_B(c, src[0 * 4 + 3], texture_u[next_texture_u++]);
588
589 qir_TEX_S(c, s, texture_u[next_texture_u++]);
590
591 c->num_texture_samples++;
592 struct qreg r4 = qir_TEX_RESULT(c);
593
594 enum pipe_format format = c->key->tex[unit].format;
595
596 struct qreg unpacked[4];
597 if (util_format_is_depth_or_stencil(format)) {
598 struct qreg depthf = qir_ITOF(c, qir_SHR(c, r4,
599 qir_uniform_ui(c, 8)));
600 struct qreg normalized = qir_FMUL(c, depthf,
601 qir_uniform_f(c, 1.0f/0xffffff));
602
603 struct qreg depth_output;
604
605 struct qreg one = qir_uniform_f(c, 1.0f);
606 if (c->key->tex[unit].compare_mode) {
607 struct qreg compare = src[0 * 4 + 2];
608
609 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP)
610 compare = qir_FMUL(c, compare, proj);
611
612 switch (c->key->tex[unit].compare_func) {
613 case PIPE_FUNC_NEVER:
614 depth_output = qir_uniform_f(c, 0.0f);
615 break;
616 case PIPE_FUNC_ALWAYS:
617 depth_output = one;
618 break;
619 case PIPE_FUNC_EQUAL:
620 qir_SF(c, qir_FSUB(c, compare, normalized));
621 depth_output = qir_SEL_X_0_ZS(c, one);
622 break;
623 case PIPE_FUNC_NOTEQUAL:
624 qir_SF(c, qir_FSUB(c, compare, normalized));
625 depth_output = qir_SEL_X_0_ZC(c, one);
626 break;
627 case PIPE_FUNC_GREATER:
628 qir_SF(c, qir_FSUB(c, compare, normalized));
629 depth_output = qir_SEL_X_0_NC(c, one);
630 break;
631 case PIPE_FUNC_GEQUAL:
632 qir_SF(c, qir_FSUB(c, normalized, compare));
633 depth_output = qir_SEL_X_0_NS(c, one);
634 break;
635 case PIPE_FUNC_LESS:
636 qir_SF(c, qir_FSUB(c, compare, normalized));
637 depth_output = qir_SEL_X_0_NS(c, one);
638 break;
639 case PIPE_FUNC_LEQUAL:
640 qir_SF(c, qir_FSUB(c, normalized, compare));
641 depth_output = qir_SEL_X_0_NC(c, one);
642 break;
643 }
644 } else {
645 depth_output = normalized;
646 }
647
648 for (int i = 0; i < 4; i++)
649 unpacked[i] = depth_output;
650 } else {
651 for (int i = 0; i < 4; i++)
652 unpacked[i] = qir_R4_UNPACK(c, r4, i);
653 }
654
655 const uint8_t *format_swiz = vc4_get_format_swizzle(format);
656 struct qreg texture_output[4];
657 for (int i = 0; i < 4; i++) {
658 texture_output[i] = get_swizzled_channel(c, unpacked,
659 format_swiz[i]);
660 }
661
662 if (util_format_is_srgb(format)) {
663 for (int i = 0; i < 3; i++)
664 texture_output[i] = qir_srgb_decode(c,
665 texture_output[i]);
666 }
667
668 for (int i = 0; i < 4; i++) {
669 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
670 continue;
671
672 update_dst(c, tgsi_inst, i,
673 get_swizzled_channel(c, texture_output,
674 c->key->tex[unit].swizzle[i]));
675 }
676 }
677
678 static struct qreg
679 tgsi_to_qir_trunc(struct vc4_compile *c,
680 struct tgsi_full_instruction *tgsi_inst,
681 enum qop op, struct qreg *src, int i)
682 {
683 return qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
684 }
685
686 /**
687 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
688 * to zero).
689 */
690 static struct qreg
691 tgsi_to_qir_frc(struct vc4_compile *c,
692 struct tgsi_full_instruction *tgsi_inst,
693 enum qop op, struct qreg *src, int i)
694 {
695 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
696 struct qreg diff = qir_FSUB(c, src[0 * 4 + i], trunc);
697 qir_SF(c, diff);
698 return qir_SEL_X_Y_NS(c,
699 qir_FADD(c, diff, qir_uniform_f(c, 1.0)),
700 diff);
701 }
702
703 /**
704 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
705 * zero).
706 */
707 static struct qreg
708 tgsi_to_qir_flr(struct vc4_compile *c,
709 struct tgsi_full_instruction *tgsi_inst,
710 enum qop op, struct qreg *src, int i)
711 {
712 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
713
714 /* This will be < 0 if we truncated and the truncation was of a value
715 * that was < 0 in the first place.
716 */
717 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], trunc));
718
719 return qir_SEL_X_Y_NS(c,
720 qir_FSUB(c, trunc, qir_uniform_f(c, 1.0)),
721 trunc);
722 }
723
724 static struct qreg
725 tgsi_to_qir_abs(struct vc4_compile *c,
726 struct tgsi_full_instruction *tgsi_inst,
727 enum qop op, struct qreg *src, int i)
728 {
729 struct qreg arg = src[0 * 4 + i];
730 return qir_FMAXABS(c, arg, arg);
731 }
732
733 /* Note that this instruction replicates its result from the x channel */
734 static struct qreg
735 tgsi_to_qir_sin(struct vc4_compile *c,
736 struct tgsi_full_instruction *tgsi_inst,
737 enum qop op, struct qreg *src, int i)
738 {
739 float coeff[] = {
740 2.0 * M_PI,
741 -pow(2.0 * M_PI, 3) / (3 * 2 * 1),
742 pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
743 -pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
744 };
745
746 struct qreg scaled_x =
747 qir_FMUL(c,
748 src[0 * 4 + 0],
749 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
750
751
752 struct qreg x = tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0);
753 struct qreg x2 = qir_FMUL(c, x, x);
754 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
755 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
756 x = qir_FMUL(c, x, x2);
757 sum = qir_FADD(c,
758 sum,
759 qir_FMUL(c,
760 x,
761 qir_uniform_f(c, coeff[i])));
762 }
763 return sum;
764 }
765
766 /* Note that this instruction replicates its result from the x channel */
767 static struct qreg
768 tgsi_to_qir_cos(struct vc4_compile *c,
769 struct tgsi_full_instruction *tgsi_inst,
770 enum qop op, struct qreg *src, int i)
771 {
772 float coeff[] = {
773 1.0f,
774 -pow(2.0 * M_PI, 2) / (2 * 1),
775 pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
776 -pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
777 };
778
779 struct qreg scaled_x =
780 qir_FMUL(c, src[0 * 4 + 0],
781 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
782 struct qreg x_frac = tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0);
783
784 struct qreg sum = qir_uniform_f(c, coeff[0]);
785 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
786 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
787 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
788 if (i != 1)
789 x = qir_FMUL(c, x, x2);
790
791 struct qreg mul = qir_FMUL(c,
792 x,
793 qir_uniform_f(c, coeff[i]));
794 if (i == 0)
795 sum = mul;
796 else
797 sum = qir_FADD(c, sum, mul);
798 }
799 return sum;
800 }
801
802 static struct qreg
803 tgsi_to_qir_clamp(struct vc4_compile *c,
804 struct tgsi_full_instruction *tgsi_inst,
805 enum qop op, struct qreg *src, int i)
806 {
807 return qir_FMAX(c, qir_FMIN(c,
808 src[0 * 4 + i],
809 src[2 * 4 + i]),
810 src[1 * 4 + i]);
811 }
812
813 static void
814 emit_vertex_input(struct vc4_compile *c, int attr)
815 {
816 enum pipe_format format = c->vs_key->attr_formats[attr];
817 struct qreg vpm_reads[4];
818
819 /* Right now, we're setting the VPM offsets to be 16 bytes wide every
820 * time, so we always read 4 32-bit VPM entries.
821 */
822 for (int i = 0; i < 4; i++) {
823 vpm_reads[i] = qir_get_temp(c);
824 qir_emit(c, qir_inst(QOP_VPM_READ,
825 vpm_reads[i],
826 c->undef,
827 c->undef));
828 c->num_inputs++;
829 }
830
831 bool format_warned = false;
832 const struct util_format_description *desc =
833 util_format_description(format);
834
835 for (int i = 0; i < 4; i++) {
836 uint8_t swiz = desc->swizzle[i];
837 struct qreg result;
838
839 if (swiz > UTIL_FORMAT_SWIZZLE_W)
840 result = get_swizzled_channel(c, vpm_reads, swiz);
841 else if (desc->channel[swiz].size == 32 &&
842 desc->channel[swiz].type == UTIL_FORMAT_TYPE_FLOAT) {
843 result = get_swizzled_channel(c, vpm_reads, swiz);
844 } else if (desc->channel[swiz].size == 8 &&
845 (desc->channel[swiz].type == UTIL_FORMAT_TYPE_UNSIGNED ||
846 desc->channel[swiz].type == UTIL_FORMAT_TYPE_SIGNED) &&
847 desc->channel[swiz].normalized) {
848 struct qreg vpm = vpm_reads[0];
849 if (desc->channel[swiz].type == UTIL_FORMAT_TYPE_SIGNED)
850 vpm = qir_XOR(c, vpm, qir_uniform_ui(c, 0x80808080));
851 result = qir_UNPACK_8(c, vpm, swiz);
852 } else {
853 if (!format_warned) {
854 fprintf(stderr,
855 "vtx element %d unsupported type: %s\n",
856 attr, util_format_name(format));
857 format_warned = true;
858 }
859 result = qir_uniform_f(c, 0.0);
860 }
861
862 if (desc->channel[swiz].normalized &&
863 desc->channel[swiz].type == UTIL_FORMAT_TYPE_SIGNED) {
864 result = qir_FSUB(c,
865 qir_FMUL(c,
866 result,
867 qir_uniform_f(c, 2.0)),
868 qir_uniform_f(c, 1.0));
869 }
870
871 c->inputs[attr * 4 + i] = result;
872 }
873 }
874
875 static void
876 tgsi_to_qir_kill_if(struct vc4_compile *c, struct qreg *src, int i)
877 {
878 if (c->discard.file == QFILE_NULL)
879 c->discard = qir_uniform_f(c, 0.0);
880 qir_SF(c, src[0 * 4 + i]);
881 c->discard = qir_SEL_X_Y_NS(c, qir_uniform_f(c, 1.0),
882 c->discard);
883 }
884
885 static void
886 emit_fragcoord_input(struct vc4_compile *c, int attr)
887 {
888 c->inputs[attr * 4 + 0] = qir_FRAG_X(c);
889 c->inputs[attr * 4 + 1] = qir_FRAG_Y(c);
890 c->inputs[attr * 4 + 2] =
891 qir_FMUL(c,
892 qir_ITOF(c, qir_FRAG_Z(c)),
893 qir_uniform_f(c, 1.0 / 0xffffff));
894 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
895 }
896
897 static void
898 emit_point_coord_input(struct vc4_compile *c, int attr)
899 {
900 if (c->point_x.file == QFILE_NULL) {
901 c->point_x = qir_uniform_f(c, 0.0);
902 c->point_y = qir_uniform_f(c, 0.0);
903 }
904
905 c->inputs[attr * 4 + 0] = c->point_x;
906 if (c->fs_key->point_coord_upper_left) {
907 c->inputs[attr * 4 + 1] = qir_FSUB(c,
908 qir_uniform_f(c, 1.0),
909 c->point_y);
910 } else {
911 c->inputs[attr * 4 + 1] = c->point_y;
912 }
913 c->inputs[attr * 4 + 2] = qir_uniform_f(c, 0.0);
914 c->inputs[attr * 4 + 3] = qir_uniform_f(c, 1.0);
915 }
916
917 static struct qreg
918 emit_fragment_varying(struct vc4_compile *c, int index)
919 {
920 struct qreg vary = {
921 QFILE_VARY,
922 index
923 };
924
925 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
926 }
927
928 static void
929 emit_fragment_input(struct vc4_compile *c, int attr,
930 struct tgsi_full_declaration *decl)
931 {
932 for (int i = 0; i < 4; i++) {
933 c->inputs[attr * 4 + i] =
934 emit_fragment_varying(c, attr * 4 + i);
935 c->num_inputs++;
936
937 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR ||
938 decl->Semantic.Name == TGSI_SEMANTIC_BCOLOR)
939 c->color_inputs |= 1 << i;
940 }
941 }
942
943 static void
944 emit_face_input(struct vc4_compile *c, int attr)
945 {
946 c->inputs[attr * 4 + 0] = qir_FSUB(c,
947 qir_uniform_f(c, 1.0),
948 qir_FMUL(c,
949 qir_ITOF(c, qir_FRAG_REV_FLAG(c)),
950 qir_uniform_f(c, 2.0)));
951 c->inputs[attr * 4 + 1] = qir_uniform_f(c, 0.0);
952 c->inputs[attr * 4 + 2] = qir_uniform_f(c, 0.0);
953 c->inputs[attr * 4 + 3] = qir_uniform_f(c, 1.0);
954 }
955
956 static void
957 emit_tgsi_declaration(struct vc4_compile *c,
958 struct tgsi_full_declaration *decl)
959 {
960 switch (decl->Declaration.File) {
961 case TGSI_FILE_TEMPORARY: {
962 uint32_t old_size = c->temps_array_size;
963 resize_qreg_array(c, &c->temps, &c->temps_array_size,
964 (decl->Range.Last + 1) * 4);
965
966 for (int i = old_size; i < c->temps_array_size; i++)
967 c->temps[i] = qir_uniform_ui(c, 0);
968 break;
969 }
970
971 case TGSI_FILE_INPUT:
972 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
973 (decl->Range.Last + 1) * 4);
974
975 for (int i = decl->Range.First;
976 i <= decl->Range.Last;
977 i++) {
978 if (c->stage == QSTAGE_FRAG) {
979 if (decl->Semantic.Name ==
980 TGSI_SEMANTIC_POSITION) {
981 emit_fragcoord_input(c, i);
982 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
983 emit_face_input(c, i);
984 } else if (decl->Semantic.Name == TGSI_SEMANTIC_GENERIC &&
985 (c->fs_key->point_sprite_mask &
986 (1 << decl->Semantic.Index))) {
987 emit_point_coord_input(c, i);
988 } else {
989 emit_fragment_input(c, i, decl);
990 }
991 } else {
992 emit_vertex_input(c, i);
993 }
994 }
995 break;
996
997 case TGSI_FILE_OUTPUT:
998 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
999 (decl->Range.Last + 1) * 4);
1000
1001 switch (decl->Semantic.Name) {
1002 case TGSI_SEMANTIC_POSITION:
1003 c->output_position_index = decl->Range.First * 4;
1004 break;
1005 case TGSI_SEMANTIC_COLOR:
1006 c->output_color_index = decl->Range.First * 4;
1007 break;
1008 case TGSI_SEMANTIC_PSIZE:
1009 c->output_point_size_index = decl->Range.First * 4;
1010 break;
1011 }
1012
1013 break;
1014 }
1015 }
1016
1017 static void
1018 emit_tgsi_instruction(struct vc4_compile *c,
1019 struct tgsi_full_instruction *tgsi_inst)
1020 {
1021 struct {
1022 enum qop op;
1023 struct qreg (*func)(struct vc4_compile *c,
1024 struct tgsi_full_instruction *tgsi_inst,
1025 enum qop op,
1026 struct qreg *src, int i);
1027 } op_trans[] = {
1028 [TGSI_OPCODE_MOV] = { QOP_MOV, tgsi_to_qir_alu },
1029 [TGSI_OPCODE_ABS] = { 0, tgsi_to_qir_abs },
1030 [TGSI_OPCODE_MUL] = { QOP_FMUL, tgsi_to_qir_alu },
1031 [TGSI_OPCODE_ADD] = { QOP_FADD, tgsi_to_qir_alu },
1032 [TGSI_OPCODE_SUB] = { QOP_FSUB, tgsi_to_qir_alu },
1033 [TGSI_OPCODE_MIN] = { QOP_FMIN, tgsi_to_qir_alu },
1034 [TGSI_OPCODE_MAX] = { QOP_FMAX, tgsi_to_qir_alu },
1035 [TGSI_OPCODE_F2I] = { QOP_FTOI, tgsi_to_qir_alu },
1036 [TGSI_OPCODE_I2F] = { QOP_ITOF, tgsi_to_qir_alu },
1037 [TGSI_OPCODE_UADD] = { QOP_ADD, tgsi_to_qir_alu },
1038 [TGSI_OPCODE_USHR] = { QOP_SHR, tgsi_to_qir_alu },
1039 [TGSI_OPCODE_ISHR] = { QOP_ASR, tgsi_to_qir_alu },
1040 [TGSI_OPCODE_SHL] = { QOP_SHL, tgsi_to_qir_alu },
1041 [TGSI_OPCODE_IMIN] = { QOP_MIN, tgsi_to_qir_alu },
1042 [TGSI_OPCODE_IMAX] = { QOP_MAX, tgsi_to_qir_alu },
1043 [TGSI_OPCODE_AND] = { QOP_AND, tgsi_to_qir_alu },
1044 [TGSI_OPCODE_OR] = { QOP_OR, tgsi_to_qir_alu },
1045 [TGSI_OPCODE_XOR] = { QOP_XOR, tgsi_to_qir_alu },
1046 [TGSI_OPCODE_NOT] = { QOP_NOT, tgsi_to_qir_alu },
1047
1048 [TGSI_OPCODE_UMUL] = { 0, tgsi_to_qir_umul },
1049 [TGSI_OPCODE_IDIV] = { 0, tgsi_to_qir_idiv },
1050 [TGSI_OPCODE_INEG] = { 0, tgsi_to_qir_ineg },
1051
1052 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_alu },
1053 [TGSI_OPCODE_SEQ] = { 0, tgsi_to_qir_seq },
1054 [TGSI_OPCODE_SNE] = { 0, tgsi_to_qir_sne },
1055 [TGSI_OPCODE_SGE] = { 0, tgsi_to_qir_sge },
1056 [TGSI_OPCODE_SLT] = { 0, tgsi_to_qir_slt },
1057 [TGSI_OPCODE_FSEQ] = { 0, tgsi_to_qir_fseq },
1058 [TGSI_OPCODE_FSNE] = { 0, tgsi_to_qir_fsne },
1059 [TGSI_OPCODE_FSGE] = { 0, tgsi_to_qir_fsge },
1060 [TGSI_OPCODE_FSLT] = { 0, tgsi_to_qir_fslt },
1061 [TGSI_OPCODE_USEQ] = { 0, tgsi_to_qir_useq },
1062 [TGSI_OPCODE_USNE] = { 0, tgsi_to_qir_usne },
1063 [TGSI_OPCODE_ISGE] = { 0, tgsi_to_qir_isge },
1064 [TGSI_OPCODE_ISLT] = { 0, tgsi_to_qir_islt },
1065
1066 [TGSI_OPCODE_CMP] = { 0, tgsi_to_qir_cmp },
1067 [TGSI_OPCODE_MAD] = { 0, tgsi_to_qir_mad },
1068 [TGSI_OPCODE_RCP] = { QOP_RCP, tgsi_to_qir_scalar },
1069 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_scalar },
1070 [TGSI_OPCODE_EX2] = { QOP_EXP2, tgsi_to_qir_scalar },
1071 [TGSI_OPCODE_LG2] = { QOP_LOG2, tgsi_to_qir_scalar },
1072 [TGSI_OPCODE_LRP] = { 0, tgsi_to_qir_lrp },
1073 [TGSI_OPCODE_TRUNC] = { 0, tgsi_to_qir_trunc },
1074 [TGSI_OPCODE_FRC] = { 0, tgsi_to_qir_frc },
1075 [TGSI_OPCODE_FLR] = { 0, tgsi_to_qir_flr },
1076 [TGSI_OPCODE_SIN] = { 0, tgsi_to_qir_sin },
1077 [TGSI_OPCODE_COS] = { 0, tgsi_to_qir_cos },
1078 [TGSI_OPCODE_CLAMP] = { 0, tgsi_to_qir_clamp },
1079 };
1080 static int asdf = 0;
1081 uint32_t tgsi_op = tgsi_inst->Instruction.Opcode;
1082
1083 if (tgsi_op == TGSI_OPCODE_END)
1084 return;
1085
1086 struct qreg src_regs[12];
1087 for (int s = 0; s < 3; s++) {
1088 for (int i = 0; i < 4; i++) {
1089 src_regs[4 * s + i] =
1090 get_src(c, tgsi_inst->Instruction.Opcode,
1091 &tgsi_inst->Src[s].Register, i);
1092 }
1093 }
1094
1095 switch (tgsi_op) {
1096 case TGSI_OPCODE_TEX:
1097 case TGSI_OPCODE_TXP:
1098 case TGSI_OPCODE_TXB:
1099 tgsi_to_qir_tex(c, tgsi_inst,
1100 op_trans[tgsi_op].op, src_regs);
1101 return;
1102 case TGSI_OPCODE_KILL:
1103 c->discard = qir_uniform_f(c, 1.0);
1104 return;
1105 case TGSI_OPCODE_KILL_IF:
1106 for (int i = 0; i < 4; i++)
1107 tgsi_to_qir_kill_if(c, src_regs, i);
1108 return;
1109 default:
1110 break;
1111 }
1112
1113 if (tgsi_op > ARRAY_SIZE(op_trans) || !(op_trans[tgsi_op].func)) {
1114 fprintf(stderr, "unknown tgsi inst: ");
1115 tgsi_dump_instruction(tgsi_inst, asdf++);
1116 fprintf(stderr, "\n");
1117 abort();
1118 }
1119
1120 for (int i = 0; i < 4; i++) {
1121 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
1122 continue;
1123
1124 struct qreg result;
1125
1126 result = op_trans[tgsi_op].func(c, tgsi_inst,
1127 op_trans[tgsi_op].op,
1128 src_regs, i);
1129
1130 if (tgsi_inst->Instruction.Saturate) {
1131 float low = (tgsi_inst->Instruction.Saturate ==
1132 TGSI_SAT_MINUS_PLUS_ONE ? -1.0 : 0.0);
1133 result = qir_FMAX(c,
1134 qir_FMIN(c,
1135 result,
1136 qir_uniform_f(c, 1.0)),
1137 qir_uniform_f(c, low));
1138 }
1139
1140 update_dst(c, tgsi_inst, i, result);
1141 }
1142 }
1143
1144 static void
1145 parse_tgsi_immediate(struct vc4_compile *c, struct tgsi_full_immediate *imm)
1146 {
1147 for (int i = 0; i < 4; i++) {
1148 unsigned n = c->num_consts++;
1149 resize_qreg_array(c, &c->consts, &c->consts_array_size, n + 1);
1150 c->consts[n] = qir_uniform_ui(c, imm->u[i].Uint);
1151 }
1152 }
1153
1154 static struct qreg
1155 vc4_blend_channel(struct vc4_compile *c,
1156 struct qreg *dst,
1157 struct qreg *src,
1158 struct qreg val,
1159 unsigned factor,
1160 int channel)
1161 {
1162 switch(factor) {
1163 case PIPE_BLENDFACTOR_ONE:
1164 return val;
1165 case PIPE_BLENDFACTOR_SRC_COLOR:
1166 return qir_FMUL(c, val, src[channel]);
1167 case PIPE_BLENDFACTOR_SRC_ALPHA:
1168 return qir_FMUL(c, val, src[3]);
1169 case PIPE_BLENDFACTOR_DST_ALPHA:
1170 return qir_FMUL(c, val, dst[3]);
1171 case PIPE_BLENDFACTOR_DST_COLOR:
1172 return qir_FMUL(c, val, dst[channel]);
1173 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
1174 return qir_FMIN(c, src[3], qir_FSUB(c,
1175 qir_uniform_f(c, 1.0),
1176 dst[3]));
1177 case PIPE_BLENDFACTOR_CONST_COLOR:
1178 return qir_FMUL(c, val,
1179 get_temp_for_uniform(c,
1180 QUNIFORM_BLEND_CONST_COLOR,
1181 channel));
1182 case PIPE_BLENDFACTOR_CONST_ALPHA:
1183 return qir_FMUL(c, val,
1184 get_temp_for_uniform(c,
1185 QUNIFORM_BLEND_CONST_COLOR,
1186 3));
1187 case PIPE_BLENDFACTOR_ZERO:
1188 return qir_uniform_f(c, 0.0);
1189 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
1190 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1191 src[channel]));
1192 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
1193 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1194 src[3]));
1195 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
1196 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1197 dst[3]));
1198 case PIPE_BLENDFACTOR_INV_DST_COLOR:
1199 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1200 dst[channel]));
1201 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
1202 return qir_FMUL(c, val,
1203 qir_FSUB(c, qir_uniform_f(c, 1.0),
1204 get_temp_for_uniform(c,
1205 QUNIFORM_BLEND_CONST_COLOR,
1206 channel)));
1207 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
1208 return qir_FMUL(c, val,
1209 qir_FSUB(c, qir_uniform_f(c, 1.0),
1210 get_temp_for_uniform(c,
1211 QUNIFORM_BLEND_CONST_COLOR,
1212 3)));
1213
1214 default:
1215 case PIPE_BLENDFACTOR_SRC1_COLOR:
1216 case PIPE_BLENDFACTOR_SRC1_ALPHA:
1217 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
1218 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
1219 /* Unsupported. */
1220 fprintf(stderr, "Unknown blend factor %d\n", factor);
1221 return val;
1222 }
1223 }
1224
1225 static struct qreg
1226 vc4_blend_func(struct vc4_compile *c,
1227 struct qreg src, struct qreg dst,
1228 unsigned func)
1229 {
1230 switch (func) {
1231 case PIPE_BLEND_ADD:
1232 return qir_FADD(c, src, dst);
1233 case PIPE_BLEND_SUBTRACT:
1234 return qir_FSUB(c, src, dst);
1235 case PIPE_BLEND_REVERSE_SUBTRACT:
1236 return qir_FSUB(c, dst, src);
1237 case PIPE_BLEND_MIN:
1238 return qir_FMIN(c, src, dst);
1239 case PIPE_BLEND_MAX:
1240 return qir_FMAX(c, src, dst);
1241
1242 default:
1243 /* Unsupported. */
1244 fprintf(stderr, "Unknown blend func %d\n", func);
1245 return src;
1246
1247 }
1248 }
1249
1250 /**
1251 * Implements fixed function blending in shader code.
1252 *
1253 * VC4 doesn't have any hardware support for blending. Instead, you read the
1254 * current contents of the destination from the tile buffer after having
1255 * waited for the scoreboard (which is handled by vc4_qpu_emit.c), then do
1256 * math using your output color and that destination value, and update the
1257 * output color appropriately.
1258 */
1259 static void
1260 vc4_blend(struct vc4_compile *c, struct qreg *result,
1261 struct qreg *dst_color, struct qreg *src_color)
1262 {
1263 struct pipe_rt_blend_state *blend = &c->fs_key->blend;
1264
1265 if (!blend->blend_enable) {
1266 for (int i = 0; i < 4; i++)
1267 result[i] = src_color[i];
1268 return;
1269 }
1270
1271 struct qreg src_blend[4], dst_blend[4];
1272 for (int i = 0; i < 3; i++) {
1273 src_blend[i] = vc4_blend_channel(c,
1274 dst_color, src_color,
1275 src_color[i],
1276 blend->rgb_src_factor, i);
1277 dst_blend[i] = vc4_blend_channel(c,
1278 dst_color, src_color,
1279 dst_color[i],
1280 blend->rgb_dst_factor, i);
1281 }
1282 src_blend[3] = vc4_blend_channel(c,
1283 dst_color, src_color,
1284 src_color[3],
1285 blend->alpha_src_factor, 3);
1286 dst_blend[3] = vc4_blend_channel(c,
1287 dst_color, src_color,
1288 dst_color[3],
1289 blend->alpha_dst_factor, 3);
1290
1291 for (int i = 0; i < 3; i++) {
1292 result[i] = vc4_blend_func(c,
1293 src_blend[i], dst_blend[i],
1294 blend->rgb_func);
1295 }
1296 result[3] = vc4_blend_func(c,
1297 src_blend[3], dst_blend[3],
1298 blend->alpha_func);
1299 }
1300
1301 static void
1302 alpha_test_discard(struct vc4_compile *c)
1303 {
1304 struct qreg src_alpha;
1305 struct qreg alpha_ref = get_temp_for_uniform(c, QUNIFORM_ALPHA_REF, 0);
1306
1307 if (!c->fs_key->alpha_test)
1308 return;
1309
1310 if (c->output_color_index != -1)
1311 src_alpha = c->outputs[c->output_color_index + 3];
1312 else
1313 src_alpha = qir_uniform_f(c, 1.0);
1314
1315 if (c->discard.file == QFILE_NULL)
1316 c->discard = qir_uniform_f(c, 0.0);
1317
1318 switch (c->fs_key->alpha_test_func) {
1319 case PIPE_FUNC_NEVER:
1320 c->discard = qir_uniform_f(c, 1.0);
1321 break;
1322 case PIPE_FUNC_ALWAYS:
1323 break;
1324 case PIPE_FUNC_EQUAL:
1325 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1326 c->discard = qir_SEL_X_Y_ZS(c, c->discard,
1327 qir_uniform_f(c, 1.0));
1328 break;
1329 case PIPE_FUNC_NOTEQUAL:
1330 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1331 c->discard = qir_SEL_X_Y_ZC(c, c->discard,
1332 qir_uniform_f(c, 1.0));
1333 break;
1334 case PIPE_FUNC_GREATER:
1335 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1336 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1337 qir_uniform_f(c, 1.0));
1338 break;
1339 case PIPE_FUNC_GEQUAL:
1340 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1341 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1342 qir_uniform_f(c, 1.0));
1343 break;
1344 case PIPE_FUNC_LESS:
1345 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1346 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1347 qir_uniform_f(c, 1.0));
1348 break;
1349 case PIPE_FUNC_LEQUAL:
1350 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1351 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1352 qir_uniform_f(c, 1.0));
1353 break;
1354 }
1355 }
1356
1357 static void
1358 emit_frag_end(struct vc4_compile *c)
1359 {
1360 alpha_test_discard(c);
1361
1362 enum pipe_format color_format = c->fs_key->color_format;
1363 const uint8_t *format_swiz = vc4_get_format_swizzle(color_format);
1364 struct qreg tlb_read_color[4] = { c->undef, c->undef, c->undef, c->undef };
1365 struct qreg dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1366 struct qreg linear_dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1367 if (c->fs_key->blend.blend_enable ||
1368 c->fs_key->blend.colormask != 0xf) {
1369 struct qreg r4 = qir_TLB_COLOR_READ(c);
1370 for (int i = 0; i < 4; i++)
1371 tlb_read_color[i] = qir_R4_UNPACK(c, r4, i);
1372 for (int i = 0; i < 4; i++) {
1373 dst_color[i] = get_swizzled_channel(c,
1374 tlb_read_color,
1375 format_swiz[i]);
1376 if (util_format_is_srgb(color_format) && i != 3) {
1377 linear_dst_color[i] =
1378 qir_srgb_decode(c, dst_color[i]);
1379 } else {
1380 linear_dst_color[i] = dst_color[i];
1381 }
1382 }
1383 }
1384
1385 struct qreg blend_color[4];
1386 struct qreg undef_array[4] = {
1387 c->undef, c->undef, c->undef, c->undef
1388 };
1389 vc4_blend(c, blend_color, linear_dst_color,
1390 (c->output_color_index != -1 ?
1391 c->outputs + c->output_color_index :
1392 undef_array));
1393
1394 if (util_format_is_srgb(color_format)) {
1395 for (int i = 0; i < 3; i++)
1396 blend_color[i] = qir_srgb_encode(c, blend_color[i]);
1397 }
1398
1399 /* If the bit isn't set in the color mask, then just return the
1400 * original dst color, instead.
1401 */
1402 for (int i = 0; i < 4; i++) {
1403 if (!(c->fs_key->blend.colormask & (1 << i))) {
1404 blend_color[i] = dst_color[i];
1405 }
1406 }
1407
1408 /* Debug: Sometimes you're getting a black output and just want to see
1409 * if the FS is getting executed at all. Spam magenta into the color
1410 * output.
1411 */
1412 if (0) {
1413 blend_color[0] = qir_uniform_f(c, 1.0);
1414 blend_color[1] = qir_uniform_f(c, 0.0);
1415 blend_color[2] = qir_uniform_f(c, 1.0);
1416 blend_color[3] = qir_uniform_f(c, 0.5);
1417 }
1418
1419 struct qreg swizzled_outputs[4];
1420 for (int i = 0; i < 4; i++) {
1421 swizzled_outputs[i] = get_swizzled_channel(c, blend_color,
1422 format_swiz[i]);
1423 }
1424
1425 if (c->discard.file != QFILE_NULL)
1426 qir_TLB_DISCARD_SETUP(c, c->discard);
1427
1428 if (c->fs_key->stencil_enabled) {
1429 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 0));
1430 if (c->fs_key->stencil_twoside) {
1431 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 1));
1432 }
1433 if (c->fs_key->stencil_full_writemasks) {
1434 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 2));
1435 }
1436 }
1437
1438 if (c->fs_key->depth_enabled) {
1439 struct qreg z;
1440 if (c->output_position_index != -1) {
1441 z = qir_FTOI(c, qir_FMUL(c, c->outputs[c->output_position_index + 2],
1442 qir_uniform_f(c, 0xffffff)));
1443 } else {
1444 z = qir_FRAG_Z(c);
1445 }
1446 qir_TLB_Z_WRITE(c, z);
1447 }
1448
1449 bool color_written = false;
1450 for (int i = 0; i < 4; i++) {
1451 if (swizzled_outputs[i].file != QFILE_NULL)
1452 color_written = true;
1453 }
1454
1455 struct qreg packed_color;
1456 if (color_written) {
1457 /* Fill in any undefined colors. The simulator will assertion
1458 * fail if we read something that wasn't written, and I don't
1459 * know what hardware does.
1460 */
1461 for (int i = 0; i < 4; i++) {
1462 if (swizzled_outputs[i].file == QFILE_NULL)
1463 swizzled_outputs[i] = qir_uniform_f(c, 0.0);
1464 }
1465 packed_color = qir_get_temp(c);
1466 qir_emit(c, qir_inst4(QOP_PACK_COLORS, packed_color,
1467 swizzled_outputs[0],
1468 swizzled_outputs[1],
1469 swizzled_outputs[2],
1470 swizzled_outputs[3]));
1471 } else {
1472 packed_color = qir_uniform_ui(c, 0);
1473 }
1474
1475 qir_emit(c, qir_inst(QOP_TLB_COLOR_WRITE, c->undef,
1476 packed_color, c->undef));
1477 }
1478
1479 static void
1480 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1481 {
1482 struct qreg xyi[2];
1483
1484 for (int i = 0; i < 2; i++) {
1485 struct qreg scale =
1486 add_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1487
1488 xyi[i] = qir_FTOI(c, qir_FMUL(c,
1489 qir_FMUL(c,
1490 c->outputs[i],
1491 scale),
1492 rcp_w));
1493 }
1494
1495 qir_VPM_WRITE(c, qir_PACK_SCALED(c, xyi[0], xyi[1]));
1496 }
1497
1498 static void
1499 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1500 {
1501 struct qreg zscale = add_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1502 struct qreg zoffset = add_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1503
1504 qir_VPM_WRITE(c, qir_FMUL(c, qir_FADD(c, qir_FMUL(c,
1505 c->outputs[2],
1506 zscale),
1507 zoffset),
1508 rcp_w));
1509 }
1510
1511 static void
1512 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1513 {
1514 qir_VPM_WRITE(c, rcp_w);
1515 }
1516
1517 static void
1518 emit_point_size_write(struct vc4_compile *c)
1519 {
1520 struct qreg point_size;
1521
1522 if (c->output_point_size_index)
1523 point_size = c->outputs[c->output_point_size_index + 3];
1524 else
1525 point_size = qir_uniform_f(c, 1.0);
1526
1527 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1528 * BCM21553).
1529 */
1530 point_size = qir_FMAX(c, point_size, qir_uniform_f(c, .125));
1531
1532 qir_VPM_WRITE(c, point_size);
1533 }
1534
1535 static void
1536 emit_vert_end(struct vc4_compile *c)
1537 {
1538 struct qreg rcp_w = qir_RCP(c, c->outputs[3]);
1539
1540 emit_scaled_viewport_write(c, rcp_w);
1541 emit_zs_write(c, rcp_w);
1542 emit_rcp_wc_write(c, rcp_w);
1543 if (c->vs_key->per_vertex_point_size)
1544 emit_point_size_write(c);
1545
1546 for (int i = 4; i < c->num_outputs; i++) {
1547 qir_VPM_WRITE(c, c->outputs[i]);
1548 }
1549 }
1550
1551 static void
1552 emit_coord_end(struct vc4_compile *c)
1553 {
1554 struct qreg rcp_w = qir_RCP(c, c->outputs[3]);
1555
1556 for (int i = 0; i < 4; i++)
1557 qir_VPM_WRITE(c, c->outputs[i]);
1558
1559 emit_scaled_viewport_write(c, rcp_w);
1560 emit_zs_write(c, rcp_w);
1561 emit_rcp_wc_write(c, rcp_w);
1562 if (c->vs_key->per_vertex_point_size)
1563 emit_point_size_write(c);
1564 }
1565
1566 static struct vc4_compile *
1567 vc4_shader_tgsi_to_qir(struct vc4_context *vc4, enum qstage stage,
1568 struct vc4_key *key)
1569 {
1570 struct vc4_compile *c = qir_compile_init();
1571 int ret;
1572
1573 c->stage = stage;
1574 c->shader_state = &key->shader_state->base;
1575
1576 c->key = key;
1577 switch (stage) {
1578 case QSTAGE_FRAG:
1579 c->fs_key = (struct vc4_fs_key *)key;
1580 if (c->fs_key->is_points) {
1581 c->point_x = emit_fragment_varying(c, 0);
1582 c->point_y = emit_fragment_varying(c, 0);
1583 } else if (c->fs_key->is_lines) {
1584 c->line_x = emit_fragment_varying(c, 0);
1585 }
1586 break;
1587 case QSTAGE_VERT:
1588 c->vs_key = (struct vc4_vs_key *)key;
1589 break;
1590 case QSTAGE_COORD:
1591 c->vs_key = (struct vc4_vs_key *)key;
1592 break;
1593 }
1594
1595 const struct tgsi_token *tokens = key->shader_state->base.tokens;
1596 if (c->fs_key && c->fs_key->light_twoside) {
1597 if (!key->shader_state->twoside_tokens) {
1598 const struct tgsi_lowering_config lowering_config = {
1599 .color_two_side = true,
1600 };
1601 struct tgsi_shader_info info;
1602 key->shader_state->twoside_tokens =
1603 tgsi_transform_lowering(&lowering_config,
1604 key->shader_state->base.tokens,
1605 &info);
1606
1607 /* If no transformation occurred, then NULL is
1608 * returned and we just use our original tokens.
1609 */
1610 if (!key->shader_state->twoside_tokens) {
1611 key->shader_state->twoside_tokens =
1612 key->shader_state->base.tokens;
1613 }
1614 }
1615 tokens = key->shader_state->twoside_tokens;
1616 }
1617
1618 ret = tgsi_parse_init(&c->parser, tokens);
1619 assert(ret == TGSI_PARSE_OK);
1620
1621 if (vc4_debug & VC4_DEBUG_TGSI) {
1622 fprintf(stderr, "TGSI:\n");
1623 tgsi_dump(tokens, 0);
1624 }
1625
1626 while (!tgsi_parse_end_of_tokens(&c->parser)) {
1627 tgsi_parse_token(&c->parser);
1628
1629 switch (c->parser.FullToken.Token.Type) {
1630 case TGSI_TOKEN_TYPE_DECLARATION:
1631 emit_tgsi_declaration(c,
1632 &c->parser.FullToken.FullDeclaration);
1633 break;
1634
1635 case TGSI_TOKEN_TYPE_INSTRUCTION:
1636 emit_tgsi_instruction(c,
1637 &c->parser.FullToken.FullInstruction);
1638 break;
1639
1640 case TGSI_TOKEN_TYPE_IMMEDIATE:
1641 parse_tgsi_immediate(c,
1642 &c->parser.FullToken.FullImmediate);
1643 break;
1644 }
1645 }
1646
1647 switch (stage) {
1648 case QSTAGE_FRAG:
1649 emit_frag_end(c);
1650 break;
1651 case QSTAGE_VERT:
1652 emit_vert_end(c);
1653 break;
1654 case QSTAGE_COORD:
1655 emit_coord_end(c);
1656 break;
1657 }
1658
1659 tgsi_parse_free(&c->parser);
1660
1661 qir_optimize(c);
1662
1663 if (vc4_debug & VC4_DEBUG_QIR) {
1664 fprintf(stderr, "QIR:\n");
1665 qir_dump(c);
1666 }
1667 qir_reorder_uniforms(c);
1668 vc4_generate_code(vc4, c);
1669
1670 if (vc4_debug & VC4_DEBUG_SHADERDB) {
1671 fprintf(stderr, "SHADER-DB: %s: %d instructions\n",
1672 qir_get_stage_name(c->stage), c->qpu_inst_count);
1673 fprintf(stderr, "SHADER-DB: %s: %d uniforms\n",
1674 qir_get_stage_name(c->stage), c->num_uniforms);
1675 }
1676
1677 return c;
1678 }
1679
1680 static void *
1681 vc4_shader_state_create(struct pipe_context *pctx,
1682 const struct pipe_shader_state *cso)
1683 {
1684 struct vc4_uncompiled_shader *so = CALLOC_STRUCT(vc4_uncompiled_shader);
1685 if (!so)
1686 return NULL;
1687
1688 const struct tgsi_lowering_config lowering_config = {
1689 .lower_DST = true,
1690 .lower_XPD = true,
1691 .lower_SCS = true,
1692 .lower_POW = true,
1693 .lower_LIT = true,
1694 .lower_EXP = true,
1695 .lower_LOG = true,
1696 .lower_DP4 = true,
1697 .lower_DP3 = true,
1698 .lower_DPH = true,
1699 .lower_DP2 = true,
1700 .lower_DP2A = true,
1701 };
1702
1703 struct tgsi_shader_info info;
1704 so->base.tokens = tgsi_transform_lowering(&lowering_config, cso->tokens, &info);
1705 if (!so->base.tokens)
1706 so->base.tokens = tgsi_dup_tokens(cso->tokens);
1707
1708 return so;
1709 }
1710
1711 static void
1712 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
1713 struct vc4_compile *c)
1714 {
1715 int count = c->num_uniforms;
1716 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
1717
1718 uinfo->count = count;
1719 uinfo->data = ralloc_array(shader, uint32_t, count);
1720 memcpy(uinfo->data, c->uniform_data,
1721 count * sizeof(*uinfo->data));
1722 uinfo->contents = ralloc_array(shader, enum quniform_contents, count);
1723 memcpy(uinfo->contents, c->uniform_contents,
1724 count * sizeof(*uinfo->contents));
1725 uinfo->num_texture_samples = c->num_texture_samples;
1726 }
1727
1728 static struct vc4_compiled_shader *
1729 vc4_get_compiled_shader(struct vc4_context *vc4, enum qstage stage,
1730 struct vc4_key *key)
1731 {
1732 struct util_hash_table *ht;
1733 uint32_t key_size;
1734 if (stage == QSTAGE_FRAG) {
1735 ht = vc4->fs_cache;
1736 key_size = sizeof(struct vc4_fs_key);
1737 } else {
1738 ht = vc4->vs_cache;
1739 key_size = sizeof(struct vc4_vs_key);
1740 }
1741
1742 struct vc4_compiled_shader *shader;
1743 shader = util_hash_table_get(ht, key);
1744 if (shader)
1745 return shader;
1746
1747 struct vc4_compile *c = vc4_shader_tgsi_to_qir(vc4, stage, key);
1748 shader = rzalloc(NULL, struct vc4_compiled_shader);
1749
1750 shader->num_inputs = c->num_inputs;
1751 shader->color_inputs = c->color_inputs;
1752 copy_uniform_state_to_shader(shader, c);
1753 shader->bo = vc4_bo_alloc_mem(vc4->screen, c->qpu_insts,
1754 c->qpu_inst_count * sizeof(uint64_t),
1755 "code");
1756
1757 qir_compile_destroy(c);
1758
1759 struct vc4_key *dup_key;
1760 dup_key = malloc(key_size);
1761 memcpy(dup_key, key, key_size);
1762 util_hash_table_set(ht, dup_key, shader);
1763
1764 return shader;
1765 }
1766
1767 static void
1768 vc4_setup_shared_key(struct vc4_key *key, struct vc4_texture_stateobj *texstate)
1769 {
1770 for (int i = 0; i < texstate->num_textures; i++) {
1771 struct pipe_sampler_view *sampler = texstate->textures[i];
1772 struct pipe_sampler_state *sampler_state =
1773 texstate->samplers[i];
1774
1775 if (sampler) {
1776 key->tex[i].format = sampler->format;
1777 key->tex[i].swizzle[0] = sampler->swizzle_r;
1778 key->tex[i].swizzle[1] = sampler->swizzle_g;
1779 key->tex[i].swizzle[2] = sampler->swizzle_b;
1780 key->tex[i].swizzle[3] = sampler->swizzle_a;
1781 key->tex[i].compare_mode = sampler_state->compare_mode;
1782 key->tex[i].compare_func = sampler_state->compare_func;
1783 key->tex[i].wrap_s = sampler_state->wrap_s;
1784 key->tex[i].wrap_t = sampler_state->wrap_t;
1785 }
1786 }
1787 }
1788
1789 static void
1790 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
1791 {
1792 struct vc4_fs_key local_key;
1793 struct vc4_fs_key *key = &local_key;
1794
1795 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
1796 VC4_DIRTY_BLEND |
1797 VC4_DIRTY_FRAMEBUFFER |
1798 VC4_DIRTY_ZSA |
1799 VC4_DIRTY_RASTERIZER |
1800 VC4_DIRTY_FRAGTEX |
1801 VC4_DIRTY_TEXSTATE |
1802 VC4_DIRTY_PROG))) {
1803 return;
1804 }
1805
1806 memset(key, 0, sizeof(*key));
1807 vc4_setup_shared_key(&key->base, &vc4->fragtex);
1808 key->base.shader_state = vc4->prog.bind_fs;
1809 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
1810 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
1811 prim_mode <= PIPE_PRIM_LINE_STRIP);
1812 key->blend = vc4->blend->rt[0];
1813
1814 if (vc4->framebuffer.cbufs[0])
1815 key->color_format = vc4->framebuffer.cbufs[0]->format;
1816
1817 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
1818 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
1819 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
1820 key->depth_enabled = (vc4->zsa->base.depth.enabled ||
1821 key->stencil_enabled);
1822 if (vc4->zsa->base.alpha.enabled) {
1823 key->alpha_test = true;
1824 key->alpha_test_func = vc4->zsa->base.alpha.func;
1825 }
1826
1827 if (key->is_points) {
1828 key->point_sprite_mask =
1829 vc4->rasterizer->base.sprite_coord_enable;
1830 key->point_coord_upper_left =
1831 (vc4->rasterizer->base.sprite_coord_mode ==
1832 PIPE_SPRITE_COORD_UPPER_LEFT);
1833 }
1834
1835 key->light_twoside = vc4->rasterizer->base.light_twoside;
1836
1837 struct vc4_compiled_shader *old_fs = vc4->prog.fs;
1838 vc4->prog.fs = vc4_get_compiled_shader(vc4, QSTAGE_FRAG, &key->base);
1839 if (vc4->prog.fs == old_fs)
1840 return;
1841
1842 if (vc4->rasterizer->base.flatshade &&
1843 old_fs && vc4->prog.fs->color_inputs != old_fs->color_inputs) {
1844 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
1845 }
1846 }
1847
1848 static void
1849 vc4_update_compiled_vs(struct vc4_context *vc4, uint8_t prim_mode)
1850 {
1851 struct vc4_vs_key local_key;
1852 struct vc4_vs_key *key = &local_key;
1853
1854 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
1855 VC4_DIRTY_RASTERIZER |
1856 VC4_DIRTY_VERTTEX |
1857 VC4_DIRTY_TEXSTATE |
1858 VC4_DIRTY_VTXSTATE |
1859 VC4_DIRTY_PROG))) {
1860 return;
1861 }
1862
1863 memset(key, 0, sizeof(*key));
1864 vc4_setup_shared_key(&key->base, &vc4->verttex);
1865 key->base.shader_state = vc4->prog.bind_vs;
1866
1867 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
1868 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
1869
1870 key->per_vertex_point_size =
1871 (prim_mode == PIPE_PRIM_POINTS &&
1872 vc4->rasterizer->base.point_size_per_vertex);
1873
1874 vc4->prog.vs = vc4_get_compiled_shader(vc4, QSTAGE_VERT, &key->base);
1875 key->is_coord = true;
1876 vc4->prog.cs = vc4_get_compiled_shader(vc4, QSTAGE_COORD, &key->base);
1877 }
1878
1879 void
1880 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
1881 {
1882 vc4_update_compiled_fs(vc4, prim_mode);
1883 vc4_update_compiled_vs(vc4, prim_mode);
1884 }
1885
1886 static unsigned
1887 fs_cache_hash(void *key)
1888 {
1889 return util_hash_crc32(key, sizeof(struct vc4_fs_key));
1890 }
1891
1892 static unsigned
1893 vs_cache_hash(void *key)
1894 {
1895 return util_hash_crc32(key, sizeof(struct vc4_vs_key));
1896 }
1897
1898 static int
1899 fs_cache_compare(void *key1, void *key2)
1900 {
1901 return memcmp(key1, key2, sizeof(struct vc4_fs_key));
1902 }
1903
1904 static int
1905 vs_cache_compare(void *key1, void *key2)
1906 {
1907 return memcmp(key1, key2, sizeof(struct vc4_vs_key));
1908 }
1909
1910 struct delete_state {
1911 struct vc4_context *vc4;
1912 struct vc4_uncompiled_shader *shader_state;
1913 };
1914
1915 static enum pipe_error
1916 fs_delete_from_cache(void *in_key, void *in_value, void *data)
1917 {
1918 struct delete_state *del = data;
1919 struct vc4_fs_key *key = in_key;
1920 struct vc4_compiled_shader *shader = in_value;
1921
1922 if (key->base.shader_state == data) {
1923 util_hash_table_remove(del->vc4->fs_cache, key);
1924 vc4_bo_unreference(&shader->bo);
1925 ralloc_free(shader);
1926 }
1927
1928 return 0;
1929 }
1930
1931 static enum pipe_error
1932 vs_delete_from_cache(void *in_key, void *in_value, void *data)
1933 {
1934 struct delete_state *del = data;
1935 struct vc4_vs_key *key = in_key;
1936 struct vc4_compiled_shader *shader = in_value;
1937
1938 if (key->base.shader_state == data) {
1939 util_hash_table_remove(del->vc4->vs_cache, key);
1940 vc4_bo_unreference(&shader->bo);
1941 ralloc_free(shader);
1942 }
1943
1944 return 0;
1945 }
1946
1947 static void
1948 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
1949 {
1950 struct vc4_context *vc4 = vc4_context(pctx);
1951 struct vc4_uncompiled_shader *so = hwcso;
1952 struct delete_state del;
1953
1954 del.vc4 = vc4;
1955 del.shader_state = so;
1956 util_hash_table_foreach(vc4->fs_cache, fs_delete_from_cache, &del);
1957 util_hash_table_foreach(vc4->vs_cache, vs_delete_from_cache, &del);
1958
1959 if (so->twoside_tokens != so->base.tokens)
1960 free((void *)so->twoside_tokens);
1961 free((void *)so->base.tokens);
1962 free(so);
1963 }
1964
1965 static uint32_t translate_wrap(uint32_t p_wrap, bool using_nearest)
1966 {
1967 switch (p_wrap) {
1968 case PIPE_TEX_WRAP_REPEAT:
1969 return 0;
1970 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1971 return 1;
1972 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1973 return 2;
1974 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1975 return 3;
1976 case PIPE_TEX_WRAP_CLAMP:
1977 return (using_nearest ? 1 : 3);
1978 default:
1979 fprintf(stderr, "Unknown wrap mode %d\n", p_wrap);
1980 assert(!"not reached");
1981 return 0;
1982 }
1983 }
1984
1985 static void
1986 write_texture_p0(struct vc4_context *vc4,
1987 struct vc4_texture_stateobj *texstate,
1988 uint32_t unit)
1989 {
1990 struct pipe_sampler_view *texture = texstate->textures[unit];
1991 struct vc4_resource *rsc = vc4_resource(texture->texture);
1992
1993 cl_reloc(vc4, &vc4->uniforms, rsc->bo,
1994 VC4_SET_FIELD(rsc->slices[0].offset >> 12, VC4_TEX_P0_OFFSET) |
1995 VC4_SET_FIELD(texture->u.tex.last_level, VC4_TEX_P0_MIPLVLS) |
1996 VC4_SET_FIELD(texture->target == PIPE_TEXTURE_CUBE,
1997 VC4_TEX_P0_CMMODE) |
1998 VC4_SET_FIELD(rsc->vc4_format & 7, VC4_TEX_P0_TYPE));
1999 }
2000
2001 static void
2002 write_texture_p1(struct vc4_context *vc4,
2003 struct vc4_texture_stateobj *texstate,
2004 uint32_t unit)
2005 {
2006 struct pipe_sampler_view *texture = texstate->textures[unit];
2007 struct vc4_resource *rsc = vc4_resource(texture->texture);
2008 struct pipe_sampler_state *sampler = texstate->samplers[unit];
2009 static const uint8_t minfilter_map[6] = {
2010 VC4_TEX_P1_MINFILT_NEAR_MIP_NEAR,
2011 VC4_TEX_P1_MINFILT_LIN_MIP_NEAR,
2012 VC4_TEX_P1_MINFILT_NEAR_MIP_LIN,
2013 VC4_TEX_P1_MINFILT_LIN_MIP_LIN,
2014 VC4_TEX_P1_MINFILT_NEAREST,
2015 VC4_TEX_P1_MINFILT_LINEAR,
2016 };
2017 static const uint32_t magfilter_map[] = {
2018 [PIPE_TEX_FILTER_NEAREST] = VC4_TEX_P1_MAGFILT_NEAREST,
2019 [PIPE_TEX_FILTER_LINEAR] = VC4_TEX_P1_MAGFILT_LINEAR,
2020 };
2021
2022 bool either_nearest =
2023 (sampler->mag_img_filter == PIPE_TEX_MIPFILTER_NEAREST ||
2024 sampler->min_img_filter == PIPE_TEX_MIPFILTER_NEAREST);
2025
2026 cl_u32(&vc4->uniforms,
2027 VC4_SET_FIELD(rsc->vc4_format >> 4, VC4_TEX_P1_TYPE4) |
2028 VC4_SET_FIELD(texture->texture->height0 & 2047,
2029 VC4_TEX_P1_HEIGHT) |
2030 VC4_SET_FIELD(texture->texture->width0 & 2047,
2031 VC4_TEX_P1_WIDTH) |
2032 VC4_SET_FIELD(magfilter_map[sampler->mag_img_filter],
2033 VC4_TEX_P1_MAGFILT) |
2034 VC4_SET_FIELD(minfilter_map[sampler->min_mip_filter * 2 +
2035 sampler->min_img_filter],
2036 VC4_TEX_P1_MINFILT) |
2037 VC4_SET_FIELD(translate_wrap(sampler->wrap_s, either_nearest),
2038 VC4_TEX_P1_WRAP_S) |
2039 VC4_SET_FIELD(translate_wrap(sampler->wrap_t, either_nearest),
2040 VC4_TEX_P1_WRAP_T));
2041 }
2042
2043 static void
2044 write_texture_p2(struct vc4_context *vc4,
2045 struct vc4_texture_stateobj *texstate,
2046 uint32_t unit)
2047 {
2048 struct pipe_sampler_view *texture = texstate->textures[unit];
2049 struct vc4_resource *rsc = vc4_resource(texture->texture);
2050
2051 cl_u32(&vc4->uniforms,
2052 VC4_SET_FIELD(VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE,
2053 VC4_TEX_P2_PTYPE) |
2054 VC4_SET_FIELD(rsc->cube_map_stride >> 12, VC4_TEX_P2_CMST));
2055 }
2056
2057
2058 #define SWIZ(x,y,z,w) { \
2059 UTIL_FORMAT_SWIZZLE_##x, \
2060 UTIL_FORMAT_SWIZZLE_##y, \
2061 UTIL_FORMAT_SWIZZLE_##z, \
2062 UTIL_FORMAT_SWIZZLE_##w \
2063 }
2064
2065 static void
2066 write_texture_border_color(struct vc4_context *vc4,
2067 struct vc4_texture_stateobj *texstate,
2068 uint32_t unit)
2069 {
2070 struct pipe_sampler_state *sampler = texstate->samplers[unit];
2071 struct pipe_sampler_view *texture = texstate->textures[unit];
2072 struct vc4_resource *rsc = vc4_resource(texture->texture);
2073 union util_color uc;
2074
2075 const struct util_format_description *tex_format_desc =
2076 util_format_description(texture->format);
2077
2078 float border_color[4];
2079 for (int i = 0; i < 4; i++)
2080 border_color[i] = sampler->border_color.f[i];
2081 if (util_format_is_srgb(texture->format)) {
2082 for (int i = 0; i < 3; i++)
2083 border_color[i] =
2084 util_format_linear_to_srgb_float(border_color[i]);
2085 }
2086
2087 /* Turn the border color into the layout of channels that it would
2088 * have when stored as texture contents.
2089 */
2090 float storage_color[4];
2091 util_format_unswizzle_4f(storage_color,
2092 border_color,
2093 tex_format_desc->swizzle);
2094
2095 /* Now, pack so that when the vc4_format-sampled texture contents are
2096 * replaced with our border color, the vc4_get_format_swizzle()
2097 * swizzling will get the right channels.
2098 */
2099 if (util_format_is_depth_or_stencil(texture->format)) {
2100 uc.ui[0] = util_pack_z(PIPE_FORMAT_Z24X8_UNORM,
2101 sampler->border_color.f[0]) << 8;
2102 } else {
2103 switch (rsc->vc4_format) {
2104 default:
2105 case VC4_TEXTURE_TYPE_RGBA8888:
2106 util_pack_color(storage_color,
2107 PIPE_FORMAT_R8G8B8A8_UNORM, &uc);
2108 break;
2109 case VC4_TEXTURE_TYPE_RGBA4444:
2110 util_pack_color(storage_color,
2111 PIPE_FORMAT_A8B8G8R8_UNORM, &uc);
2112 break;
2113 case VC4_TEXTURE_TYPE_RGB565:
2114 util_pack_color(storage_color,
2115 PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
2116 break;
2117 case VC4_TEXTURE_TYPE_ALPHA:
2118 uc.ui[0] = float_to_ubyte(storage_color[0]) << 24;
2119 break;
2120 case VC4_TEXTURE_TYPE_LUMALPHA:
2121 uc.ui[0] = ((float_to_ubyte(storage_color[1]) << 24) |
2122 (float_to_ubyte(storage_color[0]) << 0));
2123 break;
2124 }
2125 }
2126
2127 cl_u32(&vc4->uniforms, uc.ui[0]);
2128 }
2129
2130 static uint32_t
2131 get_texrect_scale(struct vc4_texture_stateobj *texstate,
2132 enum quniform_contents contents,
2133 uint32_t data)
2134 {
2135 struct pipe_sampler_view *texture = texstate->textures[data];
2136 uint32_t dim;
2137
2138 if (contents == QUNIFORM_TEXRECT_SCALE_X)
2139 dim = texture->texture->width0;
2140 else
2141 dim = texture->texture->height0;
2142
2143 return fui(1.0f / dim);
2144 }
2145
2146 void
2147 vc4_write_uniforms(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
2148 struct vc4_constbuf_stateobj *cb,
2149 struct vc4_texture_stateobj *texstate)
2150 {
2151 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
2152 const uint32_t *gallium_uniforms = cb->cb[0].user_buffer;
2153
2154 cl_start_shader_reloc(&vc4->uniforms, uinfo->num_texture_samples);
2155
2156 for (int i = 0; i < uinfo->count; i++) {
2157
2158 switch (uinfo->contents[i]) {
2159 case QUNIFORM_CONSTANT:
2160 cl_u32(&vc4->uniforms, uinfo->data[i]);
2161 break;
2162 case QUNIFORM_UNIFORM:
2163 cl_u32(&vc4->uniforms,
2164 gallium_uniforms[uinfo->data[i]]);
2165 break;
2166 case QUNIFORM_VIEWPORT_X_SCALE:
2167 cl_f(&vc4->uniforms, vc4->viewport.scale[0] * 16.0f);
2168 break;
2169 case QUNIFORM_VIEWPORT_Y_SCALE:
2170 cl_f(&vc4->uniforms, vc4->viewport.scale[1] * 16.0f);
2171 break;
2172
2173 case QUNIFORM_VIEWPORT_Z_OFFSET:
2174 cl_f(&vc4->uniforms, vc4->viewport.translate[2]);
2175 break;
2176 case QUNIFORM_VIEWPORT_Z_SCALE:
2177 cl_f(&vc4->uniforms, vc4->viewport.scale[2]);
2178 break;
2179
2180 case QUNIFORM_TEXTURE_CONFIG_P0:
2181 write_texture_p0(vc4, texstate, uinfo->data[i]);
2182 break;
2183
2184 case QUNIFORM_TEXTURE_CONFIG_P1:
2185 write_texture_p1(vc4, texstate, uinfo->data[i]);
2186 break;
2187
2188 case QUNIFORM_TEXTURE_CONFIG_P2:
2189 write_texture_p2(vc4, texstate, uinfo->data[i]);
2190 break;
2191
2192 case QUNIFORM_TEXTURE_BORDER_COLOR:
2193 write_texture_border_color(vc4, texstate, uinfo->data[i]);
2194 break;
2195
2196 case QUNIFORM_TEXRECT_SCALE_X:
2197 case QUNIFORM_TEXRECT_SCALE_Y:
2198 cl_u32(&vc4->uniforms,
2199 get_texrect_scale(texstate,
2200 uinfo->contents[i],
2201 uinfo->data[i]));
2202 break;
2203
2204 case QUNIFORM_BLEND_CONST_COLOR:
2205 cl_f(&vc4->uniforms,
2206 vc4->blend_color.color[uinfo->data[i]]);
2207 break;
2208
2209 case QUNIFORM_STENCIL:
2210 cl_u32(&vc4->uniforms,
2211 vc4->zsa->stencil_uniforms[uinfo->data[i]] |
2212 (uinfo->data[i] <= 1 ?
2213 (vc4->stencil_ref.ref_value[uinfo->data[i]] << 8) :
2214 0));
2215 break;
2216
2217 case QUNIFORM_ALPHA_REF:
2218 cl_f(&vc4->uniforms, vc4->zsa->base.alpha.ref_value);
2219 break;
2220 }
2221 #if 0
2222 uint32_t written_val = *(uint32_t *)(vc4->uniforms.next - 4);
2223 fprintf(stderr, "%p/%d: %d: 0x%08x (%f)\n",
2224 shader, i, written_val, uif(written_val));
2225 #endif
2226 }
2227 }
2228
2229 static void
2230 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
2231 {
2232 struct vc4_context *vc4 = vc4_context(pctx);
2233 vc4->prog.bind_fs = hwcso;
2234 vc4->prog.dirty |= VC4_SHADER_DIRTY_FP;
2235 vc4->dirty |= VC4_DIRTY_PROG;
2236 }
2237
2238 static void
2239 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
2240 {
2241 struct vc4_context *vc4 = vc4_context(pctx);
2242 vc4->prog.bind_vs = hwcso;
2243 vc4->prog.dirty |= VC4_SHADER_DIRTY_VP;
2244 vc4->dirty |= VC4_DIRTY_PROG;
2245 }
2246
2247 void
2248 vc4_program_init(struct pipe_context *pctx)
2249 {
2250 struct vc4_context *vc4 = vc4_context(pctx);
2251
2252 pctx->create_vs_state = vc4_shader_state_create;
2253 pctx->delete_vs_state = vc4_shader_state_delete;
2254
2255 pctx->create_fs_state = vc4_shader_state_create;
2256 pctx->delete_fs_state = vc4_shader_state_delete;
2257
2258 pctx->bind_fs_state = vc4_fp_state_bind;
2259 pctx->bind_vs_state = vc4_vp_state_bind;
2260
2261 vc4->fs_cache = util_hash_table_create(fs_cache_hash, fs_cache_compare);
2262 vc4->vs_cache = util_hash_table_create(vs_cache_hash, vs_cache_compare);
2263 }