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vc4: Fix live intervals analysis for screening defs in if statements.
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "util/u_format.h"
27 #include "util/u_hash.h"
28 #include "util/u_math.h"
29 #include "util/u_memory.h"
30 #include "util/ralloc.h"
31 #include "util/hash_table.h"
32 #include "tgsi/tgsi_dump.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "compiler/nir/nir.h"
35 #include "compiler/nir/nir_builder.h"
36 #include "nir/tgsi_to_nir.h"
37 #include "vc4_context.h"
38 #include "vc4_qpu.h"
39 #include "vc4_qir.h"
40 #include "mesa/state_tracker/st_glsl_types.h"
41 #ifdef USE_VC4_SIMULATOR
42 #include "simpenrose/simpenrose.h"
43 #endif
44
45 static struct qreg
46 ntq_get_src(struct vc4_compile *c, nir_src src, int i);
47 static void
48 ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list);
49
50 static void
51 resize_qreg_array(struct vc4_compile *c,
52 struct qreg **regs,
53 uint32_t *size,
54 uint32_t decl_size)
55 {
56 if (*size >= decl_size)
57 return;
58
59 uint32_t old_size = *size;
60 *size = MAX2(*size * 2, decl_size);
61 *regs = reralloc(c, *regs, struct qreg, *size);
62 if (!*regs) {
63 fprintf(stderr, "Malloc failure\n");
64 abort();
65 }
66
67 for (uint32_t i = old_size; i < *size; i++)
68 (*regs)[i] = c->undef;
69 }
70
71 static struct qreg
72 indirect_uniform_load(struct vc4_compile *c, nir_intrinsic_instr *intr)
73 {
74 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0);
75 uint32_t offset = nir_intrinsic_base(intr);
76 struct vc4_compiler_ubo_range *range = NULL;
77 unsigned i;
78 for (i = 0; i < c->num_uniform_ranges; i++) {
79 range = &c->ubo_ranges[i];
80 if (offset >= range->src_offset &&
81 offset < range->src_offset + range->size) {
82 break;
83 }
84 }
85 /* The driver-location-based offset always has to be within a declared
86 * uniform range.
87 */
88 assert(range);
89 if (!range->used) {
90 range->used = true;
91 range->dst_offset = c->next_ubo_dst_offset;
92 c->next_ubo_dst_offset += range->size;
93 c->num_ubo_ranges++;
94 }
95
96 offset -= range->src_offset;
97
98 /* Adjust for where we stored the TGSI register base. */
99 indirect_offset = qir_ADD(c, indirect_offset,
100 qir_uniform_ui(c, (range->dst_offset +
101 offset)));
102
103 /* Clamp to [0, array size). Note that MIN/MAX are signed. */
104 indirect_offset = qir_MAX(c, indirect_offset, qir_uniform_ui(c, 0));
105 indirect_offset = qir_MIN(c, indirect_offset,
106 qir_uniform_ui(c, (range->dst_offset +
107 range->size - 4)));
108
109 qir_TEX_DIRECT(c, indirect_offset, qir_uniform(c, QUNIFORM_UBO_ADDR, 0));
110 c->num_texture_samples++;
111 return qir_TEX_RESULT(c);
112 }
113
114 nir_ssa_def *
115 vc4_nir_get_swizzled_channel(nir_builder *b, nir_ssa_def **srcs, int swiz)
116 {
117 switch (swiz) {
118 default:
119 case PIPE_SWIZZLE_NONE:
120 fprintf(stderr, "warning: unknown swizzle\n");
121 /* FALLTHROUGH */
122 case PIPE_SWIZZLE_0:
123 return nir_imm_float(b, 0.0);
124 case PIPE_SWIZZLE_1:
125 return nir_imm_float(b, 1.0);
126 case PIPE_SWIZZLE_X:
127 case PIPE_SWIZZLE_Y:
128 case PIPE_SWIZZLE_Z:
129 case PIPE_SWIZZLE_W:
130 return srcs[swiz];
131 }
132 }
133
134 static struct qreg *
135 ntq_init_ssa_def(struct vc4_compile *c, nir_ssa_def *def)
136 {
137 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
138 def->num_components);
139 _mesa_hash_table_insert(c->def_ht, def, qregs);
140 return qregs;
141 }
142
143 static void
144 ntq_store_dest(struct vc4_compile *c, nir_dest *dest, int chan,
145 struct qreg result)
146 {
147 if (dest->is_ssa) {
148 assert(chan < dest->ssa.num_components);
149
150 struct qreg *qregs;
151 struct hash_entry *entry =
152 _mesa_hash_table_search(c->def_ht, &dest->ssa);
153
154 if (entry)
155 qregs = entry->data;
156 else
157 qregs = ntq_init_ssa_def(c, &dest->ssa);
158
159 qregs[chan] = result;
160 } else {
161 nir_register *reg = dest->reg.reg;
162 assert(dest->reg.base_offset == 0);
163 assert(reg->num_array_elems == 0);
164 struct hash_entry *entry =
165 _mesa_hash_table_search(c->def_ht, reg);
166 struct qreg *qregs = entry->data;
167
168 /* Conditionally move the result to the destination if the
169 * channel is active.
170 */
171 if (c->execute.file != QFILE_NULL) {
172 struct qinst *mov;
173
174 qir_SF(c, c->execute);
175 mov = qir_MOV_cond(c, QPU_COND_ZS, qregs[chan], result);
176 mov->cond_is_exec_mask = true;
177 } else {
178 qir_MOV_dest(c, qregs[chan], result);
179 }
180 }
181 }
182
183 static struct qreg *
184 ntq_get_dest(struct vc4_compile *c, nir_dest *dest)
185 {
186 if (dest->is_ssa) {
187 struct qreg *qregs = ntq_init_ssa_def(c, &dest->ssa);
188 for (int i = 0; i < dest->ssa.num_components; i++)
189 qregs[i] = c->undef;
190 return qregs;
191 } else {
192 nir_register *reg = dest->reg.reg;
193 assert(dest->reg.base_offset == 0);
194 assert(reg->num_array_elems == 0);
195 struct hash_entry *entry =
196 _mesa_hash_table_search(c->def_ht, reg);
197 return entry->data;
198 }
199 }
200
201 static struct qreg
202 ntq_get_src(struct vc4_compile *c, nir_src src, int i)
203 {
204 struct hash_entry *entry;
205 if (src.is_ssa) {
206 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
207 assert(i < src.ssa->num_components);
208 } else {
209 nir_register *reg = src.reg.reg;
210 entry = _mesa_hash_table_search(c->def_ht, reg);
211 assert(reg->num_array_elems == 0);
212 assert(src.reg.base_offset == 0);
213 assert(i < reg->num_components);
214 }
215
216 struct qreg *qregs = entry->data;
217 return qregs[i];
218 }
219
220 static struct qreg
221 ntq_get_alu_src(struct vc4_compile *c, nir_alu_instr *instr,
222 unsigned src)
223 {
224 assert(util_is_power_of_two(instr->dest.write_mask));
225 unsigned chan = ffs(instr->dest.write_mask) - 1;
226 struct qreg r = ntq_get_src(c, instr->src[src].src,
227 instr->src[src].swizzle[chan]);
228
229 assert(!instr->src[src].abs);
230 assert(!instr->src[src].negate);
231
232 return r;
233 };
234
235 static inline struct qreg
236 qir_SAT(struct vc4_compile *c, struct qreg val)
237 {
238 return qir_FMAX(c,
239 qir_FMIN(c, val, qir_uniform_f(c, 1.0)),
240 qir_uniform_f(c, 0.0));
241 }
242
243 static struct qreg
244 ntq_rcp(struct vc4_compile *c, struct qreg x)
245 {
246 struct qreg r = qir_RCP(c, x);
247
248 /* Apply a Newton-Raphson step to improve the accuracy. */
249 r = qir_FMUL(c, r, qir_FSUB(c,
250 qir_uniform_f(c, 2.0),
251 qir_FMUL(c, x, r)));
252
253 return r;
254 }
255
256 static struct qreg
257 ntq_rsq(struct vc4_compile *c, struct qreg x)
258 {
259 struct qreg r = qir_RSQ(c, x);
260
261 /* Apply a Newton-Raphson step to improve the accuracy. */
262 r = qir_FMUL(c, r, qir_FSUB(c,
263 qir_uniform_f(c, 1.5),
264 qir_FMUL(c,
265 qir_uniform_f(c, 0.5),
266 qir_FMUL(c, x,
267 qir_FMUL(c, r, r)))));
268
269 return r;
270 }
271
272 static struct qreg
273 ntq_umul(struct vc4_compile *c, struct qreg src0, struct qreg src1)
274 {
275 struct qreg src0_hi = qir_SHR(c, src0,
276 qir_uniform_ui(c, 24));
277 struct qreg src1_hi = qir_SHR(c, src1,
278 qir_uniform_ui(c, 24));
279
280 struct qreg hilo = qir_MUL24(c, src0_hi, src1);
281 struct qreg lohi = qir_MUL24(c, src0, src1_hi);
282 struct qreg lolo = qir_MUL24(c, src0, src1);
283
284 return qir_ADD(c, lolo, qir_SHL(c,
285 qir_ADD(c, hilo, lohi),
286 qir_uniform_ui(c, 24)));
287 }
288
289 static struct qreg
290 ntq_scale_depth_texture(struct vc4_compile *c, struct qreg src)
291 {
292 struct qreg depthf = qir_ITOF(c, qir_SHR(c, src,
293 qir_uniform_ui(c, 8)));
294 return qir_FMUL(c, depthf, qir_uniform_f(c, 1.0f/0xffffff));
295 }
296
297 /**
298 * Emits a lowered TXF_MS from an MSAA texture.
299 *
300 * The addressing math has been lowered in NIR, and now we just need to read
301 * it like a UBO.
302 */
303 static void
304 ntq_emit_txf(struct vc4_compile *c, nir_tex_instr *instr)
305 {
306 uint32_t tile_width = 32;
307 uint32_t tile_height = 32;
308 uint32_t tile_size = (tile_height * tile_width *
309 VC4_MAX_SAMPLES * sizeof(uint32_t));
310
311 unsigned unit = instr->texture_index;
312 uint32_t w = align(c->key->tex[unit].msaa_width, tile_width);
313 uint32_t w_tiles = w / tile_width;
314 uint32_t h = align(c->key->tex[unit].msaa_height, tile_height);
315 uint32_t h_tiles = h / tile_height;
316 uint32_t size = w_tiles * h_tiles * tile_size;
317
318 struct qreg addr;
319 assert(instr->num_srcs == 1);
320 assert(instr->src[0].src_type == nir_tex_src_coord);
321 addr = ntq_get_src(c, instr->src[0].src, 0);
322
323 /* Perform the clamping required by kernel validation. */
324 addr = qir_MAX(c, addr, qir_uniform_ui(c, 0));
325 addr = qir_MIN(c, addr, qir_uniform_ui(c, size - 4));
326
327 qir_TEX_DIRECT(c, addr, qir_uniform(c, QUNIFORM_TEXTURE_MSAA_ADDR, unit));
328
329 struct qreg tex = qir_TEX_RESULT(c);
330 c->num_texture_samples++;
331
332 struct qreg dest[4];
333 enum pipe_format format = c->key->tex[unit].format;
334 if (util_format_is_depth_or_stencil(format)) {
335 struct qreg scaled = ntq_scale_depth_texture(c, tex);
336 for (int i = 0; i < 4; i++)
337 dest[i] = scaled;
338 } else {
339 for (int i = 0; i < 4; i++)
340 dest[i] = qir_UNPACK_8_F(c, tex, i);
341 }
342
343 for (int i = 0; i < 4; i++)
344 ntq_store_dest(c, &instr->dest, i, dest[i]);
345 }
346
347 static void
348 ntq_emit_tex(struct vc4_compile *c, nir_tex_instr *instr)
349 {
350 struct qreg s, t, r, lod, compare;
351 bool is_txb = false, is_txl = false;
352 unsigned unit = instr->texture_index;
353
354 if (instr->op == nir_texop_txf) {
355 ntq_emit_txf(c, instr);
356 return;
357 }
358
359 for (unsigned i = 0; i < instr->num_srcs; i++) {
360 switch (instr->src[i].src_type) {
361 case nir_tex_src_coord:
362 s = ntq_get_src(c, instr->src[i].src, 0);
363 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D)
364 t = qir_uniform_f(c, 0.5);
365 else
366 t = ntq_get_src(c, instr->src[i].src, 1);
367 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
368 r = ntq_get_src(c, instr->src[i].src, 2);
369 break;
370 case nir_tex_src_bias:
371 lod = ntq_get_src(c, instr->src[i].src, 0);
372 is_txb = true;
373 break;
374 case nir_tex_src_lod:
375 lod = ntq_get_src(c, instr->src[i].src, 0);
376 is_txl = true;
377 break;
378 case nir_tex_src_comparitor:
379 compare = ntq_get_src(c, instr->src[i].src, 0);
380 break;
381 default:
382 unreachable("unknown texture source");
383 }
384 }
385
386 if (c->key->tex[unit].force_first_level) {
387 lod = qir_uniform(c, QUNIFORM_TEXTURE_FIRST_LEVEL, unit);
388 is_txl = true;
389 is_txb = false;
390 }
391
392 struct qreg texture_u[] = {
393 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit),
394 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
395 qir_uniform(c, QUNIFORM_CONSTANT, 0),
396 qir_uniform(c, QUNIFORM_CONSTANT, 0),
397 };
398 uint32_t next_texture_u = 0;
399
400 /* There is no native support for GL texture rectangle coordinates, so
401 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
402 * 1]).
403 */
404 if (instr->sampler_dim == GLSL_SAMPLER_DIM_RECT) {
405 s = qir_FMUL(c, s,
406 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_X, unit));
407 t = qir_FMUL(c, t,
408 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_Y, unit));
409 }
410
411 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE || is_txl) {
412 texture_u[2] = qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P2,
413 unit | (is_txl << 16));
414 }
415
416 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
417 qir_TEX_R(c, r, texture_u[next_texture_u++]);
418 } else if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
419 c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP ||
420 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
421 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
422 qir_TEX_R(c, qir_uniform(c, QUNIFORM_TEXTURE_BORDER_COLOR, unit),
423 texture_u[next_texture_u++]);
424 }
425
426 if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP) {
427 s = qir_SAT(c, s);
428 }
429
430 if (c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
431 t = qir_SAT(c, t);
432 }
433
434 qir_TEX_T(c, t, texture_u[next_texture_u++]);
435
436 if (is_txl || is_txb)
437 qir_TEX_B(c, lod, texture_u[next_texture_u++]);
438
439 qir_TEX_S(c, s, texture_u[next_texture_u++]);
440
441 c->num_texture_samples++;
442 struct qreg tex = qir_TEX_RESULT(c);
443
444 enum pipe_format format = c->key->tex[unit].format;
445
446 struct qreg *dest = ntq_get_dest(c, &instr->dest);
447 if (util_format_is_depth_or_stencil(format)) {
448 struct qreg normalized = ntq_scale_depth_texture(c, tex);
449 struct qreg depth_output;
450
451 struct qreg u0 = qir_uniform_f(c, 0.0f);
452 struct qreg u1 = qir_uniform_f(c, 1.0f);
453 if (c->key->tex[unit].compare_mode) {
454 switch (c->key->tex[unit].compare_func) {
455 case PIPE_FUNC_NEVER:
456 depth_output = qir_uniform_f(c, 0.0f);
457 break;
458 case PIPE_FUNC_ALWAYS:
459 depth_output = u1;
460 break;
461 case PIPE_FUNC_EQUAL:
462 qir_SF(c, qir_FSUB(c, compare, normalized));
463 depth_output = qir_SEL(c, QPU_COND_ZS, u1, u0);
464 break;
465 case PIPE_FUNC_NOTEQUAL:
466 qir_SF(c, qir_FSUB(c, compare, normalized));
467 depth_output = qir_SEL(c, QPU_COND_ZC, u1, u0);
468 break;
469 case PIPE_FUNC_GREATER:
470 qir_SF(c, qir_FSUB(c, compare, normalized));
471 depth_output = qir_SEL(c, QPU_COND_NC, u1, u0);
472 break;
473 case PIPE_FUNC_GEQUAL:
474 qir_SF(c, qir_FSUB(c, normalized, compare));
475 depth_output = qir_SEL(c, QPU_COND_NS, u1, u0);
476 break;
477 case PIPE_FUNC_LESS:
478 qir_SF(c, qir_FSUB(c, compare, normalized));
479 depth_output = qir_SEL(c, QPU_COND_NS, u1, u0);
480 break;
481 case PIPE_FUNC_LEQUAL:
482 qir_SF(c, qir_FSUB(c, normalized, compare));
483 depth_output = qir_SEL(c, QPU_COND_NC, u1, u0);
484 break;
485 }
486 } else {
487 depth_output = normalized;
488 }
489
490 for (int i = 0; i < 4; i++)
491 dest[i] = depth_output;
492 } else {
493 for (int i = 0; i < 4; i++)
494 dest[i] = qir_UNPACK_8_F(c, tex, i);
495 }
496 }
497
498 /**
499 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
500 * to zero).
501 */
502 static struct qreg
503 ntq_ffract(struct vc4_compile *c, struct qreg src)
504 {
505 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
506 struct qreg diff = qir_FSUB(c, src, trunc);
507 qir_SF(c, diff);
508 return qir_SEL(c, QPU_COND_NS,
509 qir_FADD(c, diff, qir_uniform_f(c, 1.0)), diff);
510 }
511
512 /**
513 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
514 * zero).
515 */
516 static struct qreg
517 ntq_ffloor(struct vc4_compile *c, struct qreg src)
518 {
519 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
520
521 /* This will be < 0 if we truncated and the truncation was of a value
522 * that was < 0 in the first place.
523 */
524 qir_SF(c, qir_FSUB(c, src, trunc));
525
526 return qir_SEL(c, QPU_COND_NS,
527 qir_FSUB(c, trunc, qir_uniform_f(c, 1.0)), trunc);
528 }
529
530 /**
531 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
532 * zero).
533 */
534 static struct qreg
535 ntq_fceil(struct vc4_compile *c, struct qreg src)
536 {
537 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
538
539 /* This will be < 0 if we truncated and the truncation was of a value
540 * that was > 0 in the first place.
541 */
542 qir_SF(c, qir_FSUB(c, trunc, src));
543
544 return qir_SEL(c, QPU_COND_NS,
545 qir_FADD(c, trunc, qir_uniform_f(c, 1.0)), trunc);
546 }
547
548 static struct qreg
549 ntq_fsin(struct vc4_compile *c, struct qreg src)
550 {
551 float coeff[] = {
552 -2.0 * M_PI,
553 pow(2.0 * M_PI, 3) / (3 * 2 * 1),
554 -pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
555 pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
556 -pow(2.0 * M_PI, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
557 };
558
559 struct qreg scaled_x =
560 qir_FMUL(c,
561 src,
562 qir_uniform_f(c, 1.0 / (M_PI * 2.0)));
563
564 struct qreg x = qir_FADD(c,
565 ntq_ffract(c, scaled_x),
566 qir_uniform_f(c, -0.5));
567 struct qreg x2 = qir_FMUL(c, x, x);
568 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
569 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
570 x = qir_FMUL(c, x, x2);
571 sum = qir_FADD(c,
572 sum,
573 qir_FMUL(c,
574 x,
575 qir_uniform_f(c, coeff[i])));
576 }
577 return sum;
578 }
579
580 static struct qreg
581 ntq_fcos(struct vc4_compile *c, struct qreg src)
582 {
583 float coeff[] = {
584 -1.0f,
585 pow(2.0 * M_PI, 2) / (2 * 1),
586 -pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
587 pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
588 -pow(2.0 * M_PI, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
589 pow(2.0 * M_PI, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
590 };
591
592 struct qreg scaled_x =
593 qir_FMUL(c, src,
594 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
595 struct qreg x_frac = qir_FADD(c,
596 ntq_ffract(c, scaled_x),
597 qir_uniform_f(c, -0.5));
598
599 struct qreg sum = qir_uniform_f(c, coeff[0]);
600 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
601 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
602 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
603 if (i != 1)
604 x = qir_FMUL(c, x, x2);
605
606 struct qreg mul = qir_FMUL(c,
607 x,
608 qir_uniform_f(c, coeff[i]));
609 if (i == 0)
610 sum = mul;
611 else
612 sum = qir_FADD(c, sum, mul);
613 }
614 return sum;
615 }
616
617 static struct qreg
618 ntq_fsign(struct vc4_compile *c, struct qreg src)
619 {
620 struct qreg t = qir_get_temp(c);
621
622 qir_SF(c, src);
623 qir_MOV_dest(c, t, qir_uniform_f(c, 0.0));
624 qir_MOV_dest(c, t, qir_uniform_f(c, 1.0))->cond = QPU_COND_ZC;
625 qir_MOV_dest(c, t, qir_uniform_f(c, -1.0))->cond = QPU_COND_NS;
626 return t;
627 }
628
629 static void
630 emit_vertex_input(struct vc4_compile *c, int attr)
631 {
632 enum pipe_format format = c->vs_key->attr_formats[attr];
633 uint32_t attr_size = util_format_get_blocksize(format);
634
635 c->vattr_sizes[attr] = align(attr_size, 4);
636 for (int i = 0; i < align(attr_size, 4) / 4; i++) {
637 c->inputs[attr * 4 + i] =
638 qir_MOV(c, qir_reg(QFILE_VPM, attr * 4 + i));
639 c->num_inputs++;
640 }
641 }
642
643 static void
644 emit_fragcoord_input(struct vc4_compile *c, int attr)
645 {
646 c->inputs[attr * 4 + 0] = qir_ITOF(c, qir_reg(QFILE_FRAG_X, 0));
647 c->inputs[attr * 4 + 1] = qir_ITOF(c, qir_reg(QFILE_FRAG_Y, 0));
648 c->inputs[attr * 4 + 2] =
649 qir_FMUL(c,
650 qir_ITOF(c, qir_FRAG_Z(c)),
651 qir_uniform_f(c, 1.0 / 0xffffff));
652 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
653 }
654
655 static struct qreg
656 emit_fragment_varying(struct vc4_compile *c, gl_varying_slot slot,
657 uint8_t swizzle)
658 {
659 uint32_t i = c->num_input_slots++;
660 struct qreg vary = {
661 QFILE_VARY,
662 i
663 };
664
665 if (c->num_input_slots >= c->input_slots_array_size) {
666 c->input_slots_array_size =
667 MAX2(4, c->input_slots_array_size * 2);
668
669 c->input_slots = reralloc(c, c->input_slots,
670 struct vc4_varying_slot,
671 c->input_slots_array_size);
672 }
673
674 c->input_slots[i].slot = slot;
675 c->input_slots[i].swizzle = swizzle;
676
677 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
678 }
679
680 static void
681 emit_fragment_input(struct vc4_compile *c, int attr, gl_varying_slot slot)
682 {
683 for (int i = 0; i < 4; i++) {
684 c->inputs[attr * 4 + i] =
685 emit_fragment_varying(c, slot, i);
686 c->num_inputs++;
687 }
688 }
689
690 static void
691 add_output(struct vc4_compile *c,
692 uint32_t decl_offset,
693 uint8_t slot,
694 uint8_t swizzle)
695 {
696 uint32_t old_array_size = c->outputs_array_size;
697 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
698 decl_offset + 1);
699
700 if (old_array_size != c->outputs_array_size) {
701 c->output_slots = reralloc(c,
702 c->output_slots,
703 struct vc4_varying_slot,
704 c->outputs_array_size);
705 }
706
707 c->output_slots[decl_offset].slot = slot;
708 c->output_slots[decl_offset].swizzle = swizzle;
709 }
710
711 static void
712 declare_uniform_range(struct vc4_compile *c, uint32_t start, uint32_t size)
713 {
714 unsigned array_id = c->num_uniform_ranges++;
715 if (array_id >= c->ubo_ranges_array_size) {
716 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
717 array_id + 1);
718 c->ubo_ranges = reralloc(c, c->ubo_ranges,
719 struct vc4_compiler_ubo_range,
720 c->ubo_ranges_array_size);
721 }
722
723 c->ubo_ranges[array_id].dst_offset = 0;
724 c->ubo_ranges[array_id].src_offset = start;
725 c->ubo_ranges[array_id].size = size;
726 c->ubo_ranges[array_id].used = false;
727 }
728
729 static bool
730 ntq_src_is_only_ssa_def_user(nir_src *src)
731 {
732 if (!src->is_ssa)
733 return false;
734
735 if (!list_empty(&src->ssa->if_uses))
736 return false;
737
738 return (src->ssa->uses.next == &src->use_link &&
739 src->ssa->uses.next->next == &src->ssa->uses);
740 }
741
742 /**
743 * In general, emits a nir_pack_unorm_4x8 as a series of MOVs with the pack
744 * bit set.
745 *
746 * However, as an optimization, it tries to find the instructions generating
747 * the sources to be packed and just emit the pack flag there, if possible.
748 */
749 static void
750 ntq_emit_pack_unorm_4x8(struct vc4_compile *c, nir_alu_instr *instr)
751 {
752 struct qreg result = qir_get_temp(c);
753 struct nir_alu_instr *vec4 = NULL;
754
755 /* If packing from a vec4 op (as expected), identify it so that we can
756 * peek back at what generated its sources.
757 */
758 if (instr->src[0].src.is_ssa &&
759 instr->src[0].src.ssa->parent_instr->type == nir_instr_type_alu &&
760 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr)->op ==
761 nir_op_vec4) {
762 vec4 = nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
763 }
764
765 /* If the pack is replicating the same channel 4 times, use the 8888
766 * pack flag. This is common for blending using the alpha
767 * channel.
768 */
769 if (instr->src[0].swizzle[0] == instr->src[0].swizzle[1] &&
770 instr->src[0].swizzle[0] == instr->src[0].swizzle[2] &&
771 instr->src[0].swizzle[0] == instr->src[0].swizzle[3]) {
772 struct qreg rep = ntq_get_src(c,
773 instr->src[0].src,
774 instr->src[0].swizzle[0]);
775 ntq_store_dest(c, &instr->dest.dest, 0, qir_PACK_8888_F(c, rep));
776 return;
777 }
778
779 for (int i = 0; i < 4; i++) {
780 int swiz = instr->src[0].swizzle[i];
781 struct qreg src;
782 if (vec4) {
783 src = ntq_get_src(c, vec4->src[swiz].src,
784 vec4->src[swiz].swizzle[0]);
785 } else {
786 src = ntq_get_src(c, instr->src[0].src, swiz);
787 }
788
789 if (vec4 &&
790 ntq_src_is_only_ssa_def_user(&vec4->src[swiz].src) &&
791 src.file == QFILE_TEMP &&
792 c->defs[src.index] &&
793 qir_is_mul(c->defs[src.index]) &&
794 !c->defs[src.index]->dst.pack) {
795 struct qinst *rewrite = c->defs[src.index];
796 c->defs[src.index] = NULL;
797 rewrite->dst = result;
798 rewrite->dst.pack = QPU_PACK_MUL_8A + i;
799 continue;
800 }
801
802 qir_PACK_8_F(c, result, src, i);
803 }
804
805 ntq_store_dest(c, &instr->dest.dest, 0, result);
806 }
807
808 /** Handles sign-extended bitfield extracts for 16 bits. */
809 static struct qreg
810 ntq_emit_ibfe(struct vc4_compile *c, struct qreg base, struct qreg offset,
811 struct qreg bits)
812 {
813 assert(bits.file == QFILE_UNIF &&
814 c->uniform_contents[bits.index] == QUNIFORM_CONSTANT &&
815 c->uniform_data[bits.index] == 16);
816
817 assert(offset.file == QFILE_UNIF &&
818 c->uniform_contents[offset.index] == QUNIFORM_CONSTANT);
819 int offset_bit = c->uniform_data[offset.index];
820 assert(offset_bit % 16 == 0);
821
822 return qir_UNPACK_16_I(c, base, offset_bit / 16);
823 }
824
825 /** Handles unsigned bitfield extracts for 8 bits. */
826 static struct qreg
827 ntq_emit_ubfe(struct vc4_compile *c, struct qreg base, struct qreg offset,
828 struct qreg bits)
829 {
830 assert(bits.file == QFILE_UNIF &&
831 c->uniform_contents[bits.index] == QUNIFORM_CONSTANT &&
832 c->uniform_data[bits.index] == 8);
833
834 assert(offset.file == QFILE_UNIF &&
835 c->uniform_contents[offset.index] == QUNIFORM_CONSTANT);
836 int offset_bit = c->uniform_data[offset.index];
837 assert(offset_bit % 8 == 0);
838
839 return qir_UNPACK_8_I(c, base, offset_bit / 8);
840 }
841
842 /**
843 * If compare_instr is a valid comparison instruction, emits the
844 * compare_instr's comparison and returns the sel_instr's return value based
845 * on the compare_instr's result.
846 */
847 static bool
848 ntq_emit_comparison(struct vc4_compile *c, struct qreg *dest,
849 nir_alu_instr *compare_instr,
850 nir_alu_instr *sel_instr)
851 {
852 enum qpu_cond cond;
853
854 switch (compare_instr->op) {
855 case nir_op_feq:
856 case nir_op_ieq:
857 case nir_op_seq:
858 cond = QPU_COND_ZS;
859 break;
860 case nir_op_fne:
861 case nir_op_ine:
862 case nir_op_sne:
863 cond = QPU_COND_ZC;
864 break;
865 case nir_op_fge:
866 case nir_op_ige:
867 case nir_op_uge:
868 case nir_op_sge:
869 cond = QPU_COND_NC;
870 break;
871 case nir_op_flt:
872 case nir_op_ilt:
873 case nir_op_slt:
874 cond = QPU_COND_NS;
875 break;
876 default:
877 return false;
878 }
879
880 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
881 struct qreg src1 = ntq_get_alu_src(c, compare_instr, 1);
882
883 unsigned unsized_type =
884 nir_alu_type_get_base_type(nir_op_infos[compare_instr->op].input_types[0]);
885 if (unsized_type == nir_type_float)
886 qir_SF(c, qir_FSUB(c, src0, src1));
887 else
888 qir_SF(c, qir_SUB(c, src0, src1));
889
890 switch (sel_instr->op) {
891 case nir_op_seq:
892 case nir_op_sne:
893 case nir_op_sge:
894 case nir_op_slt:
895 *dest = qir_SEL(c, cond,
896 qir_uniform_f(c, 1.0), qir_uniform_f(c, 0.0));
897 break;
898
899 case nir_op_bcsel:
900 *dest = qir_SEL(c, cond,
901 ntq_get_alu_src(c, sel_instr, 1),
902 ntq_get_alu_src(c, sel_instr, 2));
903 break;
904
905 default:
906 *dest = qir_SEL(c, cond,
907 qir_uniform_ui(c, ~0), qir_uniform_ui(c, 0));
908 break;
909 }
910
911 return true;
912 }
913
914 /**
915 * Attempts to fold a comparison generating a boolean result into the
916 * condition code for selecting between two values, instead of comparing the
917 * boolean result against 0 to generate the condition code.
918 */
919 static struct qreg ntq_emit_bcsel(struct vc4_compile *c, nir_alu_instr *instr,
920 struct qreg *src)
921 {
922 if (!instr->src[0].src.is_ssa)
923 goto out;
924 if (instr->src[0].src.ssa->parent_instr->type != nir_instr_type_alu)
925 goto out;
926 nir_alu_instr *compare =
927 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
928 if (!compare)
929 goto out;
930
931 struct qreg dest;
932 if (ntq_emit_comparison(c, &dest, compare, instr))
933 return dest;
934
935 out:
936 qir_SF(c, src[0]);
937 return qir_SEL(c, QPU_COND_NS, src[1], src[2]);
938 }
939
940 static struct qreg
941 ntq_fddx(struct vc4_compile *c, struct qreg src)
942 {
943 /* Make sure that we have a bare temp to use for MUL rotation, so it
944 * can be allocated to an accumulator.
945 */
946 if (src.pack || src.file != QFILE_TEMP)
947 src = qir_MOV(c, src);
948
949 struct qreg from_left = qir_ROT_MUL(c, src, 1);
950 struct qreg from_right = qir_ROT_MUL(c, src, 15);
951
952 /* Distinguish left/right pixels of the quad. */
953 qir_SF(c, qir_AND(c, qir_reg(QFILE_QPU_ELEMENT, 0),
954 qir_uniform_ui(c, 1)));
955
956 return qir_SEL(c, QPU_COND_ZS,
957 qir_FSUB(c, from_right, src),
958 qir_FSUB(c, src, from_left));
959 }
960
961 static struct qreg
962 ntq_fddy(struct vc4_compile *c, struct qreg src)
963 {
964 if (src.pack || src.file != QFILE_TEMP)
965 src = qir_MOV(c, src);
966
967 struct qreg from_bottom = qir_ROT_MUL(c, src, 2);
968 struct qreg from_top = qir_ROT_MUL(c, src, 14);
969
970 /* Distinguish top/bottom pixels of the quad. */
971 qir_SF(c, qir_AND(c,
972 qir_reg(QFILE_QPU_ELEMENT, 0),
973 qir_uniform_ui(c, 2)));
974
975 return qir_SEL(c, QPU_COND_ZS,
976 qir_FSUB(c, from_top, src),
977 qir_FSUB(c, src, from_bottom));
978 }
979
980 static void
981 ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr)
982 {
983 /* This should always be lowered to ALU operations for VC4. */
984 assert(!instr->dest.saturate);
985
986 /* Vectors are special in that they have non-scalarized writemasks,
987 * and just take the first swizzle channel for each argument in order
988 * into each writemask channel.
989 */
990 if (instr->op == nir_op_vec2 ||
991 instr->op == nir_op_vec3 ||
992 instr->op == nir_op_vec4) {
993 struct qreg srcs[4];
994 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
995 srcs[i] = ntq_get_src(c, instr->src[i].src,
996 instr->src[i].swizzle[0]);
997 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
998 ntq_store_dest(c, &instr->dest.dest, i, srcs[i]);
999 return;
1000 }
1001
1002 if (instr->op == nir_op_pack_unorm_4x8) {
1003 ntq_emit_pack_unorm_4x8(c, instr);
1004 return;
1005 }
1006
1007 if (instr->op == nir_op_unpack_unorm_4x8) {
1008 struct qreg src = ntq_get_src(c, instr->src[0].src,
1009 instr->src[0].swizzle[0]);
1010 for (int i = 0; i < 4; i++) {
1011 if (instr->dest.write_mask & (1 << i))
1012 ntq_store_dest(c, &instr->dest.dest, i,
1013 qir_UNPACK_8_F(c, src, i));
1014 }
1015 return;
1016 }
1017
1018 /* General case: We can just grab the one used channel per src. */
1019 struct qreg src[nir_op_infos[instr->op].num_inputs];
1020 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
1021 src[i] = ntq_get_alu_src(c, instr, i);
1022 }
1023
1024 struct qreg result;
1025
1026 switch (instr->op) {
1027 case nir_op_fmov:
1028 case nir_op_imov:
1029 result = qir_MOV(c, src[0]);
1030 break;
1031 case nir_op_fmul:
1032 result = qir_FMUL(c, src[0], src[1]);
1033 break;
1034 case nir_op_fadd:
1035 result = qir_FADD(c, src[0], src[1]);
1036 break;
1037 case nir_op_fsub:
1038 result = qir_FSUB(c, src[0], src[1]);
1039 break;
1040 case nir_op_fmin:
1041 result = qir_FMIN(c, src[0], src[1]);
1042 break;
1043 case nir_op_fmax:
1044 result = qir_FMAX(c, src[0], src[1]);
1045 break;
1046
1047 case nir_op_f2i:
1048 case nir_op_f2u:
1049 result = qir_FTOI(c, src[0]);
1050 break;
1051 case nir_op_i2f:
1052 case nir_op_u2f:
1053 result = qir_ITOF(c, src[0]);
1054 break;
1055 case nir_op_b2f:
1056 result = qir_AND(c, src[0], qir_uniform_f(c, 1.0));
1057 break;
1058 case nir_op_b2i:
1059 result = qir_AND(c, src[0], qir_uniform_ui(c, 1));
1060 break;
1061 case nir_op_i2b:
1062 case nir_op_f2b:
1063 qir_SF(c, src[0]);
1064 result = qir_SEL(c, QPU_COND_ZC,
1065 qir_uniform_ui(c, ~0),
1066 qir_uniform_ui(c, 0));
1067 break;
1068
1069 case nir_op_iadd:
1070 result = qir_ADD(c, src[0], src[1]);
1071 break;
1072 case nir_op_ushr:
1073 result = qir_SHR(c, src[0], src[1]);
1074 break;
1075 case nir_op_isub:
1076 result = qir_SUB(c, src[0], src[1]);
1077 break;
1078 case nir_op_ishr:
1079 result = qir_ASR(c, src[0], src[1]);
1080 break;
1081 case nir_op_ishl:
1082 result = qir_SHL(c, src[0], src[1]);
1083 break;
1084 case nir_op_imin:
1085 result = qir_MIN(c, src[0], src[1]);
1086 break;
1087 case nir_op_imax:
1088 result = qir_MAX(c, src[0], src[1]);
1089 break;
1090 case nir_op_iand:
1091 result = qir_AND(c, src[0], src[1]);
1092 break;
1093 case nir_op_ior:
1094 result = qir_OR(c, src[0], src[1]);
1095 break;
1096 case nir_op_ixor:
1097 result = qir_XOR(c, src[0], src[1]);
1098 break;
1099 case nir_op_inot:
1100 result = qir_NOT(c, src[0]);
1101 break;
1102
1103 case nir_op_imul:
1104 result = ntq_umul(c, src[0], src[1]);
1105 break;
1106
1107 case nir_op_seq:
1108 case nir_op_sne:
1109 case nir_op_sge:
1110 case nir_op_slt:
1111 case nir_op_feq:
1112 case nir_op_fne:
1113 case nir_op_fge:
1114 case nir_op_flt:
1115 case nir_op_ieq:
1116 case nir_op_ine:
1117 case nir_op_ige:
1118 case nir_op_uge:
1119 case nir_op_ilt:
1120 if (!ntq_emit_comparison(c, &result, instr, instr)) {
1121 fprintf(stderr, "Bad comparison instruction\n");
1122 }
1123 break;
1124
1125 case nir_op_bcsel:
1126 result = ntq_emit_bcsel(c, instr, src);
1127 break;
1128 case nir_op_fcsel:
1129 qir_SF(c, src[0]);
1130 result = qir_SEL(c, QPU_COND_ZC, src[1], src[2]);
1131 break;
1132
1133 case nir_op_frcp:
1134 result = ntq_rcp(c, src[0]);
1135 break;
1136 case nir_op_frsq:
1137 result = ntq_rsq(c, src[0]);
1138 break;
1139 case nir_op_fexp2:
1140 result = qir_EXP2(c, src[0]);
1141 break;
1142 case nir_op_flog2:
1143 result = qir_LOG2(c, src[0]);
1144 break;
1145
1146 case nir_op_ftrunc:
1147 result = qir_ITOF(c, qir_FTOI(c, src[0]));
1148 break;
1149 case nir_op_fceil:
1150 result = ntq_fceil(c, src[0]);
1151 break;
1152 case nir_op_ffract:
1153 result = ntq_ffract(c, src[0]);
1154 break;
1155 case nir_op_ffloor:
1156 result = ntq_ffloor(c, src[0]);
1157 break;
1158
1159 case nir_op_fsin:
1160 result = ntq_fsin(c, src[0]);
1161 break;
1162 case nir_op_fcos:
1163 result = ntq_fcos(c, src[0]);
1164 break;
1165
1166 case nir_op_fsign:
1167 result = ntq_fsign(c, src[0]);
1168 break;
1169
1170 case nir_op_fabs:
1171 result = qir_FMAXABS(c, src[0], src[0]);
1172 break;
1173 case nir_op_iabs:
1174 result = qir_MAX(c, src[0],
1175 qir_SUB(c, qir_uniform_ui(c, 0), src[0]));
1176 break;
1177
1178 case nir_op_ibitfield_extract:
1179 result = ntq_emit_ibfe(c, src[0], src[1], src[2]);
1180 break;
1181
1182 case nir_op_ubitfield_extract:
1183 result = ntq_emit_ubfe(c, src[0], src[1], src[2]);
1184 break;
1185
1186 case nir_op_usadd_4x8:
1187 result = qir_V8ADDS(c, src[0], src[1]);
1188 break;
1189
1190 case nir_op_ussub_4x8:
1191 result = qir_V8SUBS(c, src[0], src[1]);
1192 break;
1193
1194 case nir_op_umin_4x8:
1195 result = qir_V8MIN(c, src[0], src[1]);
1196 break;
1197
1198 case nir_op_umax_4x8:
1199 result = qir_V8MAX(c, src[0], src[1]);
1200 break;
1201
1202 case nir_op_umul_unorm_4x8:
1203 result = qir_V8MULD(c, src[0], src[1]);
1204 break;
1205
1206 case nir_op_fddx:
1207 case nir_op_fddx_coarse:
1208 case nir_op_fddx_fine:
1209 result = ntq_fddx(c, src[0]);
1210 break;
1211
1212 case nir_op_fddy:
1213 case nir_op_fddy_coarse:
1214 case nir_op_fddy_fine:
1215 result = ntq_fddy(c, src[0]);
1216 break;
1217
1218 default:
1219 fprintf(stderr, "unknown NIR ALU inst: ");
1220 nir_print_instr(&instr->instr, stderr);
1221 fprintf(stderr, "\n");
1222 abort();
1223 }
1224
1225 /* We have a scalar result, so the instruction should only have a
1226 * single channel written to.
1227 */
1228 assert(util_is_power_of_two(instr->dest.write_mask));
1229 ntq_store_dest(c, &instr->dest.dest,
1230 ffs(instr->dest.write_mask) - 1, result);
1231 }
1232
1233 static void
1234 emit_frag_end(struct vc4_compile *c)
1235 {
1236 struct qreg color;
1237 if (c->output_color_index != -1) {
1238 color = c->outputs[c->output_color_index];
1239 } else {
1240 color = qir_uniform_ui(c, 0);
1241 }
1242
1243 uint32_t discard_cond = QPU_COND_ALWAYS;
1244 if (c->s->info.fs.uses_discard) {
1245 qir_SF(c, c->discard);
1246 discard_cond = QPU_COND_ZS;
1247 }
1248
1249 if (c->fs_key->stencil_enabled) {
1250 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1251 qir_uniform(c, QUNIFORM_STENCIL, 0));
1252 if (c->fs_key->stencil_twoside) {
1253 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1254 qir_uniform(c, QUNIFORM_STENCIL, 1));
1255 }
1256 if (c->fs_key->stencil_full_writemasks) {
1257 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1258 qir_uniform(c, QUNIFORM_STENCIL, 2));
1259 }
1260 }
1261
1262 if (c->output_sample_mask_index != -1) {
1263 qir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1264 }
1265
1266 if (c->fs_key->depth_enabled) {
1267 if (c->output_position_index != -1) {
1268 qir_FTOI_dest(c, qir_reg(QFILE_TLB_Z_WRITE, 0),
1269 qir_FMUL(c,
1270 c->outputs[c->output_position_index],
1271 qir_uniform_f(c, 0xffffff)))->cond = discard_cond;
1272 } else {
1273 qir_MOV_dest(c, qir_reg(QFILE_TLB_Z_WRITE, 0),
1274 qir_FRAG_Z(c))->cond = discard_cond;
1275 }
1276 }
1277
1278 if (!c->msaa_per_sample_output) {
1279 qir_MOV_dest(c, qir_reg(QFILE_TLB_COLOR_WRITE, 0),
1280 color)->cond = discard_cond;
1281 } else {
1282 for (int i = 0; i < VC4_MAX_SAMPLES; i++) {
1283 qir_MOV_dest(c, qir_reg(QFILE_TLB_COLOR_WRITE_MS, 0),
1284 c->sample_colors[i])->cond = discard_cond;
1285 }
1286 }
1287 }
1288
1289 static void
1290 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1291 {
1292 struct qreg packed = qir_get_temp(c);
1293
1294 for (int i = 0; i < 2; i++) {
1295 struct qreg scale =
1296 qir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1297
1298 struct qreg packed_chan = packed;
1299 packed_chan.pack = QPU_PACK_A_16A + i;
1300
1301 qir_FTOI_dest(c, packed_chan,
1302 qir_FMUL(c,
1303 qir_FMUL(c,
1304 c->outputs[c->output_position_index + i],
1305 scale),
1306 rcp_w));
1307 }
1308
1309 qir_VPM_WRITE(c, packed);
1310 }
1311
1312 static void
1313 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1314 {
1315 struct qreg zscale = qir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1316 struct qreg zoffset = qir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1317
1318 qir_VPM_WRITE(c, qir_FADD(c, qir_FMUL(c, qir_FMUL(c,
1319 c->outputs[c->output_position_index + 2],
1320 zscale),
1321 rcp_w),
1322 zoffset));
1323 }
1324
1325 static void
1326 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1327 {
1328 qir_VPM_WRITE(c, rcp_w);
1329 }
1330
1331 static void
1332 emit_point_size_write(struct vc4_compile *c)
1333 {
1334 struct qreg point_size;
1335
1336 if (c->output_point_size_index != -1)
1337 point_size = c->outputs[c->output_point_size_index];
1338 else
1339 point_size = qir_uniform_f(c, 1.0);
1340
1341 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1342 * BCM21553).
1343 */
1344 point_size = qir_FMAX(c, point_size, qir_uniform_f(c, .125));
1345
1346 qir_VPM_WRITE(c, point_size);
1347 }
1348
1349 /**
1350 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1351 *
1352 * The simulator insists that there be at least one vertex attribute, so
1353 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also
1354 * insists that all vertex attributes loaded get read by the VS/CS, so we have
1355 * to consume it here.
1356 */
1357 static void
1358 emit_stub_vpm_read(struct vc4_compile *c)
1359 {
1360 if (c->num_inputs)
1361 return;
1362
1363 c->vattr_sizes[0] = 4;
1364 (void)qir_MOV(c, qir_reg(QFILE_VPM, 0));
1365 c->num_inputs++;
1366 }
1367
1368 static void
1369 emit_vert_end(struct vc4_compile *c,
1370 struct vc4_varying_slot *fs_inputs,
1371 uint32_t num_fs_inputs)
1372 {
1373 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1374
1375 emit_stub_vpm_read(c);
1376
1377 emit_scaled_viewport_write(c, rcp_w);
1378 emit_zs_write(c, rcp_w);
1379 emit_rcp_wc_write(c, rcp_w);
1380 if (c->vs_key->per_vertex_point_size)
1381 emit_point_size_write(c);
1382
1383 for (int i = 0; i < num_fs_inputs; i++) {
1384 struct vc4_varying_slot *input = &fs_inputs[i];
1385 int j;
1386
1387 for (j = 0; j < c->num_outputs; j++) {
1388 struct vc4_varying_slot *output =
1389 &c->output_slots[j];
1390
1391 if (input->slot == output->slot &&
1392 input->swizzle == output->swizzle) {
1393 qir_VPM_WRITE(c, c->outputs[j]);
1394 break;
1395 }
1396 }
1397 /* Emit padding if we didn't find a declared VS output for
1398 * this FS input.
1399 */
1400 if (j == c->num_outputs)
1401 qir_VPM_WRITE(c, qir_uniform_f(c, 0.0));
1402 }
1403 }
1404
1405 static void
1406 emit_coord_end(struct vc4_compile *c)
1407 {
1408 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1409
1410 emit_stub_vpm_read(c);
1411
1412 for (int i = 0; i < 4; i++)
1413 qir_VPM_WRITE(c, c->outputs[c->output_position_index + i]);
1414
1415 emit_scaled_viewport_write(c, rcp_w);
1416 emit_zs_write(c, rcp_w);
1417 emit_rcp_wc_write(c, rcp_w);
1418 if (c->vs_key->per_vertex_point_size)
1419 emit_point_size_write(c);
1420 }
1421
1422 static void
1423 vc4_optimize_nir(struct nir_shader *s)
1424 {
1425 bool progress;
1426
1427 do {
1428 progress = false;
1429
1430 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1431 NIR_PASS(progress, s, nir_lower_alu_to_scalar);
1432 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1433 NIR_PASS(progress, s, nir_copy_prop);
1434 NIR_PASS(progress, s, nir_opt_remove_phis);
1435 NIR_PASS(progress, s, nir_opt_dce);
1436 NIR_PASS(progress, s, nir_opt_dead_cf);
1437 NIR_PASS(progress, s, nir_opt_cse);
1438 NIR_PASS(progress, s, nir_opt_peephole_select, 8);
1439 NIR_PASS(progress, s, nir_opt_algebraic);
1440 NIR_PASS(progress, s, nir_opt_constant_folding);
1441 NIR_PASS(progress, s, nir_opt_undef);
1442 } while (progress);
1443 }
1444
1445 static int
1446 driver_location_compare(const void *in_a, const void *in_b)
1447 {
1448 const nir_variable *const *a = in_a;
1449 const nir_variable *const *b = in_b;
1450
1451 return (*a)->data.driver_location - (*b)->data.driver_location;
1452 }
1453
1454 static void
1455 ntq_setup_inputs(struct vc4_compile *c)
1456 {
1457 unsigned num_entries = 0;
1458 nir_foreach_variable(var, &c->s->inputs)
1459 num_entries++;
1460
1461 nir_variable *vars[num_entries];
1462
1463 unsigned i = 0;
1464 nir_foreach_variable(var, &c->s->inputs)
1465 vars[i++] = var;
1466
1467 /* Sort the variables so that we emit the input setup in
1468 * driver_location order. This is required for VPM reads, whose data
1469 * is fetched into the VPM in driver_location (TGSI register index)
1470 * order.
1471 */
1472 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1473
1474 for (unsigned i = 0; i < num_entries; i++) {
1475 nir_variable *var = vars[i];
1476 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1477 unsigned loc = var->data.driver_location;
1478
1479 assert(array_len == 1);
1480 (void)array_len;
1481 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1482 (loc + 1) * 4);
1483
1484 if (c->stage == QSTAGE_FRAG) {
1485 if (var->data.location == VARYING_SLOT_POS) {
1486 emit_fragcoord_input(c, loc);
1487 } else if (var->data.location == VARYING_SLOT_PNTC ||
1488 (var->data.location >= VARYING_SLOT_VAR0 &&
1489 (c->fs_key->point_sprite_mask &
1490 (1 << (var->data.location -
1491 VARYING_SLOT_VAR0))))) {
1492 c->inputs[loc * 4 + 0] = c->point_x;
1493 c->inputs[loc * 4 + 1] = c->point_y;
1494 } else {
1495 emit_fragment_input(c, loc, var->data.location);
1496 }
1497 } else {
1498 emit_vertex_input(c, loc);
1499 }
1500 }
1501 }
1502
1503 static void
1504 ntq_setup_outputs(struct vc4_compile *c)
1505 {
1506 nir_foreach_variable(var, &c->s->outputs) {
1507 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1508 unsigned loc = var->data.driver_location * 4;
1509
1510 assert(array_len == 1);
1511 (void)array_len;
1512
1513 for (int i = 0; i < 4; i++)
1514 add_output(c, loc + i, var->data.location, i);
1515
1516 if (c->stage == QSTAGE_FRAG) {
1517 switch (var->data.location) {
1518 case FRAG_RESULT_COLOR:
1519 case FRAG_RESULT_DATA0:
1520 c->output_color_index = loc;
1521 break;
1522 case FRAG_RESULT_DEPTH:
1523 c->output_position_index = loc;
1524 break;
1525 case FRAG_RESULT_SAMPLE_MASK:
1526 c->output_sample_mask_index = loc;
1527 break;
1528 }
1529 } else {
1530 switch (var->data.location) {
1531 case VARYING_SLOT_POS:
1532 c->output_position_index = loc;
1533 break;
1534 case VARYING_SLOT_PSIZ:
1535 c->output_point_size_index = loc;
1536 break;
1537 }
1538 }
1539 }
1540 }
1541
1542 static void
1543 ntq_setup_uniforms(struct vc4_compile *c)
1544 {
1545 nir_foreach_variable(var, &c->s->uniforms) {
1546 uint32_t vec4_count = st_glsl_type_size(var->type);
1547 unsigned vec4_size = 4 * sizeof(float);
1548
1549 declare_uniform_range(c, var->data.driver_location * vec4_size,
1550 vec4_count * vec4_size);
1551
1552 }
1553 }
1554
1555 /**
1556 * Sets up the mapping from nir_register to struct qreg *.
1557 *
1558 * Each nir_register gets a struct qreg per 32-bit component being stored.
1559 */
1560 static void
1561 ntq_setup_registers(struct vc4_compile *c, struct exec_list *list)
1562 {
1563 foreach_list_typed(nir_register, nir_reg, node, list) {
1564 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1565 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1566 array_len *
1567 nir_reg->num_components);
1568
1569 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1570
1571 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1572 qregs[i] = qir_get_temp(c);
1573 }
1574 }
1575
1576 static void
1577 ntq_emit_load_const(struct vc4_compile *c, nir_load_const_instr *instr)
1578 {
1579 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1580 for (int i = 0; i < instr->def.num_components; i++)
1581 qregs[i] = qir_uniform_ui(c, instr->value.u32[i]);
1582
1583 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1584 }
1585
1586 static void
1587 ntq_emit_ssa_undef(struct vc4_compile *c, nir_ssa_undef_instr *instr)
1588 {
1589 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1590
1591 /* QIR needs there to be *some* value, so pick 0 (same as for
1592 * ntq_setup_registers().
1593 */
1594 for (int i = 0; i < instr->def.num_components; i++)
1595 qregs[i] = qir_uniform_ui(c, 0);
1596 }
1597
1598 static void
1599 ntq_emit_intrinsic(struct vc4_compile *c, nir_intrinsic_instr *instr)
1600 {
1601 nir_const_value *const_offset;
1602 unsigned offset;
1603
1604 switch (instr->intrinsic) {
1605 case nir_intrinsic_load_uniform:
1606 assert(instr->num_components == 1);
1607 const_offset = nir_src_as_const_value(instr->src[0]);
1608 if (const_offset) {
1609 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1610 assert(offset % 4 == 0);
1611 /* We need dwords */
1612 offset = offset / 4;
1613 ntq_store_dest(c, &instr->dest, 0,
1614 qir_uniform(c, QUNIFORM_UNIFORM,
1615 offset));
1616 } else {
1617 ntq_store_dest(c, &instr->dest, 0,
1618 indirect_uniform_load(c, instr));
1619 }
1620 break;
1621
1622 case nir_intrinsic_load_user_clip_plane:
1623 for (int i = 0; i < instr->num_components; i++) {
1624 ntq_store_dest(c, &instr->dest, i,
1625 qir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1626 nir_intrinsic_ucp_id(instr) *
1627 4 + i));
1628 }
1629 break;
1630
1631 case nir_intrinsic_load_blend_const_color_r_float:
1632 case nir_intrinsic_load_blend_const_color_g_float:
1633 case nir_intrinsic_load_blend_const_color_b_float:
1634 case nir_intrinsic_load_blend_const_color_a_float:
1635 ntq_store_dest(c, &instr->dest, 0,
1636 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_X +
1637 (instr->intrinsic -
1638 nir_intrinsic_load_blend_const_color_r_float),
1639 0));
1640 break;
1641
1642 case nir_intrinsic_load_blend_const_color_rgba8888_unorm:
1643 ntq_store_dest(c, &instr->dest, 0,
1644 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_RGBA,
1645 0));
1646 break;
1647
1648 case nir_intrinsic_load_blend_const_color_aaaa8888_unorm:
1649 ntq_store_dest(c, &instr->dest, 0,
1650 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_AAAA,
1651 0));
1652 break;
1653
1654 case nir_intrinsic_load_alpha_ref_float:
1655 ntq_store_dest(c, &instr->dest, 0,
1656 qir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1657 break;
1658
1659 case nir_intrinsic_load_sample_mask_in:
1660 ntq_store_dest(c, &instr->dest, 0,
1661 qir_uniform(c, QUNIFORM_SAMPLE_MASK, 0));
1662 break;
1663
1664 case nir_intrinsic_load_front_face:
1665 /* The register contains 0 (front) or 1 (back), and we need to
1666 * turn it into a NIR bool where true means front.
1667 */
1668 ntq_store_dest(c, &instr->dest, 0,
1669 qir_ADD(c,
1670 qir_uniform_ui(c, -1),
1671 qir_reg(QFILE_FRAG_REV_FLAG, 0)));
1672 break;
1673
1674 case nir_intrinsic_load_input:
1675 assert(instr->num_components == 1);
1676 const_offset = nir_src_as_const_value(instr->src[0]);
1677 assert(const_offset && "vc4 doesn't support indirect inputs");
1678 if (c->stage == QSTAGE_FRAG &&
1679 nir_intrinsic_base(instr) >= VC4_NIR_TLB_COLOR_READ_INPUT) {
1680 assert(const_offset->u32[0] == 0);
1681 /* Reads of the per-sample color need to be done in
1682 * order.
1683 */
1684 int sample_index = (nir_intrinsic_base(instr) -
1685 VC4_NIR_TLB_COLOR_READ_INPUT);
1686 for (int i = 0; i <= sample_index; i++) {
1687 if (c->color_reads[i].file == QFILE_NULL) {
1688 c->color_reads[i] =
1689 qir_TLB_COLOR_READ(c);
1690 }
1691 }
1692 ntq_store_dest(c, &instr->dest, 0,
1693 c->color_reads[sample_index]);
1694 } else {
1695 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1696 int comp = nir_intrinsic_component(instr);
1697 ntq_store_dest(c, &instr->dest, 0,
1698 c->inputs[offset * 4 + comp]);
1699 }
1700 break;
1701
1702 case nir_intrinsic_store_output:
1703 const_offset = nir_src_as_const_value(instr->src[1]);
1704 assert(const_offset && "vc4 doesn't support indirect outputs");
1705 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1706
1707 /* MSAA color outputs are the only case where we have an
1708 * output that's not lowered to being a store of a single 32
1709 * bit value.
1710 */
1711 if (c->stage == QSTAGE_FRAG && instr->num_components == 4) {
1712 assert(offset == c->output_color_index);
1713 for (int i = 0; i < 4; i++) {
1714 c->sample_colors[i] =
1715 qir_MOV(c, ntq_get_src(c, instr->src[0],
1716 i));
1717 }
1718 } else {
1719 offset = offset * 4 + nir_intrinsic_component(instr);
1720 assert(instr->num_components == 1);
1721 c->outputs[offset] =
1722 qir_MOV(c, ntq_get_src(c, instr->src[0], 0));
1723 c->num_outputs = MAX2(c->num_outputs, offset + 1);
1724 }
1725 break;
1726
1727 case nir_intrinsic_discard:
1728 if (c->execute.file != QFILE_NULL) {
1729 qir_SF(c, c->execute);
1730 qir_MOV_cond(c, QPU_COND_ZS, c->discard,
1731 qir_uniform_ui(c, ~0));
1732 } else {
1733 qir_MOV_dest(c, c->discard, qir_uniform_ui(c, ~0));
1734 }
1735 break;
1736
1737 case nir_intrinsic_discard_if: {
1738 /* true (~0) if we're discarding */
1739 struct qreg cond = ntq_get_src(c, instr->src[0], 0);
1740
1741 if (c->execute.file != QFILE_NULL) {
1742 /* execute == 0 means the channel is active. Invert
1743 * the condition so that we can use zero as "executing
1744 * and discarding."
1745 */
1746 qir_SF(c, qir_AND(c, c->execute, qir_NOT(c, cond)));
1747 qir_MOV_cond(c, QPU_COND_ZS, c->discard, cond);
1748 } else {
1749 qir_OR_dest(c, c->discard, c->discard,
1750 ntq_get_src(c, instr->src[0], 0));
1751 }
1752
1753 break;
1754 }
1755
1756 default:
1757 fprintf(stderr, "Unknown intrinsic: ");
1758 nir_print_instr(&instr->instr, stderr);
1759 fprintf(stderr, "\n");
1760 break;
1761 }
1762 }
1763
1764 /* Clears (activates) the execute flags for any channels whose jump target
1765 * matches this block.
1766 */
1767 static void
1768 ntq_activate_execute_for_block(struct vc4_compile *c)
1769 {
1770 qir_SF(c, qir_SUB(c,
1771 c->execute,
1772 qir_uniform_ui(c, c->cur_block->index)));
1773 qir_MOV_cond(c, QPU_COND_ZS, c->execute, qir_uniform_ui(c, 0));
1774 }
1775
1776 static void
1777 ntq_emit_if(struct vc4_compile *c, nir_if *if_stmt)
1778 {
1779 if (!c->vc4->screen->has_control_flow) {
1780 fprintf(stderr,
1781 "IF statement support requires updated kernel.\n");
1782 return;
1783 }
1784
1785 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
1786 bool empty_else_block =
1787 (nir_else_block == nir_if_last_else_block(if_stmt) &&
1788 exec_list_is_empty(&nir_else_block->instr_list));
1789
1790 struct qblock *then_block = qir_new_block(c);
1791 struct qblock *after_block = qir_new_block(c);
1792 struct qblock *else_block;
1793 if (empty_else_block)
1794 else_block = after_block;
1795 else
1796 else_block = qir_new_block(c);
1797
1798 bool was_top_level = false;
1799 if (c->execute.file == QFILE_NULL) {
1800 c->execute = qir_MOV(c, qir_uniform_ui(c, 0));
1801 was_top_level = true;
1802 }
1803
1804 /* Set ZS for executing (execute == 0) and jumping (if->condition ==
1805 * 0) channels, and then update execute flags for those to point to
1806 * the ELSE block.
1807 */
1808 qir_SF(c, qir_OR(c,
1809 c->execute,
1810 ntq_get_src(c, if_stmt->condition, 0)));
1811 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
1812 qir_uniform_ui(c, else_block->index));
1813
1814 /* Jump to ELSE if nothing is active for THEN, otherwise fall
1815 * through.
1816 */
1817 qir_SF(c, c->execute);
1818 qir_BRANCH(c, QPU_COND_BRANCH_ALL_ZC);
1819 qir_link_blocks(c->cur_block, else_block);
1820 qir_link_blocks(c->cur_block, then_block);
1821
1822 /* Process the THEN block. */
1823 qir_set_emit_block(c, then_block);
1824 ntq_emit_cf_list(c, &if_stmt->then_list);
1825
1826 if (!empty_else_block) {
1827 /* Handle the end of the THEN block. First, all currently
1828 * active channels update their execute flags to point to
1829 * ENDIF
1830 */
1831 qir_SF(c, c->execute);
1832 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
1833 qir_uniform_ui(c, after_block->index));
1834
1835 /* If everything points at ENDIF, then jump there immediately. */
1836 qir_SF(c, qir_SUB(c, c->execute, qir_uniform_ui(c, after_block->index)));
1837 qir_BRANCH(c, QPU_COND_BRANCH_ALL_ZS);
1838 qir_link_blocks(c->cur_block, after_block);
1839 qir_link_blocks(c->cur_block, else_block);
1840
1841 qir_set_emit_block(c, else_block);
1842 ntq_activate_execute_for_block(c);
1843 ntq_emit_cf_list(c, &if_stmt->else_list);
1844 }
1845
1846 qir_link_blocks(c->cur_block, after_block);
1847
1848 qir_set_emit_block(c, after_block);
1849 if (was_top_level)
1850 c->execute = c->undef;
1851 else
1852 ntq_activate_execute_for_block(c);
1853
1854 }
1855
1856 static void
1857 ntq_emit_jump(struct vc4_compile *c, nir_jump_instr *jump)
1858 {
1859 switch (jump->type) {
1860 case nir_jump_break:
1861 qir_SF(c, c->execute);
1862 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
1863 qir_uniform_ui(c, c->loop_break_block->index));
1864 break;
1865
1866 case nir_jump_continue:
1867 qir_SF(c, c->execute);
1868 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
1869 qir_uniform_ui(c, c->loop_cont_block->index));
1870 break;
1871
1872 case nir_jump_return:
1873 unreachable("All returns shouold be lowered\n");
1874 }
1875 }
1876
1877 static void
1878 ntq_emit_instr(struct vc4_compile *c, nir_instr *instr)
1879 {
1880 switch (instr->type) {
1881 case nir_instr_type_alu:
1882 ntq_emit_alu(c, nir_instr_as_alu(instr));
1883 break;
1884
1885 case nir_instr_type_intrinsic:
1886 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
1887 break;
1888
1889 case nir_instr_type_load_const:
1890 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
1891 break;
1892
1893 case nir_instr_type_ssa_undef:
1894 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
1895 break;
1896
1897 case nir_instr_type_tex:
1898 ntq_emit_tex(c, nir_instr_as_tex(instr));
1899 break;
1900
1901 case nir_instr_type_jump:
1902 ntq_emit_jump(c, nir_instr_as_jump(instr));
1903 break;
1904
1905 default:
1906 fprintf(stderr, "Unknown NIR instr type: ");
1907 nir_print_instr(instr, stderr);
1908 fprintf(stderr, "\n");
1909 abort();
1910 }
1911 }
1912
1913 static void
1914 ntq_emit_block(struct vc4_compile *c, nir_block *block)
1915 {
1916 nir_foreach_instr(instr, block) {
1917 ntq_emit_instr(c, instr);
1918 }
1919 }
1920
1921 static void ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list);
1922
1923 static void
1924 ntq_emit_loop(struct vc4_compile *c, nir_loop *loop)
1925 {
1926 if (!c->vc4->screen->has_control_flow) {
1927 fprintf(stderr,
1928 "loop support requires updated kernel.\n");
1929 ntq_emit_cf_list(c, &loop->body);
1930 return;
1931 }
1932
1933 bool was_top_level = false;
1934 if (c->execute.file == QFILE_NULL) {
1935 c->execute = qir_MOV(c, qir_uniform_ui(c, 0));
1936 was_top_level = true;
1937 }
1938
1939 struct qblock *save_loop_cont_block = c->loop_cont_block;
1940 struct qblock *save_loop_break_block = c->loop_break_block;
1941
1942 c->loop_cont_block = qir_new_block(c);
1943 c->loop_break_block = qir_new_block(c);
1944
1945 qir_link_blocks(c->cur_block, c->loop_cont_block);
1946 qir_set_emit_block(c, c->loop_cont_block);
1947 ntq_activate_execute_for_block(c);
1948
1949 ntq_emit_cf_list(c, &loop->body);
1950
1951 /* If anything had explicitly continued, or is here at the end of the
1952 * loop, then we need to loop again. SF updates are masked by the
1953 * instruction's condition, so we can do the OR of the two conditions
1954 * within SF.
1955 */
1956 qir_SF(c, c->execute);
1957 struct qinst *cont_check =
1958 qir_SUB_dest(c,
1959 c->undef,
1960 c->execute,
1961 qir_uniform_ui(c, c->loop_cont_block->index));
1962 cont_check->cond = QPU_COND_ZC;
1963 cont_check->sf = true;
1964
1965 qir_BRANCH(c, QPU_COND_BRANCH_ANY_ZS);
1966 qir_link_blocks(c->cur_block, c->loop_cont_block);
1967 qir_link_blocks(c->cur_block, c->loop_break_block);
1968
1969 qir_set_emit_block(c, c->loop_break_block);
1970 if (was_top_level)
1971 c->execute = c->undef;
1972 else
1973 ntq_activate_execute_for_block(c);
1974
1975 c->loop_break_block = save_loop_break_block;
1976 c->loop_cont_block = save_loop_cont_block;
1977 }
1978
1979 static void
1980 ntq_emit_function(struct vc4_compile *c, nir_function_impl *func)
1981 {
1982 fprintf(stderr, "FUNCTIONS not handled.\n");
1983 abort();
1984 }
1985
1986 static void
1987 ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list)
1988 {
1989 foreach_list_typed(nir_cf_node, node, node, list) {
1990 switch (node->type) {
1991 case nir_cf_node_block:
1992 ntq_emit_block(c, nir_cf_node_as_block(node));
1993 break;
1994
1995 case nir_cf_node_if:
1996 ntq_emit_if(c, nir_cf_node_as_if(node));
1997 break;
1998
1999 case nir_cf_node_loop:
2000 ntq_emit_loop(c, nir_cf_node_as_loop(node));
2001 break;
2002
2003 case nir_cf_node_function:
2004 ntq_emit_function(c, nir_cf_node_as_function(node));
2005 break;
2006
2007 default:
2008 fprintf(stderr, "Unknown NIR node type\n");
2009 abort();
2010 }
2011 }
2012 }
2013
2014 static void
2015 ntq_emit_impl(struct vc4_compile *c, nir_function_impl *impl)
2016 {
2017 ntq_setup_registers(c, &impl->registers);
2018 ntq_emit_cf_list(c, &impl->body);
2019 }
2020
2021 static void
2022 nir_to_qir(struct vc4_compile *c)
2023 {
2024 if (c->stage == QSTAGE_FRAG && c->s->info.fs.uses_discard)
2025 c->discard = qir_MOV(c, qir_uniform_ui(c, 0));
2026
2027 ntq_setup_inputs(c);
2028 ntq_setup_outputs(c);
2029 ntq_setup_uniforms(c);
2030 ntq_setup_registers(c, &c->s->registers);
2031
2032 /* Find the main function and emit the body. */
2033 nir_foreach_function(function, c->s) {
2034 assert(strcmp(function->name, "main") == 0);
2035 assert(function->impl);
2036 ntq_emit_impl(c, function->impl);
2037 }
2038 }
2039
2040 static const nir_shader_compiler_options nir_options = {
2041 .lower_extract_byte = true,
2042 .lower_extract_word = true,
2043 .lower_ffma = true,
2044 .lower_flrp32 = true,
2045 .lower_fpow = true,
2046 .lower_fsat = true,
2047 .lower_fsqrt = true,
2048 .lower_negate = true,
2049 .native_integers = true,
2050 };
2051
2052 const void *
2053 vc4_screen_get_compiler_options(struct pipe_screen *pscreen,
2054 enum pipe_shader_ir ir, unsigned shader)
2055 {
2056 return &nir_options;
2057 }
2058
2059 static int
2060 count_nir_instrs(nir_shader *nir)
2061 {
2062 int count = 0;
2063 nir_foreach_function(function, nir) {
2064 if (!function->impl)
2065 continue;
2066 nir_foreach_block(block, function->impl) {
2067 nir_foreach_instr(instr, block)
2068 count++;
2069 }
2070 }
2071 return count;
2072 }
2073
2074 static struct vc4_compile *
2075 vc4_shader_ntq(struct vc4_context *vc4, enum qstage stage,
2076 struct vc4_key *key)
2077 {
2078 struct vc4_compile *c = qir_compile_init();
2079
2080 c->vc4 = vc4;
2081 c->stage = stage;
2082 c->shader_state = &key->shader_state->base;
2083 c->program_id = key->shader_state->program_id;
2084 c->variant_id =
2085 p_atomic_inc_return(&key->shader_state->compiled_variant_count);
2086
2087 c->key = key;
2088 switch (stage) {
2089 case QSTAGE_FRAG:
2090 c->fs_key = (struct vc4_fs_key *)key;
2091 if (c->fs_key->is_points) {
2092 c->point_x = emit_fragment_varying(c, ~0, 0);
2093 c->point_y = emit_fragment_varying(c, ~0, 0);
2094 } else if (c->fs_key->is_lines) {
2095 c->line_x = emit_fragment_varying(c, ~0, 0);
2096 }
2097 break;
2098 case QSTAGE_VERT:
2099 c->vs_key = (struct vc4_vs_key *)key;
2100 break;
2101 case QSTAGE_COORD:
2102 c->vs_key = (struct vc4_vs_key *)key;
2103 break;
2104 }
2105
2106 c->s = nir_shader_clone(c, key->shader_state->base.ir.nir);
2107
2108 if (stage == QSTAGE_FRAG)
2109 NIR_PASS_V(c->s, vc4_nir_lower_blend, c);
2110
2111 struct nir_lower_tex_options tex_options = {
2112 /* We would need to implement txs, but we don't want the
2113 * int/float conversions
2114 */
2115 .lower_rect = false,
2116
2117 .lower_txp = ~0,
2118
2119 /* Apply swizzles to all samplers. */
2120 .swizzle_result = ~0,
2121 };
2122
2123 /* Lower the format swizzle and ARB_texture_swizzle-style swizzle.
2124 * The format swizzling applies before sRGB decode, and
2125 * ARB_texture_swizzle is the last thing before returning the sample.
2126 */
2127 for (int i = 0; i < ARRAY_SIZE(key->tex); i++) {
2128 enum pipe_format format = c->key->tex[i].format;
2129
2130 if (!format)
2131 continue;
2132
2133 const uint8_t *format_swizzle = vc4_get_format_swizzle(format);
2134
2135 for (int j = 0; j < 4; j++) {
2136 uint8_t arb_swiz = c->key->tex[i].swizzle[j];
2137
2138 if (arb_swiz <= 3) {
2139 tex_options.swizzles[i][j] =
2140 format_swizzle[arb_swiz];
2141 } else {
2142 tex_options.swizzles[i][j] = arb_swiz;
2143 }
2144 }
2145
2146 if (util_format_is_srgb(format))
2147 tex_options.lower_srgb |= (1 << i);
2148 }
2149
2150 NIR_PASS_V(c->s, nir_lower_tex, &tex_options);
2151
2152 if (c->fs_key && c->fs_key->light_twoside)
2153 NIR_PASS_V(c->s, nir_lower_two_sided_color);
2154
2155 if (c->vs_key && c->vs_key->clamp_color)
2156 NIR_PASS_V(c->s, nir_lower_clamp_color_outputs);
2157
2158 if (c->key->ucp_enables) {
2159 if (stage == QSTAGE_FRAG) {
2160 NIR_PASS_V(c->s, nir_lower_clip_fs, c->key->ucp_enables);
2161 } else {
2162 NIR_PASS_V(c->s, nir_lower_clip_vs, c->key->ucp_enables);
2163 NIR_PASS_V(c->s, nir_lower_io_to_scalar,
2164 nir_var_shader_out);
2165 }
2166 }
2167
2168 /* FS input scalarizing must happen after nir_lower_two_sided_color,
2169 * which only handles a vec4 at a time. Similarly, VS output
2170 * scalarizing must happen after nir_lower_clip_vs.
2171 */
2172 if (c->stage == QSTAGE_FRAG)
2173 NIR_PASS_V(c->s, nir_lower_io_to_scalar, nir_var_shader_in);
2174 else
2175 NIR_PASS_V(c->s, nir_lower_io_to_scalar, nir_var_shader_out);
2176
2177 NIR_PASS_V(c->s, vc4_nir_lower_io, c);
2178 NIR_PASS_V(c->s, vc4_nir_lower_txf_ms, c);
2179 NIR_PASS_V(c->s, nir_lower_idiv);
2180
2181 vc4_optimize_nir(c->s);
2182
2183 NIR_PASS_V(c->s, nir_convert_from_ssa, true);
2184
2185 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2186 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d NIR instructions\n",
2187 qir_get_stage_name(c->stage),
2188 c->program_id, c->variant_id,
2189 count_nir_instrs(c->s));
2190 }
2191
2192 if (vc4_debug & VC4_DEBUG_NIR) {
2193 fprintf(stderr, "%s prog %d/%d NIR:\n",
2194 qir_get_stage_name(c->stage),
2195 c->program_id, c->variant_id);
2196 nir_print_shader(c->s, stderr);
2197 }
2198
2199 nir_to_qir(c);
2200
2201 switch (stage) {
2202 case QSTAGE_FRAG:
2203 emit_frag_end(c);
2204 break;
2205 case QSTAGE_VERT:
2206 emit_vert_end(c,
2207 c->vs_key->fs_inputs->input_slots,
2208 c->vs_key->fs_inputs->num_inputs);
2209 break;
2210 case QSTAGE_COORD:
2211 emit_coord_end(c);
2212 break;
2213 }
2214
2215 if (vc4_debug & VC4_DEBUG_QIR) {
2216 fprintf(stderr, "%s prog %d/%d pre-opt QIR:\n",
2217 qir_get_stage_name(c->stage),
2218 c->program_id, c->variant_id);
2219 qir_dump(c);
2220 fprintf(stderr, "\n");
2221 }
2222
2223 qir_optimize(c);
2224 qir_lower_uniforms(c);
2225
2226 qir_schedule_instructions(c);
2227 qir_emit_uniform_stream_resets(c);
2228
2229 if (vc4_debug & VC4_DEBUG_QIR) {
2230 fprintf(stderr, "%s prog %d/%d QIR:\n",
2231 qir_get_stage_name(c->stage),
2232 c->program_id, c->variant_id);
2233 qir_dump(c);
2234 fprintf(stderr, "\n");
2235 }
2236
2237 qir_reorder_uniforms(c);
2238 vc4_generate_code(vc4, c);
2239
2240 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2241 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d instructions\n",
2242 qir_get_stage_name(c->stage),
2243 c->program_id, c->variant_id,
2244 c->qpu_inst_count);
2245 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d uniforms\n",
2246 qir_get_stage_name(c->stage),
2247 c->program_id, c->variant_id,
2248 c->num_uniforms);
2249 }
2250
2251 ralloc_free(c->s);
2252
2253 return c;
2254 }
2255
2256 static void *
2257 vc4_shader_state_create(struct pipe_context *pctx,
2258 const struct pipe_shader_state *cso)
2259 {
2260 struct vc4_context *vc4 = vc4_context(pctx);
2261 struct vc4_uncompiled_shader *so = CALLOC_STRUCT(vc4_uncompiled_shader);
2262 if (!so)
2263 return NULL;
2264
2265 so->program_id = vc4->next_uncompiled_program_id++;
2266
2267 nir_shader *s;
2268
2269 if (cso->type == PIPE_SHADER_IR_NIR) {
2270 /* The backend takes ownership of the NIR shader on state
2271 * creation.
2272 */
2273 s = cso->ir.nir;
2274 } else {
2275 assert(cso->type == PIPE_SHADER_IR_TGSI);
2276
2277 if (vc4_debug & VC4_DEBUG_TGSI) {
2278 fprintf(stderr, "prog %d TGSI:\n",
2279 so->program_id);
2280 tgsi_dump(cso->tokens, 0);
2281 fprintf(stderr, "\n");
2282 }
2283 s = tgsi_to_nir(cso->tokens, &nir_options);
2284 }
2285
2286 NIR_PASS_V(s, nir_opt_global_to_local);
2287 NIR_PASS_V(s, nir_convert_to_ssa);
2288 NIR_PASS_V(s, nir_normalize_cubemap_coords);
2289
2290 NIR_PASS_V(s, nir_lower_load_const_to_scalar);
2291
2292 vc4_optimize_nir(s);
2293
2294 NIR_PASS_V(s, nir_remove_dead_variables, nir_var_local);
2295
2296 /* Garbage collect dead instructions */
2297 nir_sweep(s);
2298
2299 so->base.type = PIPE_SHADER_IR_NIR;
2300 so->base.ir.nir = s;
2301
2302 if (vc4_debug & VC4_DEBUG_NIR) {
2303 fprintf(stderr, "%s prog %d NIR:\n",
2304 gl_shader_stage_name(s->stage),
2305 so->program_id);
2306 nir_print_shader(s, stderr);
2307 fprintf(stderr, "\n");
2308 }
2309
2310 return so;
2311 }
2312
2313 static void
2314 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
2315 struct vc4_compile *c)
2316 {
2317 int count = c->num_uniforms;
2318 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
2319
2320 uinfo->count = count;
2321 uinfo->data = ralloc_array(shader, uint32_t, count);
2322 memcpy(uinfo->data, c->uniform_data,
2323 count * sizeof(*uinfo->data));
2324 uinfo->contents = ralloc_array(shader, enum quniform_contents, count);
2325 memcpy(uinfo->contents, c->uniform_contents,
2326 count * sizeof(*uinfo->contents));
2327 uinfo->num_texture_samples = c->num_texture_samples;
2328
2329 vc4_set_shader_uniform_dirty_flags(shader);
2330 }
2331
2332 static void
2333 vc4_setup_compiled_fs_inputs(struct vc4_context *vc4, struct vc4_compile *c,
2334 struct vc4_compiled_shader *shader)
2335 {
2336 struct vc4_fs_inputs inputs;
2337
2338 memset(&inputs, 0, sizeof(inputs));
2339 inputs.input_slots = ralloc_array(shader,
2340 struct vc4_varying_slot,
2341 c->num_input_slots);
2342
2343 bool input_live[c->num_input_slots];
2344
2345 memset(input_live, 0, sizeof(input_live));
2346 qir_for_each_inst_inorder(inst, c) {
2347 for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) {
2348 if (inst->src[i].file == QFILE_VARY)
2349 input_live[inst->src[i].index] = true;
2350 }
2351 }
2352
2353 for (int i = 0; i < c->num_input_slots; i++) {
2354 struct vc4_varying_slot *slot = &c->input_slots[i];
2355
2356 if (!input_live[i])
2357 continue;
2358
2359 /* Skip non-VS-output inputs. */
2360 if (slot->slot == (uint8_t)~0)
2361 continue;
2362
2363 if (slot->slot == VARYING_SLOT_COL0 ||
2364 slot->slot == VARYING_SLOT_COL1 ||
2365 slot->slot == VARYING_SLOT_BFC0 ||
2366 slot->slot == VARYING_SLOT_BFC1) {
2367 shader->color_inputs |= (1 << inputs.num_inputs);
2368 }
2369
2370 inputs.input_slots[inputs.num_inputs] = *slot;
2371 inputs.num_inputs++;
2372 }
2373 shader->num_inputs = inputs.num_inputs;
2374
2375 /* Add our set of inputs to the set of all inputs seen. This way, we
2376 * can have a single pointer that identifies an FS inputs set,
2377 * allowing VS to avoid recompiling when the FS is recompiled (or a
2378 * new one is bound using separate shader objects) but the inputs
2379 * don't change.
2380 */
2381 struct set_entry *entry = _mesa_set_search(vc4->fs_inputs_set, &inputs);
2382 if (entry) {
2383 shader->fs_inputs = entry->key;
2384 ralloc_free(inputs.input_slots);
2385 } else {
2386 struct vc4_fs_inputs *alloc_inputs;
2387
2388 alloc_inputs = rzalloc(vc4->fs_inputs_set, struct vc4_fs_inputs);
2389 memcpy(alloc_inputs, &inputs, sizeof(inputs));
2390 ralloc_steal(alloc_inputs, inputs.input_slots);
2391 _mesa_set_add(vc4->fs_inputs_set, alloc_inputs);
2392
2393 shader->fs_inputs = alloc_inputs;
2394 }
2395 }
2396
2397 static struct vc4_compiled_shader *
2398 vc4_get_compiled_shader(struct vc4_context *vc4, enum qstage stage,
2399 struct vc4_key *key)
2400 {
2401 struct hash_table *ht;
2402 uint32_t key_size;
2403 if (stage == QSTAGE_FRAG) {
2404 ht = vc4->fs_cache;
2405 key_size = sizeof(struct vc4_fs_key);
2406 } else {
2407 ht = vc4->vs_cache;
2408 key_size = sizeof(struct vc4_vs_key);
2409 }
2410
2411 struct vc4_compiled_shader *shader;
2412 struct hash_entry *entry = _mesa_hash_table_search(ht, key);
2413 if (entry)
2414 return entry->data;
2415
2416 struct vc4_compile *c = vc4_shader_ntq(vc4, stage, key);
2417 shader = rzalloc(NULL, struct vc4_compiled_shader);
2418
2419 shader->program_id = vc4->next_compiled_program_id++;
2420 if (stage == QSTAGE_FRAG) {
2421 vc4_setup_compiled_fs_inputs(vc4, c, shader);
2422
2423 /* Note: the temporary clone in c->s has been freed. */
2424 nir_shader *orig_shader = key->shader_state->base.ir.nir;
2425 if (orig_shader->info.outputs_written & (1 << FRAG_RESULT_DEPTH))
2426 shader->disable_early_z = true;
2427 } else {
2428 shader->num_inputs = c->num_inputs;
2429
2430 shader->vattr_offsets[0] = 0;
2431 for (int i = 0; i < 8; i++) {
2432 shader->vattr_offsets[i + 1] =
2433 shader->vattr_offsets[i] + c->vattr_sizes[i];
2434
2435 if (c->vattr_sizes[i])
2436 shader->vattrs_live |= (1 << i);
2437 }
2438 }
2439
2440 copy_uniform_state_to_shader(shader, c);
2441 shader->bo = vc4_bo_alloc_shader(vc4->screen, c->qpu_insts,
2442 c->qpu_inst_count * sizeof(uint64_t));
2443
2444 /* Copy the compiler UBO range state to the compiled shader, dropping
2445 * out arrays that were never referenced by an indirect load.
2446 *
2447 * (Note that QIR dead code elimination of an array access still
2448 * leaves that array alive, though)
2449 */
2450 if (c->num_ubo_ranges) {
2451 shader->num_ubo_ranges = c->num_ubo_ranges;
2452 shader->ubo_ranges = ralloc_array(shader, struct vc4_ubo_range,
2453 c->num_ubo_ranges);
2454 uint32_t j = 0;
2455 for (int i = 0; i < c->num_uniform_ranges; i++) {
2456 struct vc4_compiler_ubo_range *range =
2457 &c->ubo_ranges[i];
2458 if (!range->used)
2459 continue;
2460
2461 shader->ubo_ranges[j].dst_offset = range->dst_offset;
2462 shader->ubo_ranges[j].src_offset = range->src_offset;
2463 shader->ubo_ranges[j].size = range->size;
2464 shader->ubo_size += c->ubo_ranges[i].size;
2465 j++;
2466 }
2467 }
2468 if (shader->ubo_size) {
2469 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2470 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d UBO uniforms\n",
2471 qir_get_stage_name(c->stage),
2472 c->program_id, c->variant_id,
2473 shader->ubo_size / 4);
2474 }
2475 }
2476
2477 qir_compile_destroy(c);
2478
2479 struct vc4_key *dup_key;
2480 dup_key = ralloc_size(shader, key_size);
2481 memcpy(dup_key, key, key_size);
2482 _mesa_hash_table_insert(ht, dup_key, shader);
2483
2484 return shader;
2485 }
2486
2487 static void
2488 vc4_setup_shared_key(struct vc4_context *vc4, struct vc4_key *key,
2489 struct vc4_texture_stateobj *texstate)
2490 {
2491 for (int i = 0; i < texstate->num_textures; i++) {
2492 struct pipe_sampler_view *sampler = texstate->textures[i];
2493 struct vc4_sampler_view *vc4_sampler = vc4_sampler_view(sampler);
2494 struct pipe_sampler_state *sampler_state =
2495 texstate->samplers[i];
2496
2497 if (!sampler)
2498 continue;
2499
2500 key->tex[i].format = sampler->format;
2501 key->tex[i].swizzle[0] = sampler->swizzle_r;
2502 key->tex[i].swizzle[1] = sampler->swizzle_g;
2503 key->tex[i].swizzle[2] = sampler->swizzle_b;
2504 key->tex[i].swizzle[3] = sampler->swizzle_a;
2505
2506 if (sampler->texture->nr_samples > 1) {
2507 key->tex[i].msaa_width = sampler->texture->width0;
2508 key->tex[i].msaa_height = sampler->texture->height0;
2509 } else if (sampler){
2510 key->tex[i].compare_mode = sampler_state->compare_mode;
2511 key->tex[i].compare_func = sampler_state->compare_func;
2512 key->tex[i].wrap_s = sampler_state->wrap_s;
2513 key->tex[i].wrap_t = sampler_state->wrap_t;
2514 key->tex[i].force_first_level =
2515 vc4_sampler->force_first_level;
2516 }
2517 }
2518
2519 key->ucp_enables = vc4->rasterizer->base.clip_plane_enable;
2520 }
2521
2522 static void
2523 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
2524 {
2525 struct vc4_job *job = vc4->job;
2526 struct vc4_fs_key local_key;
2527 struct vc4_fs_key *key = &local_key;
2528
2529 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2530 VC4_DIRTY_BLEND |
2531 VC4_DIRTY_FRAMEBUFFER |
2532 VC4_DIRTY_ZSA |
2533 VC4_DIRTY_RASTERIZER |
2534 VC4_DIRTY_SAMPLE_MASK |
2535 VC4_DIRTY_FRAGTEX |
2536 VC4_DIRTY_UNCOMPILED_FS))) {
2537 return;
2538 }
2539
2540 memset(key, 0, sizeof(*key));
2541 vc4_setup_shared_key(vc4, &key->base, &vc4->fragtex);
2542 key->base.shader_state = vc4->prog.bind_fs;
2543 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
2544 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
2545 prim_mode <= PIPE_PRIM_LINE_STRIP);
2546 key->blend = vc4->blend->rt[0];
2547 if (vc4->blend->logicop_enable) {
2548 key->logicop_func = vc4->blend->logicop_func;
2549 } else {
2550 key->logicop_func = PIPE_LOGICOP_COPY;
2551 }
2552 if (job->msaa) {
2553 key->msaa = vc4->rasterizer->base.multisample;
2554 key->sample_coverage = (vc4->rasterizer->base.multisample &&
2555 vc4->sample_mask != (1 << VC4_MAX_SAMPLES) - 1);
2556 key->sample_alpha_to_coverage = vc4->blend->alpha_to_coverage;
2557 key->sample_alpha_to_one = vc4->blend->alpha_to_one;
2558 }
2559
2560 if (vc4->framebuffer.cbufs[0])
2561 key->color_format = vc4->framebuffer.cbufs[0]->format;
2562
2563 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
2564 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
2565 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
2566 key->depth_enabled = (vc4->zsa->base.depth.enabled ||
2567 key->stencil_enabled);
2568 if (vc4->zsa->base.alpha.enabled) {
2569 key->alpha_test = true;
2570 key->alpha_test_func = vc4->zsa->base.alpha.func;
2571 }
2572
2573 if (key->is_points) {
2574 key->point_sprite_mask =
2575 vc4->rasterizer->base.sprite_coord_enable;
2576 key->point_coord_upper_left =
2577 (vc4->rasterizer->base.sprite_coord_mode ==
2578 PIPE_SPRITE_COORD_UPPER_LEFT);
2579 }
2580
2581 key->light_twoside = vc4->rasterizer->base.light_twoside;
2582
2583 struct vc4_compiled_shader *old_fs = vc4->prog.fs;
2584 vc4->prog.fs = vc4_get_compiled_shader(vc4, QSTAGE_FRAG, &key->base);
2585 if (vc4->prog.fs == old_fs)
2586 return;
2587
2588 vc4->dirty |= VC4_DIRTY_COMPILED_FS;
2589
2590 if (vc4->rasterizer->base.flatshade &&
2591 old_fs && vc4->prog.fs->color_inputs != old_fs->color_inputs) {
2592 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
2593 }
2594
2595 if (old_fs && vc4->prog.fs->fs_inputs != old_fs->fs_inputs)
2596 vc4->dirty |= VC4_DIRTY_FS_INPUTS;
2597 }
2598
2599 static void
2600 vc4_update_compiled_vs(struct vc4_context *vc4, uint8_t prim_mode)
2601 {
2602 struct vc4_vs_key local_key;
2603 struct vc4_vs_key *key = &local_key;
2604
2605 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2606 VC4_DIRTY_RASTERIZER |
2607 VC4_DIRTY_VERTTEX |
2608 VC4_DIRTY_VTXSTATE |
2609 VC4_DIRTY_UNCOMPILED_VS |
2610 VC4_DIRTY_FS_INPUTS))) {
2611 return;
2612 }
2613
2614 memset(key, 0, sizeof(*key));
2615 vc4_setup_shared_key(vc4, &key->base, &vc4->verttex);
2616 key->base.shader_state = vc4->prog.bind_vs;
2617 key->fs_inputs = vc4->prog.fs->fs_inputs;
2618 key->clamp_color = vc4->rasterizer->base.clamp_vertex_color;
2619
2620 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
2621 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
2622
2623 key->per_vertex_point_size =
2624 (prim_mode == PIPE_PRIM_POINTS &&
2625 vc4->rasterizer->base.point_size_per_vertex);
2626
2627 struct vc4_compiled_shader *vs =
2628 vc4_get_compiled_shader(vc4, QSTAGE_VERT, &key->base);
2629 if (vs != vc4->prog.vs) {
2630 vc4->prog.vs = vs;
2631 vc4->dirty |= VC4_DIRTY_COMPILED_VS;
2632 }
2633
2634 key->is_coord = true;
2635 /* Coord shaders don't care what the FS inputs are. */
2636 key->fs_inputs = NULL;
2637 struct vc4_compiled_shader *cs =
2638 vc4_get_compiled_shader(vc4, QSTAGE_COORD, &key->base);
2639 if (cs != vc4->prog.cs) {
2640 vc4->prog.cs = cs;
2641 vc4->dirty |= VC4_DIRTY_COMPILED_CS;
2642 }
2643 }
2644
2645 void
2646 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
2647 {
2648 vc4_update_compiled_fs(vc4, prim_mode);
2649 vc4_update_compiled_vs(vc4, prim_mode);
2650 }
2651
2652 static uint32_t
2653 fs_cache_hash(const void *key)
2654 {
2655 return _mesa_hash_data(key, sizeof(struct vc4_fs_key));
2656 }
2657
2658 static uint32_t
2659 vs_cache_hash(const void *key)
2660 {
2661 return _mesa_hash_data(key, sizeof(struct vc4_vs_key));
2662 }
2663
2664 static bool
2665 fs_cache_compare(const void *key1, const void *key2)
2666 {
2667 return memcmp(key1, key2, sizeof(struct vc4_fs_key)) == 0;
2668 }
2669
2670 static bool
2671 vs_cache_compare(const void *key1, const void *key2)
2672 {
2673 return memcmp(key1, key2, sizeof(struct vc4_vs_key)) == 0;
2674 }
2675
2676 static uint32_t
2677 fs_inputs_hash(const void *key)
2678 {
2679 const struct vc4_fs_inputs *inputs = key;
2680
2681 return _mesa_hash_data(inputs->input_slots,
2682 sizeof(*inputs->input_slots) *
2683 inputs->num_inputs);
2684 }
2685
2686 static bool
2687 fs_inputs_compare(const void *key1, const void *key2)
2688 {
2689 const struct vc4_fs_inputs *inputs1 = key1;
2690 const struct vc4_fs_inputs *inputs2 = key2;
2691
2692 return (inputs1->num_inputs == inputs2->num_inputs &&
2693 memcmp(inputs1->input_slots,
2694 inputs2->input_slots,
2695 sizeof(*inputs1->input_slots) *
2696 inputs1->num_inputs) == 0);
2697 }
2698
2699 static void
2700 delete_from_cache_if_matches(struct hash_table *ht,
2701 struct hash_entry *entry,
2702 struct vc4_uncompiled_shader *so)
2703 {
2704 const struct vc4_key *key = entry->key;
2705
2706 if (key->shader_state == so) {
2707 struct vc4_compiled_shader *shader = entry->data;
2708 _mesa_hash_table_remove(ht, entry);
2709 vc4_bo_unreference(&shader->bo);
2710 ralloc_free(shader);
2711 }
2712 }
2713
2714 static void
2715 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
2716 {
2717 struct vc4_context *vc4 = vc4_context(pctx);
2718 struct vc4_uncompiled_shader *so = hwcso;
2719
2720 struct hash_entry *entry;
2721 hash_table_foreach(vc4->fs_cache, entry)
2722 delete_from_cache_if_matches(vc4->fs_cache, entry, so);
2723 hash_table_foreach(vc4->vs_cache, entry)
2724 delete_from_cache_if_matches(vc4->vs_cache, entry, so);
2725
2726 ralloc_free(so->base.ir.nir);
2727 free(so);
2728 }
2729
2730 static void
2731 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
2732 {
2733 struct vc4_context *vc4 = vc4_context(pctx);
2734 vc4->prog.bind_fs = hwcso;
2735 vc4->dirty |= VC4_DIRTY_UNCOMPILED_FS;
2736 }
2737
2738 static void
2739 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
2740 {
2741 struct vc4_context *vc4 = vc4_context(pctx);
2742 vc4->prog.bind_vs = hwcso;
2743 vc4->dirty |= VC4_DIRTY_UNCOMPILED_VS;
2744 }
2745
2746 void
2747 vc4_program_init(struct pipe_context *pctx)
2748 {
2749 struct vc4_context *vc4 = vc4_context(pctx);
2750
2751 pctx->create_vs_state = vc4_shader_state_create;
2752 pctx->delete_vs_state = vc4_shader_state_delete;
2753
2754 pctx->create_fs_state = vc4_shader_state_create;
2755 pctx->delete_fs_state = vc4_shader_state_delete;
2756
2757 pctx->bind_fs_state = vc4_fp_state_bind;
2758 pctx->bind_vs_state = vc4_vp_state_bind;
2759
2760 vc4->fs_cache = _mesa_hash_table_create(pctx, fs_cache_hash,
2761 fs_cache_compare);
2762 vc4->vs_cache = _mesa_hash_table_create(pctx, vs_cache_hash,
2763 vs_cache_compare);
2764 vc4->fs_inputs_set = _mesa_set_create(pctx, fs_inputs_hash,
2765 fs_inputs_compare);
2766 }
2767
2768 void
2769 vc4_program_fini(struct pipe_context *pctx)
2770 {
2771 struct vc4_context *vc4 = vc4_context(pctx);
2772
2773 struct hash_entry *entry;
2774 hash_table_foreach(vc4->fs_cache, entry) {
2775 struct vc4_compiled_shader *shader = entry->data;
2776 vc4_bo_unreference(&shader->bo);
2777 ralloc_free(shader);
2778 _mesa_hash_table_remove(vc4->fs_cache, entry);
2779 }
2780
2781 hash_table_foreach(vc4->vs_cache, entry) {
2782 struct vc4_compiled_shader *shader = entry->data;
2783 vc4_bo_unreference(&shader->bo);
2784 ralloc_free(shader);
2785 _mesa_hash_table_remove(vc4->vs_cache, entry);
2786 }
2787 }