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nir: Define system values for vc4's blending-lowering arguments.
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "util/u_format.h"
27 #include "util/u_hash.h"
28 #include "util/u_math.h"
29 #include "util/u_memory.h"
30 #include "util/ralloc.h"
31 #include "util/hash_table.h"
32 #include "tgsi/tgsi_dump.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "compiler/nir/nir.h"
35 #include "compiler/nir/nir_builder.h"
36 #include "nir/tgsi_to_nir.h"
37 #include "vc4_context.h"
38 #include "vc4_qpu.h"
39 #include "vc4_qir.h"
40 #ifdef USE_VC4_SIMULATOR
41 #include "simpenrose/simpenrose.h"
42 #endif
43
44 static struct qreg
45 ntq_get_src(struct vc4_compile *c, nir_src src, int i);
46 static void
47 ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list);
48
49 static void
50 resize_qreg_array(struct vc4_compile *c,
51 struct qreg **regs,
52 uint32_t *size,
53 uint32_t decl_size)
54 {
55 if (*size >= decl_size)
56 return;
57
58 uint32_t old_size = *size;
59 *size = MAX2(*size * 2, decl_size);
60 *regs = reralloc(c, *regs, struct qreg, *size);
61 if (!*regs) {
62 fprintf(stderr, "Malloc failure\n");
63 abort();
64 }
65
66 for (uint32_t i = old_size; i < *size; i++)
67 (*regs)[i] = c->undef;
68 }
69
70 static struct qreg
71 indirect_uniform_load(struct vc4_compile *c, nir_intrinsic_instr *intr)
72 {
73 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0);
74 uint32_t offset = nir_intrinsic_base(intr);
75 struct vc4_compiler_ubo_range *range = NULL;
76 unsigned i;
77 for (i = 0; i < c->num_uniform_ranges; i++) {
78 range = &c->ubo_ranges[i];
79 if (offset >= range->src_offset &&
80 offset < range->src_offset + range->size) {
81 break;
82 }
83 }
84 /* The driver-location-based offset always has to be within a declared
85 * uniform range.
86 */
87 assert(range);
88 if (!range->used) {
89 range->used = true;
90 range->dst_offset = c->next_ubo_dst_offset;
91 c->next_ubo_dst_offset += range->size;
92 c->num_ubo_ranges++;
93 }
94
95 offset -= range->src_offset;
96
97 /* Adjust for where we stored the TGSI register base. */
98 indirect_offset = qir_ADD(c, indirect_offset,
99 qir_uniform_ui(c, (range->dst_offset +
100 offset)));
101
102 /* Clamp to [0, array size). Note that MIN/MAX are signed. */
103 indirect_offset = qir_MAX(c, indirect_offset, qir_uniform_ui(c, 0));
104 indirect_offset = qir_MIN(c, indirect_offset,
105 qir_uniform_ui(c, (range->dst_offset +
106 range->size - 4)));
107
108 qir_TEX_DIRECT(c, indirect_offset, qir_uniform(c, QUNIFORM_UBO_ADDR, 0));
109 c->num_texture_samples++;
110 return qir_TEX_RESULT(c);
111 }
112
113 nir_ssa_def *
114 vc4_nir_get_swizzled_channel(nir_builder *b, nir_ssa_def **srcs, int swiz)
115 {
116 switch (swiz) {
117 default:
118 case PIPE_SWIZZLE_NONE:
119 fprintf(stderr, "warning: unknown swizzle\n");
120 /* FALLTHROUGH */
121 case PIPE_SWIZZLE_0:
122 return nir_imm_float(b, 0.0);
123 case PIPE_SWIZZLE_1:
124 return nir_imm_float(b, 1.0);
125 case PIPE_SWIZZLE_X:
126 case PIPE_SWIZZLE_Y:
127 case PIPE_SWIZZLE_Z:
128 case PIPE_SWIZZLE_W:
129 return srcs[swiz];
130 }
131 }
132
133 static struct qreg *
134 ntq_init_ssa_def(struct vc4_compile *c, nir_ssa_def *def)
135 {
136 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
137 def->num_components);
138 _mesa_hash_table_insert(c->def_ht, def, qregs);
139 return qregs;
140 }
141
142 static void
143 ntq_store_dest(struct vc4_compile *c, nir_dest *dest, int chan,
144 struct qreg result)
145 {
146 if (dest->is_ssa) {
147 assert(chan < dest->ssa.num_components);
148
149 struct qreg *qregs;
150 struct hash_entry *entry =
151 _mesa_hash_table_search(c->def_ht, &dest->ssa);
152
153 if (entry)
154 qregs = entry->data;
155 else
156 qregs = ntq_init_ssa_def(c, &dest->ssa);
157
158 qregs[chan] = result;
159 } else {
160 nir_register *reg = dest->reg.reg;
161 assert(dest->reg.base_offset == 0);
162 assert(reg->num_array_elems == 0);
163 struct hash_entry *entry =
164 _mesa_hash_table_search(c->def_ht, reg);
165 struct qreg *qregs = entry->data;
166
167 /* Conditionally move the result to the destination if the
168 * channel is active.
169 */
170 if (c->execute.file != QFILE_NULL) {
171 qir_SF(c, c->execute);
172 qir_MOV_cond(c, QPU_COND_ZS, qregs[chan], result);
173 } else {
174 qir_MOV_dest(c, qregs[chan], result);
175 }
176 }
177 }
178
179 static struct qreg *
180 ntq_get_dest(struct vc4_compile *c, nir_dest *dest)
181 {
182 if (dest->is_ssa) {
183 struct qreg *qregs = ntq_init_ssa_def(c, &dest->ssa);
184 for (int i = 0; i < dest->ssa.num_components; i++)
185 qregs[i] = c->undef;
186 return qregs;
187 } else {
188 nir_register *reg = dest->reg.reg;
189 assert(dest->reg.base_offset == 0);
190 assert(reg->num_array_elems == 0);
191 struct hash_entry *entry =
192 _mesa_hash_table_search(c->def_ht, reg);
193 return entry->data;
194 }
195 }
196
197 static struct qreg
198 ntq_get_src(struct vc4_compile *c, nir_src src, int i)
199 {
200 struct hash_entry *entry;
201 if (src.is_ssa) {
202 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
203 assert(i < src.ssa->num_components);
204 } else {
205 nir_register *reg = src.reg.reg;
206 entry = _mesa_hash_table_search(c->def_ht, reg);
207 assert(reg->num_array_elems == 0);
208 assert(src.reg.base_offset == 0);
209 assert(i < reg->num_components);
210 }
211
212 struct qreg *qregs = entry->data;
213 return qregs[i];
214 }
215
216 static struct qreg
217 ntq_get_alu_src(struct vc4_compile *c, nir_alu_instr *instr,
218 unsigned src)
219 {
220 assert(util_is_power_of_two(instr->dest.write_mask));
221 unsigned chan = ffs(instr->dest.write_mask) - 1;
222 struct qreg r = ntq_get_src(c, instr->src[src].src,
223 instr->src[src].swizzle[chan]);
224
225 assert(!instr->src[src].abs);
226 assert(!instr->src[src].negate);
227
228 return r;
229 };
230
231 static inline struct qreg
232 qir_SAT(struct vc4_compile *c, struct qreg val)
233 {
234 return qir_FMAX(c,
235 qir_FMIN(c, val, qir_uniform_f(c, 1.0)),
236 qir_uniform_f(c, 0.0));
237 }
238
239 static struct qreg
240 ntq_rcp(struct vc4_compile *c, struct qreg x)
241 {
242 struct qreg r = qir_RCP(c, x);
243
244 /* Apply a Newton-Raphson step to improve the accuracy. */
245 r = qir_FMUL(c, r, qir_FSUB(c,
246 qir_uniform_f(c, 2.0),
247 qir_FMUL(c, x, r)));
248
249 return r;
250 }
251
252 static struct qreg
253 ntq_rsq(struct vc4_compile *c, struct qreg x)
254 {
255 struct qreg r = qir_RSQ(c, x);
256
257 /* Apply a Newton-Raphson step to improve the accuracy. */
258 r = qir_FMUL(c, r, qir_FSUB(c,
259 qir_uniform_f(c, 1.5),
260 qir_FMUL(c,
261 qir_uniform_f(c, 0.5),
262 qir_FMUL(c, x,
263 qir_FMUL(c, r, r)))));
264
265 return r;
266 }
267
268 static struct qreg
269 ntq_umul(struct vc4_compile *c, struct qreg src0, struct qreg src1)
270 {
271 struct qreg src0_hi = qir_SHR(c, src0,
272 qir_uniform_ui(c, 24));
273 struct qreg src1_hi = qir_SHR(c, src1,
274 qir_uniform_ui(c, 24));
275
276 struct qreg hilo = qir_MUL24(c, src0_hi, src1);
277 struct qreg lohi = qir_MUL24(c, src0, src1_hi);
278 struct qreg lolo = qir_MUL24(c, src0, src1);
279
280 return qir_ADD(c, lolo, qir_SHL(c,
281 qir_ADD(c, hilo, lohi),
282 qir_uniform_ui(c, 24)));
283 }
284
285 static struct qreg
286 ntq_scale_depth_texture(struct vc4_compile *c, struct qreg src)
287 {
288 struct qreg depthf = qir_ITOF(c, qir_SHR(c, src,
289 qir_uniform_ui(c, 8)));
290 return qir_FMUL(c, depthf, qir_uniform_f(c, 1.0f/0xffffff));
291 }
292
293 /**
294 * Emits a lowered TXF_MS from an MSAA texture.
295 *
296 * The addressing math has been lowered in NIR, and now we just need to read
297 * it like a UBO.
298 */
299 static void
300 ntq_emit_txf(struct vc4_compile *c, nir_tex_instr *instr)
301 {
302 uint32_t tile_width = 32;
303 uint32_t tile_height = 32;
304 uint32_t tile_size = (tile_height * tile_width *
305 VC4_MAX_SAMPLES * sizeof(uint32_t));
306
307 unsigned unit = instr->texture_index;
308 uint32_t w = align(c->key->tex[unit].msaa_width, tile_width);
309 uint32_t w_tiles = w / tile_width;
310 uint32_t h = align(c->key->tex[unit].msaa_height, tile_height);
311 uint32_t h_tiles = h / tile_height;
312 uint32_t size = w_tiles * h_tiles * tile_size;
313
314 struct qreg addr;
315 assert(instr->num_srcs == 1);
316 assert(instr->src[0].src_type == nir_tex_src_coord);
317 addr = ntq_get_src(c, instr->src[0].src, 0);
318
319 /* Perform the clamping required by kernel validation. */
320 addr = qir_MAX(c, addr, qir_uniform_ui(c, 0));
321 addr = qir_MIN(c, addr, qir_uniform_ui(c, size - 4));
322
323 qir_TEX_DIRECT(c, addr, qir_uniform(c, QUNIFORM_TEXTURE_MSAA_ADDR, unit));
324
325 struct qreg tex = qir_TEX_RESULT(c);
326 c->num_texture_samples++;
327
328 struct qreg dest[4];
329 enum pipe_format format = c->key->tex[unit].format;
330 if (util_format_is_depth_or_stencil(format)) {
331 struct qreg scaled = ntq_scale_depth_texture(c, tex);
332 for (int i = 0; i < 4; i++)
333 dest[i] = scaled;
334 } else {
335 for (int i = 0; i < 4; i++)
336 dest[i] = qir_UNPACK_8_F(c, tex, i);
337 }
338
339 for (int i = 0; i < 4; i++)
340 ntq_store_dest(c, &instr->dest, i, dest[i]);
341 }
342
343 static void
344 ntq_emit_tex(struct vc4_compile *c, nir_tex_instr *instr)
345 {
346 struct qreg s, t, r, lod, compare;
347 bool is_txb = false, is_txl = false;
348 unsigned unit = instr->texture_index;
349
350 if (instr->op == nir_texop_txf) {
351 ntq_emit_txf(c, instr);
352 return;
353 }
354
355 for (unsigned i = 0; i < instr->num_srcs; i++) {
356 switch (instr->src[i].src_type) {
357 case nir_tex_src_coord:
358 s = ntq_get_src(c, instr->src[i].src, 0);
359 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D)
360 t = qir_uniform_f(c, 0.5);
361 else
362 t = ntq_get_src(c, instr->src[i].src, 1);
363 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
364 r = ntq_get_src(c, instr->src[i].src, 2);
365 break;
366 case nir_tex_src_bias:
367 lod = ntq_get_src(c, instr->src[i].src, 0);
368 is_txb = true;
369 break;
370 case nir_tex_src_lod:
371 lod = ntq_get_src(c, instr->src[i].src, 0);
372 is_txl = true;
373 break;
374 case nir_tex_src_comparitor:
375 compare = ntq_get_src(c, instr->src[i].src, 0);
376 break;
377 default:
378 unreachable("unknown texture source");
379 }
380 }
381
382 if (c->key->tex[unit].force_first_level) {
383 lod = qir_uniform(c, QUNIFORM_TEXTURE_FIRST_LEVEL, unit);
384 is_txl = true;
385 is_txb = false;
386 }
387
388 struct qreg texture_u[] = {
389 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit),
390 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
391 qir_uniform(c, QUNIFORM_CONSTANT, 0),
392 qir_uniform(c, QUNIFORM_CONSTANT, 0),
393 };
394 uint32_t next_texture_u = 0;
395
396 /* There is no native support for GL texture rectangle coordinates, so
397 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
398 * 1]).
399 */
400 if (instr->sampler_dim == GLSL_SAMPLER_DIM_RECT) {
401 s = qir_FMUL(c, s,
402 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_X, unit));
403 t = qir_FMUL(c, t,
404 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_Y, unit));
405 }
406
407 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE || is_txl) {
408 texture_u[2] = qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P2,
409 unit | (is_txl << 16));
410 }
411
412 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
413 qir_TEX_R(c, r, texture_u[next_texture_u++]);
414 } else if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
415 c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP ||
416 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
417 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
418 qir_TEX_R(c, qir_uniform(c, QUNIFORM_TEXTURE_BORDER_COLOR, unit),
419 texture_u[next_texture_u++]);
420 }
421
422 if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP) {
423 s = qir_SAT(c, s);
424 }
425
426 if (c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
427 t = qir_SAT(c, t);
428 }
429
430 qir_TEX_T(c, t, texture_u[next_texture_u++]);
431
432 if (is_txl || is_txb)
433 qir_TEX_B(c, lod, texture_u[next_texture_u++]);
434
435 qir_TEX_S(c, s, texture_u[next_texture_u++]);
436
437 c->num_texture_samples++;
438 struct qreg tex = qir_TEX_RESULT(c);
439
440 enum pipe_format format = c->key->tex[unit].format;
441
442 struct qreg *dest = ntq_get_dest(c, &instr->dest);
443 if (util_format_is_depth_or_stencil(format)) {
444 struct qreg normalized = ntq_scale_depth_texture(c, tex);
445 struct qreg depth_output;
446
447 struct qreg u0 = qir_uniform_f(c, 0.0f);
448 struct qreg u1 = qir_uniform_f(c, 1.0f);
449 if (c->key->tex[unit].compare_mode) {
450 switch (c->key->tex[unit].compare_func) {
451 case PIPE_FUNC_NEVER:
452 depth_output = qir_uniform_f(c, 0.0f);
453 break;
454 case PIPE_FUNC_ALWAYS:
455 depth_output = u1;
456 break;
457 case PIPE_FUNC_EQUAL:
458 qir_SF(c, qir_FSUB(c, compare, normalized));
459 depth_output = qir_SEL(c, QPU_COND_ZS, u1, u0);
460 break;
461 case PIPE_FUNC_NOTEQUAL:
462 qir_SF(c, qir_FSUB(c, compare, normalized));
463 depth_output = qir_SEL(c, QPU_COND_ZC, u1, u0);
464 break;
465 case PIPE_FUNC_GREATER:
466 qir_SF(c, qir_FSUB(c, compare, normalized));
467 depth_output = qir_SEL(c, QPU_COND_NC, u1, u0);
468 break;
469 case PIPE_FUNC_GEQUAL:
470 qir_SF(c, qir_FSUB(c, normalized, compare));
471 depth_output = qir_SEL(c, QPU_COND_NS, u1, u0);
472 break;
473 case PIPE_FUNC_LESS:
474 qir_SF(c, qir_FSUB(c, compare, normalized));
475 depth_output = qir_SEL(c, QPU_COND_NS, u1, u0);
476 break;
477 case PIPE_FUNC_LEQUAL:
478 qir_SF(c, qir_FSUB(c, normalized, compare));
479 depth_output = qir_SEL(c, QPU_COND_NC, u1, u0);
480 break;
481 }
482 } else {
483 depth_output = normalized;
484 }
485
486 for (int i = 0; i < 4; i++)
487 dest[i] = depth_output;
488 } else {
489 for (int i = 0; i < 4; i++)
490 dest[i] = qir_UNPACK_8_F(c, tex, i);
491 }
492 }
493
494 /**
495 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
496 * to zero).
497 */
498 static struct qreg
499 ntq_ffract(struct vc4_compile *c, struct qreg src)
500 {
501 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
502 struct qreg diff = qir_FSUB(c, src, trunc);
503 qir_SF(c, diff);
504 return qir_SEL(c, QPU_COND_NS,
505 qir_FADD(c, diff, qir_uniform_f(c, 1.0)), diff);
506 }
507
508 /**
509 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
510 * zero).
511 */
512 static struct qreg
513 ntq_ffloor(struct vc4_compile *c, struct qreg src)
514 {
515 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
516
517 /* This will be < 0 if we truncated and the truncation was of a value
518 * that was < 0 in the first place.
519 */
520 qir_SF(c, qir_FSUB(c, src, trunc));
521
522 return qir_SEL(c, QPU_COND_NS,
523 qir_FSUB(c, trunc, qir_uniform_f(c, 1.0)), trunc);
524 }
525
526 /**
527 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
528 * zero).
529 */
530 static struct qreg
531 ntq_fceil(struct vc4_compile *c, struct qreg src)
532 {
533 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
534
535 /* This will be < 0 if we truncated and the truncation was of a value
536 * that was > 0 in the first place.
537 */
538 qir_SF(c, qir_FSUB(c, trunc, src));
539
540 return qir_SEL(c, QPU_COND_NS,
541 qir_FADD(c, trunc, qir_uniform_f(c, 1.0)), trunc);
542 }
543
544 static struct qreg
545 ntq_fsin(struct vc4_compile *c, struct qreg src)
546 {
547 float coeff[] = {
548 -2.0 * M_PI,
549 pow(2.0 * M_PI, 3) / (3 * 2 * 1),
550 -pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
551 pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
552 -pow(2.0 * M_PI, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
553 };
554
555 struct qreg scaled_x =
556 qir_FMUL(c,
557 src,
558 qir_uniform_f(c, 1.0 / (M_PI * 2.0)));
559
560 struct qreg x = qir_FADD(c,
561 ntq_ffract(c, scaled_x),
562 qir_uniform_f(c, -0.5));
563 struct qreg x2 = qir_FMUL(c, x, x);
564 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
565 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
566 x = qir_FMUL(c, x, x2);
567 sum = qir_FADD(c,
568 sum,
569 qir_FMUL(c,
570 x,
571 qir_uniform_f(c, coeff[i])));
572 }
573 return sum;
574 }
575
576 static struct qreg
577 ntq_fcos(struct vc4_compile *c, struct qreg src)
578 {
579 float coeff[] = {
580 -1.0f,
581 pow(2.0 * M_PI, 2) / (2 * 1),
582 -pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
583 pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
584 -pow(2.0 * M_PI, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
585 pow(2.0 * M_PI, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
586 };
587
588 struct qreg scaled_x =
589 qir_FMUL(c, src,
590 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
591 struct qreg x_frac = qir_FADD(c,
592 ntq_ffract(c, scaled_x),
593 qir_uniform_f(c, -0.5));
594
595 struct qreg sum = qir_uniform_f(c, coeff[0]);
596 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
597 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
598 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
599 if (i != 1)
600 x = qir_FMUL(c, x, x2);
601
602 struct qreg mul = qir_FMUL(c,
603 x,
604 qir_uniform_f(c, coeff[i]));
605 if (i == 0)
606 sum = mul;
607 else
608 sum = qir_FADD(c, sum, mul);
609 }
610 return sum;
611 }
612
613 static struct qreg
614 ntq_fsign(struct vc4_compile *c, struct qreg src)
615 {
616 struct qreg t = qir_get_temp(c);
617
618 qir_SF(c, src);
619 qir_MOV_dest(c, t, qir_uniform_f(c, 0.0));
620 qir_MOV_dest(c, t, qir_uniform_f(c, 1.0))->cond = QPU_COND_ZC;
621 qir_MOV_dest(c, t, qir_uniform_f(c, -1.0))->cond = QPU_COND_NS;
622 return t;
623 }
624
625 static void
626 emit_vertex_input(struct vc4_compile *c, int attr)
627 {
628 enum pipe_format format = c->vs_key->attr_formats[attr];
629 uint32_t attr_size = util_format_get_blocksize(format);
630
631 c->vattr_sizes[attr] = align(attr_size, 4);
632 for (int i = 0; i < align(attr_size, 4) / 4; i++) {
633 c->inputs[attr * 4 + i] =
634 qir_MOV(c, qir_reg(QFILE_VPM, attr * 4 + i));
635 c->num_inputs++;
636 }
637 }
638
639 static void
640 emit_fragcoord_input(struct vc4_compile *c, int attr)
641 {
642 c->inputs[attr * 4 + 0] = qir_ITOF(c, qir_reg(QFILE_FRAG_X, 0));
643 c->inputs[attr * 4 + 1] = qir_ITOF(c, qir_reg(QFILE_FRAG_Y, 0));
644 c->inputs[attr * 4 + 2] =
645 qir_FMUL(c,
646 qir_ITOF(c, qir_FRAG_Z(c)),
647 qir_uniform_f(c, 1.0 / 0xffffff));
648 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
649 }
650
651 static struct qreg
652 emit_fragment_varying(struct vc4_compile *c, gl_varying_slot slot,
653 uint8_t swizzle)
654 {
655 uint32_t i = c->num_input_slots++;
656 struct qreg vary = {
657 QFILE_VARY,
658 i
659 };
660
661 if (c->num_input_slots >= c->input_slots_array_size) {
662 c->input_slots_array_size =
663 MAX2(4, c->input_slots_array_size * 2);
664
665 c->input_slots = reralloc(c, c->input_slots,
666 struct vc4_varying_slot,
667 c->input_slots_array_size);
668 }
669
670 c->input_slots[i].slot = slot;
671 c->input_slots[i].swizzle = swizzle;
672
673 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
674 }
675
676 static void
677 emit_fragment_input(struct vc4_compile *c, int attr, gl_varying_slot slot)
678 {
679 for (int i = 0; i < 4; i++) {
680 c->inputs[attr * 4 + i] =
681 emit_fragment_varying(c, slot, i);
682 c->num_inputs++;
683 }
684 }
685
686 static void
687 add_output(struct vc4_compile *c,
688 uint32_t decl_offset,
689 uint8_t slot,
690 uint8_t swizzle)
691 {
692 uint32_t old_array_size = c->outputs_array_size;
693 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
694 decl_offset + 1);
695
696 if (old_array_size != c->outputs_array_size) {
697 c->output_slots = reralloc(c,
698 c->output_slots,
699 struct vc4_varying_slot,
700 c->outputs_array_size);
701 }
702
703 c->output_slots[decl_offset].slot = slot;
704 c->output_slots[decl_offset].swizzle = swizzle;
705 }
706
707 static void
708 declare_uniform_range(struct vc4_compile *c, uint32_t start, uint32_t size)
709 {
710 unsigned array_id = c->num_uniform_ranges++;
711 if (array_id >= c->ubo_ranges_array_size) {
712 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
713 array_id + 1);
714 c->ubo_ranges = reralloc(c, c->ubo_ranges,
715 struct vc4_compiler_ubo_range,
716 c->ubo_ranges_array_size);
717 }
718
719 c->ubo_ranges[array_id].dst_offset = 0;
720 c->ubo_ranges[array_id].src_offset = start;
721 c->ubo_ranges[array_id].size = size;
722 c->ubo_ranges[array_id].used = false;
723 }
724
725 static bool
726 ntq_src_is_only_ssa_def_user(nir_src *src)
727 {
728 if (!src->is_ssa)
729 return false;
730
731 if (!list_empty(&src->ssa->if_uses))
732 return false;
733
734 return (src->ssa->uses.next == &src->use_link &&
735 src->ssa->uses.next->next == &src->ssa->uses);
736 }
737
738 /**
739 * In general, emits a nir_pack_unorm_4x8 as a series of MOVs with the pack
740 * bit set.
741 *
742 * However, as an optimization, it tries to find the instructions generating
743 * the sources to be packed and just emit the pack flag there, if possible.
744 */
745 static void
746 ntq_emit_pack_unorm_4x8(struct vc4_compile *c, nir_alu_instr *instr)
747 {
748 struct qreg result = qir_get_temp(c);
749 struct nir_alu_instr *vec4 = NULL;
750
751 /* If packing from a vec4 op (as expected), identify it so that we can
752 * peek back at what generated its sources.
753 */
754 if (instr->src[0].src.is_ssa &&
755 instr->src[0].src.ssa->parent_instr->type == nir_instr_type_alu &&
756 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr)->op ==
757 nir_op_vec4) {
758 vec4 = nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
759 }
760
761 /* If the pack is replicating the same channel 4 times, use the 8888
762 * pack flag. This is common for blending using the alpha
763 * channel.
764 */
765 if (instr->src[0].swizzle[0] == instr->src[0].swizzle[1] &&
766 instr->src[0].swizzle[0] == instr->src[0].swizzle[2] &&
767 instr->src[0].swizzle[0] == instr->src[0].swizzle[3]) {
768 struct qreg rep = ntq_get_src(c,
769 instr->src[0].src,
770 instr->src[0].swizzle[0]);
771 ntq_store_dest(c, &instr->dest.dest, 0, qir_PACK_8888_F(c, rep));
772 return;
773 }
774
775 for (int i = 0; i < 4; i++) {
776 int swiz = instr->src[0].swizzle[i];
777 struct qreg src;
778 if (vec4) {
779 src = ntq_get_src(c, vec4->src[swiz].src,
780 vec4->src[swiz].swizzle[0]);
781 } else {
782 src = ntq_get_src(c, instr->src[0].src, swiz);
783 }
784
785 if (vec4 &&
786 ntq_src_is_only_ssa_def_user(&vec4->src[swiz].src) &&
787 src.file == QFILE_TEMP &&
788 c->defs[src.index] &&
789 qir_is_mul(c->defs[src.index]) &&
790 !c->defs[src.index]->dst.pack) {
791 struct qinst *rewrite = c->defs[src.index];
792 c->defs[src.index] = NULL;
793 rewrite->dst = result;
794 rewrite->dst.pack = QPU_PACK_MUL_8A + i;
795 continue;
796 }
797
798 qir_PACK_8_F(c, result, src, i);
799 }
800
801 ntq_store_dest(c, &instr->dest.dest, 0, result);
802 }
803
804 /** Handles sign-extended bitfield extracts for 16 bits. */
805 static struct qreg
806 ntq_emit_ibfe(struct vc4_compile *c, struct qreg base, struct qreg offset,
807 struct qreg bits)
808 {
809 assert(bits.file == QFILE_UNIF &&
810 c->uniform_contents[bits.index] == QUNIFORM_CONSTANT &&
811 c->uniform_data[bits.index] == 16);
812
813 assert(offset.file == QFILE_UNIF &&
814 c->uniform_contents[offset.index] == QUNIFORM_CONSTANT);
815 int offset_bit = c->uniform_data[offset.index];
816 assert(offset_bit % 16 == 0);
817
818 return qir_UNPACK_16_I(c, base, offset_bit / 16);
819 }
820
821 /** Handles unsigned bitfield extracts for 8 bits. */
822 static struct qreg
823 ntq_emit_ubfe(struct vc4_compile *c, struct qreg base, struct qreg offset,
824 struct qreg bits)
825 {
826 assert(bits.file == QFILE_UNIF &&
827 c->uniform_contents[bits.index] == QUNIFORM_CONSTANT &&
828 c->uniform_data[bits.index] == 8);
829
830 assert(offset.file == QFILE_UNIF &&
831 c->uniform_contents[offset.index] == QUNIFORM_CONSTANT);
832 int offset_bit = c->uniform_data[offset.index];
833 assert(offset_bit % 8 == 0);
834
835 return qir_UNPACK_8_I(c, base, offset_bit / 8);
836 }
837
838 /**
839 * If compare_instr is a valid comparison instruction, emits the
840 * compare_instr's comparison and returns the sel_instr's return value based
841 * on the compare_instr's result.
842 */
843 static bool
844 ntq_emit_comparison(struct vc4_compile *c, struct qreg *dest,
845 nir_alu_instr *compare_instr,
846 nir_alu_instr *sel_instr)
847 {
848 enum qpu_cond cond;
849
850 switch (compare_instr->op) {
851 case nir_op_feq:
852 case nir_op_ieq:
853 case nir_op_seq:
854 cond = QPU_COND_ZS;
855 break;
856 case nir_op_fne:
857 case nir_op_ine:
858 case nir_op_sne:
859 cond = QPU_COND_ZC;
860 break;
861 case nir_op_fge:
862 case nir_op_ige:
863 case nir_op_uge:
864 case nir_op_sge:
865 cond = QPU_COND_NC;
866 break;
867 case nir_op_flt:
868 case nir_op_ilt:
869 case nir_op_slt:
870 cond = QPU_COND_NS;
871 break;
872 default:
873 return false;
874 }
875
876 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
877 struct qreg src1 = ntq_get_alu_src(c, compare_instr, 1);
878
879 unsigned unsized_type =
880 nir_alu_type_get_base_type(nir_op_infos[compare_instr->op].input_types[0]);
881 if (unsized_type == nir_type_float)
882 qir_SF(c, qir_FSUB(c, src0, src1));
883 else
884 qir_SF(c, qir_SUB(c, src0, src1));
885
886 switch (sel_instr->op) {
887 case nir_op_seq:
888 case nir_op_sne:
889 case nir_op_sge:
890 case nir_op_slt:
891 *dest = qir_SEL(c, cond,
892 qir_uniform_f(c, 1.0), qir_uniform_f(c, 0.0));
893 break;
894
895 case nir_op_bcsel:
896 *dest = qir_SEL(c, cond,
897 ntq_get_alu_src(c, sel_instr, 1),
898 ntq_get_alu_src(c, sel_instr, 2));
899 break;
900
901 default:
902 *dest = qir_SEL(c, cond,
903 qir_uniform_ui(c, ~0), qir_uniform_ui(c, 0));
904 break;
905 }
906
907 return true;
908 }
909
910 /**
911 * Attempts to fold a comparison generating a boolean result into the
912 * condition code for selecting between two values, instead of comparing the
913 * boolean result against 0 to generate the condition code.
914 */
915 static struct qreg ntq_emit_bcsel(struct vc4_compile *c, nir_alu_instr *instr,
916 struct qreg *src)
917 {
918 if (!instr->src[0].src.is_ssa)
919 goto out;
920 nir_alu_instr *compare =
921 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
922 if (!compare)
923 goto out;
924
925 struct qreg dest;
926 if (ntq_emit_comparison(c, &dest, compare, instr))
927 return dest;
928
929 out:
930 qir_SF(c, src[0]);
931 return qir_SEL(c, QPU_COND_NS, src[1], src[2]);
932 }
933
934 static void
935 ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr)
936 {
937 /* This should always be lowered to ALU operations for VC4. */
938 assert(!instr->dest.saturate);
939
940 /* Vectors are special in that they have non-scalarized writemasks,
941 * and just take the first swizzle channel for each argument in order
942 * into each writemask channel.
943 */
944 if (instr->op == nir_op_vec2 ||
945 instr->op == nir_op_vec3 ||
946 instr->op == nir_op_vec4) {
947 struct qreg srcs[4];
948 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
949 srcs[i] = ntq_get_src(c, instr->src[i].src,
950 instr->src[i].swizzle[0]);
951 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
952 ntq_store_dest(c, &instr->dest.dest, i, srcs[i]);
953 return;
954 }
955
956 if (instr->op == nir_op_pack_unorm_4x8) {
957 ntq_emit_pack_unorm_4x8(c, instr);
958 return;
959 }
960
961 if (instr->op == nir_op_unpack_unorm_4x8) {
962 struct qreg src = ntq_get_src(c, instr->src[0].src,
963 instr->src[0].swizzle[0]);
964 for (int i = 0; i < 4; i++) {
965 if (instr->dest.write_mask & (1 << i))
966 ntq_store_dest(c, &instr->dest.dest, i,
967 qir_UNPACK_8_F(c, src, i));
968 }
969 return;
970 }
971
972 /* General case: We can just grab the one used channel per src. */
973 struct qreg src[nir_op_infos[instr->op].num_inputs];
974 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
975 src[i] = ntq_get_alu_src(c, instr, i);
976 }
977
978 struct qreg result;
979
980 switch (instr->op) {
981 case nir_op_fmov:
982 case nir_op_imov:
983 result = qir_MOV(c, src[0]);
984 break;
985 case nir_op_fmul:
986 result = qir_FMUL(c, src[0], src[1]);
987 break;
988 case nir_op_fadd:
989 result = qir_FADD(c, src[0], src[1]);
990 break;
991 case nir_op_fsub:
992 result = qir_FSUB(c, src[0], src[1]);
993 break;
994 case nir_op_fmin:
995 result = qir_FMIN(c, src[0], src[1]);
996 break;
997 case nir_op_fmax:
998 result = qir_FMAX(c, src[0], src[1]);
999 break;
1000
1001 case nir_op_f2i:
1002 case nir_op_f2u:
1003 result = qir_FTOI(c, src[0]);
1004 break;
1005 case nir_op_i2f:
1006 case nir_op_u2f:
1007 result = qir_ITOF(c, src[0]);
1008 break;
1009 case nir_op_b2f:
1010 result = qir_AND(c, src[0], qir_uniform_f(c, 1.0));
1011 break;
1012 case nir_op_b2i:
1013 result = qir_AND(c, src[0], qir_uniform_ui(c, 1));
1014 break;
1015 case nir_op_i2b:
1016 case nir_op_f2b:
1017 qir_SF(c, src[0]);
1018 result = qir_SEL(c, QPU_COND_ZC,
1019 qir_uniform_ui(c, ~0),
1020 qir_uniform_ui(c, 0));
1021 break;
1022
1023 case nir_op_iadd:
1024 result = qir_ADD(c, src[0], src[1]);
1025 break;
1026 case nir_op_ushr:
1027 result = qir_SHR(c, src[0], src[1]);
1028 break;
1029 case nir_op_isub:
1030 result = qir_SUB(c, src[0], src[1]);
1031 break;
1032 case nir_op_ishr:
1033 result = qir_ASR(c, src[0], src[1]);
1034 break;
1035 case nir_op_ishl:
1036 result = qir_SHL(c, src[0], src[1]);
1037 break;
1038 case nir_op_imin:
1039 result = qir_MIN(c, src[0], src[1]);
1040 break;
1041 case nir_op_imax:
1042 result = qir_MAX(c, src[0], src[1]);
1043 break;
1044 case nir_op_iand:
1045 result = qir_AND(c, src[0], src[1]);
1046 break;
1047 case nir_op_ior:
1048 result = qir_OR(c, src[0], src[1]);
1049 break;
1050 case nir_op_ixor:
1051 result = qir_XOR(c, src[0], src[1]);
1052 break;
1053 case nir_op_inot:
1054 result = qir_NOT(c, src[0]);
1055 break;
1056
1057 case nir_op_imul:
1058 result = ntq_umul(c, src[0], src[1]);
1059 break;
1060
1061 case nir_op_seq:
1062 case nir_op_sne:
1063 case nir_op_sge:
1064 case nir_op_slt:
1065 case nir_op_feq:
1066 case nir_op_fne:
1067 case nir_op_fge:
1068 case nir_op_flt:
1069 case nir_op_ieq:
1070 case nir_op_ine:
1071 case nir_op_ige:
1072 case nir_op_uge:
1073 case nir_op_ilt:
1074 if (!ntq_emit_comparison(c, &result, instr, instr)) {
1075 fprintf(stderr, "Bad comparison instruction\n");
1076 }
1077 break;
1078
1079 case nir_op_bcsel:
1080 result = ntq_emit_bcsel(c, instr, src);
1081 break;
1082 case nir_op_fcsel:
1083 qir_SF(c, src[0]);
1084 result = qir_SEL(c, QPU_COND_ZC, src[1], src[2]);
1085 break;
1086
1087 case nir_op_frcp:
1088 result = ntq_rcp(c, src[0]);
1089 break;
1090 case nir_op_frsq:
1091 result = ntq_rsq(c, src[0]);
1092 break;
1093 case nir_op_fexp2:
1094 result = qir_EXP2(c, src[0]);
1095 break;
1096 case nir_op_flog2:
1097 result = qir_LOG2(c, src[0]);
1098 break;
1099
1100 case nir_op_ftrunc:
1101 result = qir_ITOF(c, qir_FTOI(c, src[0]));
1102 break;
1103 case nir_op_fceil:
1104 result = ntq_fceil(c, src[0]);
1105 break;
1106 case nir_op_ffract:
1107 result = ntq_ffract(c, src[0]);
1108 break;
1109 case nir_op_ffloor:
1110 result = ntq_ffloor(c, src[0]);
1111 break;
1112
1113 case nir_op_fsin:
1114 result = ntq_fsin(c, src[0]);
1115 break;
1116 case nir_op_fcos:
1117 result = ntq_fcos(c, src[0]);
1118 break;
1119
1120 case nir_op_fsign:
1121 result = ntq_fsign(c, src[0]);
1122 break;
1123
1124 case nir_op_fabs:
1125 result = qir_FMAXABS(c, src[0], src[0]);
1126 break;
1127 case nir_op_iabs:
1128 result = qir_MAX(c, src[0],
1129 qir_SUB(c, qir_uniform_ui(c, 0), src[0]));
1130 break;
1131
1132 case nir_op_ibitfield_extract:
1133 result = ntq_emit_ibfe(c, src[0], src[1], src[2]);
1134 break;
1135
1136 case nir_op_ubitfield_extract:
1137 result = ntq_emit_ubfe(c, src[0], src[1], src[2]);
1138 break;
1139
1140 case nir_op_usadd_4x8:
1141 result = qir_V8ADDS(c, src[0], src[1]);
1142 break;
1143
1144 case nir_op_ussub_4x8:
1145 result = qir_V8SUBS(c, src[0], src[1]);
1146 break;
1147
1148 case nir_op_umin_4x8:
1149 result = qir_V8MIN(c, src[0], src[1]);
1150 break;
1151
1152 case nir_op_umax_4x8:
1153 result = qir_V8MAX(c, src[0], src[1]);
1154 break;
1155
1156 case nir_op_umul_unorm_4x8:
1157 result = qir_V8MULD(c, src[0], src[1]);
1158 break;
1159
1160 default:
1161 fprintf(stderr, "unknown NIR ALU inst: ");
1162 nir_print_instr(&instr->instr, stderr);
1163 fprintf(stderr, "\n");
1164 abort();
1165 }
1166
1167 /* We have a scalar result, so the instruction should only have a
1168 * single channel written to.
1169 */
1170 assert(util_is_power_of_two(instr->dest.write_mask));
1171 ntq_store_dest(c, &instr->dest.dest,
1172 ffs(instr->dest.write_mask) - 1, result);
1173 }
1174
1175 static void
1176 emit_frag_end(struct vc4_compile *c)
1177 {
1178 struct qreg color;
1179 if (c->output_color_index != -1) {
1180 color = c->outputs[c->output_color_index];
1181 } else {
1182 color = qir_uniform_ui(c, 0);
1183 }
1184
1185 uint32_t discard_cond = QPU_COND_ALWAYS;
1186 if (c->discard.file != QFILE_NULL) {
1187 qir_SF(c, c->discard);
1188 discard_cond = QPU_COND_ZS;
1189 }
1190
1191 if (c->fs_key->stencil_enabled) {
1192 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1193 qir_uniform(c, QUNIFORM_STENCIL, 0));
1194 if (c->fs_key->stencil_twoside) {
1195 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1196 qir_uniform(c, QUNIFORM_STENCIL, 1));
1197 }
1198 if (c->fs_key->stencil_full_writemasks) {
1199 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1200 qir_uniform(c, QUNIFORM_STENCIL, 2));
1201 }
1202 }
1203
1204 if (c->output_sample_mask_index != -1) {
1205 qir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1206 }
1207
1208 if (c->fs_key->depth_enabled) {
1209 if (c->output_position_index != -1) {
1210 qir_FTOI_dest(c, qir_reg(QFILE_TLB_Z_WRITE, 0),
1211 qir_FMUL(c,
1212 c->outputs[c->output_position_index],
1213 qir_uniform_f(c, 0xffffff)))->cond = discard_cond;
1214 } else {
1215 qir_MOV_dest(c, qir_reg(QFILE_TLB_Z_WRITE, 0),
1216 qir_FRAG_Z(c))->cond = discard_cond;
1217 }
1218 }
1219
1220 if (!c->msaa_per_sample_output) {
1221 qir_MOV_dest(c, qir_reg(QFILE_TLB_COLOR_WRITE, 0),
1222 color)->cond = discard_cond;
1223 } else {
1224 for (int i = 0; i < VC4_MAX_SAMPLES; i++) {
1225 qir_MOV_dest(c, qir_reg(QFILE_TLB_COLOR_WRITE_MS, 0),
1226 c->sample_colors[i])->cond = discard_cond;
1227 }
1228 }
1229 }
1230
1231 static void
1232 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1233 {
1234 struct qreg packed = qir_get_temp(c);
1235
1236 for (int i = 0; i < 2; i++) {
1237 struct qreg scale =
1238 qir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1239
1240 struct qreg packed_chan = packed;
1241 packed_chan.pack = QPU_PACK_A_16A + i;
1242
1243 qir_FTOI_dest(c, packed_chan,
1244 qir_FMUL(c,
1245 qir_FMUL(c,
1246 c->outputs[c->output_position_index + i],
1247 scale),
1248 rcp_w));
1249 }
1250
1251 qir_VPM_WRITE(c, packed);
1252 }
1253
1254 static void
1255 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1256 {
1257 struct qreg zscale = qir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1258 struct qreg zoffset = qir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1259
1260 qir_VPM_WRITE(c, qir_FADD(c, qir_FMUL(c, qir_FMUL(c,
1261 c->outputs[c->output_position_index + 2],
1262 zscale),
1263 rcp_w),
1264 zoffset));
1265 }
1266
1267 static void
1268 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1269 {
1270 qir_VPM_WRITE(c, rcp_w);
1271 }
1272
1273 static void
1274 emit_point_size_write(struct vc4_compile *c)
1275 {
1276 struct qreg point_size;
1277
1278 if (c->output_point_size_index != -1)
1279 point_size = c->outputs[c->output_point_size_index];
1280 else
1281 point_size = qir_uniform_f(c, 1.0);
1282
1283 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1284 * BCM21553).
1285 */
1286 point_size = qir_FMAX(c, point_size, qir_uniform_f(c, .125));
1287
1288 qir_VPM_WRITE(c, point_size);
1289 }
1290
1291 /**
1292 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1293 *
1294 * The simulator insists that there be at least one vertex attribute, so
1295 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also
1296 * insists that all vertex attributes loaded get read by the VS/CS, so we have
1297 * to consume it here.
1298 */
1299 static void
1300 emit_stub_vpm_read(struct vc4_compile *c)
1301 {
1302 if (c->num_inputs)
1303 return;
1304
1305 c->vattr_sizes[0] = 4;
1306 (void)qir_MOV(c, qir_reg(QFILE_VPM, 0));
1307 c->num_inputs++;
1308 }
1309
1310 static void
1311 emit_vert_end(struct vc4_compile *c,
1312 struct vc4_varying_slot *fs_inputs,
1313 uint32_t num_fs_inputs)
1314 {
1315 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1316
1317 emit_stub_vpm_read(c);
1318
1319 emit_scaled_viewport_write(c, rcp_w);
1320 emit_zs_write(c, rcp_w);
1321 emit_rcp_wc_write(c, rcp_w);
1322 if (c->vs_key->per_vertex_point_size)
1323 emit_point_size_write(c);
1324
1325 for (int i = 0; i < num_fs_inputs; i++) {
1326 struct vc4_varying_slot *input = &fs_inputs[i];
1327 int j;
1328
1329 for (j = 0; j < c->num_outputs; j++) {
1330 struct vc4_varying_slot *output =
1331 &c->output_slots[j];
1332
1333 if (input->slot == output->slot &&
1334 input->swizzle == output->swizzle) {
1335 qir_VPM_WRITE(c, c->outputs[j]);
1336 break;
1337 }
1338 }
1339 /* Emit padding if we didn't find a declared VS output for
1340 * this FS input.
1341 */
1342 if (j == c->num_outputs)
1343 qir_VPM_WRITE(c, qir_uniform_f(c, 0.0));
1344 }
1345 }
1346
1347 static void
1348 emit_coord_end(struct vc4_compile *c)
1349 {
1350 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1351
1352 emit_stub_vpm_read(c);
1353
1354 for (int i = 0; i < 4; i++)
1355 qir_VPM_WRITE(c, c->outputs[c->output_position_index + i]);
1356
1357 emit_scaled_viewport_write(c, rcp_w);
1358 emit_zs_write(c, rcp_w);
1359 emit_rcp_wc_write(c, rcp_w);
1360 if (c->vs_key->per_vertex_point_size)
1361 emit_point_size_write(c);
1362 }
1363
1364 static void
1365 vc4_optimize_nir(struct nir_shader *s)
1366 {
1367 bool progress;
1368
1369 do {
1370 progress = false;
1371
1372 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1373 NIR_PASS_V(s, nir_lower_alu_to_scalar);
1374 NIR_PASS_V(s, nir_lower_phis_to_scalar);
1375
1376 NIR_PASS(progress, s, nir_copy_prop);
1377 NIR_PASS(progress, s, nir_opt_remove_phis);
1378 NIR_PASS(progress, s, nir_opt_dce);
1379 NIR_PASS(progress, s, nir_opt_dead_cf);
1380 NIR_PASS(progress, s, nir_opt_cse);
1381 NIR_PASS(progress, s, nir_opt_peephole_select);
1382 NIR_PASS(progress, s, nir_opt_algebraic);
1383 NIR_PASS(progress, s, nir_opt_constant_folding);
1384 NIR_PASS(progress, s, nir_opt_undef);
1385 } while (progress);
1386 }
1387
1388 static int
1389 driver_location_compare(const void *in_a, const void *in_b)
1390 {
1391 const nir_variable *const *a = in_a;
1392 const nir_variable *const *b = in_b;
1393
1394 return (*a)->data.driver_location - (*b)->data.driver_location;
1395 }
1396
1397 static void
1398 ntq_setup_inputs(struct vc4_compile *c)
1399 {
1400 unsigned num_entries = 0;
1401 nir_foreach_variable(var, &c->s->inputs)
1402 num_entries++;
1403
1404 nir_variable *vars[num_entries];
1405
1406 unsigned i = 0;
1407 nir_foreach_variable(var, &c->s->inputs)
1408 vars[i++] = var;
1409
1410 /* Sort the variables so that we emit the input setup in
1411 * driver_location order. This is required for VPM reads, whose data
1412 * is fetched into the VPM in driver_location (TGSI register index)
1413 * order.
1414 */
1415 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1416
1417 for (unsigned i = 0; i < num_entries; i++) {
1418 nir_variable *var = vars[i];
1419 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1420 unsigned loc = var->data.driver_location;
1421
1422 assert(array_len == 1);
1423 (void)array_len;
1424 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1425 (loc + 1) * 4);
1426
1427 if (c->stage == QSTAGE_FRAG) {
1428 if (var->data.location == VARYING_SLOT_POS) {
1429 emit_fragcoord_input(c, loc);
1430 } else if (var->data.location >= VARYING_SLOT_VAR0 &&
1431 (c->fs_key->point_sprite_mask &
1432 (1 << (var->data.location -
1433 VARYING_SLOT_VAR0)))) {
1434 c->inputs[loc * 4 + 0] = c->point_x;
1435 c->inputs[loc * 4 + 1] = c->point_y;
1436 } else {
1437 emit_fragment_input(c, loc, var->data.location);
1438 }
1439 } else {
1440 emit_vertex_input(c, loc);
1441 }
1442 }
1443 }
1444
1445 static void
1446 ntq_setup_outputs(struct vc4_compile *c)
1447 {
1448 nir_foreach_variable(var, &c->s->outputs) {
1449 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1450 unsigned loc = var->data.driver_location * 4;
1451
1452 assert(array_len == 1);
1453 (void)array_len;
1454
1455 for (int i = 0; i < 4; i++)
1456 add_output(c, loc + i, var->data.location, i);
1457
1458 if (c->stage == QSTAGE_FRAG) {
1459 switch (var->data.location) {
1460 case FRAG_RESULT_COLOR:
1461 case FRAG_RESULT_DATA0:
1462 c->output_color_index = loc;
1463 break;
1464 case FRAG_RESULT_DEPTH:
1465 c->output_position_index = loc;
1466 break;
1467 case FRAG_RESULT_SAMPLE_MASK:
1468 c->output_sample_mask_index = loc;
1469 break;
1470 }
1471 } else {
1472 switch (var->data.location) {
1473 case VARYING_SLOT_POS:
1474 c->output_position_index = loc;
1475 break;
1476 case VARYING_SLOT_PSIZ:
1477 c->output_point_size_index = loc;
1478 break;
1479 }
1480 }
1481 }
1482 }
1483
1484 static void
1485 ntq_setup_uniforms(struct vc4_compile *c)
1486 {
1487 nir_foreach_variable(var, &c->s->uniforms) {
1488 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1489 unsigned array_elem_size = 4 * sizeof(float);
1490
1491 declare_uniform_range(c, var->data.driver_location * array_elem_size,
1492 array_len * array_elem_size);
1493
1494 }
1495 }
1496
1497 /**
1498 * Sets up the mapping from nir_register to struct qreg *.
1499 *
1500 * Each nir_register gets a struct qreg per 32-bit component being stored.
1501 */
1502 static void
1503 ntq_setup_registers(struct vc4_compile *c, struct exec_list *list)
1504 {
1505 foreach_list_typed(nir_register, nir_reg, node, list) {
1506 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1507 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1508 array_len *
1509 nir_reg->num_components);
1510
1511 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1512
1513 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1514 qregs[i] = qir_get_temp(c);
1515 }
1516 }
1517
1518 static void
1519 ntq_emit_load_const(struct vc4_compile *c, nir_load_const_instr *instr)
1520 {
1521 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1522 for (int i = 0; i < instr->def.num_components; i++)
1523 qregs[i] = qir_uniform_ui(c, instr->value.u32[i]);
1524
1525 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1526 }
1527
1528 static void
1529 ntq_emit_ssa_undef(struct vc4_compile *c, nir_ssa_undef_instr *instr)
1530 {
1531 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1532
1533 /* QIR needs there to be *some* value, so pick 0 (same as for
1534 * ntq_setup_registers().
1535 */
1536 for (int i = 0; i < instr->def.num_components; i++)
1537 qregs[i] = qir_uniform_ui(c, 0);
1538 }
1539
1540 static void
1541 ntq_emit_intrinsic(struct vc4_compile *c, nir_intrinsic_instr *instr)
1542 {
1543 nir_const_value *const_offset;
1544 unsigned offset;
1545
1546 switch (instr->intrinsic) {
1547 case nir_intrinsic_load_uniform:
1548 assert(instr->num_components == 1);
1549 const_offset = nir_src_as_const_value(instr->src[0]);
1550 if (const_offset) {
1551 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1552 assert(offset % 4 == 0);
1553 /* We need dwords */
1554 offset = offset / 4;
1555 ntq_store_dest(c, &instr->dest, 0,
1556 qir_uniform(c, QUNIFORM_UNIFORM,
1557 offset));
1558 } else {
1559 ntq_store_dest(c, &instr->dest, 0,
1560 indirect_uniform_load(c, instr));
1561 }
1562 break;
1563
1564 case nir_intrinsic_load_user_clip_plane:
1565 for (int i = 0; i < instr->num_components; i++) {
1566 ntq_store_dest(c, &instr->dest, i,
1567 qir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1568 nir_intrinsic_ucp_id(instr) *
1569 4 + i));
1570 }
1571 break;
1572
1573 case nir_intrinsic_load_blend_const_color_r_float:
1574 case nir_intrinsic_load_blend_const_color_g_float:
1575 case nir_intrinsic_load_blend_const_color_b_float:
1576 case nir_intrinsic_load_blend_const_color_a_float:
1577 ntq_store_dest(c, &instr->dest, 0,
1578 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_X +
1579 (instr->intrinsic -
1580 nir_intrinsic_load_blend_const_color_r_float),
1581 0));
1582 break;
1583
1584 case nir_intrinsic_load_blend_const_color_rgba8888_unorm:
1585 ntq_store_dest(c, &instr->dest, 0,
1586 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_RGBA,
1587 0));
1588 break;
1589
1590 case nir_intrinsic_load_blend_const_color_aaaa8888_unorm:
1591 ntq_store_dest(c, &instr->dest, 0,
1592 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_AAAA,
1593 0));
1594 break;
1595
1596 case nir_intrinsic_load_alpha_ref_float:
1597 ntq_store_dest(c, &instr->dest, 0,
1598 qir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1599 break;
1600
1601 case nir_intrinsic_load_sample_mask_in:
1602 ntq_store_dest(c, &instr->dest, 0,
1603 qir_uniform(c, QUNIFORM_SAMPLE_MASK, 0));
1604 break;
1605
1606 case nir_intrinsic_load_front_face:
1607 /* The register contains 0 (front) or 1 (back), and we need to
1608 * turn it into a NIR bool where true means front.
1609 */
1610 ntq_store_dest(c, &instr->dest, 0,
1611 qir_ADD(c,
1612 qir_uniform_ui(c, -1),
1613 qir_reg(QFILE_FRAG_REV_FLAG, 0)));
1614 break;
1615
1616 case nir_intrinsic_load_input:
1617 assert(instr->num_components == 1);
1618 const_offset = nir_src_as_const_value(instr->src[0]);
1619 assert(const_offset && "vc4 doesn't support indirect inputs");
1620 if (c->stage == QSTAGE_FRAG &&
1621 nir_intrinsic_base(instr) >= VC4_NIR_TLB_COLOR_READ_INPUT) {
1622 assert(const_offset->u32[0] == 0);
1623 /* Reads of the per-sample color need to be done in
1624 * order.
1625 */
1626 int sample_index = (nir_intrinsic_base(instr) -
1627 VC4_NIR_TLB_COLOR_READ_INPUT);
1628 for (int i = 0; i <= sample_index; i++) {
1629 if (c->color_reads[i].file == QFILE_NULL) {
1630 c->color_reads[i] =
1631 qir_TLB_COLOR_READ(c);
1632 }
1633 }
1634 ntq_store_dest(c, &instr->dest, 0,
1635 c->color_reads[sample_index]);
1636 } else {
1637 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1638 int comp = nir_intrinsic_component(instr);
1639 ntq_store_dest(c, &instr->dest, 0,
1640 c->inputs[offset * 4 + comp]);
1641 }
1642 break;
1643
1644 case nir_intrinsic_store_output:
1645 const_offset = nir_src_as_const_value(instr->src[1]);
1646 assert(const_offset && "vc4 doesn't support indirect outputs");
1647 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1648
1649 /* MSAA color outputs are the only case where we have an
1650 * output that's not lowered to being a store of a single 32
1651 * bit value.
1652 */
1653 if (c->stage == QSTAGE_FRAG && instr->num_components == 4) {
1654 assert(offset == c->output_color_index);
1655 for (int i = 0; i < 4; i++) {
1656 c->sample_colors[i] =
1657 qir_MOV(c, ntq_get_src(c, instr->src[0],
1658 i));
1659 }
1660 } else {
1661 offset = offset * 4 + nir_intrinsic_component(instr);
1662 assert(instr->num_components == 1);
1663 c->outputs[offset] =
1664 qir_MOV(c, ntq_get_src(c, instr->src[0], 0));
1665 c->num_outputs = MAX2(c->num_outputs, offset + 1);
1666 }
1667 break;
1668
1669 case nir_intrinsic_discard:
1670 c->discard = qir_uniform_ui(c, ~0);
1671 break;
1672
1673 case nir_intrinsic_discard_if:
1674 if (c->discard.file == QFILE_NULL)
1675 c->discard = qir_uniform_ui(c, 0);
1676 c->discard = qir_OR(c, c->discard,
1677 ntq_get_src(c, instr->src[0], 0));
1678 break;
1679
1680 default:
1681 fprintf(stderr, "Unknown intrinsic: ");
1682 nir_print_instr(&instr->instr, stderr);
1683 fprintf(stderr, "\n");
1684 break;
1685 }
1686 }
1687
1688 /* Clears (activates) the execute flags for any channels whose jump target
1689 * matches this block.
1690 */
1691 static void
1692 ntq_activate_execute_for_block(struct vc4_compile *c)
1693 {
1694 qir_SF(c, qir_SUB(c,
1695 c->execute,
1696 qir_uniform_ui(c, c->cur_block->index)));
1697 qir_MOV_cond(c, QPU_COND_ZS, c->execute, qir_uniform_ui(c, 0));
1698 }
1699
1700 static void
1701 ntq_emit_if(struct vc4_compile *c, nir_if *if_stmt)
1702 {
1703 if (!c->vc4->screen->has_control_flow) {
1704 fprintf(stderr,
1705 "IF statement support requires updated kernel.\n");
1706 return;
1707 }
1708
1709 nir_cf_node *nir_first_else_node = nir_if_first_else_node(if_stmt);
1710 nir_cf_node *nir_last_else_node = nir_if_last_else_node(if_stmt);
1711 nir_block *nir_else_block = nir_cf_node_as_block(nir_first_else_node);
1712 bool empty_else_block =
1713 (nir_first_else_node == nir_last_else_node &&
1714 exec_list_is_empty(&nir_else_block->instr_list));
1715
1716 struct qblock *then_block = qir_new_block(c);
1717 struct qblock *after_block = qir_new_block(c);
1718 struct qblock *else_block;
1719 if (empty_else_block)
1720 else_block = after_block;
1721 else
1722 else_block = qir_new_block(c);
1723
1724 bool was_top_level = false;
1725 if (c->execute.file == QFILE_NULL) {
1726 c->execute = qir_MOV(c, qir_uniform_ui(c, 0));
1727 was_top_level = true;
1728 }
1729
1730 /* Set ZS for executing (execute == 0) and jumping (if->condition ==
1731 * 0) channels, and then update execute flags for those to point to
1732 * the ELSE block.
1733 */
1734 qir_SF(c, qir_OR(c,
1735 c->execute,
1736 ntq_get_src(c, if_stmt->condition, 0)));
1737 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
1738 qir_uniform_ui(c, else_block->index));
1739
1740 /* Jump to ELSE if nothing is active for THEN, otherwise fall
1741 * through.
1742 */
1743 qir_SF(c, c->execute);
1744 qir_BRANCH(c, QPU_COND_BRANCH_ALL_ZC);
1745 qir_link_blocks(c->cur_block, else_block);
1746 qir_link_blocks(c->cur_block, then_block);
1747
1748 /* Process the THEN block. */
1749 qir_set_emit_block(c, then_block);
1750 ntq_emit_cf_list(c, &if_stmt->then_list);
1751
1752 if (!empty_else_block) {
1753 /* Handle the end of the THEN block. First, all currently
1754 * active channels update their execute flags to point to
1755 * ENDIF
1756 */
1757 qir_SF(c, c->execute);
1758 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
1759 qir_uniform_ui(c, after_block->index));
1760
1761 /* If everything points at ENDIF, then jump there immediately. */
1762 qir_SF(c, qir_SUB(c, c->execute, qir_uniform_ui(c, after_block->index)));
1763 qir_BRANCH(c, QPU_COND_BRANCH_ALL_ZS);
1764 qir_link_blocks(c->cur_block, after_block);
1765 qir_link_blocks(c->cur_block, else_block);
1766
1767 qir_set_emit_block(c, else_block);
1768 ntq_activate_execute_for_block(c);
1769 ntq_emit_cf_list(c, &if_stmt->else_list);
1770 }
1771
1772 qir_link_blocks(c->cur_block, after_block);
1773
1774 qir_set_emit_block(c, after_block);
1775 if (was_top_level)
1776 c->execute = c->undef;
1777 else
1778 ntq_activate_execute_for_block(c);
1779
1780 }
1781
1782 static void
1783 ntq_emit_jump(struct vc4_compile *c, nir_jump_instr *jump)
1784 {
1785 switch (jump->type) {
1786 case nir_jump_break:
1787 qir_SF(c, c->execute);
1788 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
1789 qir_uniform_ui(c, c->loop_break_block->index));
1790 break;
1791
1792 case nir_jump_continue:
1793 qir_SF(c, c->execute);
1794 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
1795 qir_uniform_ui(c, c->loop_cont_block->index));
1796 break;
1797
1798 case nir_jump_return:
1799 unreachable("All returns shouold be lowered\n");
1800 }
1801 }
1802
1803 static void
1804 ntq_emit_instr(struct vc4_compile *c, nir_instr *instr)
1805 {
1806 switch (instr->type) {
1807 case nir_instr_type_alu:
1808 ntq_emit_alu(c, nir_instr_as_alu(instr));
1809 break;
1810
1811 case nir_instr_type_intrinsic:
1812 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
1813 break;
1814
1815 case nir_instr_type_load_const:
1816 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
1817 break;
1818
1819 case nir_instr_type_ssa_undef:
1820 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
1821 break;
1822
1823 case nir_instr_type_tex:
1824 ntq_emit_tex(c, nir_instr_as_tex(instr));
1825 break;
1826
1827 case nir_instr_type_jump:
1828 ntq_emit_jump(c, nir_instr_as_jump(instr));
1829 break;
1830
1831 default:
1832 fprintf(stderr, "Unknown NIR instr type: ");
1833 nir_print_instr(instr, stderr);
1834 fprintf(stderr, "\n");
1835 abort();
1836 }
1837 }
1838
1839 static void
1840 ntq_emit_block(struct vc4_compile *c, nir_block *block)
1841 {
1842 nir_foreach_instr(instr, block) {
1843 ntq_emit_instr(c, instr);
1844 }
1845 }
1846
1847 static void ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list);
1848
1849 static void
1850 ntq_emit_loop(struct vc4_compile *c, nir_loop *loop)
1851 {
1852 if (!c->vc4->screen->has_control_flow) {
1853 fprintf(stderr,
1854 "loop support requires updated kernel.\n");
1855 ntq_emit_cf_list(c, &loop->body);
1856 return;
1857 }
1858
1859 bool was_top_level = false;
1860 if (c->execute.file == QFILE_NULL) {
1861 c->execute = qir_MOV(c, qir_uniform_ui(c, 0));
1862 was_top_level = true;
1863 }
1864
1865 struct qblock *save_loop_cont_block = c->loop_cont_block;
1866 struct qblock *save_loop_break_block = c->loop_break_block;
1867
1868 c->loop_cont_block = qir_new_block(c);
1869 c->loop_break_block = qir_new_block(c);
1870
1871 qir_link_blocks(c->cur_block, c->loop_cont_block);
1872 qir_set_emit_block(c, c->loop_cont_block);
1873 ntq_activate_execute_for_block(c);
1874
1875 ntq_emit_cf_list(c, &loop->body);
1876
1877 /* If anything had explicitly continued, or is here at the end of the
1878 * loop, then we need to loop again. SF updates are masked by the
1879 * instruction's condition, so we can do the OR of the two conditions
1880 * within SF.
1881 */
1882 qir_SF(c, c->execute);
1883 struct qinst *cont_check =
1884 qir_SUB_dest(c,
1885 c->undef,
1886 c->execute,
1887 qir_uniform_ui(c, c->loop_cont_block->index));
1888 cont_check->cond = QPU_COND_ZC;
1889 cont_check->sf = true;
1890
1891 qir_BRANCH(c, QPU_COND_BRANCH_ANY_ZS);
1892 qir_link_blocks(c->cur_block, c->loop_cont_block);
1893 qir_link_blocks(c->cur_block, c->loop_break_block);
1894
1895 qir_set_emit_block(c, c->loop_break_block);
1896 if (was_top_level)
1897 c->execute = c->undef;
1898 else
1899 ntq_activate_execute_for_block(c);
1900
1901 c->loop_break_block = save_loop_break_block;
1902 c->loop_cont_block = save_loop_cont_block;
1903 }
1904
1905 static void
1906 ntq_emit_function(struct vc4_compile *c, nir_function_impl *func)
1907 {
1908 fprintf(stderr, "FUNCTIONS not handled.\n");
1909 abort();
1910 }
1911
1912 static void
1913 ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list)
1914 {
1915 foreach_list_typed(nir_cf_node, node, node, list) {
1916 switch (node->type) {
1917 case nir_cf_node_block:
1918 ntq_emit_block(c, nir_cf_node_as_block(node));
1919 break;
1920
1921 case nir_cf_node_if:
1922 ntq_emit_if(c, nir_cf_node_as_if(node));
1923 break;
1924
1925 case nir_cf_node_loop:
1926 ntq_emit_loop(c, nir_cf_node_as_loop(node));
1927 break;
1928
1929 case nir_cf_node_function:
1930 ntq_emit_function(c, nir_cf_node_as_function(node));
1931 break;
1932
1933 default:
1934 fprintf(stderr, "Unknown NIR node type\n");
1935 abort();
1936 }
1937 }
1938 }
1939
1940 static void
1941 ntq_emit_impl(struct vc4_compile *c, nir_function_impl *impl)
1942 {
1943 ntq_setup_registers(c, &impl->registers);
1944 ntq_emit_cf_list(c, &impl->body);
1945 }
1946
1947 static void
1948 nir_to_qir(struct vc4_compile *c)
1949 {
1950 ntq_setup_inputs(c);
1951 ntq_setup_outputs(c);
1952 ntq_setup_uniforms(c);
1953 ntq_setup_registers(c, &c->s->registers);
1954
1955 /* Find the main function and emit the body. */
1956 nir_foreach_function(function, c->s) {
1957 assert(strcmp(function->name, "main") == 0);
1958 assert(function->impl);
1959 ntq_emit_impl(c, function->impl);
1960 }
1961 }
1962
1963 static const nir_shader_compiler_options nir_options = {
1964 .lower_extract_byte = true,
1965 .lower_extract_word = true,
1966 .lower_ffma = true,
1967 .lower_flrp32 = true,
1968 .lower_fpow = true,
1969 .lower_fsat = true,
1970 .lower_fsqrt = true,
1971 .lower_negate = true,
1972 };
1973
1974 static int
1975 count_nir_instrs(nir_shader *nir)
1976 {
1977 int count = 0;
1978 nir_foreach_function(function, nir) {
1979 if (!function->impl)
1980 continue;
1981 nir_foreach_block(block, function->impl) {
1982 nir_foreach_instr(instr, block)
1983 count++;
1984 }
1985 }
1986 return count;
1987 }
1988
1989 static struct vc4_compile *
1990 vc4_shader_ntq(struct vc4_context *vc4, enum qstage stage,
1991 struct vc4_key *key)
1992 {
1993 struct vc4_compile *c = qir_compile_init();
1994
1995 c->vc4 = vc4;
1996 c->stage = stage;
1997 c->shader_state = &key->shader_state->base;
1998 c->program_id = key->shader_state->program_id;
1999 c->variant_id =
2000 p_atomic_inc_return(&key->shader_state->compiled_variant_count);
2001
2002 c->key = key;
2003 switch (stage) {
2004 case QSTAGE_FRAG:
2005 c->fs_key = (struct vc4_fs_key *)key;
2006 if (c->fs_key->is_points) {
2007 c->point_x = emit_fragment_varying(c, ~0, 0);
2008 c->point_y = emit_fragment_varying(c, ~0, 0);
2009 } else if (c->fs_key->is_lines) {
2010 c->line_x = emit_fragment_varying(c, ~0, 0);
2011 }
2012 break;
2013 case QSTAGE_VERT:
2014 c->vs_key = (struct vc4_vs_key *)key;
2015 break;
2016 case QSTAGE_COORD:
2017 c->vs_key = (struct vc4_vs_key *)key;
2018 break;
2019 }
2020
2021 c->s = nir_shader_clone(c, key->shader_state->base.ir.nir);
2022
2023 if (stage == QSTAGE_FRAG)
2024 NIR_PASS_V(c->s, vc4_nir_lower_blend, c);
2025
2026 struct nir_lower_tex_options tex_options = {
2027 /* We would need to implement txs, but we don't want the
2028 * int/float conversions
2029 */
2030 .lower_rect = false,
2031
2032 .lower_txp = ~0,
2033
2034 /* Apply swizzles to all samplers. */
2035 .swizzle_result = ~0,
2036 };
2037
2038 /* Lower the format swizzle and ARB_texture_swizzle-style swizzle.
2039 * The format swizzling applies before sRGB decode, and
2040 * ARB_texture_swizzle is the last thing before returning the sample.
2041 */
2042 for (int i = 0; i < ARRAY_SIZE(key->tex); i++) {
2043 enum pipe_format format = c->key->tex[i].format;
2044
2045 if (!format)
2046 continue;
2047
2048 const uint8_t *format_swizzle = vc4_get_format_swizzle(format);
2049
2050 for (int j = 0; j < 4; j++) {
2051 uint8_t arb_swiz = c->key->tex[i].swizzle[j];
2052
2053 if (arb_swiz <= 3) {
2054 tex_options.swizzles[i][j] =
2055 format_swizzle[arb_swiz];
2056 } else {
2057 tex_options.swizzles[i][j] = arb_swiz;
2058 }
2059 }
2060
2061 if (util_format_is_srgb(format))
2062 tex_options.lower_srgb |= (1 << i);
2063 }
2064
2065 NIR_PASS_V(c->s, nir_lower_tex, &tex_options);
2066
2067 if (c->fs_key && c->fs_key->light_twoside)
2068 NIR_PASS_V(c->s, nir_lower_two_sided_color);
2069
2070 if (c->vs_key && c->vs_key->clamp_color)
2071 NIR_PASS_V(c->s, nir_lower_clamp_color_outputs);
2072
2073 if (c->key->ucp_enables) {
2074 if (stage == QSTAGE_FRAG) {
2075 NIR_PASS_V(c->s, nir_lower_clip_fs, c->key->ucp_enables);
2076 } else {
2077 NIR_PASS_V(c->s, nir_lower_clip_vs, c->key->ucp_enables);
2078 NIR_PASS_V(c->s, nir_lower_io_to_scalar,
2079 nir_var_shader_out);
2080 }
2081 }
2082
2083 /* FS input scalarizing must happen after nir_lower_two_sided_color,
2084 * which only handles a vec4 at a time. Similarly, VS output
2085 * scalarizing must happen after nir_lower_clip_vs.
2086 */
2087 if (c->stage == QSTAGE_FRAG)
2088 NIR_PASS_V(c->s, nir_lower_io_to_scalar, nir_var_shader_in);
2089 else
2090 NIR_PASS_V(c->s, nir_lower_io_to_scalar, nir_var_shader_out);
2091
2092 NIR_PASS_V(c->s, vc4_nir_lower_io, c);
2093 NIR_PASS_V(c->s, vc4_nir_lower_txf_ms, c);
2094 NIR_PASS_V(c->s, nir_lower_idiv);
2095
2096 vc4_optimize_nir(c->s);
2097
2098 NIR_PASS_V(c->s, nir_convert_from_ssa, true);
2099
2100 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2101 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d NIR instructions\n",
2102 qir_get_stage_name(c->stage),
2103 c->program_id, c->variant_id,
2104 count_nir_instrs(c->s));
2105 }
2106
2107 if (vc4_debug & VC4_DEBUG_NIR) {
2108 fprintf(stderr, "%s prog %d/%d NIR:\n",
2109 qir_get_stage_name(c->stage),
2110 c->program_id, c->variant_id);
2111 nir_print_shader(c->s, stderr);
2112 }
2113
2114 nir_to_qir(c);
2115
2116 switch (stage) {
2117 case QSTAGE_FRAG:
2118 emit_frag_end(c);
2119 break;
2120 case QSTAGE_VERT:
2121 emit_vert_end(c,
2122 c->vs_key->fs_inputs->input_slots,
2123 c->vs_key->fs_inputs->num_inputs);
2124 break;
2125 case QSTAGE_COORD:
2126 emit_coord_end(c);
2127 break;
2128 }
2129
2130 if (vc4_debug & VC4_DEBUG_QIR) {
2131 fprintf(stderr, "%s prog %d/%d pre-opt QIR:\n",
2132 qir_get_stage_name(c->stage),
2133 c->program_id, c->variant_id);
2134 qir_dump(c);
2135 fprintf(stderr, "\n");
2136 }
2137
2138 qir_optimize(c);
2139 qir_lower_uniforms(c);
2140
2141 qir_schedule_instructions(c);
2142 qir_emit_uniform_stream_resets(c);
2143
2144 if (vc4_debug & VC4_DEBUG_QIR) {
2145 fprintf(stderr, "%s prog %d/%d QIR:\n",
2146 qir_get_stage_name(c->stage),
2147 c->program_id, c->variant_id);
2148 qir_dump(c);
2149 fprintf(stderr, "\n");
2150 }
2151
2152 qir_reorder_uniforms(c);
2153 vc4_generate_code(vc4, c);
2154
2155 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2156 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d instructions\n",
2157 qir_get_stage_name(c->stage),
2158 c->program_id, c->variant_id,
2159 c->qpu_inst_count);
2160 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d uniforms\n",
2161 qir_get_stage_name(c->stage),
2162 c->program_id, c->variant_id,
2163 c->num_uniforms);
2164 }
2165
2166 ralloc_free(c->s);
2167
2168 return c;
2169 }
2170
2171 static void *
2172 vc4_shader_state_create(struct pipe_context *pctx,
2173 const struct pipe_shader_state *cso)
2174 {
2175 struct vc4_context *vc4 = vc4_context(pctx);
2176 struct vc4_uncompiled_shader *so = CALLOC_STRUCT(vc4_uncompiled_shader);
2177 if (!so)
2178 return NULL;
2179
2180 so->program_id = vc4->next_uncompiled_program_id++;
2181
2182 if (vc4_debug & VC4_DEBUG_TGSI) {
2183 fprintf(stderr, "prog %d TGSI:\n",
2184 so->program_id);
2185 tgsi_dump(cso->tokens, 0);
2186 fprintf(stderr, "\n");
2187 }
2188
2189 nir_shader *s = tgsi_to_nir(cso->tokens, &nir_options);
2190
2191 NIR_PASS_V(s, nir_opt_global_to_local);
2192 NIR_PASS_V(s, nir_convert_to_ssa);
2193 NIR_PASS_V(s, nir_normalize_cubemap_coords);
2194
2195 NIR_PASS_V(s, nir_lower_load_const_to_scalar);
2196
2197 vc4_optimize_nir(s);
2198
2199 NIR_PASS_V(s, nir_remove_dead_variables, nir_var_local);
2200
2201 /* Garbage collect dead instructions */
2202 nir_sweep(s);
2203
2204 so->base.type = PIPE_SHADER_IR_NIR;
2205 so->base.ir.nir = s;
2206
2207 if (vc4_debug & VC4_DEBUG_NIR) {
2208 fprintf(stderr, "%s prog %d NIR:\n",
2209 gl_shader_stage_name(s->stage),
2210 so->program_id);
2211 nir_print_shader(s, stderr);
2212 fprintf(stderr, "\n");
2213 }
2214
2215 return so;
2216 }
2217
2218 static void
2219 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
2220 struct vc4_compile *c)
2221 {
2222 int count = c->num_uniforms;
2223 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
2224
2225 uinfo->count = count;
2226 uinfo->data = ralloc_array(shader, uint32_t, count);
2227 memcpy(uinfo->data, c->uniform_data,
2228 count * sizeof(*uinfo->data));
2229 uinfo->contents = ralloc_array(shader, enum quniform_contents, count);
2230 memcpy(uinfo->contents, c->uniform_contents,
2231 count * sizeof(*uinfo->contents));
2232 uinfo->num_texture_samples = c->num_texture_samples;
2233
2234 vc4_set_shader_uniform_dirty_flags(shader);
2235 }
2236
2237 static void
2238 vc4_setup_compiled_fs_inputs(struct vc4_context *vc4, struct vc4_compile *c,
2239 struct vc4_compiled_shader *shader)
2240 {
2241 struct vc4_fs_inputs inputs;
2242
2243 memset(&inputs, 0, sizeof(inputs));
2244 inputs.input_slots = ralloc_array(shader,
2245 struct vc4_varying_slot,
2246 c->num_input_slots);
2247
2248 bool input_live[c->num_input_slots];
2249
2250 memset(input_live, 0, sizeof(input_live));
2251 qir_for_each_inst_inorder(inst, c) {
2252 for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) {
2253 if (inst->src[i].file == QFILE_VARY)
2254 input_live[inst->src[i].index] = true;
2255 }
2256 }
2257
2258 for (int i = 0; i < c->num_input_slots; i++) {
2259 struct vc4_varying_slot *slot = &c->input_slots[i];
2260
2261 if (!input_live[i])
2262 continue;
2263
2264 /* Skip non-VS-output inputs. */
2265 if (slot->slot == (uint8_t)~0)
2266 continue;
2267
2268 if (slot->slot == VARYING_SLOT_COL0 ||
2269 slot->slot == VARYING_SLOT_COL1 ||
2270 slot->slot == VARYING_SLOT_BFC0 ||
2271 slot->slot == VARYING_SLOT_BFC1) {
2272 shader->color_inputs |= (1 << inputs.num_inputs);
2273 }
2274
2275 inputs.input_slots[inputs.num_inputs] = *slot;
2276 inputs.num_inputs++;
2277 }
2278 shader->num_inputs = inputs.num_inputs;
2279
2280 /* Add our set of inputs to the set of all inputs seen. This way, we
2281 * can have a single pointer that identifies an FS inputs set,
2282 * allowing VS to avoid recompiling when the FS is recompiled (or a
2283 * new one is bound using separate shader objects) but the inputs
2284 * don't change.
2285 */
2286 struct set_entry *entry = _mesa_set_search(vc4->fs_inputs_set, &inputs);
2287 if (entry) {
2288 shader->fs_inputs = entry->key;
2289 ralloc_free(inputs.input_slots);
2290 } else {
2291 struct vc4_fs_inputs *alloc_inputs;
2292
2293 alloc_inputs = rzalloc(vc4->fs_inputs_set, struct vc4_fs_inputs);
2294 memcpy(alloc_inputs, &inputs, sizeof(inputs));
2295 ralloc_steal(alloc_inputs, inputs.input_slots);
2296 _mesa_set_add(vc4->fs_inputs_set, alloc_inputs);
2297
2298 shader->fs_inputs = alloc_inputs;
2299 }
2300 }
2301
2302 static struct vc4_compiled_shader *
2303 vc4_get_compiled_shader(struct vc4_context *vc4, enum qstage stage,
2304 struct vc4_key *key)
2305 {
2306 struct hash_table *ht;
2307 uint32_t key_size;
2308 if (stage == QSTAGE_FRAG) {
2309 ht = vc4->fs_cache;
2310 key_size = sizeof(struct vc4_fs_key);
2311 } else {
2312 ht = vc4->vs_cache;
2313 key_size = sizeof(struct vc4_vs_key);
2314 }
2315
2316 struct vc4_compiled_shader *shader;
2317 struct hash_entry *entry = _mesa_hash_table_search(ht, key);
2318 if (entry)
2319 return entry->data;
2320
2321 struct vc4_compile *c = vc4_shader_ntq(vc4, stage, key);
2322 shader = rzalloc(NULL, struct vc4_compiled_shader);
2323
2324 shader->program_id = vc4->next_compiled_program_id++;
2325 if (stage == QSTAGE_FRAG) {
2326 vc4_setup_compiled_fs_inputs(vc4, c, shader);
2327
2328 /* Note: the temporary clone in c->s has been freed. */
2329 nir_shader *orig_shader = key->shader_state->base.ir.nir;
2330 if (orig_shader->info.outputs_written & (1 << FRAG_RESULT_DEPTH))
2331 shader->disable_early_z = true;
2332 } else {
2333 shader->num_inputs = c->num_inputs;
2334
2335 shader->vattr_offsets[0] = 0;
2336 for (int i = 0; i < 8; i++) {
2337 shader->vattr_offsets[i + 1] =
2338 shader->vattr_offsets[i] + c->vattr_sizes[i];
2339
2340 if (c->vattr_sizes[i])
2341 shader->vattrs_live |= (1 << i);
2342 }
2343 }
2344
2345 copy_uniform_state_to_shader(shader, c);
2346 shader->bo = vc4_bo_alloc_shader(vc4->screen, c->qpu_insts,
2347 c->qpu_inst_count * sizeof(uint64_t));
2348
2349 /* Copy the compiler UBO range state to the compiled shader, dropping
2350 * out arrays that were never referenced by an indirect load.
2351 *
2352 * (Note that QIR dead code elimination of an array access still
2353 * leaves that array alive, though)
2354 */
2355 if (c->num_ubo_ranges) {
2356 shader->num_ubo_ranges = c->num_ubo_ranges;
2357 shader->ubo_ranges = ralloc_array(shader, struct vc4_ubo_range,
2358 c->num_ubo_ranges);
2359 uint32_t j = 0;
2360 for (int i = 0; i < c->num_uniform_ranges; i++) {
2361 struct vc4_compiler_ubo_range *range =
2362 &c->ubo_ranges[i];
2363 if (!range->used)
2364 continue;
2365
2366 shader->ubo_ranges[j].dst_offset = range->dst_offset;
2367 shader->ubo_ranges[j].src_offset = range->src_offset;
2368 shader->ubo_ranges[j].size = range->size;
2369 shader->ubo_size += c->ubo_ranges[i].size;
2370 j++;
2371 }
2372 }
2373 if (shader->ubo_size) {
2374 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2375 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d UBO uniforms\n",
2376 qir_get_stage_name(c->stage),
2377 c->program_id, c->variant_id,
2378 shader->ubo_size / 4);
2379 }
2380 }
2381
2382 qir_compile_destroy(c);
2383
2384 struct vc4_key *dup_key;
2385 dup_key = ralloc_size(shader, key_size);
2386 memcpy(dup_key, key, key_size);
2387 _mesa_hash_table_insert(ht, dup_key, shader);
2388
2389 return shader;
2390 }
2391
2392 static void
2393 vc4_setup_shared_key(struct vc4_context *vc4, struct vc4_key *key,
2394 struct vc4_texture_stateobj *texstate)
2395 {
2396 for (int i = 0; i < texstate->num_textures; i++) {
2397 struct pipe_sampler_view *sampler = texstate->textures[i];
2398 struct vc4_sampler_view *vc4_sampler = vc4_sampler_view(sampler);
2399 struct pipe_sampler_state *sampler_state =
2400 texstate->samplers[i];
2401
2402 if (!sampler)
2403 continue;
2404
2405 key->tex[i].format = sampler->format;
2406 key->tex[i].swizzle[0] = sampler->swizzle_r;
2407 key->tex[i].swizzle[1] = sampler->swizzle_g;
2408 key->tex[i].swizzle[2] = sampler->swizzle_b;
2409 key->tex[i].swizzle[3] = sampler->swizzle_a;
2410
2411 if (sampler->texture->nr_samples > 1) {
2412 key->tex[i].msaa_width = sampler->texture->width0;
2413 key->tex[i].msaa_height = sampler->texture->height0;
2414 } else if (sampler){
2415 key->tex[i].compare_mode = sampler_state->compare_mode;
2416 key->tex[i].compare_func = sampler_state->compare_func;
2417 key->tex[i].wrap_s = sampler_state->wrap_s;
2418 key->tex[i].wrap_t = sampler_state->wrap_t;
2419 key->tex[i].force_first_level =
2420 vc4_sampler->force_first_level;
2421 }
2422 }
2423
2424 key->ucp_enables = vc4->rasterizer->base.clip_plane_enable;
2425 }
2426
2427 static void
2428 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
2429 {
2430 struct vc4_fs_key local_key;
2431 struct vc4_fs_key *key = &local_key;
2432
2433 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2434 VC4_DIRTY_BLEND |
2435 VC4_DIRTY_FRAMEBUFFER |
2436 VC4_DIRTY_ZSA |
2437 VC4_DIRTY_RASTERIZER |
2438 VC4_DIRTY_SAMPLE_MASK |
2439 VC4_DIRTY_FRAGTEX |
2440 VC4_DIRTY_UNCOMPILED_FS))) {
2441 return;
2442 }
2443
2444 memset(key, 0, sizeof(*key));
2445 vc4_setup_shared_key(vc4, &key->base, &vc4->fragtex);
2446 key->base.shader_state = vc4->prog.bind_fs;
2447 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
2448 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
2449 prim_mode <= PIPE_PRIM_LINE_STRIP);
2450 key->blend = vc4->blend->rt[0];
2451 if (vc4->blend->logicop_enable) {
2452 key->logicop_func = vc4->blend->logicop_func;
2453 } else {
2454 key->logicop_func = PIPE_LOGICOP_COPY;
2455 }
2456 if (vc4->msaa) {
2457 key->msaa = vc4->rasterizer->base.multisample;
2458 key->sample_coverage = (vc4->rasterizer->base.multisample &&
2459 vc4->sample_mask != (1 << VC4_MAX_SAMPLES) - 1);
2460 key->sample_alpha_to_coverage = vc4->blend->alpha_to_coverage;
2461 key->sample_alpha_to_one = vc4->blend->alpha_to_one;
2462 }
2463
2464 if (vc4->framebuffer.cbufs[0])
2465 key->color_format = vc4->framebuffer.cbufs[0]->format;
2466
2467 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
2468 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
2469 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
2470 key->depth_enabled = (vc4->zsa->base.depth.enabled ||
2471 key->stencil_enabled);
2472 if (vc4->zsa->base.alpha.enabled) {
2473 key->alpha_test = true;
2474 key->alpha_test_func = vc4->zsa->base.alpha.func;
2475 }
2476
2477 if (key->is_points) {
2478 key->point_sprite_mask =
2479 vc4->rasterizer->base.sprite_coord_enable;
2480 key->point_coord_upper_left =
2481 (vc4->rasterizer->base.sprite_coord_mode ==
2482 PIPE_SPRITE_COORD_UPPER_LEFT);
2483 }
2484
2485 key->light_twoside = vc4->rasterizer->base.light_twoside;
2486
2487 struct vc4_compiled_shader *old_fs = vc4->prog.fs;
2488 vc4->prog.fs = vc4_get_compiled_shader(vc4, QSTAGE_FRAG, &key->base);
2489 if (vc4->prog.fs == old_fs)
2490 return;
2491
2492 vc4->dirty |= VC4_DIRTY_COMPILED_FS;
2493
2494 if (vc4->rasterizer->base.flatshade &&
2495 old_fs && vc4->prog.fs->color_inputs != old_fs->color_inputs) {
2496 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
2497 }
2498
2499 if (old_fs && vc4->prog.fs->fs_inputs != old_fs->fs_inputs)
2500 vc4->dirty |= VC4_DIRTY_FS_INPUTS;
2501 }
2502
2503 static void
2504 vc4_update_compiled_vs(struct vc4_context *vc4, uint8_t prim_mode)
2505 {
2506 struct vc4_vs_key local_key;
2507 struct vc4_vs_key *key = &local_key;
2508
2509 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2510 VC4_DIRTY_RASTERIZER |
2511 VC4_DIRTY_VERTTEX |
2512 VC4_DIRTY_VTXSTATE |
2513 VC4_DIRTY_UNCOMPILED_VS |
2514 VC4_DIRTY_FS_INPUTS))) {
2515 return;
2516 }
2517
2518 memset(key, 0, sizeof(*key));
2519 vc4_setup_shared_key(vc4, &key->base, &vc4->verttex);
2520 key->base.shader_state = vc4->prog.bind_vs;
2521 key->fs_inputs = vc4->prog.fs->fs_inputs;
2522 key->clamp_color = vc4->rasterizer->base.clamp_vertex_color;
2523
2524 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
2525 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
2526
2527 key->per_vertex_point_size =
2528 (prim_mode == PIPE_PRIM_POINTS &&
2529 vc4->rasterizer->base.point_size_per_vertex);
2530
2531 struct vc4_compiled_shader *vs =
2532 vc4_get_compiled_shader(vc4, QSTAGE_VERT, &key->base);
2533 if (vs != vc4->prog.vs) {
2534 vc4->prog.vs = vs;
2535 vc4->dirty |= VC4_DIRTY_COMPILED_VS;
2536 }
2537
2538 key->is_coord = true;
2539 /* Coord shaders don't care what the FS inputs are. */
2540 key->fs_inputs = NULL;
2541 struct vc4_compiled_shader *cs =
2542 vc4_get_compiled_shader(vc4, QSTAGE_COORD, &key->base);
2543 if (cs != vc4->prog.cs) {
2544 vc4->prog.cs = cs;
2545 vc4->dirty |= VC4_DIRTY_COMPILED_CS;
2546 }
2547 }
2548
2549 void
2550 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
2551 {
2552 vc4_update_compiled_fs(vc4, prim_mode);
2553 vc4_update_compiled_vs(vc4, prim_mode);
2554 }
2555
2556 static uint32_t
2557 fs_cache_hash(const void *key)
2558 {
2559 return _mesa_hash_data(key, sizeof(struct vc4_fs_key));
2560 }
2561
2562 static uint32_t
2563 vs_cache_hash(const void *key)
2564 {
2565 return _mesa_hash_data(key, sizeof(struct vc4_vs_key));
2566 }
2567
2568 static bool
2569 fs_cache_compare(const void *key1, const void *key2)
2570 {
2571 return memcmp(key1, key2, sizeof(struct vc4_fs_key)) == 0;
2572 }
2573
2574 static bool
2575 vs_cache_compare(const void *key1, const void *key2)
2576 {
2577 return memcmp(key1, key2, sizeof(struct vc4_vs_key)) == 0;
2578 }
2579
2580 static uint32_t
2581 fs_inputs_hash(const void *key)
2582 {
2583 const struct vc4_fs_inputs *inputs = key;
2584
2585 return _mesa_hash_data(inputs->input_slots,
2586 sizeof(*inputs->input_slots) *
2587 inputs->num_inputs);
2588 }
2589
2590 static bool
2591 fs_inputs_compare(const void *key1, const void *key2)
2592 {
2593 const struct vc4_fs_inputs *inputs1 = key1;
2594 const struct vc4_fs_inputs *inputs2 = key2;
2595
2596 return (inputs1->num_inputs == inputs2->num_inputs &&
2597 memcmp(inputs1->input_slots,
2598 inputs2->input_slots,
2599 sizeof(*inputs1->input_slots) *
2600 inputs1->num_inputs) == 0);
2601 }
2602
2603 static void
2604 delete_from_cache_if_matches(struct hash_table *ht,
2605 struct hash_entry *entry,
2606 struct vc4_uncompiled_shader *so)
2607 {
2608 const struct vc4_key *key = entry->key;
2609
2610 if (key->shader_state == so) {
2611 struct vc4_compiled_shader *shader = entry->data;
2612 _mesa_hash_table_remove(ht, entry);
2613 vc4_bo_unreference(&shader->bo);
2614 ralloc_free(shader);
2615 }
2616 }
2617
2618 static void
2619 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
2620 {
2621 struct vc4_context *vc4 = vc4_context(pctx);
2622 struct vc4_uncompiled_shader *so = hwcso;
2623
2624 struct hash_entry *entry;
2625 hash_table_foreach(vc4->fs_cache, entry)
2626 delete_from_cache_if_matches(vc4->fs_cache, entry, so);
2627 hash_table_foreach(vc4->vs_cache, entry)
2628 delete_from_cache_if_matches(vc4->vs_cache, entry, so);
2629
2630 ralloc_free(so->base.ir.nir);
2631 free(so);
2632 }
2633
2634 static void
2635 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
2636 {
2637 struct vc4_context *vc4 = vc4_context(pctx);
2638 vc4->prog.bind_fs = hwcso;
2639 vc4->dirty |= VC4_DIRTY_UNCOMPILED_FS;
2640 }
2641
2642 static void
2643 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
2644 {
2645 struct vc4_context *vc4 = vc4_context(pctx);
2646 vc4->prog.bind_vs = hwcso;
2647 vc4->dirty |= VC4_DIRTY_UNCOMPILED_VS;
2648 }
2649
2650 void
2651 vc4_program_init(struct pipe_context *pctx)
2652 {
2653 struct vc4_context *vc4 = vc4_context(pctx);
2654
2655 pctx->create_vs_state = vc4_shader_state_create;
2656 pctx->delete_vs_state = vc4_shader_state_delete;
2657
2658 pctx->create_fs_state = vc4_shader_state_create;
2659 pctx->delete_fs_state = vc4_shader_state_delete;
2660
2661 pctx->bind_fs_state = vc4_fp_state_bind;
2662 pctx->bind_vs_state = vc4_vp_state_bind;
2663
2664 vc4->fs_cache = _mesa_hash_table_create(pctx, fs_cache_hash,
2665 fs_cache_compare);
2666 vc4->vs_cache = _mesa_hash_table_create(pctx, vs_cache_hash,
2667 vs_cache_compare);
2668 vc4->fs_inputs_set = _mesa_set_create(pctx, fs_inputs_hash,
2669 fs_inputs_compare);
2670 }
2671
2672 void
2673 vc4_program_fini(struct pipe_context *pctx)
2674 {
2675 struct vc4_context *vc4 = vc4_context(pctx);
2676
2677 struct hash_entry *entry;
2678 hash_table_foreach(vc4->fs_cache, entry) {
2679 struct vc4_compiled_shader *shader = entry->data;
2680 vc4_bo_unreference(&shader->bo);
2681 ralloc_free(shader);
2682 _mesa_hash_table_remove(vc4->fs_cache, entry);
2683 }
2684
2685 hash_table_foreach(vc4->vs_cache, entry) {
2686 struct vc4_compiled_shader *shader = entry->data;
2687 vc4_bo_unreference(&shader->bo);
2688 ralloc_free(shader);
2689 _mesa_hash_table_remove(vc4->vs_cache, entry);
2690 }
2691 }