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vc4: Enable LIT lowering in TGSI instead of our own code.
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "pipe/p_state.h"
27 #include "util/u_format.h"
28 #include "util/u_hash_table.h"
29 #include "util/u_hash.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include "util/format_srgb.h"
33 #include "util/ralloc.h"
34 #include "tgsi/tgsi_dump.h"
35 #include "tgsi/tgsi_info.h"
36 #include "tgsi/tgsi_lowering.h"
37
38 #include "vc4_context.h"
39 #include "vc4_qpu.h"
40 #include "vc4_qir.h"
41 #ifdef USE_VC4_SIMULATOR
42 #include "simpenrose/simpenrose.h"
43 #endif
44
45 struct vc4_key {
46 struct vc4_uncompiled_shader *shader_state;
47 struct {
48 enum pipe_format format;
49 unsigned compare_mode:1;
50 unsigned compare_func:3;
51 unsigned wrap_s:3;
52 unsigned wrap_t:3;
53 uint8_t swizzle[4];
54 } tex[VC4_MAX_TEXTURE_SAMPLERS];
55 };
56
57 struct vc4_fs_key {
58 struct vc4_key base;
59 enum pipe_format color_format;
60 bool depth_enabled;
61 bool stencil_enabled;
62 bool stencil_twoside;
63 bool stencil_full_writemasks;
64 bool is_points;
65 bool is_lines;
66 bool alpha_test;
67 bool point_coord_upper_left;
68 bool light_twoside;
69 uint8_t alpha_test_func;
70 uint32_t point_sprite_mask;
71
72 struct pipe_rt_blend_state blend;
73 };
74
75 struct vc4_vs_key {
76 struct vc4_key base;
77 enum pipe_format attr_formats[8];
78 bool per_vertex_point_size;
79 };
80
81 static void
82 resize_qreg_array(struct vc4_compile *c,
83 struct qreg **regs,
84 uint32_t *size,
85 uint32_t decl_size)
86 {
87 if (*size >= decl_size)
88 return;
89
90 uint32_t old_size = *size;
91 *size = MAX2(*size * 2, decl_size);
92 *regs = reralloc(c, *regs, struct qreg, *size);
93 if (!*regs) {
94 fprintf(stderr, "Malloc failure\n");
95 abort();
96 }
97
98 for (uint32_t i = old_size; i < *size; i++)
99 (*regs)[i] = c->undef;
100 }
101
102 static struct qreg
103 add_uniform(struct vc4_compile *c,
104 enum quniform_contents contents,
105 uint32_t data)
106 {
107 uint32_t uniform = c->num_uniforms++;
108 struct qreg u = { QFILE_UNIF, uniform };
109
110 if (uniform >= c->uniform_array_size) {
111 c->uniform_array_size = MAX2(MAX2(16, uniform + 1),
112 c->uniform_array_size * 2);
113
114 c->uniform_data = reralloc(c, c->uniform_data,
115 uint32_t,
116 c->uniform_array_size);
117 c->uniform_contents = reralloc(c, c->uniform_contents,
118 enum quniform_contents,
119 c->uniform_array_size);
120 }
121
122 c->uniform_contents[uniform] = contents;
123 c->uniform_data[uniform] = data;
124
125 return u;
126 }
127
128 static struct qreg
129 get_temp_for_uniform(struct vc4_compile *c, enum quniform_contents contents,
130 uint32_t data)
131 {
132 struct qreg u = add_uniform(c, contents, data);
133 struct qreg t = qir_MOV(c, u);
134 return t;
135 }
136
137 static struct qreg
138 qir_uniform_ui(struct vc4_compile *c, uint32_t ui)
139 {
140 return get_temp_for_uniform(c, QUNIFORM_CONSTANT, ui);
141 }
142
143 static struct qreg
144 qir_uniform_f(struct vc4_compile *c, float f)
145 {
146 return qir_uniform_ui(c, fui(f));
147 }
148
149 static struct qreg
150 get_src(struct vc4_compile *c, unsigned tgsi_op,
151 struct tgsi_src_register *src, int i)
152 {
153 struct qreg r = c->undef;
154
155 uint32_t s = i;
156 switch (i) {
157 case TGSI_SWIZZLE_X:
158 s = src->SwizzleX;
159 break;
160 case TGSI_SWIZZLE_Y:
161 s = src->SwizzleY;
162 break;
163 case TGSI_SWIZZLE_Z:
164 s = src->SwizzleZ;
165 break;
166 case TGSI_SWIZZLE_W:
167 s = src->SwizzleW;
168 break;
169 default:
170 abort();
171 }
172
173 assert(!src->Indirect);
174
175 switch (src->File) {
176 case TGSI_FILE_NULL:
177 return r;
178 case TGSI_FILE_TEMPORARY:
179 r = c->temps[src->Index * 4 + s];
180 break;
181 case TGSI_FILE_IMMEDIATE:
182 r = c->consts[src->Index * 4 + s];
183 break;
184 case TGSI_FILE_CONSTANT:
185 r = get_temp_for_uniform(c, QUNIFORM_UNIFORM,
186 src->Index * 4 + s);
187 break;
188 case TGSI_FILE_INPUT:
189 r = c->inputs[src->Index * 4 + s];
190 break;
191 case TGSI_FILE_SAMPLER:
192 case TGSI_FILE_SAMPLER_VIEW:
193 r = c->undef;
194 break;
195 default:
196 fprintf(stderr, "unknown src file %d\n", src->File);
197 abort();
198 }
199
200 if (src->Absolute)
201 r = qir_FMAXABS(c, r, r);
202
203 if (src->Negate) {
204 switch (tgsi_opcode_infer_src_type(tgsi_op)) {
205 case TGSI_TYPE_SIGNED:
206 case TGSI_TYPE_UNSIGNED:
207 r = qir_SUB(c, qir_uniform_ui(c, 0), r);
208 break;
209 default:
210 r = qir_FSUB(c, qir_uniform_f(c, 0.0), r);
211 break;
212 }
213 }
214
215 return r;
216 };
217
218
219 static void
220 update_dst(struct vc4_compile *c, struct tgsi_full_instruction *tgsi_inst,
221 int i, struct qreg val)
222 {
223 struct tgsi_dst_register *tgsi_dst = &tgsi_inst->Dst[0].Register;
224
225 assert(!tgsi_dst->Indirect);
226
227 switch (tgsi_dst->File) {
228 case TGSI_FILE_TEMPORARY:
229 c->temps[tgsi_dst->Index * 4 + i] = val;
230 break;
231 case TGSI_FILE_OUTPUT:
232 c->outputs[tgsi_dst->Index * 4 + i] = val;
233 c->num_outputs = MAX2(c->num_outputs,
234 tgsi_dst->Index * 4 + i + 1);
235 break;
236 default:
237 fprintf(stderr, "unknown dst file %d\n", tgsi_dst->File);
238 abort();
239 }
240 };
241
242 static struct qreg
243 get_swizzled_channel(struct vc4_compile *c,
244 struct qreg *srcs, int swiz)
245 {
246 switch (swiz) {
247 default:
248 case UTIL_FORMAT_SWIZZLE_NONE:
249 fprintf(stderr, "warning: unknown swizzle\n");
250 /* FALLTHROUGH */
251 case UTIL_FORMAT_SWIZZLE_0:
252 return qir_uniform_f(c, 0.0);
253 case UTIL_FORMAT_SWIZZLE_1:
254 return qir_uniform_f(c, 1.0);
255 case UTIL_FORMAT_SWIZZLE_X:
256 case UTIL_FORMAT_SWIZZLE_Y:
257 case UTIL_FORMAT_SWIZZLE_Z:
258 case UTIL_FORMAT_SWIZZLE_W:
259 return srcs[swiz];
260 }
261 }
262
263 static struct qreg
264 tgsi_to_qir_alu(struct vc4_compile *c,
265 struct tgsi_full_instruction *tgsi_inst,
266 enum qop op, struct qreg *src, int i)
267 {
268 struct qreg dst = qir_get_temp(c);
269 qir_emit(c, qir_inst4(op, dst,
270 src[0 * 4 + i],
271 src[1 * 4 + i],
272 src[2 * 4 + i],
273 c->undef));
274 return dst;
275 }
276
277 static struct qreg
278 tgsi_to_qir_scalar(struct vc4_compile *c,
279 struct tgsi_full_instruction *tgsi_inst,
280 enum qop op, struct qreg *src, int i)
281 {
282 struct qreg dst = qir_get_temp(c);
283 qir_emit(c, qir_inst(op, dst,
284 src[0 * 4 + 0],
285 c->undef));
286 return dst;
287 }
288
289 static struct qreg
290 qir_srgb_decode(struct vc4_compile *c, struct qreg srgb)
291 {
292 struct qreg low = qir_FMUL(c, srgb, qir_uniform_f(c, 1.0 / 12.92));
293 struct qreg high = qir_POW(c,
294 qir_FMUL(c,
295 qir_FADD(c,
296 srgb,
297 qir_uniform_f(c, 0.055)),
298 qir_uniform_f(c, 1.0 / 1.055)),
299 qir_uniform_f(c, 2.4));
300
301 qir_SF(c, qir_FSUB(c, srgb, qir_uniform_f(c, 0.04045)));
302 return qir_SEL_X_Y_NS(c, low, high);
303 }
304
305 static struct qreg
306 qir_srgb_encode(struct vc4_compile *c, struct qreg linear)
307 {
308 struct qreg low = qir_FMUL(c, linear, qir_uniform_f(c, 12.92));
309 struct qreg high = qir_FSUB(c,
310 qir_FMUL(c,
311 qir_uniform_f(c, 1.055),
312 qir_POW(c,
313 linear,
314 qir_uniform_f(c, 0.41666))),
315 qir_uniform_f(c, 0.055));
316
317 qir_SF(c, qir_FSUB(c, linear, qir_uniform_f(c, 0.0031308)));
318 return qir_SEL_X_Y_NS(c, low, high);
319 }
320
321 static struct qreg
322 tgsi_to_qir_umul(struct vc4_compile *c,
323 struct tgsi_full_instruction *tgsi_inst,
324 enum qop op, struct qreg *src, int i)
325 {
326 struct qreg src0_hi = qir_SHR(c, src[0 * 4 + i],
327 qir_uniform_ui(c, 16));
328 struct qreg src0_lo = qir_AND(c, src[0 * 4 + i],
329 qir_uniform_ui(c, 0xffff));
330 struct qreg src1_hi = qir_SHR(c, src[1 * 4 + i],
331 qir_uniform_ui(c, 16));
332 struct qreg src1_lo = qir_AND(c, src[1 * 4 + i],
333 qir_uniform_ui(c, 0xffff));
334
335 struct qreg hilo = qir_MUL24(c, src0_hi, src1_lo);
336 struct qreg lohi = qir_MUL24(c, src0_lo, src1_hi);
337 struct qreg lolo = qir_MUL24(c, src0_lo, src1_lo);
338
339 return qir_ADD(c, lolo, qir_SHL(c,
340 qir_ADD(c, hilo, lohi),
341 qir_uniform_ui(c, 16)));
342 }
343
344 static struct qreg
345 tgsi_to_qir_idiv(struct vc4_compile *c,
346 struct tgsi_full_instruction *tgsi_inst,
347 enum qop op, struct qreg *src, int i)
348 {
349 return qir_FTOI(c, qir_FMUL(c,
350 qir_ITOF(c, src[0 * 4 + i]),
351 qir_RCP(c, qir_ITOF(c, src[1 * 4 + i]))));
352 }
353
354 static struct qreg
355 tgsi_to_qir_ineg(struct vc4_compile *c,
356 struct tgsi_full_instruction *tgsi_inst,
357 enum qop op, struct qreg *src, int i)
358 {
359 return qir_SUB(c, qir_uniform_ui(c, 0), src[0 * 4 + i]);
360 }
361
362 static struct qreg
363 tgsi_to_qir_seq(struct vc4_compile *c,
364 struct tgsi_full_instruction *tgsi_inst,
365 enum qop op, struct qreg *src, int i)
366 {
367 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
368 return qir_SEL_X_0_ZS(c, qir_uniform_f(c, 1.0));
369 }
370
371 static struct qreg
372 tgsi_to_qir_sne(struct vc4_compile *c,
373 struct tgsi_full_instruction *tgsi_inst,
374 enum qop op, struct qreg *src, int i)
375 {
376 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
377 return qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0));
378 }
379
380 static struct qreg
381 tgsi_to_qir_slt(struct vc4_compile *c,
382 struct tgsi_full_instruction *tgsi_inst,
383 enum qop op, struct qreg *src, int i)
384 {
385 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
386 return qir_SEL_X_0_NS(c, qir_uniform_f(c, 1.0));
387 }
388
389 static struct qreg
390 tgsi_to_qir_sge(struct vc4_compile *c,
391 struct tgsi_full_instruction *tgsi_inst,
392 enum qop op, struct qreg *src, int i)
393 {
394 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
395 return qir_SEL_X_0_NC(c, qir_uniform_f(c, 1.0));
396 }
397
398 static struct qreg
399 tgsi_to_qir_fseq(struct vc4_compile *c,
400 struct tgsi_full_instruction *tgsi_inst,
401 enum qop op, struct qreg *src, int i)
402 {
403 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
404 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
405 }
406
407 static struct qreg
408 tgsi_to_qir_fsne(struct vc4_compile *c,
409 struct tgsi_full_instruction *tgsi_inst,
410 enum qop op, struct qreg *src, int i)
411 {
412 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
413 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
414 }
415
416 static struct qreg
417 tgsi_to_qir_fslt(struct vc4_compile *c,
418 struct tgsi_full_instruction *tgsi_inst,
419 enum qop op, struct qreg *src, int i)
420 {
421 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
422 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
423 }
424
425 static struct qreg
426 tgsi_to_qir_fsge(struct vc4_compile *c,
427 struct tgsi_full_instruction *tgsi_inst,
428 enum qop op, struct qreg *src, int i)
429 {
430 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
431 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
432 }
433
434 static struct qreg
435 tgsi_to_qir_useq(struct vc4_compile *c,
436 struct tgsi_full_instruction *tgsi_inst,
437 enum qop op, struct qreg *src, int i)
438 {
439 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
440 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
441 }
442
443 static struct qreg
444 tgsi_to_qir_usne(struct vc4_compile *c,
445 struct tgsi_full_instruction *tgsi_inst,
446 enum qop op, struct qreg *src, int i)
447 {
448 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
449 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
450 }
451
452 static struct qreg
453 tgsi_to_qir_islt(struct vc4_compile *c,
454 struct tgsi_full_instruction *tgsi_inst,
455 enum qop op, struct qreg *src, int i)
456 {
457 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
458 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
459 }
460
461 static struct qreg
462 tgsi_to_qir_isge(struct vc4_compile *c,
463 struct tgsi_full_instruction *tgsi_inst,
464 enum qop op, struct qreg *src, int i)
465 {
466 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
467 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
468 }
469
470 static struct qreg
471 tgsi_to_qir_cmp(struct vc4_compile *c,
472 struct tgsi_full_instruction *tgsi_inst,
473 enum qop op, struct qreg *src, int i)
474 {
475 qir_SF(c, src[0 * 4 + i]);
476 return qir_SEL_X_Y_NS(c,
477 src[1 * 4 + i],
478 src[2 * 4 + i]);
479 }
480
481 static struct qreg
482 tgsi_to_qir_mad(struct vc4_compile *c,
483 struct tgsi_full_instruction *tgsi_inst,
484 enum qop op, struct qreg *src, int i)
485 {
486 return qir_FADD(c,
487 qir_FMUL(c,
488 src[0 * 4 + i],
489 src[1 * 4 + i]),
490 src[2 * 4 + i]);
491 }
492
493 static struct qreg
494 tgsi_to_qir_lrp(struct vc4_compile *c,
495 struct tgsi_full_instruction *tgsi_inst,
496 enum qop op, struct qreg *src, int i)
497 {
498 struct qreg src0 = src[0 * 4 + i];
499 struct qreg src1 = src[1 * 4 + i];
500 struct qreg src2 = src[2 * 4 + i];
501
502 /* LRP is:
503 * src0 * src1 + (1 - src0) * src2.
504 * -> src0 * src1 + src2 - src0 * src2
505 * -> src2 + src0 * (src1 - src2)
506 */
507 return qir_FADD(c, src2, qir_FMUL(c, src0, qir_FSUB(c, src1, src2)));
508
509 }
510
511 static void
512 tgsi_to_qir_tex(struct vc4_compile *c,
513 struct tgsi_full_instruction *tgsi_inst,
514 enum qop op, struct qreg *src)
515 {
516 assert(!tgsi_inst->Instruction.Saturate);
517
518 struct qreg s = src[0 * 4 + 0];
519 struct qreg t = src[0 * 4 + 1];
520 struct qreg r = src[0 * 4 + 2];
521 uint32_t unit = tgsi_inst->Src[1].Register.Index;
522
523 struct qreg proj = c->undef;
524 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
525 proj = qir_RCP(c, src[0 * 4 + 3]);
526 s = qir_FMUL(c, s, proj);
527 t = qir_FMUL(c, t, proj);
528 }
529
530 struct qreg texture_u[] = {
531 add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit),
532 add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
533 add_uniform(c, QUNIFORM_CONSTANT, 0),
534 add_uniform(c, QUNIFORM_CONSTANT, 0),
535 };
536 uint32_t next_texture_u = 0;
537
538 /* There is no native support for GL texture rectangle coordinates, so
539 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
540 * 1]).
541 */
542 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_RECT ||
543 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT) {
544 s = qir_FMUL(c, s,
545 get_temp_for_uniform(c,
546 QUNIFORM_TEXRECT_SCALE_X,
547 unit));
548 t = qir_FMUL(c, t,
549 get_temp_for_uniform(c,
550 QUNIFORM_TEXRECT_SCALE_Y,
551 unit));
552 }
553
554 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
555 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE) {
556 struct qreg ma = qir_FMAXABS(c, qir_FMAXABS(c, s, t), r);
557 struct qreg rcp_ma = qir_RCP(c, ma);
558 s = qir_FMUL(c, s, rcp_ma);
559 t = qir_FMUL(c, t, rcp_ma);
560 r = qir_FMUL(c, r, rcp_ma);
561
562 texture_u[2] = add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P2, unit);
563
564 qir_TEX_R(c, r, texture_u[next_texture_u++]);
565 } else if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
566 c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP ||
567 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
568 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
569 qir_TEX_R(c, get_temp_for_uniform(c, QUNIFORM_TEXTURE_BORDER_COLOR, unit),
570 texture_u[next_texture_u++]);
571 }
572
573 if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP) {
574 s = qir_FMIN(c, qir_FMAX(c, s, qir_uniform_f(c, 0.0)),
575 qir_uniform_f(c, 1.0));
576 }
577
578 if (c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
579 t = qir_FMIN(c, qir_FMAX(c, t, qir_uniform_f(c, 0.0)),
580 qir_uniform_f(c, 1.0));
581 }
582
583 qir_TEX_T(c, t, texture_u[next_texture_u++]);
584
585 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB)
586 qir_TEX_B(c, src[0 * 4 + 3], texture_u[next_texture_u++]);
587
588 qir_TEX_S(c, s, texture_u[next_texture_u++]);
589
590 c->num_texture_samples++;
591 struct qreg r4 = qir_TEX_RESULT(c);
592
593 enum pipe_format format = c->key->tex[unit].format;
594
595 struct qreg unpacked[4];
596 if (util_format_is_depth_or_stencil(format)) {
597 struct qreg depthf = qir_ITOF(c, qir_SHR(c, r4,
598 qir_uniform_ui(c, 8)));
599 struct qreg normalized = qir_FMUL(c, depthf,
600 qir_uniform_f(c, 1.0f/0xffffff));
601
602 struct qreg depth_output;
603
604 struct qreg one = qir_uniform_f(c, 1.0f);
605 if (c->key->tex[unit].compare_mode) {
606 struct qreg compare = src[0 * 4 + 2];
607
608 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP)
609 compare = qir_FMUL(c, compare, proj);
610
611 switch (c->key->tex[unit].compare_func) {
612 case PIPE_FUNC_NEVER:
613 depth_output = qir_uniform_f(c, 0.0f);
614 break;
615 case PIPE_FUNC_ALWAYS:
616 depth_output = one;
617 break;
618 case PIPE_FUNC_EQUAL:
619 qir_SF(c, qir_FSUB(c, compare, normalized));
620 depth_output = qir_SEL_X_0_ZS(c, one);
621 break;
622 case PIPE_FUNC_NOTEQUAL:
623 qir_SF(c, qir_FSUB(c, compare, normalized));
624 depth_output = qir_SEL_X_0_ZC(c, one);
625 break;
626 case PIPE_FUNC_GREATER:
627 qir_SF(c, qir_FSUB(c, compare, normalized));
628 depth_output = qir_SEL_X_0_NC(c, one);
629 break;
630 case PIPE_FUNC_GEQUAL:
631 qir_SF(c, qir_FSUB(c, normalized, compare));
632 depth_output = qir_SEL_X_0_NS(c, one);
633 break;
634 case PIPE_FUNC_LESS:
635 qir_SF(c, qir_FSUB(c, compare, normalized));
636 depth_output = qir_SEL_X_0_NS(c, one);
637 break;
638 case PIPE_FUNC_LEQUAL:
639 qir_SF(c, qir_FSUB(c, normalized, compare));
640 depth_output = qir_SEL_X_0_NC(c, one);
641 break;
642 }
643 } else {
644 depth_output = normalized;
645 }
646
647 for (int i = 0; i < 4; i++)
648 unpacked[i] = depth_output;
649 } else {
650 for (int i = 0; i < 4; i++)
651 unpacked[i] = qir_R4_UNPACK(c, r4, i);
652 }
653
654 const uint8_t *format_swiz = vc4_get_format_swizzle(format);
655 struct qreg texture_output[4];
656 for (int i = 0; i < 4; i++) {
657 texture_output[i] = get_swizzled_channel(c, unpacked,
658 format_swiz[i]);
659 }
660
661 if (util_format_is_srgb(format)) {
662 for (int i = 0; i < 3; i++)
663 texture_output[i] = qir_srgb_decode(c,
664 texture_output[i]);
665 }
666
667 for (int i = 0; i < 4; i++) {
668 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
669 continue;
670
671 update_dst(c, tgsi_inst, i,
672 get_swizzled_channel(c, texture_output,
673 c->key->tex[unit].swizzle[i]));
674 }
675 }
676
677 static struct qreg
678 tgsi_to_qir_trunc(struct vc4_compile *c,
679 struct tgsi_full_instruction *tgsi_inst,
680 enum qop op, struct qreg *src, int i)
681 {
682 return qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
683 }
684
685 /**
686 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
687 * to zero).
688 */
689 static struct qreg
690 tgsi_to_qir_frc(struct vc4_compile *c,
691 struct tgsi_full_instruction *tgsi_inst,
692 enum qop op, struct qreg *src, int i)
693 {
694 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
695 struct qreg diff = qir_FSUB(c, src[0 * 4 + i], trunc);
696 qir_SF(c, diff);
697 return qir_SEL_X_Y_NS(c,
698 qir_FADD(c, diff, qir_uniform_f(c, 1.0)),
699 diff);
700 }
701
702 /**
703 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
704 * zero).
705 */
706 static struct qreg
707 tgsi_to_qir_flr(struct vc4_compile *c,
708 struct tgsi_full_instruction *tgsi_inst,
709 enum qop op, struct qreg *src, int i)
710 {
711 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
712
713 /* This will be < 0 if we truncated and the truncation was of a value
714 * that was < 0 in the first place.
715 */
716 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], trunc));
717
718 return qir_SEL_X_Y_NS(c,
719 qir_FSUB(c, trunc, qir_uniform_f(c, 1.0)),
720 trunc);
721 }
722
723 static struct qreg
724 tgsi_to_qir_abs(struct vc4_compile *c,
725 struct tgsi_full_instruction *tgsi_inst,
726 enum qop op, struct qreg *src, int i)
727 {
728 struct qreg arg = src[0 * 4 + i];
729 return qir_FMAXABS(c, arg, arg);
730 }
731
732 /* Note that this instruction replicates its result from the x channel */
733 static struct qreg
734 tgsi_to_qir_sin(struct vc4_compile *c,
735 struct tgsi_full_instruction *tgsi_inst,
736 enum qop op, struct qreg *src, int i)
737 {
738 float coeff[] = {
739 2.0 * M_PI,
740 -pow(2.0 * M_PI, 3) / (3 * 2 * 1),
741 pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
742 -pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
743 };
744
745 struct qreg scaled_x =
746 qir_FMUL(c,
747 src[0 * 4 + 0],
748 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
749
750
751 struct qreg x = tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0);
752 struct qreg x2 = qir_FMUL(c, x, x);
753 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
754 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
755 x = qir_FMUL(c, x, x2);
756 sum = qir_FADD(c,
757 sum,
758 qir_FMUL(c,
759 x,
760 qir_uniform_f(c, coeff[i])));
761 }
762 return sum;
763 }
764
765 /* Note that this instruction replicates its result from the x channel */
766 static struct qreg
767 tgsi_to_qir_cos(struct vc4_compile *c,
768 struct tgsi_full_instruction *tgsi_inst,
769 enum qop op, struct qreg *src, int i)
770 {
771 float coeff[] = {
772 1.0f,
773 -pow(2.0 * M_PI, 2) / (2 * 1),
774 pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
775 -pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
776 };
777
778 struct qreg scaled_x =
779 qir_FMUL(c, src[0 * 4 + 0],
780 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
781 struct qreg x_frac = tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0);
782
783 struct qreg sum = qir_uniform_f(c, coeff[0]);
784 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
785 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
786 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
787 if (i != 1)
788 x = qir_FMUL(c, x, x2);
789
790 struct qreg mul = qir_FMUL(c,
791 x,
792 qir_uniform_f(c, coeff[i]));
793 if (i == 0)
794 sum = mul;
795 else
796 sum = qir_FADD(c, sum, mul);
797 }
798 return sum;
799 }
800
801 static struct qreg
802 tgsi_to_qir_clamp(struct vc4_compile *c,
803 struct tgsi_full_instruction *tgsi_inst,
804 enum qop op, struct qreg *src, int i)
805 {
806 return qir_FMAX(c, qir_FMIN(c,
807 src[0 * 4 + i],
808 src[2 * 4 + i]),
809 src[1 * 4 + i]);
810 }
811
812 static void
813 emit_vertex_input(struct vc4_compile *c, int attr)
814 {
815 enum pipe_format format = c->vs_key->attr_formats[attr];
816 struct qreg vpm_reads[4];
817
818 /* Right now, we're setting the VPM offsets to be 16 bytes wide every
819 * time, so we always read 4 32-bit VPM entries.
820 */
821 for (int i = 0; i < 4; i++) {
822 vpm_reads[i] = qir_get_temp(c);
823 qir_emit(c, qir_inst(QOP_VPM_READ,
824 vpm_reads[i],
825 c->undef,
826 c->undef));
827 c->num_inputs++;
828 }
829
830 bool format_warned = false;
831 const struct util_format_description *desc =
832 util_format_description(format);
833
834 for (int i = 0; i < 4; i++) {
835 uint8_t swiz = desc->swizzle[i];
836 struct qreg result;
837
838 if (swiz > UTIL_FORMAT_SWIZZLE_W)
839 result = get_swizzled_channel(c, vpm_reads, swiz);
840 else if (desc->channel[swiz].size == 32 &&
841 desc->channel[swiz].type == UTIL_FORMAT_TYPE_FLOAT) {
842 result = get_swizzled_channel(c, vpm_reads, swiz);
843 } else if (desc->channel[swiz].size == 8 &&
844 (desc->channel[swiz].type == UTIL_FORMAT_TYPE_UNSIGNED ||
845 desc->channel[swiz].type == UTIL_FORMAT_TYPE_SIGNED) &&
846 desc->channel[swiz].normalized) {
847 struct qreg vpm = vpm_reads[0];
848 if (desc->channel[swiz].type == UTIL_FORMAT_TYPE_SIGNED)
849 vpm = qir_XOR(c, vpm, qir_uniform_ui(c, 0x80808080));
850 result = qir_UNPACK_8(c, vpm, swiz);
851 } else {
852 if (!format_warned) {
853 fprintf(stderr,
854 "vtx element %d unsupported type: %s\n",
855 attr, util_format_name(format));
856 format_warned = true;
857 }
858 result = qir_uniform_f(c, 0.0);
859 }
860
861 if (desc->channel[swiz].normalized &&
862 desc->channel[swiz].type == UTIL_FORMAT_TYPE_SIGNED) {
863 result = qir_FSUB(c,
864 qir_FMUL(c,
865 result,
866 qir_uniform_f(c, 2.0)),
867 qir_uniform_f(c, 1.0));
868 }
869
870 c->inputs[attr * 4 + i] = result;
871 }
872 }
873
874 static void
875 tgsi_to_qir_kill_if(struct vc4_compile *c, struct qreg *src, int i)
876 {
877 if (c->discard.file == QFILE_NULL)
878 c->discard = qir_uniform_f(c, 0.0);
879 qir_SF(c, src[0 * 4 + i]);
880 c->discard = qir_SEL_X_Y_NS(c, qir_uniform_f(c, 1.0),
881 c->discard);
882 }
883
884 static void
885 emit_fragcoord_input(struct vc4_compile *c, int attr)
886 {
887 c->inputs[attr * 4 + 0] = qir_FRAG_X(c);
888 c->inputs[attr * 4 + 1] = qir_FRAG_Y(c);
889 c->inputs[attr * 4 + 2] =
890 qir_FMUL(c,
891 qir_ITOF(c, qir_FRAG_Z(c)),
892 qir_uniform_f(c, 1.0 / 0xffffff));
893 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
894 }
895
896 static void
897 emit_point_coord_input(struct vc4_compile *c, int attr)
898 {
899 if (c->point_x.file == QFILE_NULL) {
900 c->point_x = qir_uniform_f(c, 0.0);
901 c->point_y = qir_uniform_f(c, 0.0);
902 }
903
904 c->inputs[attr * 4 + 0] = c->point_x;
905 if (c->fs_key->point_coord_upper_left) {
906 c->inputs[attr * 4 + 1] = qir_FSUB(c,
907 qir_uniform_f(c, 1.0),
908 c->point_y);
909 } else {
910 c->inputs[attr * 4 + 1] = c->point_y;
911 }
912 c->inputs[attr * 4 + 2] = qir_uniform_f(c, 0.0);
913 c->inputs[attr * 4 + 3] = qir_uniform_f(c, 1.0);
914 }
915
916 static struct qreg
917 emit_fragment_varying(struct vc4_compile *c, int index)
918 {
919 struct qreg vary = {
920 QFILE_VARY,
921 index
922 };
923
924 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
925 }
926
927 static void
928 emit_fragment_input(struct vc4_compile *c, int attr,
929 struct tgsi_full_declaration *decl)
930 {
931 for (int i = 0; i < 4; i++) {
932 c->inputs[attr * 4 + i] =
933 emit_fragment_varying(c, attr * 4 + i);
934 c->num_inputs++;
935
936 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR ||
937 decl->Semantic.Name == TGSI_SEMANTIC_BCOLOR)
938 c->color_inputs |= 1 << i;
939 }
940 }
941
942 static void
943 emit_face_input(struct vc4_compile *c, int attr)
944 {
945 c->inputs[attr * 4 + 0] = qir_FSUB(c,
946 qir_uniform_f(c, 1.0),
947 qir_FMUL(c,
948 qir_ITOF(c, qir_FRAG_REV_FLAG(c)),
949 qir_uniform_f(c, 2.0)));
950 c->inputs[attr * 4 + 1] = qir_uniform_f(c, 0.0);
951 c->inputs[attr * 4 + 2] = qir_uniform_f(c, 0.0);
952 c->inputs[attr * 4 + 3] = qir_uniform_f(c, 1.0);
953 }
954
955 static void
956 emit_tgsi_declaration(struct vc4_compile *c,
957 struct tgsi_full_declaration *decl)
958 {
959 switch (decl->Declaration.File) {
960 case TGSI_FILE_TEMPORARY:
961 resize_qreg_array(c, &c->temps, &c->temps_array_size,
962 (decl->Range.Last + 1) * 4);
963 break;
964
965 case TGSI_FILE_INPUT:
966 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
967 (decl->Range.Last + 1) * 4);
968
969 for (int i = decl->Range.First;
970 i <= decl->Range.Last;
971 i++) {
972 if (c->stage == QSTAGE_FRAG) {
973 if (decl->Semantic.Name ==
974 TGSI_SEMANTIC_POSITION) {
975 emit_fragcoord_input(c, i);
976 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
977 emit_face_input(c, i);
978 } else if (decl->Semantic.Name == TGSI_SEMANTIC_GENERIC &&
979 (c->fs_key->point_sprite_mask &
980 (1 << decl->Semantic.Index))) {
981 emit_point_coord_input(c, i);
982 } else {
983 emit_fragment_input(c, i, decl);
984 }
985 } else {
986 emit_vertex_input(c, i);
987 }
988 }
989 break;
990
991 case TGSI_FILE_OUTPUT:
992 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
993 (decl->Range.Last + 1) * 4);
994
995 switch (decl->Semantic.Name) {
996 case TGSI_SEMANTIC_POSITION:
997 c->output_position_index = decl->Range.First * 4;
998 break;
999 case TGSI_SEMANTIC_COLOR:
1000 c->output_color_index = decl->Range.First * 4;
1001 break;
1002 case TGSI_SEMANTIC_PSIZE:
1003 c->output_point_size_index = decl->Range.First * 4;
1004 break;
1005 }
1006
1007 break;
1008 }
1009 }
1010
1011 static void
1012 emit_tgsi_instruction(struct vc4_compile *c,
1013 struct tgsi_full_instruction *tgsi_inst)
1014 {
1015 struct {
1016 enum qop op;
1017 struct qreg (*func)(struct vc4_compile *c,
1018 struct tgsi_full_instruction *tgsi_inst,
1019 enum qop op,
1020 struct qreg *src, int i);
1021 } op_trans[] = {
1022 [TGSI_OPCODE_MOV] = { QOP_MOV, tgsi_to_qir_alu },
1023 [TGSI_OPCODE_ABS] = { 0, tgsi_to_qir_abs },
1024 [TGSI_OPCODE_MUL] = { QOP_FMUL, tgsi_to_qir_alu },
1025 [TGSI_OPCODE_ADD] = { QOP_FADD, tgsi_to_qir_alu },
1026 [TGSI_OPCODE_SUB] = { QOP_FSUB, tgsi_to_qir_alu },
1027 [TGSI_OPCODE_MIN] = { QOP_FMIN, tgsi_to_qir_alu },
1028 [TGSI_OPCODE_MAX] = { QOP_FMAX, tgsi_to_qir_alu },
1029 [TGSI_OPCODE_F2I] = { QOP_FTOI, tgsi_to_qir_alu },
1030 [TGSI_OPCODE_I2F] = { QOP_ITOF, tgsi_to_qir_alu },
1031 [TGSI_OPCODE_UADD] = { QOP_ADD, tgsi_to_qir_alu },
1032 [TGSI_OPCODE_USHR] = { QOP_SHR, tgsi_to_qir_alu },
1033 [TGSI_OPCODE_ISHR] = { QOP_ASR, tgsi_to_qir_alu },
1034 [TGSI_OPCODE_SHL] = { QOP_SHL, tgsi_to_qir_alu },
1035 [TGSI_OPCODE_IMIN] = { QOP_MIN, tgsi_to_qir_alu },
1036 [TGSI_OPCODE_IMAX] = { QOP_MAX, tgsi_to_qir_alu },
1037 [TGSI_OPCODE_AND] = { QOP_AND, tgsi_to_qir_alu },
1038 [TGSI_OPCODE_OR] = { QOP_OR, tgsi_to_qir_alu },
1039 [TGSI_OPCODE_XOR] = { QOP_XOR, tgsi_to_qir_alu },
1040 [TGSI_OPCODE_NOT] = { QOP_NOT, tgsi_to_qir_alu },
1041
1042 [TGSI_OPCODE_UMUL] = { 0, tgsi_to_qir_umul },
1043 [TGSI_OPCODE_IDIV] = { 0, tgsi_to_qir_idiv },
1044 [TGSI_OPCODE_INEG] = { 0, tgsi_to_qir_ineg },
1045
1046 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_alu },
1047 [TGSI_OPCODE_SEQ] = { 0, tgsi_to_qir_seq },
1048 [TGSI_OPCODE_SNE] = { 0, tgsi_to_qir_sne },
1049 [TGSI_OPCODE_SGE] = { 0, tgsi_to_qir_sge },
1050 [TGSI_OPCODE_SLT] = { 0, tgsi_to_qir_slt },
1051 [TGSI_OPCODE_FSEQ] = { 0, tgsi_to_qir_fseq },
1052 [TGSI_OPCODE_FSNE] = { 0, tgsi_to_qir_fsne },
1053 [TGSI_OPCODE_FSGE] = { 0, tgsi_to_qir_fsge },
1054 [TGSI_OPCODE_FSLT] = { 0, tgsi_to_qir_fslt },
1055 [TGSI_OPCODE_USEQ] = { 0, tgsi_to_qir_useq },
1056 [TGSI_OPCODE_USNE] = { 0, tgsi_to_qir_usne },
1057 [TGSI_OPCODE_ISGE] = { 0, tgsi_to_qir_isge },
1058 [TGSI_OPCODE_ISLT] = { 0, tgsi_to_qir_islt },
1059
1060 [TGSI_OPCODE_CMP] = { 0, tgsi_to_qir_cmp },
1061 [TGSI_OPCODE_MAD] = { 0, tgsi_to_qir_mad },
1062 [TGSI_OPCODE_RCP] = { QOP_RCP, tgsi_to_qir_scalar },
1063 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_scalar },
1064 [TGSI_OPCODE_EX2] = { QOP_EXP2, tgsi_to_qir_scalar },
1065 [TGSI_OPCODE_LG2] = { QOP_LOG2, tgsi_to_qir_scalar },
1066 [TGSI_OPCODE_LRP] = { 0, tgsi_to_qir_lrp },
1067 [TGSI_OPCODE_TRUNC] = { 0, tgsi_to_qir_trunc },
1068 [TGSI_OPCODE_FRC] = { 0, tgsi_to_qir_frc },
1069 [TGSI_OPCODE_FLR] = { 0, tgsi_to_qir_flr },
1070 [TGSI_OPCODE_SIN] = { 0, tgsi_to_qir_sin },
1071 [TGSI_OPCODE_COS] = { 0, tgsi_to_qir_cos },
1072 [TGSI_OPCODE_CLAMP] = { 0, tgsi_to_qir_clamp },
1073 };
1074 static int asdf = 0;
1075 uint32_t tgsi_op = tgsi_inst->Instruction.Opcode;
1076
1077 if (tgsi_op == TGSI_OPCODE_END)
1078 return;
1079
1080 struct qreg src_regs[12];
1081 for (int s = 0; s < 3; s++) {
1082 for (int i = 0; i < 4; i++) {
1083 src_regs[4 * s + i] =
1084 get_src(c, tgsi_inst->Instruction.Opcode,
1085 &tgsi_inst->Src[s].Register, i);
1086 }
1087 }
1088
1089 switch (tgsi_op) {
1090 case TGSI_OPCODE_TEX:
1091 case TGSI_OPCODE_TXP:
1092 case TGSI_OPCODE_TXB:
1093 tgsi_to_qir_tex(c, tgsi_inst,
1094 op_trans[tgsi_op].op, src_regs);
1095 return;
1096 case TGSI_OPCODE_KILL:
1097 c->discard = qir_uniform_f(c, 1.0);
1098 return;
1099 case TGSI_OPCODE_KILL_IF:
1100 for (int i = 0; i < 4; i++)
1101 tgsi_to_qir_kill_if(c, src_regs, i);
1102 return;
1103 default:
1104 break;
1105 }
1106
1107 if (tgsi_op > ARRAY_SIZE(op_trans) || !(op_trans[tgsi_op].func)) {
1108 fprintf(stderr, "unknown tgsi inst: ");
1109 tgsi_dump_instruction(tgsi_inst, asdf++);
1110 fprintf(stderr, "\n");
1111 abort();
1112 }
1113
1114 for (int i = 0; i < 4; i++) {
1115 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
1116 continue;
1117
1118 struct qreg result;
1119
1120 result = op_trans[tgsi_op].func(c, tgsi_inst,
1121 op_trans[tgsi_op].op,
1122 src_regs, i);
1123
1124 if (tgsi_inst->Instruction.Saturate) {
1125 float low = (tgsi_inst->Instruction.Saturate ==
1126 TGSI_SAT_MINUS_PLUS_ONE ? -1.0 : 0.0);
1127 result = qir_FMAX(c,
1128 qir_FMIN(c,
1129 result,
1130 qir_uniform_f(c, 1.0)),
1131 qir_uniform_f(c, low));
1132 }
1133
1134 update_dst(c, tgsi_inst, i, result);
1135 }
1136 }
1137
1138 static void
1139 parse_tgsi_immediate(struct vc4_compile *c, struct tgsi_full_immediate *imm)
1140 {
1141 for (int i = 0; i < 4; i++) {
1142 unsigned n = c->num_consts++;
1143 resize_qreg_array(c, &c->consts, &c->consts_array_size, n + 1);
1144 c->consts[n] = qir_uniform_ui(c, imm->u[i].Uint);
1145 }
1146 }
1147
1148 static struct qreg
1149 vc4_blend_channel(struct vc4_compile *c,
1150 struct qreg *dst,
1151 struct qreg *src,
1152 struct qreg val,
1153 unsigned factor,
1154 int channel)
1155 {
1156 switch(factor) {
1157 case PIPE_BLENDFACTOR_ONE:
1158 return val;
1159 case PIPE_BLENDFACTOR_SRC_COLOR:
1160 return qir_FMUL(c, val, src[channel]);
1161 case PIPE_BLENDFACTOR_SRC_ALPHA:
1162 return qir_FMUL(c, val, src[3]);
1163 case PIPE_BLENDFACTOR_DST_ALPHA:
1164 return qir_FMUL(c, val, dst[3]);
1165 case PIPE_BLENDFACTOR_DST_COLOR:
1166 return qir_FMUL(c, val, dst[channel]);
1167 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
1168 return qir_FMIN(c, src[3], qir_FSUB(c,
1169 qir_uniform_f(c, 1.0),
1170 dst[3]));
1171 case PIPE_BLENDFACTOR_CONST_COLOR:
1172 return qir_FMUL(c, val,
1173 get_temp_for_uniform(c,
1174 QUNIFORM_BLEND_CONST_COLOR,
1175 channel));
1176 case PIPE_BLENDFACTOR_CONST_ALPHA:
1177 return qir_FMUL(c, val,
1178 get_temp_for_uniform(c,
1179 QUNIFORM_BLEND_CONST_COLOR,
1180 3));
1181 case PIPE_BLENDFACTOR_ZERO:
1182 return qir_uniform_f(c, 0.0);
1183 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
1184 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1185 src[channel]));
1186 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
1187 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1188 src[3]));
1189 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
1190 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1191 dst[3]));
1192 case PIPE_BLENDFACTOR_INV_DST_COLOR:
1193 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1194 dst[channel]));
1195 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
1196 return qir_FMUL(c, val,
1197 qir_FSUB(c, qir_uniform_f(c, 1.0),
1198 get_temp_for_uniform(c,
1199 QUNIFORM_BLEND_CONST_COLOR,
1200 channel)));
1201 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
1202 return qir_FMUL(c, val,
1203 qir_FSUB(c, qir_uniform_f(c, 1.0),
1204 get_temp_for_uniform(c,
1205 QUNIFORM_BLEND_CONST_COLOR,
1206 3)));
1207
1208 default:
1209 case PIPE_BLENDFACTOR_SRC1_COLOR:
1210 case PIPE_BLENDFACTOR_SRC1_ALPHA:
1211 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
1212 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
1213 /* Unsupported. */
1214 fprintf(stderr, "Unknown blend factor %d\n", factor);
1215 return val;
1216 }
1217 }
1218
1219 static struct qreg
1220 vc4_blend_func(struct vc4_compile *c,
1221 struct qreg src, struct qreg dst,
1222 unsigned func)
1223 {
1224 switch (func) {
1225 case PIPE_BLEND_ADD:
1226 return qir_FADD(c, src, dst);
1227 case PIPE_BLEND_SUBTRACT:
1228 return qir_FSUB(c, src, dst);
1229 case PIPE_BLEND_REVERSE_SUBTRACT:
1230 return qir_FSUB(c, dst, src);
1231 case PIPE_BLEND_MIN:
1232 return qir_FMIN(c, src, dst);
1233 case PIPE_BLEND_MAX:
1234 return qir_FMAX(c, src, dst);
1235
1236 default:
1237 /* Unsupported. */
1238 fprintf(stderr, "Unknown blend func %d\n", func);
1239 return src;
1240
1241 }
1242 }
1243
1244 /**
1245 * Implements fixed function blending in shader code.
1246 *
1247 * VC4 doesn't have any hardware support for blending. Instead, you read the
1248 * current contents of the destination from the tile buffer after having
1249 * waited for the scoreboard (which is handled by vc4_qpu_emit.c), then do
1250 * math using your output color and that destination value, and update the
1251 * output color appropriately.
1252 */
1253 static void
1254 vc4_blend(struct vc4_compile *c, struct qreg *result,
1255 struct qreg *dst_color, struct qreg *src_color)
1256 {
1257 struct pipe_rt_blend_state *blend = &c->fs_key->blend;
1258
1259 if (!blend->blend_enable) {
1260 for (int i = 0; i < 4; i++)
1261 result[i] = src_color[i];
1262 return;
1263 }
1264
1265 struct qreg src_blend[4], dst_blend[4];
1266 for (int i = 0; i < 3; i++) {
1267 src_blend[i] = vc4_blend_channel(c,
1268 dst_color, src_color,
1269 src_color[i],
1270 blend->rgb_src_factor, i);
1271 dst_blend[i] = vc4_blend_channel(c,
1272 dst_color, src_color,
1273 dst_color[i],
1274 blend->rgb_dst_factor, i);
1275 }
1276 src_blend[3] = vc4_blend_channel(c,
1277 dst_color, src_color,
1278 src_color[3],
1279 blend->alpha_src_factor, 3);
1280 dst_blend[3] = vc4_blend_channel(c,
1281 dst_color, src_color,
1282 dst_color[3],
1283 blend->alpha_dst_factor, 3);
1284
1285 for (int i = 0; i < 3; i++) {
1286 result[i] = vc4_blend_func(c,
1287 src_blend[i], dst_blend[i],
1288 blend->rgb_func);
1289 }
1290 result[3] = vc4_blend_func(c,
1291 src_blend[3], dst_blend[3],
1292 blend->alpha_func);
1293 }
1294
1295 static void
1296 alpha_test_discard(struct vc4_compile *c)
1297 {
1298 struct qreg src_alpha;
1299 struct qreg alpha_ref = get_temp_for_uniform(c, QUNIFORM_ALPHA_REF, 0);
1300
1301 if (!c->fs_key->alpha_test)
1302 return;
1303
1304 if (c->output_color_index != -1)
1305 src_alpha = c->outputs[c->output_color_index + 3];
1306 else
1307 src_alpha = qir_uniform_f(c, 1.0);
1308
1309 if (c->discard.file == QFILE_NULL)
1310 c->discard = qir_uniform_f(c, 0.0);
1311
1312 switch (c->fs_key->alpha_test_func) {
1313 case PIPE_FUNC_NEVER:
1314 c->discard = qir_uniform_f(c, 1.0);
1315 break;
1316 case PIPE_FUNC_ALWAYS:
1317 break;
1318 case PIPE_FUNC_EQUAL:
1319 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1320 c->discard = qir_SEL_X_Y_ZS(c, c->discard,
1321 qir_uniform_f(c, 1.0));
1322 break;
1323 case PIPE_FUNC_NOTEQUAL:
1324 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1325 c->discard = qir_SEL_X_Y_ZC(c, c->discard,
1326 qir_uniform_f(c, 1.0));
1327 break;
1328 case PIPE_FUNC_GREATER:
1329 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1330 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1331 qir_uniform_f(c, 1.0));
1332 break;
1333 case PIPE_FUNC_GEQUAL:
1334 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1335 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1336 qir_uniform_f(c, 1.0));
1337 break;
1338 case PIPE_FUNC_LESS:
1339 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1340 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1341 qir_uniform_f(c, 1.0));
1342 break;
1343 case PIPE_FUNC_LEQUAL:
1344 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1345 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1346 qir_uniform_f(c, 1.0));
1347 break;
1348 }
1349 }
1350
1351 static void
1352 emit_frag_end(struct vc4_compile *c)
1353 {
1354 alpha_test_discard(c);
1355
1356 enum pipe_format color_format = c->fs_key->color_format;
1357 const uint8_t *format_swiz = vc4_get_format_swizzle(color_format);
1358 struct qreg tlb_read_color[4] = { c->undef, c->undef, c->undef, c->undef };
1359 struct qreg dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1360 struct qreg linear_dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1361 if (c->fs_key->blend.blend_enable ||
1362 c->fs_key->blend.colormask != 0xf) {
1363 struct qreg r4 = qir_TLB_COLOR_READ(c);
1364 for (int i = 0; i < 4; i++)
1365 tlb_read_color[i] = qir_R4_UNPACK(c, r4, i);
1366 for (int i = 0; i < 4; i++) {
1367 dst_color[i] = get_swizzled_channel(c,
1368 tlb_read_color,
1369 format_swiz[i]);
1370 if (util_format_is_srgb(color_format) && i != 3) {
1371 linear_dst_color[i] =
1372 qir_srgb_decode(c, dst_color[i]);
1373 } else {
1374 linear_dst_color[i] = dst_color[i];
1375 }
1376 }
1377 }
1378
1379 struct qreg blend_color[4];
1380 struct qreg undef_array[4] = {
1381 c->undef, c->undef, c->undef, c->undef
1382 };
1383 vc4_blend(c, blend_color, linear_dst_color,
1384 (c->output_color_index != -1 ?
1385 c->outputs + c->output_color_index :
1386 undef_array));
1387
1388 if (util_format_is_srgb(color_format)) {
1389 for (int i = 0; i < 3; i++)
1390 blend_color[i] = qir_srgb_encode(c, blend_color[i]);
1391 }
1392
1393 /* If the bit isn't set in the color mask, then just return the
1394 * original dst color, instead.
1395 */
1396 for (int i = 0; i < 4; i++) {
1397 if (!(c->fs_key->blend.colormask & (1 << i))) {
1398 blend_color[i] = dst_color[i];
1399 }
1400 }
1401
1402 /* Debug: Sometimes you're getting a black output and just want to see
1403 * if the FS is getting executed at all. Spam magenta into the color
1404 * output.
1405 */
1406 if (0) {
1407 blend_color[0] = qir_uniform_f(c, 1.0);
1408 blend_color[1] = qir_uniform_f(c, 0.0);
1409 blend_color[2] = qir_uniform_f(c, 1.0);
1410 blend_color[3] = qir_uniform_f(c, 0.5);
1411 }
1412
1413 struct qreg swizzled_outputs[4];
1414 for (int i = 0; i < 4; i++) {
1415 swizzled_outputs[i] = get_swizzled_channel(c, blend_color,
1416 format_swiz[i]);
1417 }
1418
1419 if (c->discard.file != QFILE_NULL)
1420 qir_TLB_DISCARD_SETUP(c, c->discard);
1421
1422 if (c->fs_key->stencil_enabled) {
1423 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 0));
1424 if (c->fs_key->stencil_twoside) {
1425 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 1));
1426 }
1427 if (c->fs_key->stencil_full_writemasks) {
1428 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 2));
1429 }
1430 }
1431
1432 if (c->fs_key->depth_enabled) {
1433 struct qreg z;
1434 if (c->output_position_index != -1) {
1435 z = qir_FTOI(c, qir_FMUL(c, c->outputs[c->output_position_index + 2],
1436 qir_uniform_f(c, 0xffffff)));
1437 } else {
1438 z = qir_FRAG_Z(c);
1439 }
1440 qir_TLB_Z_WRITE(c, z);
1441 }
1442
1443 bool color_written = false;
1444 for (int i = 0; i < 4; i++) {
1445 if (swizzled_outputs[i].file != QFILE_NULL)
1446 color_written = true;
1447 }
1448
1449 struct qreg packed_color;
1450 if (color_written) {
1451 /* Fill in any undefined colors. The simulator will assertion
1452 * fail if we read something that wasn't written, and I don't
1453 * know what hardware does.
1454 */
1455 for (int i = 0; i < 4; i++) {
1456 if (swizzled_outputs[i].file == QFILE_NULL)
1457 swizzled_outputs[i] = qir_uniform_f(c, 0.0);
1458 }
1459 packed_color = qir_get_temp(c);
1460 qir_emit(c, qir_inst4(QOP_PACK_COLORS, packed_color,
1461 swizzled_outputs[0],
1462 swizzled_outputs[1],
1463 swizzled_outputs[2],
1464 swizzled_outputs[3]));
1465 } else {
1466 packed_color = qir_uniform_ui(c, 0);
1467 }
1468
1469 qir_emit(c, qir_inst(QOP_TLB_COLOR_WRITE, c->undef,
1470 packed_color, c->undef));
1471 }
1472
1473 static void
1474 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1475 {
1476 struct qreg xyi[2];
1477
1478 for (int i = 0; i < 2; i++) {
1479 struct qreg scale =
1480 add_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1481
1482 xyi[i] = qir_FTOI(c, qir_FMUL(c,
1483 qir_FMUL(c,
1484 c->outputs[i],
1485 scale),
1486 rcp_w));
1487 }
1488
1489 qir_VPM_WRITE(c, qir_PACK_SCALED(c, xyi[0], xyi[1]));
1490 }
1491
1492 static void
1493 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1494 {
1495 struct qreg zscale = add_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1496 struct qreg zoffset = add_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1497
1498 qir_VPM_WRITE(c, qir_FMUL(c, qir_FADD(c, qir_FMUL(c,
1499 c->outputs[2],
1500 zscale),
1501 zoffset),
1502 rcp_w));
1503 }
1504
1505 static void
1506 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1507 {
1508 qir_VPM_WRITE(c, rcp_w);
1509 }
1510
1511 static void
1512 emit_point_size_write(struct vc4_compile *c)
1513 {
1514 struct qreg point_size;
1515
1516 if (c->output_point_size_index)
1517 point_size = c->outputs[c->output_point_size_index + 3];
1518 else
1519 point_size = qir_uniform_f(c, 1.0);
1520
1521 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1522 * BCM21553).
1523 */
1524 point_size = qir_FMAX(c, point_size, qir_uniform_f(c, .125));
1525
1526 qir_VPM_WRITE(c, point_size);
1527 }
1528
1529 static void
1530 emit_vert_end(struct vc4_compile *c)
1531 {
1532 struct qreg rcp_w = qir_RCP(c, c->outputs[3]);
1533
1534 emit_scaled_viewport_write(c, rcp_w);
1535 emit_zs_write(c, rcp_w);
1536 emit_rcp_wc_write(c, rcp_w);
1537 if (c->vs_key->per_vertex_point_size)
1538 emit_point_size_write(c);
1539
1540 for (int i = 4; i < c->num_outputs; i++) {
1541 qir_VPM_WRITE(c, c->outputs[i]);
1542 }
1543 }
1544
1545 static void
1546 emit_coord_end(struct vc4_compile *c)
1547 {
1548 struct qreg rcp_w = qir_RCP(c, c->outputs[3]);
1549
1550 for (int i = 0; i < 4; i++)
1551 qir_VPM_WRITE(c, c->outputs[i]);
1552
1553 emit_scaled_viewport_write(c, rcp_w);
1554 emit_zs_write(c, rcp_w);
1555 emit_rcp_wc_write(c, rcp_w);
1556 if (c->vs_key->per_vertex_point_size)
1557 emit_point_size_write(c);
1558 }
1559
1560 static struct vc4_compile *
1561 vc4_shader_tgsi_to_qir(struct vc4_context *vc4,
1562 struct vc4_compiled_shader *shader, enum qstage stage,
1563 struct vc4_key *key)
1564 {
1565 struct vc4_compile *c = qir_compile_init();
1566 int ret;
1567
1568 c->stage = stage;
1569 c->shader_state = &key->shader_state->base;
1570
1571 c->key = key;
1572 switch (stage) {
1573 case QSTAGE_FRAG:
1574 c->fs_key = (struct vc4_fs_key *)key;
1575 if (c->fs_key->is_points) {
1576 c->point_x = emit_fragment_varying(c, 0);
1577 c->point_y = emit_fragment_varying(c, 0);
1578 } else if (c->fs_key->is_lines) {
1579 c->line_x = emit_fragment_varying(c, 0);
1580 }
1581 break;
1582 case QSTAGE_VERT:
1583 c->vs_key = (struct vc4_vs_key *)key;
1584 break;
1585 case QSTAGE_COORD:
1586 c->vs_key = (struct vc4_vs_key *)key;
1587 break;
1588 }
1589
1590 const struct tgsi_token *tokens = key->shader_state->base.tokens;
1591 if (c->fs_key && c->fs_key->light_twoside) {
1592 if (!key->shader_state->twoside_tokens) {
1593 const struct tgsi_lowering_config lowering_config = {
1594 .color_two_side = true,
1595 };
1596 struct tgsi_shader_info info;
1597 key->shader_state->twoside_tokens =
1598 tgsi_transform_lowering(&lowering_config,
1599 key->shader_state->base.tokens,
1600 &info);
1601
1602 /* If no transformation occurred, then NULL is
1603 * returned and we just use our original tokens.
1604 */
1605 if (!key->shader_state->twoside_tokens) {
1606 key->shader_state->twoside_tokens =
1607 key->shader_state->base.tokens;
1608 }
1609 }
1610 tokens = key->shader_state->twoside_tokens;
1611 }
1612
1613 ret = tgsi_parse_init(&c->parser, tokens);
1614 assert(ret == TGSI_PARSE_OK);
1615
1616 if (vc4_debug & VC4_DEBUG_TGSI) {
1617 fprintf(stderr, "TGSI:\n");
1618 tgsi_dump(tokens, 0);
1619 }
1620
1621 while (!tgsi_parse_end_of_tokens(&c->parser)) {
1622 tgsi_parse_token(&c->parser);
1623
1624 switch (c->parser.FullToken.Token.Type) {
1625 case TGSI_TOKEN_TYPE_DECLARATION:
1626 emit_tgsi_declaration(c,
1627 &c->parser.FullToken.FullDeclaration);
1628 break;
1629
1630 case TGSI_TOKEN_TYPE_INSTRUCTION:
1631 emit_tgsi_instruction(c,
1632 &c->parser.FullToken.FullInstruction);
1633 break;
1634
1635 case TGSI_TOKEN_TYPE_IMMEDIATE:
1636 parse_tgsi_immediate(c,
1637 &c->parser.FullToken.FullImmediate);
1638 break;
1639 }
1640 }
1641
1642 switch (stage) {
1643 case QSTAGE_FRAG:
1644 emit_frag_end(c);
1645 break;
1646 case QSTAGE_VERT:
1647 emit_vert_end(c);
1648 break;
1649 case QSTAGE_COORD:
1650 emit_coord_end(c);
1651 break;
1652 }
1653
1654 tgsi_parse_free(&c->parser);
1655
1656 qir_optimize(c);
1657
1658 if (vc4_debug & VC4_DEBUG_QIR) {
1659 fprintf(stderr, "QIR:\n");
1660 qir_dump(c);
1661 }
1662 qir_reorder_uniforms(c);
1663 vc4_generate_code(vc4, c);
1664
1665 if (vc4_debug & VC4_DEBUG_SHADERDB) {
1666 fprintf(stderr, "SHADER-DB: %s: %d instructions\n",
1667 qir_get_stage_name(c->stage), c->qpu_inst_count);
1668 fprintf(stderr, "SHADER-DB: %s: %d uniforms\n",
1669 qir_get_stage_name(c->stage), c->num_uniforms);
1670 }
1671
1672 return c;
1673 }
1674
1675 static void *
1676 vc4_shader_state_create(struct pipe_context *pctx,
1677 const struct pipe_shader_state *cso)
1678 {
1679 struct vc4_uncompiled_shader *so = CALLOC_STRUCT(vc4_uncompiled_shader);
1680 if (!so)
1681 return NULL;
1682
1683 const struct tgsi_lowering_config lowering_config = {
1684 .lower_DST = true,
1685 .lower_XPD = true,
1686 .lower_SCS = true,
1687 .lower_POW = true,
1688 .lower_LIT = true,
1689 .lower_EXP = true,
1690 .lower_LOG = true,
1691 .lower_DP4 = true,
1692 .lower_DP3 = true,
1693 .lower_DPH = true,
1694 .lower_DP2 = true,
1695 .lower_DP2A = true,
1696 };
1697
1698 struct tgsi_shader_info info;
1699 so->base.tokens = tgsi_transform_lowering(&lowering_config, cso->tokens, &info);
1700 if (!so->base.tokens)
1701 so->base.tokens = tgsi_dup_tokens(cso->tokens);
1702
1703 return so;
1704 }
1705
1706 static void
1707 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
1708 int shader_index,
1709 struct vc4_compile *c)
1710 {
1711 int count = c->num_uniforms;
1712 struct vc4_shader_uniform_info *uinfo = &shader->uniforms[shader_index];
1713
1714 uinfo->count = count;
1715 uinfo->data = malloc(count * sizeof(*uinfo->data));
1716 memcpy(uinfo->data, c->uniform_data,
1717 count * sizeof(*uinfo->data));
1718 uinfo->contents = malloc(count * sizeof(*uinfo->contents));
1719 memcpy(uinfo->contents, c->uniform_contents,
1720 count * sizeof(*uinfo->contents));
1721 uinfo->num_texture_samples = c->num_texture_samples;
1722 }
1723
1724 static void
1725 vc4_fs_compile(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1726 struct vc4_fs_key *key)
1727 {
1728 struct vc4_compile *c = vc4_shader_tgsi_to_qir(vc4, shader,
1729 QSTAGE_FRAG,
1730 &key->base);
1731 shader->num_inputs = c->num_inputs;
1732 shader->color_inputs = c->color_inputs;
1733 copy_uniform_state_to_shader(shader, 0, c);
1734 shader->bo = vc4_bo_alloc_mem(vc4->screen, c->qpu_insts,
1735 c->qpu_inst_count * sizeof(uint64_t),
1736 "fs_code");
1737
1738 qir_compile_destroy(c);
1739 }
1740
1741 static void
1742 vc4_vs_compile(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1743 struct vc4_vs_key *key)
1744 {
1745 struct vc4_compile *vs_c = vc4_shader_tgsi_to_qir(vc4, shader,
1746 QSTAGE_VERT,
1747 &key->base);
1748 copy_uniform_state_to_shader(shader, 0, vs_c);
1749
1750 struct vc4_compile *cs_c = vc4_shader_tgsi_to_qir(vc4, shader,
1751 QSTAGE_COORD,
1752 &key->base);
1753 copy_uniform_state_to_shader(shader, 1, cs_c);
1754
1755 uint32_t vs_size = vs_c->qpu_inst_count * sizeof(uint64_t);
1756 uint32_t cs_size = cs_c->qpu_inst_count * sizeof(uint64_t);
1757 shader->coord_shader_offset = vs_size; /* XXX: alignment? */
1758 shader->bo = vc4_bo_alloc(vc4->screen,
1759 shader->coord_shader_offset + cs_size,
1760 "vs_code");
1761
1762 void *map = vc4_bo_map(shader->bo);
1763 memcpy(map, vs_c->qpu_insts, vs_size);
1764 memcpy(map + shader->coord_shader_offset,
1765 cs_c->qpu_insts, cs_size);
1766
1767 qir_compile_destroy(vs_c);
1768 qir_compile_destroy(cs_c);
1769 }
1770
1771 static void
1772 vc4_setup_shared_key(struct vc4_key *key, struct vc4_texture_stateobj *texstate)
1773 {
1774 for (int i = 0; i < texstate->num_textures; i++) {
1775 struct pipe_sampler_view *sampler = texstate->textures[i];
1776 struct pipe_sampler_state *sampler_state =
1777 texstate->samplers[i];
1778
1779 if (sampler) {
1780 key->tex[i].format = sampler->format;
1781 key->tex[i].swizzle[0] = sampler->swizzle_r;
1782 key->tex[i].swizzle[1] = sampler->swizzle_g;
1783 key->tex[i].swizzle[2] = sampler->swizzle_b;
1784 key->tex[i].swizzle[3] = sampler->swizzle_a;
1785 key->tex[i].compare_mode = sampler_state->compare_mode;
1786 key->tex[i].compare_func = sampler_state->compare_func;
1787 key->tex[i].wrap_s = sampler_state->wrap_s;
1788 key->tex[i].wrap_t = sampler_state->wrap_t;
1789 }
1790 }
1791 }
1792
1793 static void
1794 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
1795 {
1796 struct vc4_fs_key local_key;
1797 struct vc4_fs_key *key = &local_key;
1798
1799 memset(key, 0, sizeof(*key));
1800 vc4_setup_shared_key(&key->base, &vc4->fragtex);
1801 key->base.shader_state = vc4->prog.bind_fs;
1802 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
1803 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
1804 prim_mode <= PIPE_PRIM_LINE_STRIP);
1805 key->blend = vc4->blend->rt[0];
1806
1807 if (vc4->framebuffer.cbufs[0])
1808 key->color_format = vc4->framebuffer.cbufs[0]->format;
1809
1810 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
1811 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
1812 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
1813 key->depth_enabled = (vc4->zsa->base.depth.enabled ||
1814 key->stencil_enabled);
1815 if (vc4->zsa->base.alpha.enabled) {
1816 key->alpha_test = true;
1817 key->alpha_test_func = vc4->zsa->base.alpha.func;
1818 }
1819
1820 if (key->is_points) {
1821 key->point_sprite_mask =
1822 vc4->rasterizer->base.sprite_coord_enable;
1823 key->point_coord_upper_left =
1824 (vc4->rasterizer->base.sprite_coord_mode ==
1825 PIPE_SPRITE_COORD_UPPER_LEFT);
1826 }
1827
1828 key->light_twoside = vc4->rasterizer->base.light_twoside;
1829
1830 vc4->prog.fs = util_hash_table_get(vc4->fs_cache, key);
1831 if (vc4->prog.fs)
1832 return;
1833
1834 key = malloc(sizeof(*key));
1835 memcpy(key, &local_key, sizeof(*key));
1836
1837 struct vc4_compiled_shader *shader = CALLOC_STRUCT(vc4_compiled_shader);
1838 vc4_fs_compile(vc4, shader, key);
1839 util_hash_table_set(vc4->fs_cache, key, shader);
1840
1841 if (vc4->rasterizer->base.flatshade &&
1842 vc4->prog.fs &&
1843 vc4->prog.fs->color_inputs != shader->color_inputs) {
1844 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
1845 }
1846
1847 vc4->prog.fs = shader;
1848 }
1849
1850 static void
1851 vc4_update_compiled_vs(struct vc4_context *vc4, uint8_t prim_mode)
1852 {
1853 struct vc4_vs_key local_key;
1854 struct vc4_vs_key *key = &local_key;
1855
1856 memset(key, 0, sizeof(*key));
1857 vc4_setup_shared_key(&key->base, &vc4->verttex);
1858 key->base.shader_state = vc4->prog.bind_vs;
1859
1860 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
1861 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
1862
1863 key->per_vertex_point_size =
1864 (prim_mode == PIPE_PRIM_POINTS &&
1865 vc4->rasterizer->base.point_size_per_vertex);
1866
1867 vc4->prog.vs = util_hash_table_get(vc4->vs_cache, key);
1868 if (vc4->prog.vs)
1869 return;
1870
1871 key = malloc(sizeof(*key));
1872 memcpy(key, &local_key, sizeof(*key));
1873
1874 struct vc4_compiled_shader *shader = CALLOC_STRUCT(vc4_compiled_shader);
1875 vc4_vs_compile(vc4, shader, key);
1876 util_hash_table_set(vc4->vs_cache, key, shader);
1877
1878 vc4->prog.vs = shader;
1879 }
1880
1881 void
1882 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
1883 {
1884 vc4_update_compiled_fs(vc4, prim_mode);
1885 vc4_update_compiled_vs(vc4, prim_mode);
1886 }
1887
1888 static unsigned
1889 fs_cache_hash(void *key)
1890 {
1891 return util_hash_crc32(key, sizeof(struct vc4_fs_key));
1892 }
1893
1894 static unsigned
1895 vs_cache_hash(void *key)
1896 {
1897 return util_hash_crc32(key, sizeof(struct vc4_vs_key));
1898 }
1899
1900 static int
1901 fs_cache_compare(void *key1, void *key2)
1902 {
1903 return memcmp(key1, key2, sizeof(struct vc4_fs_key));
1904 }
1905
1906 static int
1907 vs_cache_compare(void *key1, void *key2)
1908 {
1909 return memcmp(key1, key2, sizeof(struct vc4_vs_key));
1910 }
1911
1912 struct delete_state {
1913 struct vc4_context *vc4;
1914 struct vc4_uncompiled_shader *shader_state;
1915 };
1916
1917 static enum pipe_error
1918 fs_delete_from_cache(void *in_key, void *in_value, void *data)
1919 {
1920 struct delete_state *del = data;
1921 struct vc4_fs_key *key = in_key;
1922 struct vc4_compiled_shader *shader = in_value;
1923
1924 if (key->base.shader_state == data) {
1925 util_hash_table_remove(del->vc4->fs_cache, key);
1926 vc4_bo_unreference(&shader->bo);
1927 free(shader);
1928 }
1929
1930 return 0;
1931 }
1932
1933 static enum pipe_error
1934 vs_delete_from_cache(void *in_key, void *in_value, void *data)
1935 {
1936 struct delete_state *del = data;
1937 struct vc4_vs_key *key = in_key;
1938 struct vc4_compiled_shader *shader = in_value;
1939
1940 if (key->base.shader_state == data) {
1941 util_hash_table_remove(del->vc4->vs_cache, key);
1942 vc4_bo_unreference(&shader->bo);
1943 free(shader);
1944 }
1945
1946 return 0;
1947 }
1948
1949 static void
1950 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
1951 {
1952 struct vc4_context *vc4 = vc4_context(pctx);
1953 struct vc4_uncompiled_shader *so = hwcso;
1954 struct delete_state del;
1955
1956 del.vc4 = vc4;
1957 del.shader_state = so;
1958 util_hash_table_foreach(vc4->fs_cache, fs_delete_from_cache, &del);
1959 util_hash_table_foreach(vc4->vs_cache, vs_delete_from_cache, &del);
1960
1961 if (so->twoside_tokens != so->base.tokens)
1962 free((void *)so->twoside_tokens);
1963 free((void *)so->base.tokens);
1964 free(so);
1965 }
1966
1967 static uint32_t translate_wrap(uint32_t p_wrap, bool using_nearest)
1968 {
1969 switch (p_wrap) {
1970 case PIPE_TEX_WRAP_REPEAT:
1971 return 0;
1972 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1973 return 1;
1974 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1975 return 2;
1976 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1977 return 3;
1978 case PIPE_TEX_WRAP_CLAMP:
1979 return (using_nearest ? 1 : 3);
1980 default:
1981 fprintf(stderr, "Unknown wrap mode %d\n", p_wrap);
1982 assert(!"not reached");
1983 return 0;
1984 }
1985 }
1986
1987 static void
1988 write_texture_p0(struct vc4_context *vc4,
1989 struct vc4_texture_stateobj *texstate,
1990 uint32_t unit)
1991 {
1992 struct pipe_sampler_view *texture = texstate->textures[unit];
1993 struct vc4_resource *rsc = vc4_resource(texture->texture);
1994
1995 bool is_cube = texture->target == PIPE_TEXTURE_CUBE;
1996
1997 cl_reloc(vc4, &vc4->uniforms, rsc->bo,
1998 rsc->slices[0].offset | texture->u.tex.last_level |
1999 is_cube << 9 |
2000 ((rsc->vc4_format & 7) << 4));
2001 }
2002
2003 static void
2004 write_texture_p1(struct vc4_context *vc4,
2005 struct vc4_texture_stateobj *texstate,
2006 uint32_t unit)
2007 {
2008 struct pipe_sampler_view *texture = texstate->textures[unit];
2009 struct vc4_resource *rsc = vc4_resource(texture->texture);
2010 struct pipe_sampler_state *sampler = texstate->samplers[unit];
2011 static const uint8_t minfilter_map[6] = {
2012 2, 4, /* mipfilter nearest */
2013 3, 5, /* mipfilter linear */
2014 1, 0, /* mipfilter none */
2015 };
2016 static const uint32_t magfilter_map[] = {
2017 [PIPE_TEX_FILTER_NEAREST] = 1,
2018 [PIPE_TEX_FILTER_LINEAR] = 0,
2019 };
2020
2021 bool either_nearest =
2022 (sampler->mag_img_filter == PIPE_TEX_MIPFILTER_NEAREST ||
2023 sampler->min_img_filter == PIPE_TEX_MIPFILTER_NEAREST);
2024
2025 cl_u32(&vc4->uniforms,
2026 ((rsc->vc4_format >> 4) << 31) |
2027 (texture->texture->height0 << 20) |
2028 (texture->texture->width0 << 8) |
2029 (magfilter_map[sampler->mag_img_filter] << 7) |
2030 (minfilter_map[sampler->min_mip_filter * 2 +
2031 sampler->min_img_filter] << 4) |
2032 (translate_wrap(sampler->wrap_t, either_nearest) << 2) |
2033 (translate_wrap(sampler->wrap_s, either_nearest) << 0));
2034 }
2035
2036 static void
2037 write_texture_p2(struct vc4_context *vc4,
2038 struct vc4_texture_stateobj *texstate,
2039 uint32_t unit)
2040 {
2041 struct pipe_sampler_view *texture = texstate->textures[unit];
2042 struct vc4_resource *rsc = vc4_resource(texture->texture);
2043
2044 cl_u32(&vc4->uniforms, (1 << 30) | rsc->cube_map_stride);
2045 }
2046
2047
2048 #define SWIZ(x,y,z,w) { \
2049 UTIL_FORMAT_SWIZZLE_##x, \
2050 UTIL_FORMAT_SWIZZLE_##y, \
2051 UTIL_FORMAT_SWIZZLE_##z, \
2052 UTIL_FORMAT_SWIZZLE_##w \
2053 }
2054
2055 static void
2056 write_texture_border_color(struct vc4_context *vc4,
2057 struct vc4_texture_stateobj *texstate,
2058 uint32_t unit)
2059 {
2060 struct pipe_sampler_state *sampler = texstate->samplers[unit];
2061 struct pipe_sampler_view *texture = texstate->textures[unit];
2062 struct vc4_resource *rsc = vc4_resource(texture->texture);
2063 union util_color uc;
2064
2065 const struct util_format_description *tex_format_desc =
2066 util_format_description(texture->format);
2067
2068 float border_color[4];
2069 for (int i = 0; i < 4; i++)
2070 border_color[i] = sampler->border_color.f[i];
2071 if (util_format_is_srgb(texture->format)) {
2072 for (int i = 0; i < 3; i++)
2073 border_color[i] =
2074 util_format_linear_to_srgb_float(border_color[i]);
2075 }
2076
2077 /* Turn the border color into the layout of channels that it would
2078 * have when stored as texture contents.
2079 */
2080 float storage_color[4];
2081 util_format_unswizzle_4f(storage_color,
2082 border_color,
2083 tex_format_desc->swizzle);
2084
2085 /* Now, pack so that when the vc4_format-sampled texture contents are
2086 * replaced with our border color, the vc4_get_format_swizzle()
2087 * swizzling will get the right channels.
2088 */
2089 if (util_format_is_depth_or_stencil(texture->format)) {
2090 uc.ui[0] = util_pack_z(PIPE_FORMAT_Z24X8_UNORM,
2091 sampler->border_color.f[0]) << 8;
2092 } else {
2093 switch (rsc->vc4_format) {
2094 default:
2095 case VC4_TEXTURE_TYPE_RGBA8888:
2096 util_pack_color(storage_color,
2097 PIPE_FORMAT_R8G8B8A8_UNORM, &uc);
2098 break;
2099 case VC4_TEXTURE_TYPE_RGBA4444:
2100 util_pack_color(storage_color,
2101 PIPE_FORMAT_A8B8G8R8_UNORM, &uc);
2102 break;
2103 case VC4_TEXTURE_TYPE_RGB565:
2104 util_pack_color(storage_color,
2105 PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
2106 break;
2107 case VC4_TEXTURE_TYPE_ALPHA:
2108 uc.ui[0] = float_to_ubyte(storage_color[0]) << 24;
2109 break;
2110 case VC4_TEXTURE_TYPE_LUMALPHA:
2111 uc.ui[0] = ((float_to_ubyte(storage_color[1]) << 24) |
2112 (float_to_ubyte(storage_color[0]) << 0));
2113 break;
2114 }
2115 }
2116
2117 cl_u32(&vc4->uniforms, uc.ui[0]);
2118 }
2119
2120 static uint32_t
2121 get_texrect_scale(struct vc4_texture_stateobj *texstate,
2122 enum quniform_contents contents,
2123 uint32_t data)
2124 {
2125 struct pipe_sampler_view *texture = texstate->textures[data];
2126 uint32_t dim;
2127
2128 if (contents == QUNIFORM_TEXRECT_SCALE_X)
2129 dim = texture->texture->width0;
2130 else
2131 dim = texture->texture->height0;
2132
2133 return fui(1.0f / dim);
2134 }
2135
2136 void
2137 vc4_write_uniforms(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
2138 struct vc4_constbuf_stateobj *cb,
2139 struct vc4_texture_stateobj *texstate,
2140 int shader_index)
2141 {
2142 struct vc4_shader_uniform_info *uinfo = &shader->uniforms[shader_index];
2143 const uint32_t *gallium_uniforms = cb->cb[0].user_buffer;
2144
2145 cl_start_shader_reloc(&vc4->uniforms, uinfo->num_texture_samples);
2146
2147 for (int i = 0; i < uinfo->count; i++) {
2148
2149 switch (uinfo->contents[i]) {
2150 case QUNIFORM_CONSTANT:
2151 cl_u32(&vc4->uniforms, uinfo->data[i]);
2152 break;
2153 case QUNIFORM_UNIFORM:
2154 cl_u32(&vc4->uniforms,
2155 gallium_uniforms[uinfo->data[i]]);
2156 break;
2157 case QUNIFORM_VIEWPORT_X_SCALE:
2158 cl_f(&vc4->uniforms, vc4->viewport.scale[0] * 16.0f);
2159 break;
2160 case QUNIFORM_VIEWPORT_Y_SCALE:
2161 cl_f(&vc4->uniforms, vc4->viewport.scale[1] * 16.0f);
2162 break;
2163
2164 case QUNIFORM_VIEWPORT_Z_OFFSET:
2165 cl_f(&vc4->uniforms, vc4->viewport.translate[2]);
2166 break;
2167 case QUNIFORM_VIEWPORT_Z_SCALE:
2168 cl_f(&vc4->uniforms, vc4->viewport.scale[2]);
2169 break;
2170
2171 case QUNIFORM_TEXTURE_CONFIG_P0:
2172 write_texture_p0(vc4, texstate, uinfo->data[i]);
2173 break;
2174
2175 case QUNIFORM_TEXTURE_CONFIG_P1:
2176 write_texture_p1(vc4, texstate, uinfo->data[i]);
2177 break;
2178
2179 case QUNIFORM_TEXTURE_CONFIG_P2:
2180 write_texture_p2(vc4, texstate, uinfo->data[i]);
2181 break;
2182
2183 case QUNIFORM_TEXTURE_BORDER_COLOR:
2184 write_texture_border_color(vc4, texstate, uinfo->data[i]);
2185 break;
2186
2187 case QUNIFORM_TEXRECT_SCALE_X:
2188 case QUNIFORM_TEXRECT_SCALE_Y:
2189 cl_u32(&vc4->uniforms,
2190 get_texrect_scale(texstate,
2191 uinfo->contents[i],
2192 uinfo->data[i]));
2193 break;
2194
2195 case QUNIFORM_BLEND_CONST_COLOR:
2196 cl_f(&vc4->uniforms,
2197 vc4->blend_color.color[uinfo->data[i]]);
2198 break;
2199
2200 case QUNIFORM_STENCIL:
2201 cl_u32(&vc4->uniforms,
2202 vc4->zsa->stencil_uniforms[uinfo->data[i]] |
2203 (uinfo->data[i] <= 1 ?
2204 (vc4->stencil_ref.ref_value[uinfo->data[i]] << 8) :
2205 0));
2206 break;
2207
2208 case QUNIFORM_ALPHA_REF:
2209 cl_f(&vc4->uniforms, vc4->zsa->base.alpha.ref_value);
2210 break;
2211 }
2212 #if 0
2213 uint32_t written_val = *(uint32_t *)(vc4->uniforms.next - 4);
2214 fprintf(stderr, "%p/%d: %d: 0x%08x (%f)\n",
2215 shader, shader_index, i, written_val, uif(written_val));
2216 #endif
2217 }
2218 }
2219
2220 static void
2221 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
2222 {
2223 struct vc4_context *vc4 = vc4_context(pctx);
2224 vc4->prog.bind_fs = hwcso;
2225 vc4->prog.dirty |= VC4_SHADER_DIRTY_FP;
2226 vc4->dirty |= VC4_DIRTY_PROG;
2227 }
2228
2229 static void
2230 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
2231 {
2232 struct vc4_context *vc4 = vc4_context(pctx);
2233 vc4->prog.bind_vs = hwcso;
2234 vc4->prog.dirty |= VC4_SHADER_DIRTY_VP;
2235 vc4->dirty |= VC4_DIRTY_PROG;
2236 }
2237
2238 void
2239 vc4_program_init(struct pipe_context *pctx)
2240 {
2241 struct vc4_context *vc4 = vc4_context(pctx);
2242
2243 pctx->create_vs_state = vc4_shader_state_create;
2244 pctx->delete_vs_state = vc4_shader_state_delete;
2245
2246 pctx->create_fs_state = vc4_shader_state_create;
2247 pctx->delete_fs_state = vc4_shader_state_delete;
2248
2249 pctx->bind_fs_state = vc4_fp_state_bind;
2250 pctx->bind_vs_state = vc4_vp_state_bind;
2251
2252 vc4->fs_cache = util_hash_table_create(fs_cache_hash, fs_cache_compare);
2253 vc4->vs_cache = util_hash_table_create(vs_cache_hash, vs_cache_compare);
2254 }