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vc4: Add support for storing to NIR registers in a non-SSA fashion.
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "util/u_format.h"
27 #include "util/u_hash.h"
28 #include "util/u_math.h"
29 #include "util/u_memory.h"
30 #include "util/ralloc.h"
31 #include "util/hash_table.h"
32 #include "tgsi/tgsi_dump.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "compiler/nir/nir.h"
35 #include "compiler/nir/nir_builder.h"
36 #include "nir/tgsi_to_nir.h"
37 #include "vc4_context.h"
38 #include "vc4_qpu.h"
39 #include "vc4_qir.h"
40 #ifdef USE_VC4_SIMULATOR
41 #include "simpenrose/simpenrose.h"
42 #endif
43
44 static struct qreg
45 ntq_get_src(struct vc4_compile *c, nir_src src, int i);
46
47 static void
48 resize_qreg_array(struct vc4_compile *c,
49 struct qreg **regs,
50 uint32_t *size,
51 uint32_t decl_size)
52 {
53 if (*size >= decl_size)
54 return;
55
56 uint32_t old_size = *size;
57 *size = MAX2(*size * 2, decl_size);
58 *regs = reralloc(c, *regs, struct qreg, *size);
59 if (!*regs) {
60 fprintf(stderr, "Malloc failure\n");
61 abort();
62 }
63
64 for (uint32_t i = old_size; i < *size; i++)
65 (*regs)[i] = c->undef;
66 }
67
68 static struct qreg
69 indirect_uniform_load(struct vc4_compile *c, nir_intrinsic_instr *intr)
70 {
71 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0);
72 uint32_t offset = intr->const_index[0];
73 struct vc4_compiler_ubo_range *range = NULL;
74 unsigned i;
75 for (i = 0; i < c->num_uniform_ranges; i++) {
76 range = &c->ubo_ranges[i];
77 if (offset >= range->src_offset &&
78 offset < range->src_offset + range->size) {
79 break;
80 }
81 }
82 /* The driver-location-based offset always has to be within a declared
83 * uniform range.
84 */
85 assert(range);
86 if (!range->used) {
87 range->used = true;
88 range->dst_offset = c->next_ubo_dst_offset;
89 c->next_ubo_dst_offset += range->size;
90 c->num_ubo_ranges++;
91 }
92
93 offset -= range->src_offset;
94
95 /* Adjust for where we stored the TGSI register base. */
96 indirect_offset = qir_ADD(c, indirect_offset,
97 qir_uniform_ui(c, (range->dst_offset +
98 offset)));
99
100 /* Clamp to [0, array size). Note that MIN/MAX are signed. */
101 indirect_offset = qir_MAX(c, indirect_offset, qir_uniform_ui(c, 0));
102 indirect_offset = qir_MIN(c, indirect_offset,
103 qir_uniform_ui(c, (range->dst_offset +
104 range->size - 4)));
105
106 qir_TEX_DIRECT(c, indirect_offset, qir_uniform(c, QUNIFORM_UBO_ADDR, 0));
107 c->num_texture_samples++;
108 return qir_TEX_RESULT(c);
109 }
110
111 nir_ssa_def *vc4_nir_get_state_uniform(struct nir_builder *b,
112 enum quniform_contents contents)
113 {
114 nir_intrinsic_instr *intr =
115 nir_intrinsic_instr_create(b->shader,
116 nir_intrinsic_load_uniform);
117 intr->const_index[0] = (VC4_NIR_STATE_UNIFORM_OFFSET + contents) * 4;
118 intr->num_components = 1;
119 intr->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
120 nir_ssa_dest_init(&intr->instr, &intr->dest, 1, 32, NULL);
121 nir_builder_instr_insert(b, &intr->instr);
122 return &intr->dest.ssa;
123 }
124
125 nir_ssa_def *
126 vc4_nir_get_swizzled_channel(nir_builder *b, nir_ssa_def **srcs, int swiz)
127 {
128 switch (swiz) {
129 default:
130 case PIPE_SWIZZLE_NONE:
131 fprintf(stderr, "warning: unknown swizzle\n");
132 /* FALLTHROUGH */
133 case PIPE_SWIZZLE_0:
134 return nir_imm_float(b, 0.0);
135 case PIPE_SWIZZLE_1:
136 return nir_imm_float(b, 1.0);
137 case PIPE_SWIZZLE_X:
138 case PIPE_SWIZZLE_Y:
139 case PIPE_SWIZZLE_Z:
140 case PIPE_SWIZZLE_W:
141 return srcs[swiz];
142 }
143 }
144
145 static struct qreg *
146 ntq_init_ssa_def(struct vc4_compile *c, nir_ssa_def *def)
147 {
148 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
149 def->num_components);
150 _mesa_hash_table_insert(c->def_ht, def, qregs);
151 return qregs;
152 }
153
154 static void
155 ntq_store_dest(struct vc4_compile *c, nir_dest *dest, int chan,
156 struct qreg result)
157 {
158 if (dest->is_ssa) {
159 assert(chan < dest->ssa.num_components);
160
161 struct qreg *qregs;
162 struct hash_entry *entry =
163 _mesa_hash_table_search(c->def_ht, &dest->ssa);
164
165 if (entry)
166 qregs = entry->data;
167 else
168 qregs = ntq_init_ssa_def(c, &dest->ssa);
169
170 qregs[chan] = result;
171 } else {
172 nir_register *reg = dest->reg.reg;
173 assert(dest->reg.base_offset == 0);
174 assert(reg->num_array_elems == 0);
175 struct hash_entry *entry =
176 _mesa_hash_table_search(c->def_ht, reg);
177 struct qreg *qregs = entry->data;
178
179 /* Conditionally move the result to the destination if the
180 * channel is active.
181 */
182 if (c->execute.file != QFILE_NULL) {
183 qir_SF(c, c->execute);
184 qir_MOV_cond(c, QPU_COND_ZS, qregs[chan], result);
185 } else {
186 qir_MOV_dest(c, qregs[chan], result);
187 }
188 }
189 }
190
191 static struct qreg *
192 ntq_get_dest(struct vc4_compile *c, nir_dest *dest)
193 {
194 if (dest->is_ssa) {
195 struct qreg *qregs = ntq_init_ssa_def(c, &dest->ssa);
196 for (int i = 0; i < dest->ssa.num_components; i++)
197 qregs[i] = c->undef;
198 return qregs;
199 } else {
200 nir_register *reg = dest->reg.reg;
201 assert(dest->reg.base_offset == 0);
202 assert(reg->num_array_elems == 0);
203 struct hash_entry *entry =
204 _mesa_hash_table_search(c->def_ht, reg);
205 return entry->data;
206 }
207 }
208
209 static struct qreg
210 ntq_get_src(struct vc4_compile *c, nir_src src, int i)
211 {
212 struct hash_entry *entry;
213 if (src.is_ssa) {
214 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
215 assert(i < src.ssa->num_components);
216 } else {
217 nir_register *reg = src.reg.reg;
218 entry = _mesa_hash_table_search(c->def_ht, reg);
219 assert(reg->num_array_elems == 0);
220 assert(src.reg.base_offset == 0);
221 assert(i < reg->num_components);
222 }
223
224 struct qreg *qregs = entry->data;
225 return qregs[i];
226 }
227
228 static struct qreg
229 ntq_get_alu_src(struct vc4_compile *c, nir_alu_instr *instr,
230 unsigned src)
231 {
232 assert(util_is_power_of_two(instr->dest.write_mask));
233 unsigned chan = ffs(instr->dest.write_mask) - 1;
234 struct qreg r = ntq_get_src(c, instr->src[src].src,
235 instr->src[src].swizzle[chan]);
236
237 assert(!instr->src[src].abs);
238 assert(!instr->src[src].negate);
239
240 return r;
241 };
242
243 static inline struct qreg
244 qir_SAT(struct vc4_compile *c, struct qreg val)
245 {
246 return qir_FMAX(c,
247 qir_FMIN(c, val, qir_uniform_f(c, 1.0)),
248 qir_uniform_f(c, 0.0));
249 }
250
251 static struct qreg
252 ntq_rcp(struct vc4_compile *c, struct qreg x)
253 {
254 struct qreg r = qir_RCP(c, x);
255
256 /* Apply a Newton-Raphson step to improve the accuracy. */
257 r = qir_FMUL(c, r, qir_FSUB(c,
258 qir_uniform_f(c, 2.0),
259 qir_FMUL(c, x, r)));
260
261 return r;
262 }
263
264 static struct qreg
265 ntq_rsq(struct vc4_compile *c, struct qreg x)
266 {
267 struct qreg r = qir_RSQ(c, x);
268
269 /* Apply a Newton-Raphson step to improve the accuracy. */
270 r = qir_FMUL(c, r, qir_FSUB(c,
271 qir_uniform_f(c, 1.5),
272 qir_FMUL(c,
273 qir_uniform_f(c, 0.5),
274 qir_FMUL(c, x,
275 qir_FMUL(c, r, r)))));
276
277 return r;
278 }
279
280 static struct qreg
281 ntq_umul(struct vc4_compile *c, struct qreg src0, struct qreg src1)
282 {
283 struct qreg src0_hi = qir_SHR(c, src0,
284 qir_uniform_ui(c, 24));
285 struct qreg src1_hi = qir_SHR(c, src1,
286 qir_uniform_ui(c, 24));
287
288 struct qreg hilo = qir_MUL24(c, src0_hi, src1);
289 struct qreg lohi = qir_MUL24(c, src0, src1_hi);
290 struct qreg lolo = qir_MUL24(c, src0, src1);
291
292 return qir_ADD(c, lolo, qir_SHL(c,
293 qir_ADD(c, hilo, lohi),
294 qir_uniform_ui(c, 24)));
295 }
296
297 static struct qreg
298 ntq_scale_depth_texture(struct vc4_compile *c, struct qreg src)
299 {
300 struct qreg depthf = qir_ITOF(c, qir_SHR(c, src,
301 qir_uniform_ui(c, 8)));
302 return qir_FMUL(c, depthf, qir_uniform_f(c, 1.0f/0xffffff));
303 }
304
305 /**
306 * Emits a lowered TXF_MS from an MSAA texture.
307 *
308 * The addressing math has been lowered in NIR, and now we just need to read
309 * it like a UBO.
310 */
311 static void
312 ntq_emit_txf(struct vc4_compile *c, nir_tex_instr *instr)
313 {
314 uint32_t tile_width = 32;
315 uint32_t tile_height = 32;
316 uint32_t tile_size = (tile_height * tile_width *
317 VC4_MAX_SAMPLES * sizeof(uint32_t));
318
319 unsigned unit = instr->texture_index;
320 uint32_t w = align(c->key->tex[unit].msaa_width, tile_width);
321 uint32_t w_tiles = w / tile_width;
322 uint32_t h = align(c->key->tex[unit].msaa_height, tile_height);
323 uint32_t h_tiles = h / tile_height;
324 uint32_t size = w_tiles * h_tiles * tile_size;
325
326 struct qreg addr;
327 assert(instr->num_srcs == 1);
328 assert(instr->src[0].src_type == nir_tex_src_coord);
329 addr = ntq_get_src(c, instr->src[0].src, 0);
330
331 /* Perform the clamping required by kernel validation. */
332 addr = qir_MAX(c, addr, qir_uniform_ui(c, 0));
333 addr = qir_MIN(c, addr, qir_uniform_ui(c, size - 4));
334
335 qir_TEX_DIRECT(c, addr, qir_uniform(c, QUNIFORM_TEXTURE_MSAA_ADDR, unit));
336
337 struct qreg tex = qir_TEX_RESULT(c);
338 c->num_texture_samples++;
339
340 struct qreg dest[4];
341 enum pipe_format format = c->key->tex[unit].format;
342 if (util_format_is_depth_or_stencil(format)) {
343 struct qreg scaled = ntq_scale_depth_texture(c, tex);
344 for (int i = 0; i < 4; i++)
345 dest[i] = scaled;
346 } else {
347 for (int i = 0; i < 4; i++)
348 dest[i] = qir_UNPACK_8_F(c, tex, i);
349 }
350
351 for (int i = 0; i < 4; i++)
352 ntq_store_dest(c, &instr->dest, i, dest[i]);
353 }
354
355 static void
356 ntq_emit_tex(struct vc4_compile *c, nir_tex_instr *instr)
357 {
358 struct qreg s, t, r, lod, compare;
359 bool is_txb = false, is_txl = false;
360 unsigned unit = instr->texture_index;
361
362 if (instr->op == nir_texop_txf) {
363 ntq_emit_txf(c, instr);
364 return;
365 }
366
367 for (unsigned i = 0; i < instr->num_srcs; i++) {
368 switch (instr->src[i].src_type) {
369 case nir_tex_src_coord:
370 s = ntq_get_src(c, instr->src[i].src, 0);
371 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D)
372 t = qir_uniform_f(c, 0.5);
373 else
374 t = ntq_get_src(c, instr->src[i].src, 1);
375 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
376 r = ntq_get_src(c, instr->src[i].src, 2);
377 break;
378 case nir_tex_src_bias:
379 lod = ntq_get_src(c, instr->src[i].src, 0);
380 is_txb = true;
381 break;
382 case nir_tex_src_lod:
383 lod = ntq_get_src(c, instr->src[i].src, 0);
384 is_txl = true;
385 break;
386 case nir_tex_src_comparitor:
387 compare = ntq_get_src(c, instr->src[i].src, 0);
388 break;
389 default:
390 unreachable("unknown texture source");
391 }
392 }
393
394 struct qreg texture_u[] = {
395 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit),
396 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
397 qir_uniform(c, QUNIFORM_CONSTANT, 0),
398 qir_uniform(c, QUNIFORM_CONSTANT, 0),
399 };
400 uint32_t next_texture_u = 0;
401
402 /* There is no native support for GL texture rectangle coordinates, so
403 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
404 * 1]).
405 */
406 if (instr->sampler_dim == GLSL_SAMPLER_DIM_RECT) {
407 s = qir_FMUL(c, s,
408 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_X, unit));
409 t = qir_FMUL(c, t,
410 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_Y, unit));
411 }
412
413 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE || is_txl) {
414 texture_u[2] = qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P2,
415 unit | (is_txl << 16));
416 }
417
418 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
419 qir_TEX_R(c, r, texture_u[next_texture_u++]);
420 } else if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
421 c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP ||
422 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
423 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
424 qir_TEX_R(c, qir_uniform(c, QUNIFORM_TEXTURE_BORDER_COLOR, unit),
425 texture_u[next_texture_u++]);
426 }
427
428 if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP) {
429 s = qir_SAT(c, s);
430 }
431
432 if (c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
433 t = qir_SAT(c, t);
434 }
435
436 qir_TEX_T(c, t, texture_u[next_texture_u++]);
437
438 if (is_txl || is_txb)
439 qir_TEX_B(c, lod, texture_u[next_texture_u++]);
440
441 qir_TEX_S(c, s, texture_u[next_texture_u++]);
442
443 c->num_texture_samples++;
444 struct qreg tex = qir_TEX_RESULT(c);
445
446 enum pipe_format format = c->key->tex[unit].format;
447
448 struct qreg *dest = ntq_get_dest(c, &instr->dest);
449 if (util_format_is_depth_or_stencil(format)) {
450 struct qreg normalized = ntq_scale_depth_texture(c, tex);
451 struct qreg depth_output;
452
453 struct qreg u0 = qir_uniform_f(c, 0.0f);
454 struct qreg u1 = qir_uniform_f(c, 1.0f);
455 if (c->key->tex[unit].compare_mode) {
456 switch (c->key->tex[unit].compare_func) {
457 case PIPE_FUNC_NEVER:
458 depth_output = qir_uniform_f(c, 0.0f);
459 break;
460 case PIPE_FUNC_ALWAYS:
461 depth_output = u1;
462 break;
463 case PIPE_FUNC_EQUAL:
464 qir_SF(c, qir_FSUB(c, compare, normalized));
465 depth_output = qir_SEL(c, QPU_COND_ZS, u1, u0);
466 break;
467 case PIPE_FUNC_NOTEQUAL:
468 qir_SF(c, qir_FSUB(c, compare, normalized));
469 depth_output = qir_SEL(c, QPU_COND_ZC, u1, u0);
470 break;
471 case PIPE_FUNC_GREATER:
472 qir_SF(c, qir_FSUB(c, compare, normalized));
473 depth_output = qir_SEL(c, QPU_COND_NC, u1, u0);
474 break;
475 case PIPE_FUNC_GEQUAL:
476 qir_SF(c, qir_FSUB(c, normalized, compare));
477 depth_output = qir_SEL(c, QPU_COND_NS, u1, u0);
478 break;
479 case PIPE_FUNC_LESS:
480 qir_SF(c, qir_FSUB(c, compare, normalized));
481 depth_output = qir_SEL(c, QPU_COND_NS, u1, u0);
482 break;
483 case PIPE_FUNC_LEQUAL:
484 qir_SF(c, qir_FSUB(c, normalized, compare));
485 depth_output = qir_SEL(c, QPU_COND_NC, u1, u0);
486 break;
487 }
488 } else {
489 depth_output = normalized;
490 }
491
492 for (int i = 0; i < 4; i++)
493 dest[i] = depth_output;
494 } else {
495 for (int i = 0; i < 4; i++)
496 dest[i] = qir_UNPACK_8_F(c, tex, i);
497 }
498 }
499
500 /**
501 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
502 * to zero).
503 */
504 static struct qreg
505 ntq_ffract(struct vc4_compile *c, struct qreg src)
506 {
507 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
508 struct qreg diff = qir_FSUB(c, src, trunc);
509 qir_SF(c, diff);
510 return qir_SEL(c, QPU_COND_NS,
511 qir_FADD(c, diff, qir_uniform_f(c, 1.0)), diff);
512 }
513
514 /**
515 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
516 * zero).
517 */
518 static struct qreg
519 ntq_ffloor(struct vc4_compile *c, struct qreg src)
520 {
521 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
522
523 /* This will be < 0 if we truncated and the truncation was of a value
524 * that was < 0 in the first place.
525 */
526 qir_SF(c, qir_FSUB(c, src, trunc));
527
528 return qir_SEL(c, QPU_COND_NS,
529 qir_FSUB(c, trunc, qir_uniform_f(c, 1.0)), trunc);
530 }
531
532 /**
533 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
534 * zero).
535 */
536 static struct qreg
537 ntq_fceil(struct vc4_compile *c, struct qreg src)
538 {
539 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
540
541 /* This will be < 0 if we truncated and the truncation was of a value
542 * that was > 0 in the first place.
543 */
544 qir_SF(c, qir_FSUB(c, trunc, src));
545
546 return qir_SEL(c, QPU_COND_NS,
547 qir_FADD(c, trunc, qir_uniform_f(c, 1.0)), trunc);
548 }
549
550 static struct qreg
551 ntq_fsin(struct vc4_compile *c, struct qreg src)
552 {
553 float coeff[] = {
554 -2.0 * M_PI,
555 pow(2.0 * M_PI, 3) / (3 * 2 * 1),
556 -pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
557 pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
558 -pow(2.0 * M_PI, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
559 };
560
561 struct qreg scaled_x =
562 qir_FMUL(c,
563 src,
564 qir_uniform_f(c, 1.0 / (M_PI * 2.0)));
565
566 struct qreg x = qir_FADD(c,
567 ntq_ffract(c, scaled_x),
568 qir_uniform_f(c, -0.5));
569 struct qreg x2 = qir_FMUL(c, x, x);
570 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
571 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
572 x = qir_FMUL(c, x, x2);
573 sum = qir_FADD(c,
574 sum,
575 qir_FMUL(c,
576 x,
577 qir_uniform_f(c, coeff[i])));
578 }
579 return sum;
580 }
581
582 static struct qreg
583 ntq_fcos(struct vc4_compile *c, struct qreg src)
584 {
585 float coeff[] = {
586 -1.0f,
587 pow(2.0 * M_PI, 2) / (2 * 1),
588 -pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
589 pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
590 -pow(2.0 * M_PI, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
591 pow(2.0 * M_PI, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
592 };
593
594 struct qreg scaled_x =
595 qir_FMUL(c, src,
596 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
597 struct qreg x_frac = qir_FADD(c,
598 ntq_ffract(c, scaled_x),
599 qir_uniform_f(c, -0.5));
600
601 struct qreg sum = qir_uniform_f(c, coeff[0]);
602 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
603 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
604 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
605 if (i != 1)
606 x = qir_FMUL(c, x, x2);
607
608 struct qreg mul = qir_FMUL(c,
609 x,
610 qir_uniform_f(c, coeff[i]));
611 if (i == 0)
612 sum = mul;
613 else
614 sum = qir_FADD(c, sum, mul);
615 }
616 return sum;
617 }
618
619 static struct qreg
620 ntq_fsign(struct vc4_compile *c, struct qreg src)
621 {
622 struct qreg t = qir_get_temp(c);
623
624 qir_SF(c, src);
625 qir_MOV_dest(c, t, qir_uniform_f(c, 0.0));
626 qir_MOV_dest(c, t, qir_uniform_f(c, 1.0))->cond = QPU_COND_ZC;
627 qir_MOV_dest(c, t, qir_uniform_f(c, -1.0))->cond = QPU_COND_NS;
628 return t;
629 }
630
631 static void
632 emit_vertex_input(struct vc4_compile *c, int attr)
633 {
634 enum pipe_format format = c->vs_key->attr_formats[attr];
635 uint32_t attr_size = util_format_get_blocksize(format);
636
637 c->vattr_sizes[attr] = align(attr_size, 4);
638 for (int i = 0; i < align(attr_size, 4) / 4; i++) {
639 c->inputs[attr * 4 + i] =
640 qir_MOV(c, qir_reg(QFILE_VPM, attr * 4 + i));
641 c->num_inputs++;
642 }
643 }
644
645 static void
646 emit_fragcoord_input(struct vc4_compile *c, int attr)
647 {
648 c->inputs[attr * 4 + 0] = qir_ITOF(c, qir_reg(QFILE_FRAG_X, 0));
649 c->inputs[attr * 4 + 1] = qir_ITOF(c, qir_reg(QFILE_FRAG_Y, 0));
650 c->inputs[attr * 4 + 2] =
651 qir_FMUL(c,
652 qir_ITOF(c, qir_FRAG_Z(c)),
653 qir_uniform_f(c, 1.0 / 0xffffff));
654 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
655 }
656
657 static struct qreg
658 emit_fragment_varying(struct vc4_compile *c, gl_varying_slot slot,
659 uint8_t swizzle)
660 {
661 uint32_t i = c->num_input_slots++;
662 struct qreg vary = {
663 QFILE_VARY,
664 i
665 };
666
667 if (c->num_input_slots >= c->input_slots_array_size) {
668 c->input_slots_array_size =
669 MAX2(4, c->input_slots_array_size * 2);
670
671 c->input_slots = reralloc(c, c->input_slots,
672 struct vc4_varying_slot,
673 c->input_slots_array_size);
674 }
675
676 c->input_slots[i].slot = slot;
677 c->input_slots[i].swizzle = swizzle;
678
679 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
680 }
681
682 static void
683 emit_fragment_input(struct vc4_compile *c, int attr, gl_varying_slot slot)
684 {
685 for (int i = 0; i < 4; i++) {
686 c->inputs[attr * 4 + i] =
687 emit_fragment_varying(c, slot, i);
688 c->num_inputs++;
689 }
690 }
691
692 static void
693 add_output(struct vc4_compile *c,
694 uint32_t decl_offset,
695 uint8_t slot,
696 uint8_t swizzle)
697 {
698 uint32_t old_array_size = c->outputs_array_size;
699 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
700 decl_offset + 1);
701
702 if (old_array_size != c->outputs_array_size) {
703 c->output_slots = reralloc(c,
704 c->output_slots,
705 struct vc4_varying_slot,
706 c->outputs_array_size);
707 }
708
709 c->output_slots[decl_offset].slot = slot;
710 c->output_slots[decl_offset].swizzle = swizzle;
711 }
712
713 static void
714 declare_uniform_range(struct vc4_compile *c, uint32_t start, uint32_t size)
715 {
716 unsigned array_id = c->num_uniform_ranges++;
717 if (array_id >= c->ubo_ranges_array_size) {
718 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
719 array_id + 1);
720 c->ubo_ranges = reralloc(c, c->ubo_ranges,
721 struct vc4_compiler_ubo_range,
722 c->ubo_ranges_array_size);
723 }
724
725 c->ubo_ranges[array_id].dst_offset = 0;
726 c->ubo_ranges[array_id].src_offset = start;
727 c->ubo_ranges[array_id].size = size;
728 c->ubo_ranges[array_id].used = false;
729 }
730
731 static bool
732 ntq_src_is_only_ssa_def_user(nir_src *src)
733 {
734 if (!src->is_ssa)
735 return false;
736
737 if (!list_empty(&src->ssa->if_uses))
738 return false;
739
740 return (src->ssa->uses.next == &src->use_link &&
741 src->ssa->uses.next->next == &src->ssa->uses);
742 }
743
744 /**
745 * In general, emits a nir_pack_unorm_4x8 as a series of MOVs with the pack
746 * bit set.
747 *
748 * However, as an optimization, it tries to find the instructions generating
749 * the sources to be packed and just emit the pack flag there, if possible.
750 */
751 static void
752 ntq_emit_pack_unorm_4x8(struct vc4_compile *c, nir_alu_instr *instr)
753 {
754 struct qreg result = qir_get_temp(c);
755 struct nir_alu_instr *vec4 = NULL;
756
757 /* If packing from a vec4 op (as expected), identify it so that we can
758 * peek back at what generated its sources.
759 */
760 if (instr->src[0].src.is_ssa &&
761 instr->src[0].src.ssa->parent_instr->type == nir_instr_type_alu &&
762 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr)->op ==
763 nir_op_vec4) {
764 vec4 = nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
765 }
766
767 /* If the pack is replicating the same channel 4 times, use the 8888
768 * pack flag. This is common for blending using the alpha
769 * channel.
770 */
771 if (instr->src[0].swizzle[0] == instr->src[0].swizzle[1] &&
772 instr->src[0].swizzle[0] == instr->src[0].swizzle[2] &&
773 instr->src[0].swizzle[0] == instr->src[0].swizzle[3]) {
774 struct qreg rep = ntq_get_src(c,
775 instr->src[0].src,
776 instr->src[0].swizzle[0]);
777 ntq_store_dest(c, &instr->dest.dest, 0, qir_PACK_8888_F(c, rep));
778 return;
779 }
780
781 for (int i = 0; i < 4; i++) {
782 int swiz = instr->src[0].swizzle[i];
783 struct qreg src;
784 if (vec4) {
785 src = ntq_get_src(c, vec4->src[swiz].src,
786 vec4->src[swiz].swizzle[0]);
787 } else {
788 src = ntq_get_src(c, instr->src[0].src, swiz);
789 }
790
791 if (vec4 &&
792 ntq_src_is_only_ssa_def_user(&vec4->src[swiz].src) &&
793 src.file == QFILE_TEMP &&
794 c->defs[src.index] &&
795 qir_is_mul(c->defs[src.index]) &&
796 !c->defs[src.index]->dst.pack) {
797 struct qinst *rewrite = c->defs[src.index];
798 c->defs[src.index] = NULL;
799 rewrite->dst = result;
800 rewrite->dst.pack = QPU_PACK_MUL_8A + i;
801 continue;
802 }
803
804 qir_PACK_8_F(c, result, src, i);
805 }
806
807 ntq_store_dest(c, &instr->dest.dest, 0, result);
808 }
809
810 /** Handles sign-extended bitfield extracts for 16 bits. */
811 static struct qreg
812 ntq_emit_ibfe(struct vc4_compile *c, struct qreg base, struct qreg offset,
813 struct qreg bits)
814 {
815 assert(bits.file == QFILE_UNIF &&
816 c->uniform_contents[bits.index] == QUNIFORM_CONSTANT &&
817 c->uniform_data[bits.index] == 16);
818
819 assert(offset.file == QFILE_UNIF &&
820 c->uniform_contents[offset.index] == QUNIFORM_CONSTANT);
821 int offset_bit = c->uniform_data[offset.index];
822 assert(offset_bit % 16 == 0);
823
824 return qir_UNPACK_16_I(c, base, offset_bit / 16);
825 }
826
827 /** Handles unsigned bitfield extracts for 8 bits. */
828 static struct qreg
829 ntq_emit_ubfe(struct vc4_compile *c, struct qreg base, struct qreg offset,
830 struct qreg bits)
831 {
832 assert(bits.file == QFILE_UNIF &&
833 c->uniform_contents[bits.index] == QUNIFORM_CONSTANT &&
834 c->uniform_data[bits.index] == 8);
835
836 assert(offset.file == QFILE_UNIF &&
837 c->uniform_contents[offset.index] == QUNIFORM_CONSTANT);
838 int offset_bit = c->uniform_data[offset.index];
839 assert(offset_bit % 8 == 0);
840
841 return qir_UNPACK_8_I(c, base, offset_bit / 8);
842 }
843
844 /**
845 * If compare_instr is a valid comparison instruction, emits the
846 * compare_instr's comparison and returns the sel_instr's return value based
847 * on the compare_instr's result.
848 */
849 static bool
850 ntq_emit_comparison(struct vc4_compile *c, struct qreg *dest,
851 nir_alu_instr *compare_instr,
852 nir_alu_instr *sel_instr)
853 {
854 enum qpu_cond cond;
855
856 switch (compare_instr->op) {
857 case nir_op_feq:
858 case nir_op_ieq:
859 case nir_op_seq:
860 cond = QPU_COND_ZS;
861 break;
862 case nir_op_fne:
863 case nir_op_ine:
864 case nir_op_sne:
865 cond = QPU_COND_ZC;
866 break;
867 case nir_op_fge:
868 case nir_op_ige:
869 case nir_op_uge:
870 case nir_op_sge:
871 cond = QPU_COND_NC;
872 break;
873 case nir_op_flt:
874 case nir_op_ilt:
875 case nir_op_slt:
876 cond = QPU_COND_NS;
877 break;
878 default:
879 return false;
880 }
881
882 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
883 struct qreg src1 = ntq_get_alu_src(c, compare_instr, 1);
884
885 unsigned unsized_type =
886 nir_alu_type_get_base_type(nir_op_infos[compare_instr->op].input_types[0]);
887 if (unsized_type == nir_type_float)
888 qir_SF(c, qir_FSUB(c, src0, src1));
889 else
890 qir_SF(c, qir_SUB(c, src0, src1));
891
892 switch (sel_instr->op) {
893 case nir_op_seq:
894 case nir_op_sne:
895 case nir_op_sge:
896 case nir_op_slt:
897 *dest = qir_SEL(c, cond,
898 qir_uniform_f(c, 1.0), qir_uniform_f(c, 0.0));
899 break;
900
901 case nir_op_bcsel:
902 *dest = qir_SEL(c, cond,
903 ntq_get_alu_src(c, sel_instr, 1),
904 ntq_get_alu_src(c, sel_instr, 2));
905 break;
906
907 default:
908 *dest = qir_SEL(c, cond,
909 qir_uniform_ui(c, ~0), qir_uniform_ui(c, 0));
910 break;
911 }
912
913 return true;
914 }
915
916 /**
917 * Attempts to fold a comparison generating a boolean result into the
918 * condition code for selecting between two values, instead of comparing the
919 * boolean result against 0 to generate the condition code.
920 */
921 static struct qreg ntq_emit_bcsel(struct vc4_compile *c, nir_alu_instr *instr,
922 struct qreg *src)
923 {
924 if (!instr->src[0].src.is_ssa)
925 goto out;
926 nir_alu_instr *compare =
927 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
928 if (!compare)
929 goto out;
930
931 struct qreg dest;
932 if (ntq_emit_comparison(c, &dest, compare, instr))
933 return dest;
934
935 out:
936 qir_SF(c, src[0]);
937 return qir_SEL(c, QPU_COND_NS, src[1], src[2]);
938 }
939
940 static void
941 ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr)
942 {
943 /* This should always be lowered to ALU operations for VC4. */
944 assert(!instr->dest.saturate);
945
946 /* Vectors are special in that they have non-scalarized writemasks,
947 * and just take the first swizzle channel for each argument in order
948 * into each writemask channel.
949 */
950 if (instr->op == nir_op_vec2 ||
951 instr->op == nir_op_vec3 ||
952 instr->op == nir_op_vec4) {
953 struct qreg srcs[4];
954 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
955 srcs[i] = ntq_get_src(c, instr->src[i].src,
956 instr->src[i].swizzle[0]);
957 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
958 ntq_store_dest(c, &instr->dest.dest, i, srcs[i]);
959 return;
960 }
961
962 if (instr->op == nir_op_pack_unorm_4x8) {
963 ntq_emit_pack_unorm_4x8(c, instr);
964 return;
965 }
966
967 if (instr->op == nir_op_unpack_unorm_4x8) {
968 struct qreg src = ntq_get_src(c, instr->src[0].src,
969 instr->src[0].swizzle[0]);
970 for (int i = 0; i < 4; i++) {
971 if (instr->dest.write_mask & (1 << i))
972 ntq_store_dest(c, &instr->dest.dest, i,
973 qir_UNPACK_8_F(c, src, i));
974 }
975 return;
976 }
977
978 /* General case: We can just grab the one used channel per src. */
979 struct qreg src[nir_op_infos[instr->op].num_inputs];
980 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
981 src[i] = ntq_get_alu_src(c, instr, i);
982 }
983
984 struct qreg result;
985
986 switch (instr->op) {
987 case nir_op_fmov:
988 case nir_op_imov:
989 result = qir_MOV(c, src[0]);
990 break;
991 case nir_op_fmul:
992 result = qir_FMUL(c, src[0], src[1]);
993 break;
994 case nir_op_fadd:
995 result = qir_FADD(c, src[0], src[1]);
996 break;
997 case nir_op_fsub:
998 result = qir_FSUB(c, src[0], src[1]);
999 break;
1000 case nir_op_fmin:
1001 result = qir_FMIN(c, src[0], src[1]);
1002 break;
1003 case nir_op_fmax:
1004 result = qir_FMAX(c, src[0], src[1]);
1005 break;
1006
1007 case nir_op_f2i:
1008 case nir_op_f2u:
1009 result = qir_FTOI(c, src[0]);
1010 break;
1011 case nir_op_i2f:
1012 case nir_op_u2f:
1013 result = qir_ITOF(c, src[0]);
1014 break;
1015 case nir_op_b2f:
1016 result = qir_AND(c, src[0], qir_uniform_f(c, 1.0));
1017 break;
1018 case nir_op_b2i:
1019 result = qir_AND(c, src[0], qir_uniform_ui(c, 1));
1020 break;
1021 case nir_op_i2b:
1022 case nir_op_f2b:
1023 qir_SF(c, src[0]);
1024 result = qir_SEL(c, QPU_COND_ZC,
1025 qir_uniform_ui(c, ~0),
1026 qir_uniform_ui(c, 0));
1027 break;
1028
1029 case nir_op_iadd:
1030 result = qir_ADD(c, src[0], src[1]);
1031 break;
1032 case nir_op_ushr:
1033 result = qir_SHR(c, src[0], src[1]);
1034 break;
1035 case nir_op_isub:
1036 result = qir_SUB(c, src[0], src[1]);
1037 break;
1038 case nir_op_ishr:
1039 result = qir_ASR(c, src[0], src[1]);
1040 break;
1041 case nir_op_ishl:
1042 result = qir_SHL(c, src[0], src[1]);
1043 break;
1044 case nir_op_imin:
1045 result = qir_MIN(c, src[0], src[1]);
1046 break;
1047 case nir_op_imax:
1048 result = qir_MAX(c, src[0], src[1]);
1049 break;
1050 case nir_op_iand:
1051 result = qir_AND(c, src[0], src[1]);
1052 break;
1053 case nir_op_ior:
1054 result = qir_OR(c, src[0], src[1]);
1055 break;
1056 case nir_op_ixor:
1057 result = qir_XOR(c, src[0], src[1]);
1058 break;
1059 case nir_op_inot:
1060 result = qir_NOT(c, src[0]);
1061 break;
1062
1063 case nir_op_imul:
1064 result = ntq_umul(c, src[0], src[1]);
1065 break;
1066
1067 case nir_op_seq:
1068 case nir_op_sne:
1069 case nir_op_sge:
1070 case nir_op_slt:
1071 case nir_op_feq:
1072 case nir_op_fne:
1073 case nir_op_fge:
1074 case nir_op_flt:
1075 case nir_op_ieq:
1076 case nir_op_ine:
1077 case nir_op_ige:
1078 case nir_op_uge:
1079 case nir_op_ilt:
1080 if (!ntq_emit_comparison(c, &result, instr, instr)) {
1081 fprintf(stderr, "Bad comparison instruction\n");
1082 }
1083 break;
1084
1085 case nir_op_bcsel:
1086 result = ntq_emit_bcsel(c, instr, src);
1087 break;
1088 case nir_op_fcsel:
1089 qir_SF(c, src[0]);
1090 result = qir_SEL(c, QPU_COND_ZC, src[1], src[2]);
1091 break;
1092
1093 case nir_op_frcp:
1094 result = ntq_rcp(c, src[0]);
1095 break;
1096 case nir_op_frsq:
1097 result = ntq_rsq(c, src[0]);
1098 break;
1099 case nir_op_fexp2:
1100 result = qir_EXP2(c, src[0]);
1101 break;
1102 case nir_op_flog2:
1103 result = qir_LOG2(c, src[0]);
1104 break;
1105
1106 case nir_op_ftrunc:
1107 result = qir_ITOF(c, qir_FTOI(c, src[0]));
1108 break;
1109 case nir_op_fceil:
1110 result = ntq_fceil(c, src[0]);
1111 break;
1112 case nir_op_ffract:
1113 result = ntq_ffract(c, src[0]);
1114 break;
1115 case nir_op_ffloor:
1116 result = ntq_ffloor(c, src[0]);
1117 break;
1118
1119 case nir_op_fsin:
1120 result = ntq_fsin(c, src[0]);
1121 break;
1122 case nir_op_fcos:
1123 result = ntq_fcos(c, src[0]);
1124 break;
1125
1126 case nir_op_fsign:
1127 result = ntq_fsign(c, src[0]);
1128 break;
1129
1130 case nir_op_fabs:
1131 result = qir_FMAXABS(c, src[0], src[0]);
1132 break;
1133 case nir_op_iabs:
1134 result = qir_MAX(c, src[0],
1135 qir_SUB(c, qir_uniform_ui(c, 0), src[0]));
1136 break;
1137
1138 case nir_op_ibitfield_extract:
1139 result = ntq_emit_ibfe(c, src[0], src[1], src[2]);
1140 break;
1141
1142 case nir_op_ubitfield_extract:
1143 result = ntq_emit_ubfe(c, src[0], src[1], src[2]);
1144 break;
1145
1146 case nir_op_usadd_4x8:
1147 result = qir_V8ADDS(c, src[0], src[1]);
1148 break;
1149
1150 case nir_op_ussub_4x8:
1151 result = qir_V8SUBS(c, src[0], src[1]);
1152 break;
1153
1154 case nir_op_umin_4x8:
1155 result = qir_V8MIN(c, src[0], src[1]);
1156 break;
1157
1158 case nir_op_umax_4x8:
1159 result = qir_V8MAX(c, src[0], src[1]);
1160 break;
1161
1162 case nir_op_umul_unorm_4x8:
1163 result = qir_V8MULD(c, src[0], src[1]);
1164 break;
1165
1166 default:
1167 fprintf(stderr, "unknown NIR ALU inst: ");
1168 nir_print_instr(&instr->instr, stderr);
1169 fprintf(stderr, "\n");
1170 abort();
1171 }
1172
1173 /* We have a scalar result, so the instruction should only have a
1174 * single channel written to.
1175 */
1176 assert(util_is_power_of_two(instr->dest.write_mask));
1177 ntq_store_dest(c, &instr->dest.dest,
1178 ffs(instr->dest.write_mask) - 1, result);
1179 }
1180
1181 static void
1182 emit_frag_end(struct vc4_compile *c)
1183 {
1184 struct qreg color;
1185 if (c->output_color_index != -1) {
1186 color = c->outputs[c->output_color_index];
1187 } else {
1188 color = qir_uniform_ui(c, 0);
1189 }
1190
1191 uint32_t discard_cond = QPU_COND_ALWAYS;
1192 if (c->discard.file != QFILE_NULL) {
1193 qir_SF(c, c->discard);
1194 discard_cond = QPU_COND_ZS;
1195 }
1196
1197 if (c->fs_key->stencil_enabled) {
1198 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1199 qir_uniform(c, QUNIFORM_STENCIL, 0));
1200 if (c->fs_key->stencil_twoside) {
1201 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1202 qir_uniform(c, QUNIFORM_STENCIL, 1));
1203 }
1204 if (c->fs_key->stencil_full_writemasks) {
1205 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1206 qir_uniform(c, QUNIFORM_STENCIL, 2));
1207 }
1208 }
1209
1210 if (c->output_sample_mask_index != -1) {
1211 qir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1212 }
1213
1214 if (c->fs_key->depth_enabled) {
1215 if (c->output_position_index != -1) {
1216 qir_FTOI_dest(c, qir_reg(QFILE_TLB_Z_WRITE, 0),
1217 qir_FMUL(c,
1218 c->outputs[c->output_position_index + 2],
1219 qir_uniform_f(c, 0xffffff)))->cond = discard_cond;
1220 } else {
1221 qir_MOV_dest(c, qir_reg(QFILE_TLB_Z_WRITE, 0),
1222 qir_FRAG_Z(c))->cond = discard_cond;
1223 }
1224 }
1225
1226 if (!c->msaa_per_sample_output) {
1227 qir_MOV_dest(c, qir_reg(QFILE_TLB_COLOR_WRITE, 0),
1228 color)->cond = discard_cond;
1229 } else {
1230 for (int i = 0; i < VC4_MAX_SAMPLES; i++) {
1231 qir_MOV_dest(c, qir_reg(QFILE_TLB_COLOR_WRITE_MS, 0),
1232 c->sample_colors[i])->cond = discard_cond;
1233 }
1234 }
1235 }
1236
1237 static void
1238 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1239 {
1240 struct qreg packed = qir_get_temp(c);
1241
1242 for (int i = 0; i < 2; i++) {
1243 struct qreg scale =
1244 qir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1245
1246 struct qreg packed_chan = packed;
1247 packed_chan.pack = QPU_PACK_A_16A + i;
1248
1249 qir_FTOI_dest(c, packed_chan,
1250 qir_FMUL(c,
1251 qir_FMUL(c,
1252 c->outputs[c->output_position_index + i],
1253 scale),
1254 rcp_w));
1255 }
1256
1257 qir_VPM_WRITE(c, packed);
1258 }
1259
1260 static void
1261 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1262 {
1263 struct qreg zscale = qir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1264 struct qreg zoffset = qir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1265
1266 qir_VPM_WRITE(c, qir_FADD(c, qir_FMUL(c, qir_FMUL(c,
1267 c->outputs[c->output_position_index + 2],
1268 zscale),
1269 rcp_w),
1270 zoffset));
1271 }
1272
1273 static void
1274 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1275 {
1276 qir_VPM_WRITE(c, rcp_w);
1277 }
1278
1279 static void
1280 emit_point_size_write(struct vc4_compile *c)
1281 {
1282 struct qreg point_size;
1283
1284 if (c->output_point_size_index != -1)
1285 point_size = c->outputs[c->output_point_size_index];
1286 else
1287 point_size = qir_uniform_f(c, 1.0);
1288
1289 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1290 * BCM21553).
1291 */
1292 point_size = qir_FMAX(c, point_size, qir_uniform_f(c, .125));
1293
1294 qir_VPM_WRITE(c, point_size);
1295 }
1296
1297 /**
1298 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1299 *
1300 * The simulator insists that there be at least one vertex attribute, so
1301 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also
1302 * insists that all vertex attributes loaded get read by the VS/CS, so we have
1303 * to consume it here.
1304 */
1305 static void
1306 emit_stub_vpm_read(struct vc4_compile *c)
1307 {
1308 if (c->num_inputs)
1309 return;
1310
1311 c->vattr_sizes[0] = 4;
1312 (void)qir_MOV(c, qir_reg(QFILE_VPM, 0));
1313 c->num_inputs++;
1314 }
1315
1316 static void
1317 emit_vert_end(struct vc4_compile *c,
1318 struct vc4_varying_slot *fs_inputs,
1319 uint32_t num_fs_inputs)
1320 {
1321 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1322
1323 emit_stub_vpm_read(c);
1324
1325 emit_scaled_viewport_write(c, rcp_w);
1326 emit_zs_write(c, rcp_w);
1327 emit_rcp_wc_write(c, rcp_w);
1328 if (c->vs_key->per_vertex_point_size)
1329 emit_point_size_write(c);
1330
1331 for (int i = 0; i < num_fs_inputs; i++) {
1332 struct vc4_varying_slot *input = &fs_inputs[i];
1333 int j;
1334
1335 for (j = 0; j < c->num_outputs; j++) {
1336 struct vc4_varying_slot *output =
1337 &c->output_slots[j];
1338
1339 if (input->slot == output->slot &&
1340 input->swizzle == output->swizzle) {
1341 qir_VPM_WRITE(c, c->outputs[j]);
1342 break;
1343 }
1344 }
1345 /* Emit padding if we didn't find a declared VS output for
1346 * this FS input.
1347 */
1348 if (j == c->num_outputs)
1349 qir_VPM_WRITE(c, qir_uniform_f(c, 0.0));
1350 }
1351 }
1352
1353 static void
1354 emit_coord_end(struct vc4_compile *c)
1355 {
1356 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1357
1358 emit_stub_vpm_read(c);
1359
1360 for (int i = 0; i < 4; i++)
1361 qir_VPM_WRITE(c, c->outputs[c->output_position_index + i]);
1362
1363 emit_scaled_viewport_write(c, rcp_w);
1364 emit_zs_write(c, rcp_w);
1365 emit_rcp_wc_write(c, rcp_w);
1366 if (c->vs_key->per_vertex_point_size)
1367 emit_point_size_write(c);
1368 }
1369
1370 static void
1371 vc4_optimize_nir(struct nir_shader *s)
1372 {
1373 bool progress;
1374
1375 do {
1376 progress = false;
1377
1378 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1379 NIR_PASS_V(s, nir_lower_alu_to_scalar);
1380 NIR_PASS_V(s, nir_lower_phis_to_scalar);
1381
1382 NIR_PASS(progress, s, nir_copy_prop);
1383 NIR_PASS(progress, s, nir_opt_remove_phis);
1384 NIR_PASS(progress, s, nir_opt_dce);
1385 NIR_PASS(progress, s, nir_opt_dead_cf);
1386 NIR_PASS(progress, s, nir_opt_cse);
1387 NIR_PASS(progress, s, nir_opt_peephole_select);
1388 NIR_PASS(progress, s, nir_opt_algebraic);
1389 NIR_PASS(progress, s, nir_opt_constant_folding);
1390 NIR_PASS(progress, s, nir_opt_undef);
1391 } while (progress);
1392 }
1393
1394 static int
1395 driver_location_compare(const void *in_a, const void *in_b)
1396 {
1397 const nir_variable *const *a = in_a;
1398 const nir_variable *const *b = in_b;
1399
1400 return (*a)->data.driver_location - (*b)->data.driver_location;
1401 }
1402
1403 static void
1404 ntq_setup_inputs(struct vc4_compile *c)
1405 {
1406 unsigned num_entries = 0;
1407 nir_foreach_variable(var, &c->s->inputs)
1408 num_entries++;
1409
1410 nir_variable *vars[num_entries];
1411
1412 unsigned i = 0;
1413 nir_foreach_variable(var, &c->s->inputs)
1414 vars[i++] = var;
1415
1416 /* Sort the variables so that we emit the input setup in
1417 * driver_location order. This is required for VPM reads, whose data
1418 * is fetched into the VPM in driver_location (TGSI register index)
1419 * order.
1420 */
1421 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1422
1423 for (unsigned i = 0; i < num_entries; i++) {
1424 nir_variable *var = vars[i];
1425 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1426 unsigned loc = var->data.driver_location;
1427
1428 assert(array_len == 1);
1429 (void)array_len;
1430 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1431 (loc + 1) * 4);
1432
1433 if (c->stage == QSTAGE_FRAG) {
1434 if (var->data.location == VARYING_SLOT_POS) {
1435 emit_fragcoord_input(c, loc);
1436 } else if (var->data.location >= VARYING_SLOT_VAR0 &&
1437 (c->fs_key->point_sprite_mask &
1438 (1 << (var->data.location -
1439 VARYING_SLOT_VAR0)))) {
1440 c->inputs[loc * 4 + 0] = c->point_x;
1441 c->inputs[loc * 4 + 1] = c->point_y;
1442 } else {
1443 emit_fragment_input(c, loc, var->data.location);
1444 }
1445 } else {
1446 emit_vertex_input(c, loc);
1447 }
1448 }
1449 }
1450
1451 static void
1452 ntq_setup_outputs(struct vc4_compile *c)
1453 {
1454 nir_foreach_variable(var, &c->s->outputs) {
1455 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1456 unsigned loc = var->data.driver_location * 4;
1457
1458 assert(array_len == 1);
1459 (void)array_len;
1460
1461 for (int i = 0; i < 4; i++)
1462 add_output(c, loc + i, var->data.location, i);
1463
1464 if (c->stage == QSTAGE_FRAG) {
1465 switch (var->data.location) {
1466 case FRAG_RESULT_COLOR:
1467 case FRAG_RESULT_DATA0:
1468 c->output_color_index = loc;
1469 break;
1470 case FRAG_RESULT_DEPTH:
1471 c->output_position_index = loc;
1472 break;
1473 case FRAG_RESULT_SAMPLE_MASK:
1474 c->output_sample_mask_index = loc;
1475 break;
1476 }
1477 } else {
1478 switch (var->data.location) {
1479 case VARYING_SLOT_POS:
1480 c->output_position_index = loc;
1481 break;
1482 case VARYING_SLOT_PSIZ:
1483 c->output_point_size_index = loc;
1484 break;
1485 }
1486 }
1487 }
1488 }
1489
1490 static void
1491 ntq_setup_uniforms(struct vc4_compile *c)
1492 {
1493 nir_foreach_variable(var, &c->s->uniforms) {
1494 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1495 unsigned array_elem_size = 4 * sizeof(float);
1496
1497 declare_uniform_range(c, var->data.driver_location * array_elem_size,
1498 array_len * array_elem_size);
1499
1500 }
1501 }
1502
1503 /**
1504 * Sets up the mapping from nir_register to struct qreg *.
1505 *
1506 * Each nir_register gets a struct qreg per 32-bit component being stored.
1507 */
1508 static void
1509 ntq_setup_registers(struct vc4_compile *c, struct exec_list *list)
1510 {
1511 foreach_list_typed(nir_register, nir_reg, node, list) {
1512 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1513 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1514 array_len *
1515 nir_reg->num_components);
1516
1517 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1518
1519 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1520 qregs[i] = qir_get_temp(c);
1521 }
1522 }
1523
1524 static void
1525 ntq_emit_load_const(struct vc4_compile *c, nir_load_const_instr *instr)
1526 {
1527 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1528 for (int i = 0; i < instr->def.num_components; i++)
1529 qregs[i] = qir_uniform_ui(c, instr->value.u32[i]);
1530
1531 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1532 }
1533
1534 static void
1535 ntq_emit_ssa_undef(struct vc4_compile *c, nir_ssa_undef_instr *instr)
1536 {
1537 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1538
1539 /* QIR needs there to be *some* value, so pick 0 (same as for
1540 * ntq_setup_registers().
1541 */
1542 for (int i = 0; i < instr->def.num_components; i++)
1543 qregs[i] = qir_uniform_ui(c, 0);
1544 }
1545
1546 static void
1547 ntq_emit_intrinsic(struct vc4_compile *c, nir_intrinsic_instr *instr)
1548 {
1549 nir_const_value *const_offset;
1550 unsigned offset;
1551
1552 switch (instr->intrinsic) {
1553 case nir_intrinsic_load_uniform:
1554 assert(instr->num_components == 1);
1555 const_offset = nir_src_as_const_value(instr->src[0]);
1556 if (const_offset) {
1557 offset = instr->const_index[0] + const_offset->u32[0];
1558 assert(offset % 4 == 0);
1559 /* We need dwords */
1560 offset = offset / 4;
1561 if (offset < VC4_NIR_STATE_UNIFORM_OFFSET) {
1562 ntq_store_dest(c, &instr->dest, 0,
1563 qir_uniform(c, QUNIFORM_UNIFORM,
1564 offset));
1565 } else {
1566 ntq_store_dest(c, &instr->dest, 0,
1567 qir_uniform(c, offset -
1568 VC4_NIR_STATE_UNIFORM_OFFSET,
1569 0));
1570 }
1571 } else {
1572 ntq_store_dest(c, &instr->dest, 0,
1573 indirect_uniform_load(c, instr));
1574 }
1575 break;
1576
1577 case nir_intrinsic_load_user_clip_plane:
1578 for (int i = 0; i < instr->num_components; i++) {
1579 ntq_store_dest(c, &instr->dest, i,
1580 qir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1581 instr->const_index[0] * 4 +
1582 i));
1583 }
1584 break;
1585
1586 case nir_intrinsic_load_sample_mask_in:
1587 ntq_store_dest(c, &instr->dest, 0,
1588 qir_uniform(c, QUNIFORM_SAMPLE_MASK, 0));
1589 break;
1590
1591 case nir_intrinsic_load_front_face:
1592 /* The register contains 0 (front) or 1 (back), and we need to
1593 * turn it into a NIR bool where true means front.
1594 */
1595 ntq_store_dest(c, &instr->dest, 0,
1596 qir_ADD(c,
1597 qir_uniform_ui(c, -1),
1598 qir_reg(QFILE_FRAG_REV_FLAG, 0)));
1599 break;
1600
1601 case nir_intrinsic_load_input:
1602 assert(instr->num_components == 1);
1603 const_offset = nir_src_as_const_value(instr->src[0]);
1604 assert(const_offset && "vc4 doesn't support indirect inputs");
1605 if (instr->const_index[0] >= VC4_NIR_TLB_COLOR_READ_INPUT) {
1606 assert(const_offset->u32[0] == 0);
1607 /* Reads of the per-sample color need to be done in
1608 * order.
1609 */
1610 int sample_index = (instr->const_index[0] -
1611 VC4_NIR_TLB_COLOR_READ_INPUT);
1612 for (int i = 0; i <= sample_index; i++) {
1613 if (c->color_reads[i].file == QFILE_NULL) {
1614 c->color_reads[i] =
1615 qir_TLB_COLOR_READ(c);
1616 }
1617 }
1618 ntq_store_dest(c, &instr->dest, 0,
1619 c->color_reads[sample_index]);
1620 } else {
1621 offset = instr->const_index[0] + const_offset->u32[0];
1622 ntq_store_dest(c, &instr->dest, 0,
1623 c->inputs[offset]);
1624 }
1625 break;
1626
1627 case nir_intrinsic_store_output:
1628 const_offset = nir_src_as_const_value(instr->src[1]);
1629 assert(const_offset && "vc4 doesn't support indirect outputs");
1630 offset = instr->const_index[0] + const_offset->u32[0];
1631
1632 /* MSAA color outputs are the only case where we have an
1633 * output that's not lowered to being a store of a single 32
1634 * bit value.
1635 */
1636 if (c->stage == QSTAGE_FRAG && instr->num_components == 4) {
1637 assert(offset == c->output_color_index);
1638 for (int i = 0; i < 4; i++) {
1639 c->sample_colors[i] =
1640 qir_MOV(c, ntq_get_src(c, instr->src[0],
1641 i));
1642 }
1643 } else {
1644 assert(instr->num_components == 1);
1645 c->outputs[offset] =
1646 qir_MOV(c, ntq_get_src(c, instr->src[0], 0));
1647 c->num_outputs = MAX2(c->num_outputs, offset + 1);
1648 }
1649 break;
1650
1651 case nir_intrinsic_discard:
1652 c->discard = qir_uniform_ui(c, ~0);
1653 break;
1654
1655 case nir_intrinsic_discard_if:
1656 if (c->discard.file == QFILE_NULL)
1657 c->discard = qir_uniform_ui(c, 0);
1658 c->discard = qir_OR(c, c->discard,
1659 ntq_get_src(c, instr->src[0], 0));
1660 break;
1661
1662 default:
1663 fprintf(stderr, "Unknown intrinsic: ");
1664 nir_print_instr(&instr->instr, stderr);
1665 fprintf(stderr, "\n");
1666 break;
1667 }
1668 }
1669
1670 static void
1671 ntq_emit_if(struct vc4_compile *c, nir_if *if_stmt)
1672 {
1673 fprintf(stderr, "general IF statements not handled.\n");
1674 }
1675
1676 static void
1677 ntq_emit_instr(struct vc4_compile *c, nir_instr *instr)
1678 {
1679 switch (instr->type) {
1680 case nir_instr_type_alu:
1681 ntq_emit_alu(c, nir_instr_as_alu(instr));
1682 break;
1683
1684 case nir_instr_type_intrinsic:
1685 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
1686 break;
1687
1688 case nir_instr_type_load_const:
1689 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
1690 break;
1691
1692 case nir_instr_type_ssa_undef:
1693 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
1694 break;
1695
1696 case nir_instr_type_tex:
1697 ntq_emit_tex(c, nir_instr_as_tex(instr));
1698 break;
1699
1700 default:
1701 fprintf(stderr, "Unknown NIR instr type: ");
1702 nir_print_instr(instr, stderr);
1703 fprintf(stderr, "\n");
1704 abort();
1705 }
1706 }
1707
1708 static void
1709 ntq_emit_block(struct vc4_compile *c, nir_block *block)
1710 {
1711 nir_foreach_instr(instr, block) {
1712 ntq_emit_instr(c, instr);
1713 }
1714 }
1715
1716 static void ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list);
1717
1718 static void
1719 ntq_emit_loop(struct vc4_compile *c, nir_loop *nloop)
1720 {
1721 fprintf(stderr, "LOOPS not fully handled. Rendering errors likely.\n");
1722 ntq_emit_cf_list(c, &nloop->body);
1723 }
1724
1725 static void
1726 ntq_emit_function(struct vc4_compile *c, nir_function_impl *func)
1727 {
1728 fprintf(stderr, "FUNCTIONS not handled.\n");
1729 abort();
1730 }
1731
1732 static void
1733 ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list)
1734 {
1735 foreach_list_typed(nir_cf_node, node, node, list) {
1736 switch (node->type) {
1737 case nir_cf_node_block:
1738 ntq_emit_block(c, nir_cf_node_as_block(node));
1739 break;
1740
1741 case nir_cf_node_if:
1742 ntq_emit_if(c, nir_cf_node_as_if(node));
1743 break;
1744
1745 case nir_cf_node_loop:
1746 ntq_emit_loop(c, nir_cf_node_as_loop(node));
1747 break;
1748
1749 case nir_cf_node_function:
1750 ntq_emit_function(c, nir_cf_node_as_function(node));
1751 break;
1752
1753 default:
1754 fprintf(stderr, "Unknown NIR node type\n");
1755 abort();
1756 }
1757 }
1758 }
1759
1760 static void
1761 ntq_emit_impl(struct vc4_compile *c, nir_function_impl *impl)
1762 {
1763 ntq_setup_registers(c, &impl->registers);
1764 ntq_emit_cf_list(c, &impl->body);
1765 }
1766
1767 static void
1768 nir_to_qir(struct vc4_compile *c)
1769 {
1770 ntq_setup_inputs(c);
1771 ntq_setup_outputs(c);
1772 ntq_setup_uniforms(c);
1773 ntq_setup_registers(c, &c->s->registers);
1774
1775 /* Find the main function and emit the body. */
1776 nir_foreach_function(function, c->s) {
1777 assert(strcmp(function->name, "main") == 0);
1778 assert(function->impl);
1779 ntq_emit_impl(c, function->impl);
1780 }
1781 }
1782
1783 static const nir_shader_compiler_options nir_options = {
1784 .lower_extract_byte = true,
1785 .lower_extract_word = true,
1786 .lower_ffma = true,
1787 .lower_flrp32 = true,
1788 .lower_fpow = true,
1789 .lower_fsat = true,
1790 .lower_fsqrt = true,
1791 .lower_negate = true,
1792 };
1793
1794 static int
1795 count_nir_instrs(nir_shader *nir)
1796 {
1797 int count = 0;
1798 nir_foreach_function(function, nir) {
1799 if (!function->impl)
1800 continue;
1801 nir_foreach_block(block, function->impl) {
1802 nir_foreach_instr(instr, block)
1803 count++;
1804 }
1805 }
1806 return count;
1807 }
1808
1809 static struct vc4_compile *
1810 vc4_shader_ntq(struct vc4_context *vc4, enum qstage stage,
1811 struct vc4_key *key)
1812 {
1813 struct vc4_compile *c = qir_compile_init();
1814
1815 c->vc4 = vc4;
1816 c->stage = stage;
1817 c->shader_state = &key->shader_state->base;
1818 c->program_id = key->shader_state->program_id;
1819 c->variant_id =
1820 p_atomic_inc_return(&key->shader_state->compiled_variant_count);
1821
1822 c->key = key;
1823 switch (stage) {
1824 case QSTAGE_FRAG:
1825 c->fs_key = (struct vc4_fs_key *)key;
1826 if (c->fs_key->is_points) {
1827 c->point_x = emit_fragment_varying(c, ~0, 0);
1828 c->point_y = emit_fragment_varying(c, ~0, 0);
1829 } else if (c->fs_key->is_lines) {
1830 c->line_x = emit_fragment_varying(c, ~0, 0);
1831 }
1832 break;
1833 case QSTAGE_VERT:
1834 c->vs_key = (struct vc4_vs_key *)key;
1835 break;
1836 case QSTAGE_COORD:
1837 c->vs_key = (struct vc4_vs_key *)key;
1838 break;
1839 }
1840
1841 c->s = nir_shader_clone(c, key->shader_state->base.ir.nir);
1842 NIR_PASS_V(c->s, nir_opt_global_to_local);
1843 NIR_PASS_V(c->s, nir_convert_to_ssa);
1844
1845 if (stage == QSTAGE_FRAG)
1846 NIR_PASS_V(c->s, vc4_nir_lower_blend, c);
1847
1848 struct nir_lower_tex_options tex_options = {
1849 /* We would need to implement txs, but we don't want the
1850 * int/float conversions
1851 */
1852 .lower_rect = false,
1853
1854 .lower_txp = ~0,
1855
1856 /* Apply swizzles to all samplers. */
1857 .swizzle_result = ~0,
1858 };
1859
1860 /* Lower the format swizzle and ARB_texture_swizzle-style swizzle.
1861 * The format swizzling applies before sRGB decode, and
1862 * ARB_texture_swizzle is the last thing before returning the sample.
1863 */
1864 for (int i = 0; i < ARRAY_SIZE(key->tex); i++) {
1865 enum pipe_format format = c->key->tex[i].format;
1866
1867 if (!format)
1868 continue;
1869
1870 const uint8_t *format_swizzle = vc4_get_format_swizzle(format);
1871
1872 for (int j = 0; j < 4; j++) {
1873 uint8_t arb_swiz = c->key->tex[i].swizzle[j];
1874
1875 if (arb_swiz <= 3) {
1876 tex_options.swizzles[i][j] =
1877 format_swizzle[arb_swiz];
1878 } else {
1879 tex_options.swizzles[i][j] = arb_swiz;
1880 }
1881 }
1882
1883 if (util_format_is_srgb(format))
1884 tex_options.lower_srgb |= (1 << i);
1885 }
1886
1887 NIR_PASS_V(c->s, nir_normalize_cubemap_coords);
1888 NIR_PASS_V(c->s, nir_lower_tex, &tex_options);
1889
1890 if (c->fs_key && c->fs_key->light_twoside)
1891 NIR_PASS_V(c->s, nir_lower_two_sided_color);
1892
1893 if (c->vs_key && c->vs_key->clamp_color)
1894 NIR_PASS_V(c->s, nir_lower_clamp_color_outputs);
1895
1896 if (stage == QSTAGE_FRAG)
1897 NIR_PASS_V(c->s, nir_lower_clip_fs, c->key->ucp_enables);
1898 else
1899 NIR_PASS_V(c->s, nir_lower_clip_vs, c->key->ucp_enables);
1900
1901 NIR_PASS_V(c->s, vc4_nir_lower_io, c);
1902 NIR_PASS_V(c->s, vc4_nir_lower_txf_ms, c);
1903 NIR_PASS_V(c->s, nir_lower_idiv);
1904 NIR_PASS_V(c->s, nir_lower_load_const_to_scalar);
1905
1906 vc4_optimize_nir(c->s);
1907
1908 NIR_PASS_V(c->s, nir_remove_dead_variables, nir_var_local);
1909 NIR_PASS_V(c->s, nir_convert_from_ssa, true);
1910
1911 if (vc4_debug & VC4_DEBUG_SHADERDB) {
1912 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d NIR instructions\n",
1913 qir_get_stage_name(c->stage),
1914 c->program_id, c->variant_id,
1915 count_nir_instrs(c->s));
1916 }
1917
1918 if (vc4_debug & VC4_DEBUG_NIR) {
1919 fprintf(stderr, "%s prog %d/%d NIR:\n",
1920 qir_get_stage_name(c->stage),
1921 c->program_id, c->variant_id);
1922 nir_print_shader(c->s, stderr);
1923 }
1924
1925 nir_to_qir(c);
1926
1927 switch (stage) {
1928 case QSTAGE_FRAG:
1929 emit_frag_end(c);
1930 break;
1931 case QSTAGE_VERT:
1932 emit_vert_end(c,
1933 vc4->prog.fs->input_slots,
1934 vc4->prog.fs->num_inputs);
1935 break;
1936 case QSTAGE_COORD:
1937 emit_coord_end(c);
1938 break;
1939 }
1940
1941 if (vc4_debug & VC4_DEBUG_QIR) {
1942 fprintf(stderr, "%s prog %d/%d pre-opt QIR:\n",
1943 qir_get_stage_name(c->stage),
1944 c->program_id, c->variant_id);
1945 qir_dump(c);
1946 fprintf(stderr, "\n");
1947 }
1948
1949 qir_optimize(c);
1950 qir_lower_uniforms(c);
1951
1952 qir_schedule_instructions(c);
1953
1954 if (vc4_debug & VC4_DEBUG_QIR) {
1955 fprintf(stderr, "%s prog %d/%d QIR:\n",
1956 qir_get_stage_name(c->stage),
1957 c->program_id, c->variant_id);
1958 qir_dump(c);
1959 fprintf(stderr, "\n");
1960 }
1961
1962 qir_reorder_uniforms(c);
1963 vc4_generate_code(vc4, c);
1964
1965 if (vc4_debug & VC4_DEBUG_SHADERDB) {
1966 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d instructions\n",
1967 qir_get_stage_name(c->stage),
1968 c->program_id, c->variant_id,
1969 c->qpu_inst_count);
1970 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d uniforms\n",
1971 qir_get_stage_name(c->stage),
1972 c->program_id, c->variant_id,
1973 c->num_uniforms);
1974 }
1975
1976 ralloc_free(c->s);
1977
1978 return c;
1979 }
1980
1981 static void *
1982 vc4_shader_state_create(struct pipe_context *pctx,
1983 const struct pipe_shader_state *cso)
1984 {
1985 struct vc4_context *vc4 = vc4_context(pctx);
1986 struct vc4_uncompiled_shader *so = CALLOC_STRUCT(vc4_uncompiled_shader);
1987 if (!so)
1988 return NULL;
1989
1990 so->program_id = vc4->next_uncompiled_program_id++;
1991
1992 nir_shader *s = tgsi_to_nir(cso->tokens, &nir_options);
1993
1994 if (vc4_debug & VC4_DEBUG_TGSI) {
1995 fprintf(stderr, "%s prog %d TGSI:\n",
1996 gl_shader_stage_name(s->stage),
1997 so->program_id);
1998 tgsi_dump(cso->tokens, 0);
1999 fprintf(stderr, "\n");
2000 }
2001
2002 so->base.type = PIPE_SHADER_IR_NIR;
2003 so->base.ir.nir = s;
2004
2005 return so;
2006 }
2007
2008 static void
2009 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
2010 struct vc4_compile *c)
2011 {
2012 int count = c->num_uniforms;
2013 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
2014
2015 uinfo->count = count;
2016 uinfo->data = ralloc_array(shader, uint32_t, count);
2017 memcpy(uinfo->data, c->uniform_data,
2018 count * sizeof(*uinfo->data));
2019 uinfo->contents = ralloc_array(shader, enum quniform_contents, count);
2020 memcpy(uinfo->contents, c->uniform_contents,
2021 count * sizeof(*uinfo->contents));
2022 uinfo->num_texture_samples = c->num_texture_samples;
2023
2024 vc4_set_shader_uniform_dirty_flags(shader);
2025 }
2026
2027 static struct vc4_compiled_shader *
2028 vc4_get_compiled_shader(struct vc4_context *vc4, enum qstage stage,
2029 struct vc4_key *key)
2030 {
2031 struct hash_table *ht;
2032 uint32_t key_size;
2033 if (stage == QSTAGE_FRAG) {
2034 ht = vc4->fs_cache;
2035 key_size = sizeof(struct vc4_fs_key);
2036 } else {
2037 ht = vc4->vs_cache;
2038 key_size = sizeof(struct vc4_vs_key);
2039 }
2040
2041 struct vc4_compiled_shader *shader;
2042 struct hash_entry *entry = _mesa_hash_table_search(ht, key);
2043 if (entry)
2044 return entry->data;
2045
2046 struct vc4_compile *c = vc4_shader_ntq(vc4, stage, key);
2047 shader = rzalloc(NULL, struct vc4_compiled_shader);
2048
2049 shader->program_id = vc4->next_compiled_program_id++;
2050 if (stage == QSTAGE_FRAG) {
2051 bool input_live[c->num_input_slots];
2052
2053 memset(input_live, 0, sizeof(input_live));
2054 qir_for_each_inst_inorder(inst, c) {
2055 for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) {
2056 if (inst->src[i].file == QFILE_VARY)
2057 input_live[inst->src[i].index] = true;
2058 }
2059 }
2060
2061 shader->input_slots = ralloc_array(shader,
2062 struct vc4_varying_slot,
2063 c->num_input_slots);
2064
2065 for (int i = 0; i < c->num_input_slots; i++) {
2066 struct vc4_varying_slot *slot = &c->input_slots[i];
2067
2068 if (!input_live[i])
2069 continue;
2070
2071 /* Skip non-VS-output inputs. */
2072 if (slot->slot == (uint8_t)~0)
2073 continue;
2074
2075 if (slot->slot == VARYING_SLOT_COL0 ||
2076 slot->slot == VARYING_SLOT_COL1 ||
2077 slot->slot == VARYING_SLOT_BFC0 ||
2078 slot->slot == VARYING_SLOT_BFC1) {
2079 shader->color_inputs |= (1 << shader->num_inputs);
2080 }
2081
2082 shader->input_slots[shader->num_inputs] = *slot;
2083 shader->num_inputs++;
2084 }
2085 } else {
2086 shader->num_inputs = c->num_inputs;
2087
2088 shader->vattr_offsets[0] = 0;
2089 for (int i = 0; i < 8; i++) {
2090 shader->vattr_offsets[i + 1] =
2091 shader->vattr_offsets[i] + c->vattr_sizes[i];
2092
2093 if (c->vattr_sizes[i])
2094 shader->vattrs_live |= (1 << i);
2095 }
2096 }
2097
2098 copy_uniform_state_to_shader(shader, c);
2099 shader->bo = vc4_bo_alloc_shader(vc4->screen, c->qpu_insts,
2100 c->qpu_inst_count * sizeof(uint64_t));
2101
2102 /* Copy the compiler UBO range state to the compiled shader, dropping
2103 * out arrays that were never referenced by an indirect load.
2104 *
2105 * (Note that QIR dead code elimination of an array access still
2106 * leaves that array alive, though)
2107 */
2108 if (c->num_ubo_ranges) {
2109 shader->num_ubo_ranges = c->num_ubo_ranges;
2110 shader->ubo_ranges = ralloc_array(shader, struct vc4_ubo_range,
2111 c->num_ubo_ranges);
2112 uint32_t j = 0;
2113 for (int i = 0; i < c->num_uniform_ranges; i++) {
2114 struct vc4_compiler_ubo_range *range =
2115 &c->ubo_ranges[i];
2116 if (!range->used)
2117 continue;
2118
2119 shader->ubo_ranges[j].dst_offset = range->dst_offset;
2120 shader->ubo_ranges[j].src_offset = range->src_offset;
2121 shader->ubo_ranges[j].size = range->size;
2122 shader->ubo_size += c->ubo_ranges[i].size;
2123 j++;
2124 }
2125 }
2126 if (shader->ubo_size) {
2127 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2128 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d UBO uniforms\n",
2129 qir_get_stage_name(c->stage),
2130 c->program_id, c->variant_id,
2131 shader->ubo_size / 4);
2132 }
2133 }
2134
2135 qir_compile_destroy(c);
2136
2137 struct vc4_key *dup_key;
2138 dup_key = ralloc_size(shader, key_size);
2139 memcpy(dup_key, key, key_size);
2140 _mesa_hash_table_insert(ht, dup_key, shader);
2141
2142 return shader;
2143 }
2144
2145 static void
2146 vc4_setup_shared_key(struct vc4_context *vc4, struct vc4_key *key,
2147 struct vc4_texture_stateobj *texstate)
2148 {
2149 for (int i = 0; i < texstate->num_textures; i++) {
2150 struct pipe_sampler_view *sampler = texstate->textures[i];
2151 struct pipe_sampler_state *sampler_state =
2152 texstate->samplers[i];
2153
2154 if (!sampler)
2155 continue;
2156
2157 key->tex[i].format = sampler->format;
2158 key->tex[i].swizzle[0] = sampler->swizzle_r;
2159 key->tex[i].swizzle[1] = sampler->swizzle_g;
2160 key->tex[i].swizzle[2] = sampler->swizzle_b;
2161 key->tex[i].swizzle[3] = sampler->swizzle_a;
2162
2163 if (sampler->texture->nr_samples > 1) {
2164 key->tex[i].msaa_width = sampler->texture->width0;
2165 key->tex[i].msaa_height = sampler->texture->height0;
2166 } else if (sampler){
2167 key->tex[i].compare_mode = sampler_state->compare_mode;
2168 key->tex[i].compare_func = sampler_state->compare_func;
2169 key->tex[i].wrap_s = sampler_state->wrap_s;
2170 key->tex[i].wrap_t = sampler_state->wrap_t;
2171 }
2172 }
2173
2174 key->ucp_enables = vc4->rasterizer->base.clip_plane_enable;
2175 }
2176
2177 static void
2178 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
2179 {
2180 struct vc4_fs_key local_key;
2181 struct vc4_fs_key *key = &local_key;
2182
2183 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2184 VC4_DIRTY_BLEND |
2185 VC4_DIRTY_FRAMEBUFFER |
2186 VC4_DIRTY_ZSA |
2187 VC4_DIRTY_RASTERIZER |
2188 VC4_DIRTY_SAMPLE_MASK |
2189 VC4_DIRTY_FRAGTEX |
2190 VC4_DIRTY_TEXSTATE |
2191 VC4_DIRTY_UNCOMPILED_FS))) {
2192 return;
2193 }
2194
2195 memset(key, 0, sizeof(*key));
2196 vc4_setup_shared_key(vc4, &key->base, &vc4->fragtex);
2197 key->base.shader_state = vc4->prog.bind_fs;
2198 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
2199 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
2200 prim_mode <= PIPE_PRIM_LINE_STRIP);
2201 key->blend = vc4->blend->rt[0];
2202 if (vc4->blend->logicop_enable) {
2203 key->logicop_func = vc4->blend->logicop_func;
2204 } else {
2205 key->logicop_func = PIPE_LOGICOP_COPY;
2206 }
2207 if (vc4->msaa) {
2208 key->msaa = vc4->rasterizer->base.multisample;
2209 key->sample_coverage = (vc4->rasterizer->base.multisample &&
2210 vc4->sample_mask != (1 << VC4_MAX_SAMPLES) - 1);
2211 key->sample_alpha_to_coverage = vc4->blend->alpha_to_coverage;
2212 key->sample_alpha_to_one = vc4->blend->alpha_to_one;
2213 }
2214
2215 if (vc4->framebuffer.cbufs[0])
2216 key->color_format = vc4->framebuffer.cbufs[0]->format;
2217
2218 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
2219 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
2220 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
2221 key->depth_enabled = (vc4->zsa->base.depth.enabled ||
2222 key->stencil_enabled);
2223 if (vc4->zsa->base.alpha.enabled) {
2224 key->alpha_test = true;
2225 key->alpha_test_func = vc4->zsa->base.alpha.func;
2226 }
2227
2228 if (key->is_points) {
2229 key->point_sprite_mask =
2230 vc4->rasterizer->base.sprite_coord_enable;
2231 key->point_coord_upper_left =
2232 (vc4->rasterizer->base.sprite_coord_mode ==
2233 PIPE_SPRITE_COORD_UPPER_LEFT);
2234 }
2235
2236 key->light_twoside = vc4->rasterizer->base.light_twoside;
2237
2238 struct vc4_compiled_shader *old_fs = vc4->prog.fs;
2239 vc4->prog.fs = vc4_get_compiled_shader(vc4, QSTAGE_FRAG, &key->base);
2240 if (vc4->prog.fs == old_fs)
2241 return;
2242
2243 vc4->dirty |= VC4_DIRTY_COMPILED_FS;
2244 if (vc4->rasterizer->base.flatshade &&
2245 old_fs && vc4->prog.fs->color_inputs != old_fs->color_inputs) {
2246 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
2247 }
2248 }
2249
2250 static void
2251 vc4_update_compiled_vs(struct vc4_context *vc4, uint8_t prim_mode)
2252 {
2253 struct vc4_vs_key local_key;
2254 struct vc4_vs_key *key = &local_key;
2255
2256 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2257 VC4_DIRTY_RASTERIZER |
2258 VC4_DIRTY_VERTTEX |
2259 VC4_DIRTY_TEXSTATE |
2260 VC4_DIRTY_VTXSTATE |
2261 VC4_DIRTY_UNCOMPILED_VS |
2262 VC4_DIRTY_COMPILED_FS))) {
2263 return;
2264 }
2265
2266 memset(key, 0, sizeof(*key));
2267 vc4_setup_shared_key(vc4, &key->base, &vc4->verttex);
2268 key->base.shader_state = vc4->prog.bind_vs;
2269 key->compiled_fs_id = vc4->prog.fs->program_id;
2270 key->clamp_color = vc4->rasterizer->base.clamp_vertex_color;
2271
2272 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
2273 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
2274
2275 key->per_vertex_point_size =
2276 (prim_mode == PIPE_PRIM_POINTS &&
2277 vc4->rasterizer->base.point_size_per_vertex);
2278
2279 struct vc4_compiled_shader *vs =
2280 vc4_get_compiled_shader(vc4, QSTAGE_VERT, &key->base);
2281 if (vs != vc4->prog.vs) {
2282 vc4->prog.vs = vs;
2283 vc4->dirty |= VC4_DIRTY_COMPILED_VS;
2284 }
2285
2286 key->is_coord = true;
2287 struct vc4_compiled_shader *cs =
2288 vc4_get_compiled_shader(vc4, QSTAGE_COORD, &key->base);
2289 if (cs != vc4->prog.cs) {
2290 vc4->prog.cs = cs;
2291 vc4->dirty |= VC4_DIRTY_COMPILED_CS;
2292 }
2293 }
2294
2295 void
2296 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
2297 {
2298 vc4_update_compiled_fs(vc4, prim_mode);
2299 vc4_update_compiled_vs(vc4, prim_mode);
2300 }
2301
2302 static uint32_t
2303 fs_cache_hash(const void *key)
2304 {
2305 return _mesa_hash_data(key, sizeof(struct vc4_fs_key));
2306 }
2307
2308 static uint32_t
2309 vs_cache_hash(const void *key)
2310 {
2311 return _mesa_hash_data(key, sizeof(struct vc4_vs_key));
2312 }
2313
2314 static bool
2315 fs_cache_compare(const void *key1, const void *key2)
2316 {
2317 return memcmp(key1, key2, sizeof(struct vc4_fs_key)) == 0;
2318 }
2319
2320 static bool
2321 vs_cache_compare(const void *key1, const void *key2)
2322 {
2323 return memcmp(key1, key2, sizeof(struct vc4_vs_key)) == 0;
2324 }
2325
2326 static void
2327 delete_from_cache_if_matches(struct hash_table *ht,
2328 struct hash_entry *entry,
2329 struct vc4_uncompiled_shader *so)
2330 {
2331 const struct vc4_key *key = entry->key;
2332
2333 if (key->shader_state == so) {
2334 struct vc4_compiled_shader *shader = entry->data;
2335 _mesa_hash_table_remove(ht, entry);
2336 vc4_bo_unreference(&shader->bo);
2337 ralloc_free(shader);
2338 }
2339 }
2340
2341 static void
2342 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
2343 {
2344 struct vc4_context *vc4 = vc4_context(pctx);
2345 struct vc4_uncompiled_shader *so = hwcso;
2346
2347 struct hash_entry *entry;
2348 hash_table_foreach(vc4->fs_cache, entry)
2349 delete_from_cache_if_matches(vc4->fs_cache, entry, so);
2350 hash_table_foreach(vc4->vs_cache, entry)
2351 delete_from_cache_if_matches(vc4->vs_cache, entry, so);
2352
2353 ralloc_free(so->base.ir.nir);
2354 free(so);
2355 }
2356
2357 static void
2358 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
2359 {
2360 struct vc4_context *vc4 = vc4_context(pctx);
2361 vc4->prog.bind_fs = hwcso;
2362 vc4->dirty |= VC4_DIRTY_UNCOMPILED_FS;
2363 }
2364
2365 static void
2366 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
2367 {
2368 struct vc4_context *vc4 = vc4_context(pctx);
2369 vc4->prog.bind_vs = hwcso;
2370 vc4->dirty |= VC4_DIRTY_UNCOMPILED_VS;
2371 }
2372
2373 void
2374 vc4_program_init(struct pipe_context *pctx)
2375 {
2376 struct vc4_context *vc4 = vc4_context(pctx);
2377
2378 pctx->create_vs_state = vc4_shader_state_create;
2379 pctx->delete_vs_state = vc4_shader_state_delete;
2380
2381 pctx->create_fs_state = vc4_shader_state_create;
2382 pctx->delete_fs_state = vc4_shader_state_delete;
2383
2384 pctx->bind_fs_state = vc4_fp_state_bind;
2385 pctx->bind_vs_state = vc4_vp_state_bind;
2386
2387 vc4->fs_cache = _mesa_hash_table_create(pctx, fs_cache_hash,
2388 fs_cache_compare);
2389 vc4->vs_cache = _mesa_hash_table_create(pctx, vs_cache_hash,
2390 vs_cache_compare);
2391 }
2392
2393 void
2394 vc4_program_fini(struct pipe_context *pctx)
2395 {
2396 struct vc4_context *vc4 = vc4_context(pctx);
2397
2398 struct hash_entry *entry;
2399 hash_table_foreach(vc4->fs_cache, entry) {
2400 struct vc4_compiled_shader *shader = entry->data;
2401 vc4_bo_unreference(&shader->bo);
2402 ralloc_free(shader);
2403 _mesa_hash_table_remove(vc4->fs_cache, entry);
2404 }
2405
2406 hash_table_foreach(vc4->vs_cache, entry) {
2407 struct vc4_compiled_shader *shader = entry->data;
2408 vc4_bo_unreference(&shader->bo);
2409 ralloc_free(shader);
2410 _mesa_hash_table_remove(vc4->vs_cache, entry);
2411 }
2412 }