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vc4: Fix memory leaks of some vc4_compile contents.
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "pipe/p_state.h"
27 #include "util/u_format.h"
28 #include "util/u_hash_table.h"
29 #include "util/u_hash.h"
30 #include "util/u_memory.h"
31 #include "util/ralloc.h"
32 #include "tgsi/tgsi_dump.h"
33 #include "tgsi/tgsi_info.h"
34
35 #include "vc4_context.h"
36 #include "vc4_qpu.h"
37 #include "vc4_qir.h"
38 #ifdef USE_VC4_SIMULATOR
39 #include "simpenrose/simpenrose.h"
40 #endif
41
42 struct vc4_key {
43 struct pipe_shader_state *shader_state;
44 struct {
45 enum pipe_format format;
46 unsigned compare_mode:1;
47 unsigned compare_func:3;
48 uint8_t swizzle[4];
49 } tex[VC4_MAX_TEXTURE_SAMPLERS];
50 };
51
52 struct vc4_fs_key {
53 struct vc4_key base;
54 enum pipe_format color_format;
55 bool depth_enabled;
56 bool is_points;
57 bool is_lines;
58
59 struct pipe_rt_blend_state blend;
60 };
61
62 struct vc4_vs_key {
63 struct vc4_key base;
64 enum pipe_format attr_formats[8];
65 };
66
67 static struct qreg
68 add_uniform(struct vc4_compile *c,
69 enum quniform_contents contents,
70 uint32_t data)
71 {
72 uint32_t uniform = c->num_uniforms++;
73 struct qreg u = { QFILE_UNIF, uniform };
74
75 c->uniform_contents[uniform] = contents;
76 c->uniform_data[uniform] = data;
77
78 return u;
79 }
80
81 static struct qreg
82 get_temp_for_uniform(struct vc4_compile *c, enum quniform_contents contents,
83 uint32_t data)
84 {
85 for (int i = 0; i < c->num_uniforms; i++) {
86 if (c->uniform_contents[i] == contents &&
87 c->uniform_data[i] == data)
88 return c->uniforms[i];
89 }
90
91 struct qreg u = add_uniform(c, contents, data);
92 struct qreg t = qir_MOV(c, u);
93
94 c->uniforms[u.index] = t;
95 return t;
96 }
97
98 static struct qreg
99 qir_uniform_ui(struct vc4_compile *c, uint32_t ui)
100 {
101 return get_temp_for_uniform(c, QUNIFORM_CONSTANT, ui);
102 }
103
104 static struct qreg
105 qir_uniform_f(struct vc4_compile *c, float f)
106 {
107 return qir_uniform_ui(c, fui(f));
108 }
109
110 static struct qreg
111 get_src(struct vc4_compile *c, unsigned tgsi_op,
112 struct tgsi_src_register *src, int i)
113 {
114 struct qreg r = c->undef;
115
116 uint32_t s = i;
117 switch (i) {
118 case TGSI_SWIZZLE_X:
119 s = src->SwizzleX;
120 break;
121 case TGSI_SWIZZLE_Y:
122 s = src->SwizzleY;
123 break;
124 case TGSI_SWIZZLE_Z:
125 s = src->SwizzleZ;
126 break;
127 case TGSI_SWIZZLE_W:
128 s = src->SwizzleW;
129 break;
130 default:
131 abort();
132 }
133
134 assert(!src->Indirect);
135
136 switch (src->File) {
137 case TGSI_FILE_NULL:
138 return r;
139 case TGSI_FILE_TEMPORARY:
140 r = c->temps[src->Index * 4 + s];
141 break;
142 case TGSI_FILE_IMMEDIATE:
143 r = c->consts[src->Index * 4 + s];
144 break;
145 case TGSI_FILE_CONSTANT:
146 r = get_temp_for_uniform(c, QUNIFORM_UNIFORM,
147 src->Index * 4 + s);
148 break;
149 case TGSI_FILE_INPUT:
150 r = c->inputs[src->Index * 4 + s];
151 break;
152 case TGSI_FILE_SAMPLER:
153 case TGSI_FILE_SAMPLER_VIEW:
154 r = c->undef;
155 break;
156 default:
157 fprintf(stderr, "unknown src file %d\n", src->File);
158 abort();
159 }
160
161 if (src->Absolute)
162 r = qir_FMAXABS(c, r, r);
163
164 if (src->Negate) {
165 switch (tgsi_opcode_infer_src_type(tgsi_op)) {
166 case TGSI_TYPE_SIGNED:
167 case TGSI_TYPE_UNSIGNED:
168 r = qir_SUB(c, qir_uniform_ui(c, 0), r);
169 break;
170 default:
171 r = qir_FSUB(c, qir_uniform_f(c, 0.0), r);
172 break;
173 }
174 }
175
176 return r;
177 };
178
179
180 static void
181 update_dst(struct vc4_compile *c, struct tgsi_full_instruction *tgsi_inst,
182 int i, struct qreg val)
183 {
184 struct tgsi_dst_register *tgsi_dst = &tgsi_inst->Dst[0].Register;
185
186 assert(!tgsi_dst->Indirect);
187
188 switch (tgsi_dst->File) {
189 case TGSI_FILE_TEMPORARY:
190 c->temps[tgsi_dst->Index * 4 + i] = val;
191 break;
192 case TGSI_FILE_OUTPUT:
193 c->outputs[tgsi_dst->Index * 4 + i] = val;
194 c->num_outputs = MAX2(c->num_outputs,
195 tgsi_dst->Index * 4 + i + 1);
196 break;
197 default:
198 fprintf(stderr, "unknown dst file %d\n", tgsi_dst->File);
199 abort();
200 }
201 };
202
203 static struct qreg
204 get_swizzled_channel(struct vc4_compile *c,
205 struct qreg *srcs, int swiz)
206 {
207 switch (swiz) {
208 default:
209 case UTIL_FORMAT_SWIZZLE_NONE:
210 fprintf(stderr, "warning: unknown swizzle\n");
211 /* FALLTHROUGH */
212 case UTIL_FORMAT_SWIZZLE_0:
213 return qir_uniform_f(c, 0.0);
214 case UTIL_FORMAT_SWIZZLE_1:
215 return qir_uniform_f(c, 1.0);
216 case UTIL_FORMAT_SWIZZLE_X:
217 case UTIL_FORMAT_SWIZZLE_Y:
218 case UTIL_FORMAT_SWIZZLE_Z:
219 case UTIL_FORMAT_SWIZZLE_W:
220 return srcs[swiz];
221 }
222 }
223
224 static struct qreg
225 tgsi_to_qir_alu(struct vc4_compile *c,
226 struct tgsi_full_instruction *tgsi_inst,
227 enum qop op, struct qreg *src, int i)
228 {
229 struct qreg dst = qir_get_temp(c);
230 qir_emit(c, qir_inst4(op, dst,
231 src[0 * 4 + i],
232 src[1 * 4 + i],
233 src[2 * 4 + i],
234 c->undef));
235 return dst;
236 }
237
238 static struct qreg
239 tgsi_to_qir_umul(struct vc4_compile *c,
240 struct tgsi_full_instruction *tgsi_inst,
241 enum qop op, struct qreg *src, int i)
242 {
243 struct qreg src0_hi = qir_SHR(c, src[0 * 4 + i],
244 qir_uniform_ui(c, 16));
245 struct qreg src0_lo = qir_AND(c, src[0 * 4 + i],
246 qir_uniform_ui(c, 0xffff));
247 struct qreg src1_hi = qir_SHR(c, src[1 * 4 + i],
248 qir_uniform_ui(c, 16));
249 struct qreg src1_lo = qir_AND(c, src[1 * 4 + i],
250 qir_uniform_ui(c, 0xffff));
251
252 struct qreg hilo = qir_MUL24(c, src0_hi, src1_lo);
253 struct qreg lohi = qir_MUL24(c, src0_lo, src1_hi);
254 struct qreg lolo = qir_MUL24(c, src0_lo, src1_lo);
255
256 return qir_ADD(c, lolo, qir_SHL(c,
257 qir_ADD(c, hilo, lohi),
258 qir_uniform_ui(c, 16)));
259 }
260
261 static struct qreg
262 tgsi_to_qir_idiv(struct vc4_compile *c,
263 struct tgsi_full_instruction *tgsi_inst,
264 enum qop op, struct qreg *src, int i)
265 {
266 return qir_FTOI(c, qir_FMUL(c,
267 qir_ITOF(c, src[0 * 4 + i]),
268 qir_RCP(c, qir_ITOF(c, src[1 * 4 + i]))));
269 }
270
271 static struct qreg
272 tgsi_to_qir_ineg(struct vc4_compile *c,
273 struct tgsi_full_instruction *tgsi_inst,
274 enum qop op, struct qreg *src, int i)
275 {
276 return qir_SUB(c, qir_uniform_ui(c, 0), src[0 * 4 + i]);
277 }
278
279 static struct qreg
280 tgsi_to_qir_seq(struct vc4_compile *c,
281 struct tgsi_full_instruction *tgsi_inst,
282 enum qop op, struct qreg *src, int i)
283 {
284 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
285 return qir_SEL_X_0_ZS(c, qir_uniform_f(c, 1.0));
286 }
287
288 static struct qreg
289 tgsi_to_qir_sne(struct vc4_compile *c,
290 struct tgsi_full_instruction *tgsi_inst,
291 enum qop op, struct qreg *src, int i)
292 {
293 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
294 return qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0));
295 }
296
297 static struct qreg
298 tgsi_to_qir_slt(struct vc4_compile *c,
299 struct tgsi_full_instruction *tgsi_inst,
300 enum qop op, struct qreg *src, int i)
301 {
302 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
303 return qir_SEL_X_0_NS(c, qir_uniform_f(c, 1.0));
304 }
305
306 static struct qreg
307 tgsi_to_qir_sge(struct vc4_compile *c,
308 struct tgsi_full_instruction *tgsi_inst,
309 enum qop op, struct qreg *src, int i)
310 {
311 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
312 return qir_SEL_X_0_NC(c, qir_uniform_f(c, 1.0));
313 }
314
315 static struct qreg
316 tgsi_to_qir_fseq(struct vc4_compile *c,
317 struct tgsi_full_instruction *tgsi_inst,
318 enum qop op, struct qreg *src, int i)
319 {
320 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
321 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
322 }
323
324 static struct qreg
325 tgsi_to_qir_fsne(struct vc4_compile *c,
326 struct tgsi_full_instruction *tgsi_inst,
327 enum qop op, struct qreg *src, int i)
328 {
329 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
330 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
331 }
332
333 static struct qreg
334 tgsi_to_qir_fslt(struct vc4_compile *c,
335 struct tgsi_full_instruction *tgsi_inst,
336 enum qop op, struct qreg *src, int i)
337 {
338 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
339 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
340 }
341
342 static struct qreg
343 tgsi_to_qir_fsge(struct vc4_compile *c,
344 struct tgsi_full_instruction *tgsi_inst,
345 enum qop op, struct qreg *src, int i)
346 {
347 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
348 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
349 }
350
351 static struct qreg
352 tgsi_to_qir_useq(struct vc4_compile *c,
353 struct tgsi_full_instruction *tgsi_inst,
354 enum qop op, struct qreg *src, int i)
355 {
356 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
357 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
358 }
359
360 static struct qreg
361 tgsi_to_qir_usne(struct vc4_compile *c,
362 struct tgsi_full_instruction *tgsi_inst,
363 enum qop op, struct qreg *src, int i)
364 {
365 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
366 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
367 }
368
369 static struct qreg
370 tgsi_to_qir_islt(struct vc4_compile *c,
371 struct tgsi_full_instruction *tgsi_inst,
372 enum qop op, struct qreg *src, int i)
373 {
374 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
375 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
376 }
377
378 static struct qreg
379 tgsi_to_qir_isge(struct vc4_compile *c,
380 struct tgsi_full_instruction *tgsi_inst,
381 enum qop op, struct qreg *src, int i)
382 {
383 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
384 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
385 }
386
387 static struct qreg
388 tgsi_to_qir_cmp(struct vc4_compile *c,
389 struct tgsi_full_instruction *tgsi_inst,
390 enum qop op, struct qreg *src, int i)
391 {
392 qir_SF(c, src[0 * 4 + i]);
393 return qir_SEL_X_Y_NS(c,
394 src[1 * 4 + i],
395 src[2 * 4 + i]);
396 }
397
398 static struct qreg
399 tgsi_to_qir_mad(struct vc4_compile *c,
400 struct tgsi_full_instruction *tgsi_inst,
401 enum qop op, struct qreg *src, int i)
402 {
403 return qir_FADD(c,
404 qir_FMUL(c,
405 src[0 * 4 + i],
406 src[1 * 4 + i]),
407 src[2 * 4 + i]);
408 }
409
410 static struct qreg
411 tgsi_to_qir_lit(struct vc4_compile *c,
412 struct tgsi_full_instruction *tgsi_inst,
413 enum qop op, struct qreg *src, int i)
414 {
415 struct qreg x = src[0 * 4 + 0];
416 struct qreg y = src[0 * 4 + 1];
417 struct qreg w = src[0 * 4 + 3];
418
419 switch (i) {
420 case 0:
421 case 3:
422 return qir_uniform_f(c, 1.0);
423 case 1:
424 return qir_FMAX(c, src[0 * 4 + 0], qir_uniform_f(c, 0.0));
425 case 2: {
426 struct qreg zero = qir_uniform_f(c, 0.0);
427
428 qir_SF(c, x);
429 /* XXX: Clamp w to -128..128 */
430 return qir_SEL_X_0_NC(c,
431 qir_EXP2(c, qir_FMUL(c,
432 w,
433 qir_LOG2(c,
434 qir_FMAX(c,
435 y,
436 zero)))));
437 }
438 default:
439 assert(!"not reached");
440 return c->undef;
441 }
442 }
443
444 static struct qreg
445 tgsi_to_qir_lrp(struct vc4_compile *c,
446 struct tgsi_full_instruction *tgsi_inst,
447 enum qop op, struct qreg *src, int i)
448 {
449 struct qreg src0 = src[0 * 4 + i];
450 struct qreg src1 = src[1 * 4 + i];
451 struct qreg src2 = src[2 * 4 + i];
452
453 /* LRP is:
454 * src0 * src1 + (1 - src0) * src2.
455 * -> src0 * src1 + src2 - src0 * src2
456 * -> src2 + src0 * (src1 - src2)
457 */
458 return qir_FADD(c, src2, qir_FMUL(c, src0, qir_FSUB(c, src1, src2)));
459
460 }
461
462 static void
463 tgsi_to_qir_tex(struct vc4_compile *c,
464 struct tgsi_full_instruction *tgsi_inst,
465 enum qop op, struct qreg *src)
466 {
467 assert(!tgsi_inst->Instruction.Saturate);
468
469 struct qreg s = src[0 * 4 + 0];
470 struct qreg t = src[0 * 4 + 1];
471 uint32_t unit = tgsi_inst->Src[1].Register.Index;
472
473 struct qreg proj = c->undef;
474 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
475 proj = qir_RCP(c, src[0 * 4 + 3]);
476 s = qir_FMUL(c, s, proj);
477 t = qir_FMUL(c, t, proj);
478 }
479
480 /* There is no native support for GL texture rectangle coordinates, so
481 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
482 * 1]).
483 */
484 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_RECT ||
485 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT) {
486 s = qir_FMUL(c, s,
487 get_temp_for_uniform(c,
488 QUNIFORM_TEXRECT_SCALE_X,
489 unit));
490 t = qir_FMUL(c, t,
491 get_temp_for_uniform(c,
492 QUNIFORM_TEXRECT_SCALE_Y,
493 unit));
494 }
495
496 qir_TEX_T(c, t, add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit));
497
498 struct qreg sampler_p1 = add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1,
499 unit);
500 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB) {
501 qir_TEX_B(c, src[0 * 4 + 3], sampler_p1);
502 qir_TEX_S(c, s, add_uniform(c, QUNIFORM_CONSTANT, 0));
503 } else {
504 qir_TEX_S(c, s, sampler_p1);
505 }
506
507 c->num_texture_samples++;
508 struct qreg r4 = qir_TEX_RESULT(c);
509
510 enum pipe_format format = c->key->tex[unit].format;
511
512 struct qreg unpacked[4];
513 if (util_format_is_depth_or_stencil(format)) {
514 struct qreg depthf = qir_ITOF(c, qir_SHR(c, r4,
515 qir_uniform_ui(c, 8)));
516 struct qreg normalized = qir_FMUL(c, depthf,
517 qir_uniform_f(c, 1.0f/0xffffff));
518
519 struct qreg depth_output;
520
521 struct qreg compare = src[0 * 4 + 2];
522
523 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP)
524 compare = qir_FMUL(c, compare, proj);
525
526 struct qreg one = qir_uniform_f(c, 1.0f);
527 if (c->key->tex[unit].compare_mode) {
528 switch (c->key->tex[unit].compare_func) {
529 case PIPE_FUNC_NEVER:
530 depth_output = qir_uniform_f(c, 0.0f);
531 break;
532 case PIPE_FUNC_ALWAYS:
533 depth_output = one;
534 break;
535 case PIPE_FUNC_EQUAL:
536 qir_SF(c, qir_FSUB(c, compare, normalized));
537 depth_output = qir_SEL_X_0_ZS(c, one);
538 break;
539 case PIPE_FUNC_NOTEQUAL:
540 qir_SF(c, qir_FSUB(c, compare, normalized));
541 depth_output = qir_SEL_X_0_ZC(c, one);
542 break;
543 case PIPE_FUNC_GREATER:
544 qir_SF(c, qir_FSUB(c, compare, normalized));
545 depth_output = qir_SEL_X_0_NC(c, one);
546 break;
547 case PIPE_FUNC_GEQUAL:
548 qir_SF(c, qir_FSUB(c, normalized, compare));
549 depth_output = qir_SEL_X_0_NS(c, one);
550 break;
551 case PIPE_FUNC_LESS:
552 qir_SF(c, qir_FSUB(c, compare, normalized));
553 depth_output = qir_SEL_X_0_NS(c, one);
554 break;
555 case PIPE_FUNC_LEQUAL:
556 qir_SF(c, qir_FSUB(c, normalized, compare));
557 depth_output = qir_SEL_X_0_NC(c, one);
558 break;
559 }
560 } else {
561 depth_output = normalized;
562 }
563
564 for (int i = 0; i < 4; i++)
565 unpacked[i] = depth_output;
566 } else {
567 for (int i = 0; i < 4; i++)
568 unpacked[i] = qir_R4_UNPACK(c, r4, i);
569 }
570
571 const uint8_t *format_swiz = vc4_get_format_swizzle(format);
572 uint8_t swiz[4];
573 util_format_compose_swizzles(format_swiz, c->key->tex[unit].swizzle, swiz);
574 for (int i = 0; i < 4; i++) {
575 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
576 continue;
577
578 update_dst(c, tgsi_inst, i,
579 get_swizzled_channel(c, unpacked, swiz[i]));
580 }
581 }
582
583 static struct qreg
584 tgsi_to_qir_pow(struct vc4_compile *c,
585 struct tgsi_full_instruction *tgsi_inst,
586 enum qop op, struct qreg *src, int i)
587 {
588 /* Note that this instruction replicates its result from the x channel
589 */
590 return qir_EXP2(c, qir_FMUL(c,
591 src[1 * 4 + 0],
592 qir_LOG2(c, src[0 * 4 + 0])));
593 }
594
595 static struct qreg
596 tgsi_to_qir_trunc(struct vc4_compile *c,
597 struct tgsi_full_instruction *tgsi_inst,
598 enum qop op, struct qreg *src, int i)
599 {
600 return qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
601 }
602
603 /**
604 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
605 * to zero).
606 */
607 static struct qreg
608 tgsi_to_qir_frc(struct vc4_compile *c,
609 struct tgsi_full_instruction *tgsi_inst,
610 enum qop op, struct qreg *src, int i)
611 {
612 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
613 struct qreg diff = qir_FSUB(c, src[0 * 4 + i], trunc);
614 qir_SF(c, diff);
615 return qir_SEL_X_Y_NS(c,
616 qir_FADD(c, diff, qir_uniform_f(c, 1.0)),
617 diff);
618 }
619
620 /**
621 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
622 * zero).
623 */
624 static struct qreg
625 tgsi_to_qir_flr(struct vc4_compile *c,
626 struct tgsi_full_instruction *tgsi_inst,
627 enum qop op, struct qreg *src, int i)
628 {
629 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
630
631 /* This will be < 0 if we truncated and the truncation was of a value
632 * that was < 0 in the first place.
633 */
634 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], trunc));
635
636 return qir_SEL_X_Y_NS(c,
637 qir_FSUB(c, trunc, qir_uniform_f(c, 1.0)),
638 trunc);
639 }
640
641 static struct qreg
642 tgsi_to_qir_dp(struct vc4_compile *c,
643 struct tgsi_full_instruction *tgsi_inst,
644 int num, struct qreg *src, int i)
645 {
646 struct qreg sum = qir_FMUL(c, src[0 * 4 + 0], src[1 * 4 + 0]);
647 for (int j = 1; j < num; j++) {
648 sum = qir_FADD(c, sum, qir_FMUL(c,
649 src[0 * 4 + j],
650 src[1 * 4 + j]));
651 }
652 return sum;
653 }
654
655 static struct qreg
656 tgsi_to_qir_dp2(struct vc4_compile *c,
657 struct tgsi_full_instruction *tgsi_inst,
658 enum qop op, struct qreg *src, int i)
659 {
660 return tgsi_to_qir_dp(c, tgsi_inst, 2, src, i);
661 }
662
663 static struct qreg
664 tgsi_to_qir_dp3(struct vc4_compile *c,
665 struct tgsi_full_instruction *tgsi_inst,
666 enum qop op, struct qreg *src, int i)
667 {
668 return tgsi_to_qir_dp(c, tgsi_inst, 3, src, i);
669 }
670
671 static struct qreg
672 tgsi_to_qir_dp4(struct vc4_compile *c,
673 struct tgsi_full_instruction *tgsi_inst,
674 enum qop op, struct qreg *src, int i)
675 {
676 return tgsi_to_qir_dp(c, tgsi_inst, 4, src, i);
677 }
678
679 static struct qreg
680 tgsi_to_qir_abs(struct vc4_compile *c,
681 struct tgsi_full_instruction *tgsi_inst,
682 enum qop op, struct qreg *src, int i)
683 {
684 struct qreg arg = src[0 * 4 + i];
685 return qir_FMAXABS(c, arg, arg);
686 }
687
688 /* Note that this instruction replicates its result from the x channel */
689 static struct qreg
690 tgsi_to_qir_sin(struct vc4_compile *c,
691 struct tgsi_full_instruction *tgsi_inst,
692 enum qop op, struct qreg *src, int i)
693 {
694 float coeff[] = {
695 2.0 * M_PI,
696 -pow(2.0 * M_PI, 3) / (3 * 2 * 1),
697 pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
698 -pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
699 };
700
701 struct qreg scaled_x =
702 qir_FMUL(c,
703 src[0 * 4 + 0],
704 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
705
706
707 struct qreg x = tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0);
708 struct qreg x2 = qir_FMUL(c, x, x);
709 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
710 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
711 x = qir_FMUL(c, x, x2);
712 sum = qir_FADD(c,
713 sum,
714 qir_FMUL(c,
715 x,
716 qir_uniform_f(c, coeff[i])));
717 }
718 return sum;
719 }
720
721 /* Note that this instruction replicates its result from the x channel */
722 static struct qreg
723 tgsi_to_qir_cos(struct vc4_compile *c,
724 struct tgsi_full_instruction *tgsi_inst,
725 enum qop op, struct qreg *src, int i)
726 {
727 float coeff[] = {
728 1.0f,
729 -pow(2.0 * M_PI, 2) / (2 * 1),
730 pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
731 -pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
732 };
733
734 struct qreg scaled_x =
735 qir_FMUL(c, src[0 * 4 + 0],
736 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
737 struct qreg x_frac = tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0);
738
739 struct qreg sum = qir_uniform_f(c, coeff[0]);
740 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
741 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
742 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
743 if (i != 1)
744 x = qir_FMUL(c, x, x2);
745
746 struct qreg mul = qir_FMUL(c,
747 x,
748 qir_uniform_f(c, coeff[i]));
749 if (i == 0)
750 sum = mul;
751 else
752 sum = qir_FADD(c, sum, mul);
753 }
754 return sum;
755 }
756
757 static void
758 emit_vertex_input(struct vc4_compile *c, int attr)
759 {
760 enum pipe_format format = c->vs_key->attr_formats[attr];
761 struct qreg vpm_reads[4];
762
763 /* Right now, we're setting the VPM offsets to be 16 bytes wide every
764 * time, so we always read 4 32-bit VPM entries.
765 */
766 for (int i = 0; i < 4; i++) {
767 vpm_reads[i] = qir_get_temp(c);
768 qir_emit(c, qir_inst(QOP_VPM_READ,
769 vpm_reads[i],
770 c->undef,
771 c->undef));
772 c->num_inputs++;
773 }
774
775 bool format_warned = false;
776 const struct util_format_description *desc =
777 util_format_description(format);
778
779 for (int i = 0; i < 4; i++) {
780 uint8_t swiz = desc->swizzle[i];
781
782 if (swiz <= UTIL_FORMAT_SWIZZLE_W &&
783 !format_warned &&
784 (desc->channel[swiz].type != UTIL_FORMAT_TYPE_FLOAT ||
785 desc->channel[swiz].size != 32)) {
786 fprintf(stderr,
787 "vtx element %d unsupported type: %s\n",
788 attr, util_format_name(format));
789 format_warned = true;
790 }
791
792 c->inputs[attr * 4 + i] =
793 get_swizzled_channel(c, vpm_reads, swiz);
794 }
795 }
796
797 static void
798 tgsi_to_qir_kill_if(struct vc4_compile *c, struct qreg *src, int i)
799 {
800 if (c->discard.file == QFILE_NULL)
801 c->discard = qir_uniform_f(c, 0.0);
802 qir_SF(c, src[0 * 4 + i]);
803 c->discard = qir_SEL_X_Y_NS(c, qir_uniform_f(c, 1.0),
804 c->discard);
805 }
806
807 static void
808 emit_fragcoord_input(struct vc4_compile *c, int attr)
809 {
810 c->inputs[attr * 4 + 0] = qir_FRAG_X(c);
811 c->inputs[attr * 4 + 1] = qir_FRAG_Y(c);
812 c->inputs[attr * 4 + 2] =
813 qir_FMUL(c,
814 qir_FRAG_Z(c),
815 qir_uniform_f(c, 1.0 / 0xffffff));
816 c->inputs[attr * 4 + 3] = qir_FRAG_RCP_W(c);
817 }
818
819 static struct qreg
820 emit_fragment_varying(struct vc4_compile *c, int index)
821 {
822 struct qreg vary = {
823 QFILE_VARY,
824 index
825 };
826
827 /* XXX: multiply by W */
828 return qir_VARY_ADD_C(c, qir_MOV(c, vary));
829 }
830
831 static void
832 emit_fragment_input(struct vc4_compile *c, int attr)
833 {
834 for (int i = 0; i < 4; i++) {
835 c->inputs[attr * 4 + i] =
836 emit_fragment_varying(c, attr * 4 + i);
837 c->num_inputs++;
838 }
839 }
840
841 static void
842 emit_tgsi_declaration(struct vc4_compile *c,
843 struct tgsi_full_declaration *decl)
844 {
845 switch (decl->Declaration.File) {
846 case TGSI_FILE_INPUT:
847 for (int i = decl->Range.First;
848 i <= decl->Range.Last;
849 i++) {
850 if (c->stage == QSTAGE_FRAG) {
851 if (decl->Semantic.Name ==
852 TGSI_SEMANTIC_POSITION) {
853 emit_fragcoord_input(c, i);
854 } else {
855 emit_fragment_input(c, i);
856 }
857 } else {
858 emit_vertex_input(c, i);
859 }
860 }
861 break;
862 }
863 }
864
865 static void
866 emit_tgsi_instruction(struct vc4_compile *c,
867 struct tgsi_full_instruction *tgsi_inst)
868 {
869 struct {
870 enum qop op;
871 struct qreg (*func)(struct vc4_compile *c,
872 struct tgsi_full_instruction *tgsi_inst,
873 enum qop op,
874 struct qreg *src, int i);
875 } op_trans[] = {
876 [TGSI_OPCODE_MOV] = { QOP_MOV, tgsi_to_qir_alu },
877 [TGSI_OPCODE_ABS] = { 0, tgsi_to_qir_abs },
878 [TGSI_OPCODE_MUL] = { QOP_FMUL, tgsi_to_qir_alu },
879 [TGSI_OPCODE_ADD] = { QOP_FADD, tgsi_to_qir_alu },
880 [TGSI_OPCODE_SUB] = { QOP_FSUB, tgsi_to_qir_alu },
881 [TGSI_OPCODE_MIN] = { QOP_FMIN, tgsi_to_qir_alu },
882 [TGSI_OPCODE_MAX] = { QOP_FMAX, tgsi_to_qir_alu },
883 [TGSI_OPCODE_F2I] = { QOP_FTOI, tgsi_to_qir_alu },
884 [TGSI_OPCODE_I2F] = { QOP_ITOF, tgsi_to_qir_alu },
885 [TGSI_OPCODE_UADD] = { QOP_ADD, tgsi_to_qir_alu },
886 [TGSI_OPCODE_USHR] = { QOP_SHR, tgsi_to_qir_alu },
887 [TGSI_OPCODE_ISHR] = { QOP_ASR, tgsi_to_qir_alu },
888 [TGSI_OPCODE_SHL] = { QOP_SHL, tgsi_to_qir_alu },
889 [TGSI_OPCODE_IMIN] = { QOP_MIN, tgsi_to_qir_alu },
890 [TGSI_OPCODE_IMAX] = { QOP_MAX, tgsi_to_qir_alu },
891 [TGSI_OPCODE_AND] = { QOP_AND, tgsi_to_qir_alu },
892 [TGSI_OPCODE_OR] = { QOP_OR, tgsi_to_qir_alu },
893 [TGSI_OPCODE_XOR] = { QOP_XOR, tgsi_to_qir_alu },
894 [TGSI_OPCODE_NOT] = { QOP_NOT, tgsi_to_qir_alu },
895
896 [TGSI_OPCODE_UMUL] = { 0, tgsi_to_qir_umul },
897 [TGSI_OPCODE_IDIV] = { 0, tgsi_to_qir_idiv },
898 [TGSI_OPCODE_INEG] = { 0, tgsi_to_qir_ineg },
899
900 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_alu },
901 [TGSI_OPCODE_SEQ] = { 0, tgsi_to_qir_seq },
902 [TGSI_OPCODE_SNE] = { 0, tgsi_to_qir_sne },
903 [TGSI_OPCODE_SGE] = { 0, tgsi_to_qir_sge },
904 [TGSI_OPCODE_SLT] = { 0, tgsi_to_qir_slt },
905 [TGSI_OPCODE_FSEQ] = { 0, tgsi_to_qir_fseq },
906 [TGSI_OPCODE_FSNE] = { 0, tgsi_to_qir_fsne },
907 [TGSI_OPCODE_FSGE] = { 0, tgsi_to_qir_fsge },
908 [TGSI_OPCODE_FSLT] = { 0, tgsi_to_qir_fslt },
909 [TGSI_OPCODE_USEQ] = { 0, tgsi_to_qir_useq },
910 [TGSI_OPCODE_USNE] = { 0, tgsi_to_qir_usne },
911 [TGSI_OPCODE_ISGE] = { 0, tgsi_to_qir_isge },
912 [TGSI_OPCODE_ISLT] = { 0, tgsi_to_qir_islt },
913
914 [TGSI_OPCODE_CMP] = { 0, tgsi_to_qir_cmp },
915 [TGSI_OPCODE_MAD] = { 0, tgsi_to_qir_mad },
916 [TGSI_OPCODE_DP2] = { 0, tgsi_to_qir_dp2 },
917 [TGSI_OPCODE_DP3] = { 0, tgsi_to_qir_dp3 },
918 [TGSI_OPCODE_DP4] = { 0, tgsi_to_qir_dp4 },
919 [TGSI_OPCODE_RCP] = { QOP_RCP, tgsi_to_qir_alu },
920 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_alu },
921 [TGSI_OPCODE_EX2] = { QOP_EXP2, tgsi_to_qir_alu },
922 [TGSI_OPCODE_LG2] = { QOP_LOG2, tgsi_to_qir_alu },
923 [TGSI_OPCODE_LIT] = { 0, tgsi_to_qir_lit },
924 [TGSI_OPCODE_LRP] = { 0, tgsi_to_qir_lrp },
925 [TGSI_OPCODE_POW] = { 0, tgsi_to_qir_pow },
926 [TGSI_OPCODE_TRUNC] = { 0, tgsi_to_qir_trunc },
927 [TGSI_OPCODE_FRC] = { 0, tgsi_to_qir_frc },
928 [TGSI_OPCODE_FLR] = { 0, tgsi_to_qir_flr },
929 [TGSI_OPCODE_SIN] = { 0, tgsi_to_qir_sin },
930 [TGSI_OPCODE_COS] = { 0, tgsi_to_qir_cos },
931 };
932 static int asdf = 0;
933 uint32_t tgsi_op = tgsi_inst->Instruction.Opcode;
934
935 if (tgsi_op == TGSI_OPCODE_END)
936 return;
937
938 struct qreg src_regs[12];
939 for (int s = 0; s < 3; s++) {
940 for (int i = 0; i < 4; i++) {
941 src_regs[4 * s + i] =
942 get_src(c, tgsi_inst->Instruction.Opcode,
943 &tgsi_inst->Src[s].Register, i);
944 }
945 }
946
947 switch (tgsi_op) {
948 case TGSI_OPCODE_TEX:
949 case TGSI_OPCODE_TXP:
950 case TGSI_OPCODE_TXB:
951 tgsi_to_qir_tex(c, tgsi_inst,
952 op_trans[tgsi_op].op, src_regs);
953 return;
954 case TGSI_OPCODE_KILL:
955 c->discard = qir_uniform_f(c, 1.0);
956 return;
957 case TGSI_OPCODE_KILL_IF:
958 for (int i = 0; i < 4; i++)
959 tgsi_to_qir_kill_if(c, src_regs, i);
960 return;
961 default:
962 break;
963 }
964
965 if (tgsi_op > ARRAY_SIZE(op_trans) || !(op_trans[tgsi_op].func)) {
966 fprintf(stderr, "unknown tgsi inst: ");
967 tgsi_dump_instruction(tgsi_inst, asdf++);
968 fprintf(stderr, "\n");
969 abort();
970 }
971
972 for (int i = 0; i < 4; i++) {
973 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
974 continue;
975
976 struct qreg result;
977
978 result = op_trans[tgsi_op].func(c, tgsi_inst,
979 op_trans[tgsi_op].op,
980 src_regs, i);
981
982 if (tgsi_inst->Instruction.Saturate) {
983 float low = (tgsi_inst->Instruction.Saturate ==
984 TGSI_SAT_MINUS_PLUS_ONE ? -1.0 : 0.0);
985 result = qir_FMAX(c,
986 qir_FMIN(c,
987 result,
988 qir_uniform_f(c, 1.0)),
989 qir_uniform_f(c, low));
990 }
991
992 update_dst(c, tgsi_inst, i, result);
993 }
994 }
995
996 static void
997 parse_tgsi_immediate(struct vc4_compile *c, struct tgsi_full_immediate *imm)
998 {
999 for (int i = 0; i < 4; i++) {
1000 unsigned n = c->num_consts++;
1001 c->consts[n] = qir_uniform_ui(c, imm->u[i].Uint);
1002 }
1003 }
1004
1005 static struct qreg
1006 vc4_blend_channel(struct vc4_compile *c,
1007 struct qreg *dst,
1008 struct qreg *src,
1009 struct qreg val,
1010 unsigned factor,
1011 int channel)
1012 {
1013 switch(factor) {
1014 case PIPE_BLENDFACTOR_ONE:
1015 return val;
1016 case PIPE_BLENDFACTOR_SRC_COLOR:
1017 return qir_FMUL(c, val, src[channel]);
1018 case PIPE_BLENDFACTOR_SRC_ALPHA:
1019 return qir_FMUL(c, val, src[3]);
1020 case PIPE_BLENDFACTOR_DST_ALPHA:
1021 return qir_FMUL(c, val, dst[3]);
1022 case PIPE_BLENDFACTOR_DST_COLOR:
1023 return qir_FMUL(c, val, dst[channel]);
1024 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
1025 return qir_FMIN(c, src[3], qir_FSUB(c,
1026 qir_uniform_f(c, 1.0),
1027 dst[3]));
1028 case PIPE_BLENDFACTOR_CONST_COLOR:
1029 return qir_FMUL(c, val,
1030 get_temp_for_uniform(c,
1031 QUNIFORM_BLEND_CONST_COLOR,
1032 channel));
1033 case PIPE_BLENDFACTOR_CONST_ALPHA:
1034 return qir_FMUL(c, val,
1035 get_temp_for_uniform(c,
1036 QUNIFORM_BLEND_CONST_COLOR,
1037 3));
1038 case PIPE_BLENDFACTOR_ZERO:
1039 return qir_uniform_f(c, 0.0);
1040 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
1041 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1042 src[channel]));
1043 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
1044 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1045 src[3]));
1046 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
1047 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1048 dst[3]));
1049 case PIPE_BLENDFACTOR_INV_DST_COLOR:
1050 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1051 dst[channel]));
1052 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
1053 return qir_FMUL(c, val,
1054 qir_FSUB(c, qir_uniform_f(c, 1.0),
1055 get_temp_for_uniform(c,
1056 QUNIFORM_BLEND_CONST_COLOR,
1057 channel)));
1058 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
1059 return qir_FMUL(c, val,
1060 qir_FSUB(c, qir_uniform_f(c, 1.0),
1061 get_temp_for_uniform(c,
1062 QUNIFORM_BLEND_CONST_COLOR,
1063 3)));
1064
1065 default:
1066 case PIPE_BLENDFACTOR_SRC1_COLOR:
1067 case PIPE_BLENDFACTOR_SRC1_ALPHA:
1068 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
1069 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
1070 /* Unsupported. */
1071 fprintf(stderr, "Unknown blend factor %d\n", factor);
1072 return val;
1073 }
1074 }
1075
1076 static struct qreg
1077 vc4_blend_func(struct vc4_compile *c,
1078 struct qreg src, struct qreg dst,
1079 unsigned func)
1080 {
1081 switch (func) {
1082 case PIPE_BLEND_ADD:
1083 return qir_FADD(c, src, dst);
1084 case PIPE_BLEND_SUBTRACT:
1085 return qir_FSUB(c, src, dst);
1086 case PIPE_BLEND_REVERSE_SUBTRACT:
1087 return qir_FSUB(c, dst, src);
1088 case PIPE_BLEND_MIN:
1089 return qir_FMIN(c, src, dst);
1090 case PIPE_BLEND_MAX:
1091 return qir_FMAX(c, src, dst);
1092
1093 default:
1094 /* Unsupported. */
1095 fprintf(stderr, "Unknown blend func %d\n", func);
1096 return src;
1097
1098 }
1099 }
1100
1101 /**
1102 * Implements fixed function blending in shader code.
1103 *
1104 * VC4 doesn't have any hardware support for blending. Instead, you read the
1105 * current contents of the destination from the tile buffer after having
1106 * waited for the scoreboard (which is handled by vc4_qpu_emit.c), then do
1107 * math using your output color and that destination value, and update the
1108 * output color appropriately.
1109 */
1110 static void
1111 vc4_blend(struct vc4_compile *c, struct qreg *result,
1112 struct qreg *dst_color, struct qreg *src_color)
1113 {
1114 struct pipe_rt_blend_state *blend = &c->fs_key->blend;
1115
1116 if (!blend->blend_enable) {
1117 for (int i = 0; i < 4; i++)
1118 result[i] = src_color[i];
1119 return;
1120 }
1121
1122 struct qreg src_blend[4], dst_blend[4];
1123 for (int i = 0; i < 3; i++) {
1124 src_blend[i] = vc4_blend_channel(c,
1125 dst_color, src_color,
1126 src_color[i],
1127 blend->rgb_src_factor, i);
1128 dst_blend[i] = vc4_blend_channel(c,
1129 dst_color, src_color,
1130 dst_color[i],
1131 blend->rgb_dst_factor, i);
1132 }
1133 src_blend[3] = vc4_blend_channel(c,
1134 dst_color, src_color,
1135 src_color[3],
1136 blend->alpha_src_factor, 3);
1137 dst_blend[3] = vc4_blend_channel(c,
1138 dst_color, src_color,
1139 dst_color[3],
1140 blend->alpha_dst_factor, 3);
1141
1142 for (int i = 0; i < 3; i++) {
1143 result[i] = vc4_blend_func(c,
1144 src_blend[i], dst_blend[i],
1145 blend->rgb_func);
1146 }
1147 result[3] = vc4_blend_func(c,
1148 src_blend[3], dst_blend[3],
1149 blend->alpha_func);
1150 }
1151
1152 static void
1153 emit_frag_end(struct vc4_compile *c)
1154 {
1155 struct qreg src_color[4] = {
1156 c->outputs[0], c->outputs[1], c->outputs[2], c->outputs[3],
1157 };
1158
1159 enum pipe_format color_format = c->fs_key->color_format;
1160 const uint8_t *format_swiz = vc4_get_format_swizzle(color_format);
1161 struct qreg tlb_read_color[4] = { c->undef, c->undef, c->undef, c->undef };
1162 struct qreg dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1163 if (c->fs_key->blend.blend_enable ||
1164 c->fs_key->blend.colormask != 0xf) {
1165 struct qreg r4 = qir_TLB_COLOR_READ(c);
1166 for (int i = 0; i < 4; i++)
1167 tlb_read_color[i] = qir_R4_UNPACK(c, r4, i);
1168 for (int i = 0; i < 4; i++)
1169 dst_color[i] = get_swizzled_channel(c,
1170 tlb_read_color,
1171 format_swiz[i]);
1172 }
1173
1174 struct qreg blend_color[4];
1175 vc4_blend(c, blend_color, dst_color, src_color);
1176
1177 /* If the bit isn't set in the color mask, then just return the
1178 * original dst color, instead.
1179 */
1180 for (int i = 0; i < 4; i++) {
1181 if (!(c->fs_key->blend.colormask & (1 << i))) {
1182 blend_color[i] = dst_color[i];
1183 }
1184 }
1185
1186 /* Debug: Sometimes you're getting a black output and just want to see
1187 * if the FS is getting executed at all. Spam magenta into the color
1188 * output.
1189 */
1190 if (0) {
1191 blend_color[0] = qir_uniform_f(c, 1.0);
1192 blend_color[1] = qir_uniform_f(c, 0.0);
1193 blend_color[2] = qir_uniform_f(c, 1.0);
1194 blend_color[3] = qir_uniform_f(c, 0.5);
1195 }
1196
1197 struct qreg swizzled_outputs[4];
1198 for (int i = 0; i < 4; i++) {
1199 swizzled_outputs[i] = get_swizzled_channel(c, blend_color,
1200 format_swiz[i]);
1201 }
1202
1203 if (c->discard.file != QFILE_NULL)
1204 qir_TLB_DISCARD_SETUP(c, c->discard);
1205
1206 if (c->fs_key->depth_enabled) {
1207 qir_emit(c, qir_inst(QOP_TLB_PASSTHROUGH_Z_WRITE, c->undef,
1208 c->undef, c->undef));
1209 }
1210
1211 bool color_written = false;
1212 for (int i = 0; i < 4; i++) {
1213 if (swizzled_outputs[i].file != QFILE_NULL)
1214 color_written = true;
1215 }
1216
1217 struct qreg packed_color;
1218 if (color_written) {
1219 /* Fill in any undefined colors. The simulator will assertion
1220 * fail if we read something that wasn't written, and I don't
1221 * know what hardware does.
1222 */
1223 for (int i = 0; i < 4; i++) {
1224 if (swizzled_outputs[i].file == QFILE_NULL)
1225 swizzled_outputs[i] = qir_uniform_f(c, 0.0);
1226 }
1227 packed_color = qir_get_temp(c);
1228 qir_emit(c, qir_inst4(QOP_PACK_COLORS, packed_color,
1229 swizzled_outputs[0],
1230 swizzled_outputs[1],
1231 swizzled_outputs[2],
1232 swizzled_outputs[3]));
1233 } else {
1234 packed_color = qir_uniform_ui(c, 0);
1235 }
1236
1237 qir_emit(c, qir_inst(QOP_TLB_COLOR_WRITE, c->undef,
1238 packed_color, c->undef));
1239 }
1240
1241 static void
1242 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1243 {
1244 struct qreg xyi[2];
1245
1246 for (int i = 0; i < 2; i++) {
1247 struct qreg scale =
1248 add_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1249
1250 xyi[i] = qir_FTOI(c, qir_FMUL(c,
1251 qir_FMUL(c,
1252 c->outputs[i],
1253 scale),
1254 rcp_w));
1255 }
1256
1257 qir_VPM_WRITE(c, qir_PACK_SCALED(c, xyi[0], xyi[1]));
1258 }
1259
1260 static void
1261 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1262 {
1263 struct qreg zscale = add_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1264 struct qreg zoffset = add_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1265
1266 qir_VPM_WRITE(c, qir_FMUL(c, qir_FADD(c, qir_FMUL(c,
1267 c->outputs[2],
1268 zscale),
1269 zoffset),
1270 rcp_w));
1271 }
1272
1273 static void
1274 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1275 {
1276 qir_VPM_WRITE(c, rcp_w);
1277 }
1278
1279 static void
1280 emit_vert_end(struct vc4_compile *c)
1281 {
1282 struct qreg rcp_w = qir_RCP(c, c->outputs[3]);
1283
1284 emit_scaled_viewport_write(c, rcp_w);
1285 emit_zs_write(c, rcp_w);
1286 emit_rcp_wc_write(c, rcp_w);
1287
1288 for (int i = 4; i < c->num_outputs; i++) {
1289 qir_VPM_WRITE(c, c->outputs[i]);
1290 }
1291 }
1292
1293 static void
1294 emit_coord_end(struct vc4_compile *c)
1295 {
1296 struct qreg rcp_w = qir_RCP(c, c->outputs[3]);
1297
1298 for (int i = 0; i < 4; i++)
1299 qir_VPM_WRITE(c, c->outputs[i]);
1300
1301 emit_scaled_viewport_write(c, rcp_w);
1302 emit_zs_write(c, rcp_w);
1303 emit_rcp_wc_write(c, rcp_w);
1304 }
1305
1306 static struct vc4_compile *
1307 vc4_shader_tgsi_to_qir(struct vc4_compiled_shader *shader, enum qstage stage,
1308 struct vc4_key *key)
1309 {
1310 struct vc4_compile *c = qir_compile_init();
1311 int ret;
1312
1313 c->stage = stage;
1314
1315 /* XXX sizing */
1316 c->temps = ralloc_array(c, struct qreg, 1024);
1317 c->inputs = ralloc_array(c, struct qreg, 8 * 4);
1318 c->outputs = ralloc_array(c, struct qreg, 1024);
1319 c->uniforms = ralloc_array(c, struct qreg, 1024);
1320 c->consts = ralloc_array(c, struct qreg, 1024);
1321
1322 c->uniform_data = ralloc_array(c, uint32_t, 1024);
1323 c->uniform_contents = ralloc_array(c, enum quniform_contents, 1024);
1324
1325 c->shader_state = key->shader_state;
1326 ret = tgsi_parse_init(&c->parser, c->shader_state->tokens);
1327 assert(ret == TGSI_PARSE_OK);
1328
1329 if (vc4_debug & VC4_DEBUG_TGSI) {
1330 fprintf(stderr, "TGSI:\n");
1331 tgsi_dump(c->shader_state->tokens, 0);
1332 }
1333
1334 c->key = key;
1335 switch (stage) {
1336 case QSTAGE_FRAG:
1337 c->fs_key = (struct vc4_fs_key *)key;
1338 if (c->fs_key->is_points) {
1339 c->point_x = emit_fragment_varying(c, 0);
1340 c->point_y = emit_fragment_varying(c, 0);
1341 } else if (c->fs_key->is_lines) {
1342 c->line_x = emit_fragment_varying(c, 0);
1343 }
1344 break;
1345 case QSTAGE_VERT:
1346 c->vs_key = (struct vc4_vs_key *)key;
1347 break;
1348 case QSTAGE_COORD:
1349 c->vs_key = (struct vc4_vs_key *)key;
1350 break;
1351 }
1352
1353 while (!tgsi_parse_end_of_tokens(&c->parser)) {
1354 tgsi_parse_token(&c->parser);
1355
1356 switch (c->parser.FullToken.Token.Type) {
1357 case TGSI_TOKEN_TYPE_DECLARATION:
1358 emit_tgsi_declaration(c,
1359 &c->parser.FullToken.FullDeclaration);
1360 break;
1361
1362 case TGSI_TOKEN_TYPE_INSTRUCTION:
1363 emit_tgsi_instruction(c,
1364 &c->parser.FullToken.FullInstruction);
1365 break;
1366
1367 case TGSI_TOKEN_TYPE_IMMEDIATE:
1368 parse_tgsi_immediate(c,
1369 &c->parser.FullToken.FullImmediate);
1370 break;
1371 }
1372 }
1373
1374 switch (stage) {
1375 case QSTAGE_FRAG:
1376 emit_frag_end(c);
1377 break;
1378 case QSTAGE_VERT:
1379 emit_vert_end(c);
1380 break;
1381 case QSTAGE_COORD:
1382 emit_coord_end(c);
1383 break;
1384 }
1385
1386 tgsi_parse_free(&c->parser);
1387
1388 qir_optimize(c);
1389
1390 if (vc4_debug & VC4_DEBUG_QIR) {
1391 fprintf(stderr, "QIR:\n");
1392 qir_dump(c);
1393 }
1394 vc4_generate_code(c);
1395
1396 if (vc4_debug & VC4_DEBUG_SHADERDB) {
1397 fprintf(stderr, "SHADER-DB: %s: %d instructions\n",
1398 qir_get_stage_name(c->stage), c->qpu_inst_count);
1399 fprintf(stderr, "SHADER-DB: %s: %d uniforms\n",
1400 qir_get_stage_name(c->stage), c->num_uniforms);
1401 }
1402
1403 return c;
1404 }
1405
1406 static void *
1407 vc4_shader_state_create(struct pipe_context *pctx,
1408 const struct pipe_shader_state *cso)
1409 {
1410 struct pipe_shader_state *so = CALLOC_STRUCT(pipe_shader_state);
1411 if (!so)
1412 return NULL;
1413
1414 so->tokens = tgsi_dup_tokens(cso->tokens);
1415
1416 return so;
1417 }
1418
1419 static void
1420 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
1421 int shader_index,
1422 struct vc4_compile *c)
1423 {
1424 int count = c->num_uniforms;
1425 struct vc4_shader_uniform_info *uinfo = &shader->uniforms[shader_index];
1426
1427 uinfo->count = count;
1428 uinfo->data = malloc(count * sizeof(*uinfo->data));
1429 memcpy(uinfo->data, c->uniform_data,
1430 count * sizeof(*uinfo->data));
1431 uinfo->contents = malloc(count * sizeof(*uinfo->contents));
1432 memcpy(uinfo->contents, c->uniform_contents,
1433 count * sizeof(*uinfo->contents));
1434 uinfo->num_texture_samples = c->num_texture_samples;
1435 }
1436
1437 static void
1438 vc4_fs_compile(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1439 struct vc4_fs_key *key)
1440 {
1441 struct vc4_compile *c = vc4_shader_tgsi_to_qir(shader, QSTAGE_FRAG,
1442 &key->base);
1443 shader->num_inputs = c->num_inputs;
1444 copy_uniform_state_to_shader(shader, 0, c);
1445 shader->bo = vc4_bo_alloc_mem(vc4->screen, c->qpu_insts,
1446 c->qpu_inst_count * sizeof(uint64_t),
1447 "fs_code");
1448
1449 qir_compile_destroy(c);
1450 }
1451
1452 static void
1453 vc4_vs_compile(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1454 struct vc4_vs_key *key)
1455 {
1456 struct vc4_compile *vs_c = vc4_shader_tgsi_to_qir(shader,
1457 QSTAGE_VERT,
1458 &key->base);
1459 copy_uniform_state_to_shader(shader, 0, vs_c);
1460
1461 struct vc4_compile *cs_c = vc4_shader_tgsi_to_qir(shader,
1462 QSTAGE_COORD,
1463 &key->base);
1464 copy_uniform_state_to_shader(shader, 1, cs_c);
1465
1466 uint32_t vs_size = vs_c->qpu_inst_count * sizeof(uint64_t);
1467 uint32_t cs_size = cs_c->qpu_inst_count * sizeof(uint64_t);
1468 shader->coord_shader_offset = vs_size; /* XXX: alignment? */
1469 shader->bo = vc4_bo_alloc(vc4->screen,
1470 shader->coord_shader_offset + cs_size,
1471 "vs_code");
1472
1473 void *map = vc4_bo_map(shader->bo);
1474 memcpy(map, vs_c->qpu_insts, vs_size);
1475 memcpy(map + shader->coord_shader_offset,
1476 cs_c->qpu_insts, cs_size);
1477
1478 qir_compile_destroy(vs_c);
1479 qir_compile_destroy(cs_c);
1480 }
1481
1482 static void
1483 vc4_setup_shared_key(struct vc4_key *key, struct vc4_texture_stateobj *texstate)
1484 {
1485 for (int i = 0; i < texstate->num_textures; i++) {
1486 struct pipe_sampler_view *sampler = texstate->textures[i];
1487 struct pipe_sampler_state *sampler_state =
1488 texstate->samplers[i];
1489
1490 if (sampler) {
1491 struct pipe_resource *prsc = sampler->texture;
1492 key->tex[i].format = prsc->format;
1493 key->tex[i].swizzle[0] = sampler->swizzle_r;
1494 key->tex[i].swizzle[1] = sampler->swizzle_g;
1495 key->tex[i].swizzle[2] = sampler->swizzle_b;
1496 key->tex[i].swizzle[3] = sampler->swizzle_a;
1497 key->tex[i].compare_mode = sampler_state->compare_mode;
1498 key->tex[i].compare_func = sampler_state->compare_func;
1499 }
1500 }
1501 }
1502
1503 static void
1504 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
1505 {
1506 struct vc4_fs_key local_key;
1507 struct vc4_fs_key *key = &local_key;
1508
1509 memset(key, 0, sizeof(*key));
1510 vc4_setup_shared_key(&key->base, &vc4->fragtex);
1511 key->base.shader_state = vc4->prog.bind_fs;
1512 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
1513 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
1514 prim_mode <= PIPE_PRIM_LINE_STRIP);
1515 key->blend = vc4->blend->rt[0];
1516
1517 if (vc4->framebuffer.cbufs[0])
1518 key->color_format = vc4->framebuffer.cbufs[0]->format;
1519
1520 key->depth_enabled = vc4->zsa->base.depth.enabled;
1521
1522 vc4->prog.fs = util_hash_table_get(vc4->fs_cache, key);
1523 if (vc4->prog.fs)
1524 return;
1525
1526 key = malloc(sizeof(*key));
1527 memcpy(key, &local_key, sizeof(*key));
1528
1529 struct vc4_compiled_shader *shader = CALLOC_STRUCT(vc4_compiled_shader);
1530 vc4_fs_compile(vc4, shader, key);
1531 util_hash_table_set(vc4->fs_cache, key, shader);
1532
1533 vc4->prog.fs = shader;
1534 }
1535
1536 static void
1537 vc4_update_compiled_vs(struct vc4_context *vc4)
1538 {
1539 struct vc4_vs_key local_key;
1540 struct vc4_vs_key *key = &local_key;
1541
1542 memset(key, 0, sizeof(*key));
1543 vc4_setup_shared_key(&key->base, &vc4->verttex);
1544 key->base.shader_state = vc4->prog.bind_vs;
1545
1546 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
1547 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
1548
1549 vc4->prog.vs = util_hash_table_get(vc4->vs_cache, key);
1550 if (vc4->prog.vs)
1551 return;
1552
1553 key = malloc(sizeof(*key));
1554 memcpy(key, &local_key, sizeof(*key));
1555
1556 struct vc4_compiled_shader *shader = CALLOC_STRUCT(vc4_compiled_shader);
1557 vc4_vs_compile(vc4, shader, key);
1558 util_hash_table_set(vc4->vs_cache, key, shader);
1559
1560 vc4->prog.vs = shader;
1561 }
1562
1563 void
1564 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
1565 {
1566 vc4_update_compiled_fs(vc4, prim_mode);
1567 vc4_update_compiled_vs(vc4);
1568 }
1569
1570 static unsigned
1571 fs_cache_hash(void *key)
1572 {
1573 return util_hash_crc32(key, sizeof(struct vc4_fs_key));
1574 }
1575
1576 static unsigned
1577 vs_cache_hash(void *key)
1578 {
1579 return util_hash_crc32(key, sizeof(struct vc4_vs_key));
1580 }
1581
1582 static int
1583 fs_cache_compare(void *key1, void *key2)
1584 {
1585 return memcmp(key1, key2, sizeof(struct vc4_fs_key));
1586 }
1587
1588 static int
1589 vs_cache_compare(void *key1, void *key2)
1590 {
1591 return memcmp(key1, key2, sizeof(struct vc4_vs_key));
1592 }
1593
1594 struct delete_state {
1595 struct vc4_context *vc4;
1596 struct pipe_shader_state *shader_state;
1597 };
1598
1599 static enum pipe_error
1600 fs_delete_from_cache(void *in_key, void *in_value, void *data)
1601 {
1602 struct delete_state *del = data;
1603 struct vc4_fs_key *key = in_key;
1604 struct vc4_compiled_shader *shader = in_value;
1605
1606 if (key->base.shader_state == data) {
1607 util_hash_table_remove(del->vc4->fs_cache, key);
1608 vc4_bo_unreference(&shader->bo);
1609 free(shader);
1610 }
1611
1612 return 0;
1613 }
1614
1615 static enum pipe_error
1616 vs_delete_from_cache(void *in_key, void *in_value, void *data)
1617 {
1618 struct delete_state *del = data;
1619 struct vc4_vs_key *key = in_key;
1620 struct vc4_compiled_shader *shader = in_value;
1621
1622 if (key->base.shader_state == data) {
1623 util_hash_table_remove(del->vc4->vs_cache, key);
1624 vc4_bo_unreference(&shader->bo);
1625 free(shader);
1626 }
1627
1628 return 0;
1629 }
1630
1631 static void
1632 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
1633 {
1634 struct vc4_context *vc4 = vc4_context(pctx);
1635 struct pipe_shader_state *so = hwcso;
1636 struct delete_state del;
1637
1638 del.vc4 = vc4;
1639 del.shader_state = so;
1640 util_hash_table_foreach(vc4->fs_cache, fs_delete_from_cache, &del);
1641 util_hash_table_foreach(vc4->vs_cache, vs_delete_from_cache, &del);
1642
1643 free((void *)so->tokens);
1644 free(so);
1645 }
1646
1647 static uint32_t translate_wrap(uint32_t p_wrap)
1648 {
1649 switch (p_wrap) {
1650 case PIPE_TEX_WRAP_REPEAT:
1651 return 0;
1652 case PIPE_TEX_WRAP_CLAMP:
1653 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1654 return 1;
1655 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1656 return 2;
1657 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1658 return 3;
1659 default:
1660 fprintf(stderr, "Unknown wrap mode %d\n", p_wrap);
1661 assert(!"not reached");
1662 return 0;
1663 }
1664 }
1665
1666 static void
1667 write_texture_p0(struct vc4_context *vc4,
1668 struct vc4_texture_stateobj *texstate,
1669 uint32_t unit)
1670 {
1671 struct pipe_sampler_view *texture = texstate->textures[unit];
1672 struct vc4_resource *rsc = vc4_resource(texture->texture);
1673
1674 cl_reloc(vc4, &vc4->uniforms, rsc->bo,
1675 rsc->slices[0].offset | texture->u.tex.last_level |
1676 ((rsc->vc4_format & 7) << 4));
1677 }
1678
1679 static void
1680 write_texture_p1(struct vc4_context *vc4,
1681 struct vc4_texture_stateobj *texstate,
1682 uint32_t unit)
1683 {
1684 struct pipe_sampler_view *texture = texstate->textures[unit];
1685 struct vc4_resource *rsc = vc4_resource(texture->texture);
1686 struct pipe_sampler_state *sampler = texstate->samplers[unit];
1687 static const uint32_t mipfilter_map[] = {
1688 [PIPE_TEX_MIPFILTER_NEAREST] = 2,
1689 [PIPE_TEX_MIPFILTER_LINEAR] = 4,
1690 [PIPE_TEX_MIPFILTER_NONE] = 0
1691 };
1692 static const uint32_t imgfilter_map[] = {
1693 [PIPE_TEX_FILTER_NEAREST] = 1,
1694 [PIPE_TEX_FILTER_LINEAR] = 0,
1695 };
1696
1697 cl_u32(&vc4->uniforms,
1698 ((rsc->vc4_format >> 4) << 31) |
1699 (texture->texture->height0 << 20) |
1700 (texture->texture->width0 << 8) |
1701 (imgfilter_map[sampler->mag_img_filter] << 7) |
1702 ((imgfilter_map[sampler->min_img_filter] +
1703 mipfilter_map[sampler->min_mip_filter]) << 4) |
1704 (translate_wrap(sampler->wrap_t) << 2) |
1705 (translate_wrap(sampler->wrap_s) << 0));
1706 }
1707
1708 static uint32_t
1709 get_texrect_scale(struct vc4_texture_stateobj *texstate,
1710 enum quniform_contents contents,
1711 uint32_t data)
1712 {
1713 struct pipe_sampler_view *texture = texstate->textures[data];
1714 uint32_t dim;
1715
1716 if (contents == QUNIFORM_TEXRECT_SCALE_X)
1717 dim = texture->texture->width0;
1718 else
1719 dim = texture->texture->height0;
1720
1721 return fui(1.0f / dim);
1722 }
1723
1724 void
1725 vc4_write_uniforms(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1726 struct vc4_constbuf_stateobj *cb,
1727 struct vc4_texture_stateobj *texstate,
1728 int shader_index)
1729 {
1730 struct vc4_shader_uniform_info *uinfo = &shader->uniforms[shader_index];
1731 const uint32_t *gallium_uniforms = cb->cb[0].user_buffer;
1732
1733 cl_start_shader_reloc(&vc4->uniforms, uinfo->num_texture_samples);
1734
1735 for (int i = 0; i < uinfo->count; i++) {
1736
1737 switch (uinfo->contents[i]) {
1738 case QUNIFORM_CONSTANT:
1739 cl_u32(&vc4->uniforms, uinfo->data[i]);
1740 break;
1741 case QUNIFORM_UNIFORM:
1742 cl_u32(&vc4->uniforms,
1743 gallium_uniforms[uinfo->data[i]]);
1744 break;
1745 case QUNIFORM_VIEWPORT_X_SCALE:
1746 cl_f(&vc4->uniforms, vc4->viewport.scale[0] * 16.0f);
1747 break;
1748 case QUNIFORM_VIEWPORT_Y_SCALE:
1749 cl_f(&vc4->uniforms, vc4->viewport.scale[1] * 16.0f);
1750 break;
1751
1752 case QUNIFORM_VIEWPORT_Z_OFFSET:
1753 cl_f(&vc4->uniforms, vc4->viewport.translate[2]);
1754 break;
1755 case QUNIFORM_VIEWPORT_Z_SCALE:
1756 cl_f(&vc4->uniforms, vc4->viewport.scale[2]);
1757 break;
1758
1759 case QUNIFORM_TEXTURE_CONFIG_P0:
1760 write_texture_p0(vc4, texstate, uinfo->data[i]);
1761 break;
1762
1763 case QUNIFORM_TEXTURE_CONFIG_P1:
1764 write_texture_p1(vc4, texstate, uinfo->data[i]);
1765 break;
1766
1767 case QUNIFORM_TEXRECT_SCALE_X:
1768 case QUNIFORM_TEXRECT_SCALE_Y:
1769 cl_u32(&vc4->uniforms,
1770 get_texrect_scale(texstate,
1771 uinfo->contents[i],
1772 uinfo->data[i]));
1773 break;
1774
1775 case QUNIFORM_BLEND_CONST_COLOR:
1776 cl_f(&vc4->uniforms,
1777 vc4->blend_color.color[uinfo->data[i]]);
1778 break;
1779 }
1780 #if 0
1781 uint32_t written_val = *(uint32_t *)(vc4->uniforms.next - 4);
1782 fprintf(stderr, "%p/%d: %d: 0x%08x (%f)\n",
1783 shader, shader_index, i, written_val, uif(written_val));
1784 #endif
1785 }
1786 }
1787
1788 static void
1789 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
1790 {
1791 struct vc4_context *vc4 = vc4_context(pctx);
1792 vc4->prog.bind_fs = hwcso;
1793 vc4->prog.dirty |= VC4_SHADER_DIRTY_FP;
1794 vc4->dirty |= VC4_DIRTY_PROG;
1795 }
1796
1797 static void
1798 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
1799 {
1800 struct vc4_context *vc4 = vc4_context(pctx);
1801 vc4->prog.bind_vs = hwcso;
1802 vc4->prog.dirty |= VC4_SHADER_DIRTY_VP;
1803 vc4->dirty |= VC4_DIRTY_PROG;
1804 }
1805
1806 void
1807 vc4_program_init(struct pipe_context *pctx)
1808 {
1809 struct vc4_context *vc4 = vc4_context(pctx);
1810
1811 pctx->create_vs_state = vc4_shader_state_create;
1812 pctx->delete_vs_state = vc4_shader_state_delete;
1813
1814 pctx->create_fs_state = vc4_shader_state_create;
1815 pctx->delete_fs_state = vc4_shader_state_delete;
1816
1817 pctx->bind_fs_state = vc4_fp_state_bind;
1818 pctx->bind_vs_state = vc4_vp_state_bind;
1819
1820 vc4->fs_cache = util_hash_table_create(fs_cache_hash, fs_cache_compare);
1821 vc4->vs_cache = util_hash_table_create(vs_cache_hash, vs_cache_compare);
1822 }