gallium: enable GL_AMD_depth_clamp_separate on r600, radeonsi
[mesa.git] / src / gallium / drivers / virgl / virgl_screen.c
1 /*
2 * Copyright 2014, 2015 Red Hat.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "util/u_memory.h"
24 #include "util/u_format.h"
25 #include "util/u_format_s3tc.h"
26 #include "util/u_screen.h"
27 #include "util/u_video.h"
28 #include "util/u_math.h"
29 #include "util/os_time.h"
30 #include "pipe/p_defines.h"
31 #include "pipe/p_screen.h"
32
33 #include "tgsi/tgsi_exec.h"
34
35 #include "virgl_screen.h"
36 #include "virgl_resource.h"
37 #include "virgl_public.h"
38 #include "virgl_context.h"
39
40 int virgl_debug = 0;
41 static const struct debug_named_value debug_options[] = {
42 { "verbose", VIRGL_DEBUG_VERBOSE, NULL },
43 { "tgsi", VIRGL_DEBUG_TGSI, NULL },
44 DEBUG_NAMED_VALUE_END
45 };
46 DEBUG_GET_ONCE_FLAGS_OPTION(virgl_debug, "VIRGL_DEBUG", debug_options, 0)
47
48 static const char *
49 virgl_get_vendor(struct pipe_screen *screen)
50 {
51 return "Red Hat";
52 }
53
54
55 static const char *
56 virgl_get_name(struct pipe_screen *screen)
57 {
58 return "virgl";
59 }
60
61 static int
62 virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
63 {
64 struct virgl_screen *vscreen = virgl_screen(screen);
65 switch (param) {
66 case PIPE_CAP_NPOT_TEXTURES:
67 return 1;
68 case PIPE_CAP_SM3:
69 return 1;
70 case PIPE_CAP_ANISOTROPIC_FILTER:
71 return 1;
72 case PIPE_CAP_POINT_SPRITE:
73 return 1;
74 case PIPE_CAP_MAX_RENDER_TARGETS:
75 return vscreen->caps.caps.v1.max_render_targets;
76 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
77 return vscreen->caps.caps.v1.max_dual_source_render_targets;
78 case PIPE_CAP_OCCLUSION_QUERY:
79 return vscreen->caps.caps.v1.bset.occlusion_query;
80 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
81 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
82 return vscreen->caps.caps.v1.bset.mirror_clamp;
83 case PIPE_CAP_TEXTURE_SWIZZLE:
84 return 1;
85 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
86 if (vscreen->caps.caps.v2.max_texture_2d_size)
87 return 1 + util_logbase2(vscreen->caps.caps.v2.max_texture_2d_size);
88 return 15; /* 16K x 16K */
89 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
90 if (vscreen->caps.caps.v2.max_texture_3d_size)
91 return 1 + util_logbase2(vscreen->caps.caps.v2.max_texture_3d_size);
92 return 9; /* 256 x 256 x 256 */
93 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
94 if (vscreen->caps.caps.v2.max_texture_cube_size)
95 return 1 + util_logbase2(vscreen->caps.caps.v2.max_texture_cube_size);
96 return 13; /* 4K x 4K */
97 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
98 return 1;
99 case PIPE_CAP_INDEP_BLEND_ENABLE:
100 return vscreen->caps.caps.v1.bset.indep_blend_enable;
101 case PIPE_CAP_INDEP_BLEND_FUNC:
102 return vscreen->caps.caps.v1.bset.indep_blend_func;
103 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
104 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
105 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
106 return 1;
107 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
108 return vscreen->caps.caps.v1.bset.fragment_coord_conventions;
109 case PIPE_CAP_DEPTH_CLIP_DISABLE:
110 return vscreen->caps.caps.v1.bset.depth_clip_disable;
111 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
112 return vscreen->caps.caps.v1.max_streamout_buffers;
113 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
114 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
115 return 16*4;
116 case PIPE_CAP_PRIMITIVE_RESTART:
117 return vscreen->caps.caps.v1.bset.primitive_restart;
118 case PIPE_CAP_SHADER_STENCIL_EXPORT:
119 return vscreen->caps.caps.v1.bset.shader_stencil_export;
120 case PIPE_CAP_TGSI_INSTANCEID:
121 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
122 return 1;
123 case PIPE_CAP_SEAMLESS_CUBE_MAP:
124 return vscreen->caps.caps.v1.bset.seamless_cube_map;
125 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
126 return vscreen->caps.caps.v1.bset.seamless_cube_map_per_texture;
127 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
128 return vscreen->caps.caps.v1.max_texture_array_layers;
129 case PIPE_CAP_MIN_TEXEL_OFFSET:
130 return vscreen->caps.caps.v2.min_texel_offset;
131 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
132 return vscreen->caps.caps.v2.min_texture_gather_offset;
133 case PIPE_CAP_MAX_TEXEL_OFFSET:
134 return vscreen->caps.caps.v2.max_texel_offset;
135 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
136 return vscreen->caps.caps.v2.max_texture_gather_offset;
137 case PIPE_CAP_CONDITIONAL_RENDER:
138 return vscreen->caps.caps.v1.bset.conditional_render;
139 case PIPE_CAP_TEXTURE_BARRIER:
140 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TEXTURE_BARRIER;
141 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
142 return 1;
143 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
144 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
145 return vscreen->caps.caps.v1.bset.color_clamping;
146 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
147 return 1;
148 case PIPE_CAP_GLSL_FEATURE_LEVEL:
149 return vscreen->caps.caps.v1.glsl_level;
150 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
151 return MIN2(vscreen->caps.caps.v1.glsl_level, 140);
152 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
153 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
154 return 0;
155 case PIPE_CAP_COMPUTE:
156 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER;
157 case PIPE_CAP_USER_VERTEX_BUFFERS:
158 return 0;
159 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
160 return vscreen->caps.caps.v2.uniform_buffer_offset_alignment;
161 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
162 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
163 return vscreen->caps.caps.v1.bset.streamout_pause_resume;
164 case PIPE_CAP_START_INSTANCE:
165 return vscreen->caps.caps.v1.bset.start_instance;
166 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
167 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
168 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
169 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
170 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
171 return 0;
172 case PIPE_CAP_QUERY_TIMESTAMP:
173 return 1;
174 case PIPE_CAP_QUERY_TIME_ELAPSED:
175 return 0;
176 case PIPE_CAP_TGSI_TEXCOORD:
177 return 0;
178 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
179 return VIRGL_MAP_BUFFER_ALIGNMENT;
180 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
181 return vscreen->caps.caps.v1.max_tbo_size > 0;
182 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
183 return vscreen->caps.caps.v2.texture_buffer_offset_alignment;
184 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
185 return 0;
186 case PIPE_CAP_CUBE_MAP_ARRAY:
187 return vscreen->caps.caps.v1.bset.cube_map_array;
188 case PIPE_CAP_TEXTURE_MULTISAMPLE:
189 return vscreen->caps.caps.v1.bset.texture_multisample;
190 case PIPE_CAP_MAX_VIEWPORTS:
191 return vscreen->caps.caps.v1.max_viewports;
192 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
193 return vscreen->caps.caps.v1.max_tbo_size;
194 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
195 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
196 case PIPE_CAP_ENDIANNESS:
197 return 0;
198 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
199 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
200 return 1;
201 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
202 return 0;
203 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
204 return vscreen->caps.caps.v2.max_geom_output_vertices;
205 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
206 return vscreen->caps.caps.v2.max_geom_total_output_components;
207 case PIPE_CAP_TEXTURE_QUERY_LOD:
208 return vscreen->caps.caps.v1.bset.texture_query_lod;
209 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
210 return vscreen->caps.caps.v1.max_texture_gather_components;
211 case PIPE_CAP_DRAW_INDIRECT:
212 return vscreen->caps.caps.v1.bset.has_indirect_draw;
213 case PIPE_CAP_SAMPLE_SHADING:
214 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
215 return vscreen->caps.caps.v1.bset.has_sample_shading;
216 case PIPE_CAP_CULL_DISTANCE:
217 return vscreen->caps.caps.v1.bset.has_cull;
218 case PIPE_CAP_MAX_VERTEX_STREAMS:
219 return vscreen->caps.caps.v1.glsl_level >= 400 ? 4 : 1;
220 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
221 return vscreen->caps.caps.v1.bset.conditional_render_inverted;
222 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
223 return vscreen->caps.caps.v1.bset.derivative_control;
224 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
225 return vscreen->caps.caps.v1.bset.polygon_offset_clamp;
226 case PIPE_CAP_QUERY_SO_OVERFLOW:
227 return vscreen->caps.caps.v1.bset.transform_feedback_overflow_query;
228 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
229 return vscreen->caps.caps.v2.shader_buffer_offset_alignment;
230 case PIPE_CAP_DOUBLES:
231 return vscreen->caps.caps.v1.bset.has_fp64;
232 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
233 return vscreen->caps.caps.v2.max_shader_patch_varyings;
234 case PIPE_CAP_SAMPLER_VIEW_TARGET:
235 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TEXTURE_VIEW;
236 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
237 return vscreen->caps.caps.v2.max_vertex_attrib_stride;
238 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
239 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COPY_IMAGE;
240 case PIPE_CAP_TGSI_TXQS:
241 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TXQS;
242 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
243 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_FB_NO_ATTACH;
244 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
245 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_ROBUST_BUFFER_ACCESS;
246 case PIPE_CAP_TGSI_FS_FBFETCH:
247 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TGSI_FBFETCH;
248 case PIPE_CAP_TGSI_CLOCK:
249 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_SHADER_CLOCK;
250 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
251 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TGSI_COMPONENTS;
252 case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
253 return vscreen->caps.caps.v2.max_combined_shader_buffers;
254 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
255 return vscreen->caps.caps.v2.max_combined_atomic_counters;
256 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
257 return vscreen->caps.caps.v2.max_combined_atomic_counter_buffers;
258 case PIPE_CAP_TEXTURE_GATHER_SM5:
259 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
260 case PIPE_CAP_FAKE_SW_MSAA:
261 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
262 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
263 case PIPE_CAP_MULTI_DRAW_INDIRECT:
264 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
265 case PIPE_CAP_CLIP_HALFZ:
266 case PIPE_CAP_VERTEXID_NOBASE:
267 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
268 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
269 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
270 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
271 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
272 case PIPE_CAP_DEPTH_BOUNDS_TEST:
273 case PIPE_CAP_SHAREABLE_SHADERS:
274 case PIPE_CAP_CLEAR_TEXTURE:
275 case PIPE_CAP_DRAW_PARAMETERS:
276 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
277 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
278 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
279 case PIPE_CAP_INVALIDATE_BUFFER:
280 case PIPE_CAP_GENERATE_MIPMAP:
281 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
282 case PIPE_CAP_QUERY_BUFFER_OBJECT:
283 case PIPE_CAP_STRING_MARKER:
284 case PIPE_CAP_QUERY_MEMORY_INFO:
285 case PIPE_CAP_PCI_GROUP:
286 case PIPE_CAP_PCI_BUS:
287 case PIPE_CAP_PCI_DEVICE:
288 case PIPE_CAP_PCI_FUNCTION:
289 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
290 case PIPE_CAP_TGSI_VOTE:
291 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
292 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
293 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
294 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
295 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
296 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
297 case PIPE_CAP_INT64:
298 case PIPE_CAP_INT64_DIVMOD:
299 case PIPE_CAP_TGSI_TEX_TXF_LZ:
300 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
301 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
302 case PIPE_CAP_TGSI_BALLOT:
303 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
304 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
305 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
306 case PIPE_CAP_POST_DEPTH_COVERAGE:
307 case PIPE_CAP_BINDLESS_TEXTURE:
308 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
309 case PIPE_CAP_MEMOBJ:
310 case PIPE_CAP_LOAD_CONSTBUF:
311 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
312 case PIPE_CAP_TILE_RASTER_ORDER:
313 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
314 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
315 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
316 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
317 case PIPE_CAP_FENCE_SIGNAL:
318 case PIPE_CAP_CONSTBUF0_FLAGS:
319 case PIPE_CAP_PACKED_UNIFORMS:
320 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
321 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
322 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
323 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
324 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
325 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
326 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
327 return 0;
328 case PIPE_CAP_MAX_GS_INVOCATIONS:
329 return 32;
330 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
331 return 1 << 27;
332 case PIPE_CAP_VENDOR_ID:
333 return 0x1af4;
334 case PIPE_CAP_DEVICE_ID:
335 return 0x1010;
336 case PIPE_CAP_ACCELERATED:
337 return 1;
338 case PIPE_CAP_UMA:
339 case PIPE_CAP_VIDEO_MEMORY:
340 return 0;
341 case PIPE_CAP_NATIVE_FENCE_FD:
342 return 0;
343 default:
344 return u_pipe_screen_get_param_defaults(screen, param);
345 }
346 }
347
348 static int
349 virgl_get_shader_param(struct pipe_screen *screen,
350 enum pipe_shader_type shader,
351 enum pipe_shader_cap param)
352 {
353 struct virgl_screen *vscreen = virgl_screen(screen);
354
355 if ((shader == PIPE_SHADER_TESS_CTRL || shader == PIPE_SHADER_TESS_EVAL) &&
356 !vscreen->caps.caps.v1.bset.has_tessellation_shaders)
357 return 0;
358
359 if (shader == PIPE_SHADER_COMPUTE &&
360 !(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER))
361 return 0;
362
363 switch(shader)
364 {
365 case PIPE_SHADER_FRAGMENT:
366 case PIPE_SHADER_VERTEX:
367 case PIPE_SHADER_GEOMETRY:
368 case PIPE_SHADER_TESS_CTRL:
369 case PIPE_SHADER_TESS_EVAL:
370 case PIPE_SHADER_COMPUTE:
371 switch (param) {
372 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
373 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
374 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
375 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
376 return INT_MAX;
377 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
378 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
379 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
380 return 1;
381 case PIPE_SHADER_CAP_MAX_INPUTS:
382 if (vscreen->caps.caps.v1.glsl_level < 150)
383 return vscreen->caps.caps.v2.max_vertex_attribs;
384 return (shader == PIPE_SHADER_VERTEX ||
385 shader == PIPE_SHADER_GEOMETRY) ? vscreen->caps.caps.v2.max_vertex_attribs : 32;
386 case PIPE_SHADER_CAP_MAX_OUTPUTS:
387 if (shader == PIPE_SHADER_FRAGMENT)
388 return vscreen->caps.caps.v1.max_render_targets;
389 return vscreen->caps.caps.v2.max_vertex_outputs;
390 // case PIPE_SHADER_CAP_MAX_CONSTS:
391 // return 4096;
392 case PIPE_SHADER_CAP_MAX_TEMPS:
393 return 256;
394 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
395 return vscreen->caps.caps.v1.max_uniform_blocks;
396 // case PIPE_SHADER_CAP_MAX_ADDRS:
397 // return 1;
398 case PIPE_SHADER_CAP_SUBROUTINES:
399 return 1;
400 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
401 return 16;
402 case PIPE_SHADER_CAP_INTEGERS:
403 return vscreen->caps.caps.v1.glsl_level >= 130;
404 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
405 return 32;
406 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
407 return 4096 * sizeof(float[4]);
408 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
409 if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
410 return vscreen->caps.caps.v2.max_shader_buffer_frag_compute;
411 else
412 return vscreen->caps.caps.v2.max_shader_buffer_other_stages;
413 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
414 if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
415 return vscreen->caps.caps.v2.max_shader_image_frag_compute;
416 else
417 return vscreen->caps.caps.v2.max_shader_image_other_stages;
418 case PIPE_SHADER_CAP_SUPPORTED_IRS:
419 return (1 << PIPE_SHADER_IR_TGSI);
420 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
421 return vscreen->caps.caps.v2.max_atomic_counters[shader];
422 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
423 return vscreen->caps.caps.v2.max_atomic_counter_buffers[shader];
424 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
425 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
426 case PIPE_SHADER_CAP_INT64_ATOMICS:
427 case PIPE_SHADER_CAP_FP16:
428 return 0;
429 case PIPE_SHADER_CAP_SCALAR_ISA:
430 return 1;
431 default:
432 return 0;
433 }
434 default:
435 return 0;
436 }
437 }
438
439 static float
440 virgl_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
441 {
442 struct virgl_screen *vscreen = virgl_screen(screen);
443 switch (param) {
444 case PIPE_CAPF_MAX_LINE_WIDTH:
445 return vscreen->caps.caps.v2.max_aliased_line_width;
446 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
447 return vscreen->caps.caps.v2.max_smooth_line_width;
448 case PIPE_CAPF_MAX_POINT_WIDTH:
449 return vscreen->caps.caps.v2.max_aliased_point_size;
450 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
451 return vscreen->caps.caps.v2.max_smooth_point_size;
452 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
453 return 16.0;
454 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
455 return vscreen->caps.caps.v2.max_texture_lod_bias;
456 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
457 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
458 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
459 return 0.0f;
460 }
461 /* should only get here on unhandled cases */
462 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
463 return 0.0;
464 }
465
466 static int
467 virgl_get_compute_param(struct pipe_screen *screen,
468 enum pipe_shader_ir ir_type,
469 enum pipe_compute_cap param,
470 void *ret)
471 {
472 struct virgl_screen *vscreen = virgl_screen(screen);
473 if (!(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER))
474 return 0;
475 switch (param) {
476 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
477 if (ret) {
478 uint64_t *grid_size = ret;
479 grid_size[0] = vscreen->caps.caps.v2.max_compute_grid_size[0];
480 grid_size[1] = vscreen->caps.caps.v2.max_compute_grid_size[1];
481 grid_size[2] = vscreen->caps.caps.v2.max_compute_grid_size[2];
482 }
483 return 3 * sizeof(uint64_t) ;
484 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
485 if (ret) {
486 uint64_t *block_size = ret;
487 block_size[0] = vscreen->caps.caps.v2.max_compute_block_size[0];
488 block_size[1] = vscreen->caps.caps.v2.max_compute_block_size[1];
489 block_size[2] = vscreen->caps.caps.v2.max_compute_block_size[2];
490 }
491 return 3 * sizeof(uint64_t);
492 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
493 if (ret) {
494 uint64_t *max_threads_per_block = ret;
495 *max_threads_per_block = vscreen->caps.caps.v2.max_compute_work_group_invocations;
496 }
497 return sizeof(uint64_t);
498 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
499 if (ret) {
500 uint64_t *max_local_size = ret;
501 /* Value reported by the closed source driver. */
502 *max_local_size = vscreen->caps.caps.v2.max_compute_shared_memory_size;
503 }
504 return sizeof(uint64_t);
505 default:
506 break;
507 }
508 return 0;
509 }
510
511 static boolean
512 virgl_is_vertex_format_supported(struct pipe_screen *screen,
513 enum pipe_format format)
514 {
515 struct virgl_screen *vscreen = virgl_screen(screen);
516 const struct util_format_description *format_desc;
517 int i;
518
519 format_desc = util_format_description(format);
520 if (!format_desc)
521 return FALSE;
522
523 if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
524 int vformat = VIRGL_FORMAT_R11G11B10_FLOAT;
525 int big = vformat / 32;
526 int small = vformat % 32;
527 if (!(vscreen->caps.caps.v1.vertexbuffer.bitmask[big] & (1 << small)))
528 return FALSE;
529 return TRUE;
530 }
531
532 /* Find the first non-VOID channel. */
533 for (i = 0; i < 4; i++) {
534 if (format_desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
535 break;
536 }
537 }
538
539 if (i == 4)
540 return FALSE;
541
542 if (format_desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
543 return FALSE;
544
545 if (format_desc->channel[i].type == UTIL_FORMAT_TYPE_FIXED)
546 return FALSE;
547 return TRUE;
548 }
549
550 /**
551 * Query format support for creating a texture, drawing surface, etc.
552 * \param format the format to test
553 * \param type one of PIPE_TEXTURE, PIPE_SURFACE
554 */
555 static boolean
556 virgl_is_format_supported( struct pipe_screen *screen,
557 enum pipe_format format,
558 enum pipe_texture_target target,
559 unsigned sample_count,
560 unsigned storage_sample_count,
561 unsigned bind)
562 {
563 struct virgl_screen *vscreen = virgl_screen(screen);
564 const struct util_format_description *format_desc;
565 int i;
566
567 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
568 return false;
569
570 assert(target == PIPE_BUFFER ||
571 target == PIPE_TEXTURE_1D ||
572 target == PIPE_TEXTURE_1D_ARRAY ||
573 target == PIPE_TEXTURE_2D ||
574 target == PIPE_TEXTURE_2D_ARRAY ||
575 target == PIPE_TEXTURE_RECT ||
576 target == PIPE_TEXTURE_3D ||
577 target == PIPE_TEXTURE_CUBE ||
578 target == PIPE_TEXTURE_CUBE_ARRAY);
579
580 format_desc = util_format_description(format);
581 if (!format_desc)
582 return FALSE;
583
584 if (util_format_is_intensity(format))
585 return FALSE;
586
587 if (sample_count > 1) {
588 if (!vscreen->caps.caps.v1.bset.texture_multisample)
589 return FALSE;
590
591 if (bind & PIPE_BIND_SHADER_IMAGE) {
592 if (sample_count > vscreen->caps.caps.v2.max_image_samples)
593 return FALSE;
594 }
595
596 if (sample_count > vscreen->caps.caps.v1.max_samples)
597 return FALSE;
598 }
599
600 if (bind & PIPE_BIND_VERTEX_BUFFER) {
601 return virgl_is_vertex_format_supported(screen, format);
602 }
603
604 /* Allow 3-comp 32 bit textures only for TBOs (needed for ARB_tbo_rgb32) */
605 if ((format == PIPE_FORMAT_R32G32B32_FLOAT ||
606 format == PIPE_FORMAT_R32G32B32_SINT ||
607 format == PIPE_FORMAT_R32G32B32_UINT) &&
608 target != PIPE_BUFFER)
609 return FALSE;
610
611 if (bind & PIPE_BIND_RENDER_TARGET) {
612 /* For ARB_framebuffer_no_attachments. */
613 if (format == PIPE_FORMAT_NONE)
614 return TRUE;
615
616 if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
617 return FALSE;
618
619 /*
620 * Although possible, it is unnatural to render into compressed or YUV
621 * surfaces. So disable these here to avoid going into weird paths
622 * inside the state trackers.
623 */
624 if (format_desc->block.width != 1 ||
625 format_desc->block.height != 1)
626 return FALSE;
627
628 {
629 int big = format / 32;
630 int small = format % 32;
631 if (!(vscreen->caps.caps.v1.render.bitmask[big] & (1 << small)))
632 return FALSE;
633 }
634 }
635
636 if (bind & PIPE_BIND_DEPTH_STENCIL) {
637 if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
638 return FALSE;
639 }
640
641 /*
642 * All other operations (sampling, transfer, etc).
643 */
644
645 if (format_desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
646 goto out_lookup;
647 }
648 if (format_desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
649 goto out_lookup;
650 }
651 if (format_desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
652 goto out_lookup;
653 }
654
655 if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
656 goto out_lookup;
657 } else if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
658 goto out_lookup;
659 }
660
661 /* Find the first non-VOID channel. */
662 for (i = 0; i < 4; i++) {
663 if (format_desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
664 break;
665 }
666 }
667
668 if (i == 4)
669 return FALSE;
670
671 /* no L4A4 */
672 if (format_desc->nr_channels < 4 && format_desc->channel[i].size == 4)
673 return FALSE;
674
675 out_lookup:
676 {
677 int big = format / 32;
678 int small = format % 32;
679 if (!(vscreen->caps.caps.v1.sampler.bitmask[big] & (1 << small)))
680 return FALSE;
681 }
682 /*
683 * Everything else should be supported by u_format.
684 */
685 return TRUE;
686 }
687
688 static void virgl_flush_frontbuffer(struct pipe_screen *screen,
689 struct pipe_resource *res,
690 unsigned level, unsigned layer,
691 void *winsys_drawable_handle, struct pipe_box *sub_box)
692 {
693 struct virgl_screen *vscreen = virgl_screen(screen);
694 struct virgl_winsys *vws = vscreen->vws;
695 struct virgl_resource *vres = virgl_resource(res);
696
697 if (vws->flush_frontbuffer)
698 vws->flush_frontbuffer(vws, vres->hw_res, level, layer, winsys_drawable_handle,
699 sub_box);
700 }
701
702 static void virgl_fence_reference(struct pipe_screen *screen,
703 struct pipe_fence_handle **ptr,
704 struct pipe_fence_handle *fence)
705 {
706 struct virgl_screen *vscreen = virgl_screen(screen);
707 struct virgl_winsys *vws = vscreen->vws;
708
709 vws->fence_reference(vws, ptr, fence);
710 }
711
712 static boolean virgl_fence_finish(struct pipe_screen *screen,
713 struct pipe_context *ctx,
714 struct pipe_fence_handle *fence,
715 uint64_t timeout)
716 {
717 struct virgl_screen *vscreen = virgl_screen(screen);
718 struct virgl_winsys *vws = vscreen->vws;
719
720 return vws->fence_wait(vws, fence, timeout);
721 }
722
723 static uint64_t
724 virgl_get_timestamp(struct pipe_screen *_screen)
725 {
726 return os_time_get_nano();
727 }
728
729 static void
730 virgl_destroy_screen(struct pipe_screen *screen)
731 {
732 struct virgl_screen *vscreen = virgl_screen(screen);
733 struct virgl_winsys *vws = vscreen->vws;
734
735 slab_destroy_parent(&vscreen->texture_transfer_pool);
736
737 if (vws)
738 vws->destroy(vws);
739 FREE(vscreen);
740 }
741
742 struct pipe_screen *
743 virgl_create_screen(struct virgl_winsys *vws)
744 {
745 struct virgl_screen *screen = CALLOC_STRUCT(virgl_screen);
746
747 if (!screen)
748 return NULL;
749
750 virgl_debug = debug_get_option_virgl_debug();
751
752 screen->vws = vws;
753 screen->base.get_name = virgl_get_name;
754 screen->base.get_vendor = virgl_get_vendor;
755 screen->base.get_param = virgl_get_param;
756 screen->base.get_shader_param = virgl_get_shader_param;
757 screen->base.get_compute_param = virgl_get_compute_param;
758 screen->base.get_paramf = virgl_get_paramf;
759 screen->base.is_format_supported = virgl_is_format_supported;
760 screen->base.destroy = virgl_destroy_screen;
761 screen->base.context_create = virgl_context_create;
762 screen->base.flush_frontbuffer = virgl_flush_frontbuffer;
763 screen->base.get_timestamp = virgl_get_timestamp;
764 screen->base.fence_reference = virgl_fence_reference;
765 //screen->base.fence_signalled = virgl_fence_signalled;
766 screen->base.fence_finish = virgl_fence_finish;
767
768 virgl_init_screen_resource_functions(&screen->base);
769
770 vws->get_caps(vws, &screen->caps);
771
772 screen->refcnt = 1;
773
774 slab_create_parent(&screen->texture_transfer_pool, sizeof(struct virgl_transfer), 16);
775
776 return &screen->base;
777 }