src/gallium/winsys/radeon/drm/radeon_winsys.h

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  23
  24 #ifndef RADEON_WINSYS_H
  25 #define RADEON_WINSYS_H
  26
  27 /* The public winsys interface header for the radeon driver. */
  28
  29 /* R300 features in DRM.
  30  *
  31  * 2.6.0:
  32  * - Hyper-Z
  33  * - GB_Z_PEQ_CONFIG on rv350->r4xx
  34  * - R500 FG_ALPHA_VALUE
  35  *
  36  * 2.8.0:
  37  * - R500 US_FORMAT regs
  38  * - R500 ARGB2101010 colorbuffer
  39  * - CMask and AA regs
  40  * - R16F/RG16F
  41  */
  42
  43 #include "pipebuffer/pb_buffer.h"
  44 #include "radeon_surface.h"
  45
  46 #define RADEON_MAX_CMDBUF_DWORDS (16 * 1024)
  47
  48 #define RADEON_FLUSH_ASYNC              (1 << 0)
  49 #define RADEON_FLUSH_KEEP_TILING_FLAGS  (1 << 1) /* needs DRM 2.12.0 */
  50 #define RADEON_FLUSH_COMPUTE            (1 << 2)
  51 #define RADEON_FLUSH_END_OF_FRAME       (1 << 3)
  52
  53 /* Tiling flags. */
  54 enum radeon_bo_layout {
  55     RADEON_LAYOUT_LINEAR = 0,
  56     RADEON_LAYOUT_TILED,
  57     RADEON_LAYOUT_SQUARETILED,
  58
  59     RADEON_LAYOUT_UNKNOWN
  60 };
  61
  62 enum radeon_bo_domain { /* bitfield */
  63     RADEON_DOMAIN_GTT  = 2,
  64     RADEON_DOMAIN_VRAM = 4,
  65     RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  66 };
  67
  68 enum radeon_bo_usage { /* bitfield */
  69     RADEON_USAGE_READ = 2,
  70     RADEON_USAGE_WRITE = 4,
  71     RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE
  72 };
  73
  74 enum radeon_family {
  75     CHIP_UNKNOWN = 0,
  76     CHIP_R300, /* R3xx-based cores. */
  77     CHIP_R350,
  78     CHIP_RV350,
  79     CHIP_RV370,
  80     CHIP_RV380,
  81     CHIP_RS400,
  82     CHIP_RC410,
  83     CHIP_RS480,
  84     CHIP_R420,     /* R4xx-based cores. */
  85     CHIP_R423,
  86     CHIP_R430,
  87     CHIP_R480,
  88     CHIP_R481,
  89     CHIP_RV410,
  90     CHIP_RS600,
  91     CHIP_RS690,
  92     CHIP_RS740,
  93     CHIP_RV515,    /* R5xx-based cores. */
  94     CHIP_R520,
  95     CHIP_RV530,
  96     CHIP_R580,
  97     CHIP_RV560,
  98     CHIP_RV570,
  99     CHIP_R600,
 100     CHIP_RV610,
 101     CHIP_RV630,
 102     CHIP_RV670,
 103     CHIP_RV620,
 104     CHIP_RV635,
 105     CHIP_RS780,
 106     CHIP_RS880,
 107     CHIP_RV770,
 108     CHIP_RV730,
 109     CHIP_RV710,
 110     CHIP_RV740,
 111     CHIP_CEDAR,
 112     CHIP_REDWOOD,
 113     CHIP_JUNIPER,
 114     CHIP_CYPRESS,
 115     CHIP_HEMLOCK,
 116     CHIP_PALM,
 117     CHIP_SUMO,
 118     CHIP_SUMO2,
 119     CHIP_BARTS,
 120     CHIP_TURKS,
 121     CHIP_CAICOS,
 122     CHIP_CAYMAN,
 123     CHIP_ARUBA,
 124     CHIP_TAHITI,
 125     CHIP_PITCAIRN,
 126     CHIP_VERDE,
 127     CHIP_OLAND,
 128     CHIP_HAINAN,
 129     CHIP_BONAIRE,
 130     CHIP_KAVERI,
 131     CHIP_KABINI,
 132     CHIP_HAWAII,
 133     CHIP_LAST,
 134 };
 135
 136 enum chip_class {
 137     CLASS_UNKNOWN = 0,
 138     R300,
 139     R400,
 140     R500,
 141     R600,
 142     R700,
 143     EVERGREEN,
 144     CAYMAN,
 145     SI,
 146     CIK,
 147 };
 148
 149 enum ring_type {
 150     RING_GFX = 0,
 151     RING_DMA,
 152     RING_UVD,
 153     RING_VCE,
 154     RING_LAST,
 155 };
 156
 157 enum radeon_value_id {
 158     RADEON_REQUESTED_VRAM_MEMORY,
 159     RADEON_REQUESTED_GTT_MEMORY,
 160     RADEON_BUFFER_WAIT_TIME_NS,
 161     RADEON_TIMESTAMP,
 162     RADEON_NUM_CS_FLUSHES,
 163     RADEON_NUM_BYTES_MOVED,
 164     RADEON_VRAM_USAGE,
 165     RADEON_GTT_USAGE
 166 };
 167
 168 enum radeon_bo_priority {
 169     RADEON_PRIO_MIN,
 170     RADEON_PRIO_SHADER_DATA, /* shader code, resource descriptors */
 171     RADEON_PRIO_SHADER_BUFFER_RO, /* read-only */
 172     RADEON_PRIO_SHADER_TEXTURE_RO, /* read-only */
 173     RADEON_PRIO_SHADER_RESOURCE_RW, /* buffers, textures, streamout, GS rings, RATs; read/write */
 174     RADEON_PRIO_COLOR_BUFFER,
 175     RADEON_PRIO_DEPTH_BUFFER,
 176     RADEON_PRIO_SHADER_TEXTURE_MSAA,
 177     RADEON_PRIO_COLOR_BUFFER_MSAA,
 178     RADEON_PRIO_DEPTH_BUFFER_MSAA,
 179     RADEON_PRIO_COLOR_META,
 180     RADEON_PRIO_DEPTH_META,
 181     RADEON_PRIO_MAX /* must be <= 15 */
 182 };
 183
 184 struct winsys_handle;
 185 struct radeon_winsys_cs_handle;
 186
 187 struct radeon_winsys_cs {
 188     unsigned                    cdw;  /* Number of used dwords. */
 189     uint32_t                    *buf; /* The command buffer. */
 190     enum ring_type              ring_type;
 191 };
 192
 193 struct radeon_info {
 194     uint32_t                    pci_id;
 195     enum radeon_family          family;
 196     enum chip_class             chip_class;
 197     uint32_t                    gart_size;
 198     uint32_t                    vram_size;
 199
 200     uint32_t                    drm_major; /* version */
 201     uint32_t                    drm_minor;
 202     uint32_t                    drm_patchlevel;
 203
 204     boolean                     has_uvd;
 205     uint32_t                    vce_fw_version;
 206
 207     uint32_t                    r300_num_gb_pipes;
 208     uint32_t                    r300_num_z_pipes;
 209
 210     uint32_t                    r600_num_backends;
 211     uint32_t                    r600_clock_crystal_freq;
 212     uint32_t                    r600_tiling_config;
 213     uint32_t                    r600_num_tile_pipes;
 214     uint32_t                    r600_backend_map;
 215     uint32_t                    r600_va_start;
 216     uint32_t                    r600_ib_vm_max_size;
 217     uint32_t                    r600_max_pipes;
 218     boolean                     r600_backend_map_valid;
 219     boolean                     r600_virtual_address;
 220     boolean                     r600_has_dma;
 221
 222     boolean                     si_tile_mode_array_valid;
 223     uint32_t                    si_tile_mode_array[32];
 224
 225     boolean                     cik_macrotile_mode_array_valid;
 226     uint32_t                    cik_macrotile_mode_array[16];
 227 };
 228
 229 enum radeon_feature_id {
 230     RADEON_FID_R300_HYPERZ_ACCESS,     /* ZMask + HiZ */
 231     RADEON_FID_R300_CMASK_ACCESS,
 232 };
 233
 234 struct radeon_winsys {
 235     /**
 236      * Reference counting
 237      */
 238     struct pipe_reference reference;
 239
 240     /**
 241      * The screen object this winsys was created for
 242      */
 243     struct pipe_screen *screen;
 244
 245     /**
 246      * Destroy this winsys.
 247      *
 248      * \param ws        The winsys this function is called from.
 249      */
 250     void (*destroy)(struct radeon_winsys *ws);
 251
 252     /**
 253      * Query an info structure from winsys.
 254      *
 255      * \param ws        The winsys this function is called from.
 256      * \param info      Return structure
 257      */
 258     void (*query_info)(struct radeon_winsys *ws,
 259                        struct radeon_info *info);
 260
 261     /**************************************************************************
 262      * Buffer management. Buffer attributes are mostly fixed over its lifetime.
 263      *
 264      * Remember that gallium gets to choose the interface it needs, and the
 265      * window systems must then implement that interface (rather than the
 266      * other way around...).
 267      *************************************************************************/
 268
 269     /**
 270      * Create a buffer object.
 271      *
 272      * \param ws        The winsys this function is called from.
 273      * \param size      The size to allocate.
 274      * \param alignment An alignment of the buffer in memory.
 275      * \param use_reusable_pool Whether the cache buffer manager should be used.
 276      * \param domain    A bitmask of the RADEON_DOMAIN_* flags.
 277      * \return          The created buffer object.
 278      */
 279     struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
 280                                        unsigned size,
 281                                        unsigned alignment,
 282                                        boolean use_reusable_pool,
 283                                        enum radeon_bo_domain domain);
 284
 285     struct radeon_winsys_cs_handle *(*buffer_get_cs_handle)(
 286             struct pb_buffer *buf);
 287
 288     /**
 289      * Map the entire data store of a buffer object into the client's address
 290      * space.
 291      *
 292      * \param buf       A winsys buffer object to map.
 293      * \param cs        A command stream to flush if the buffer is referenced by it.
 294      * \param usage     A bitmask of the PIPE_TRANSFER_* flags.
 295      * \return          The pointer at the beginning of the buffer.
 296      */
 297     void *(*buffer_map)(struct radeon_winsys_cs_handle *buf,
 298                         struct radeon_winsys_cs *cs,
 299                         enum pipe_transfer_usage usage);
 300
 301     /**
 302      * Unmap a buffer object from the client's address space.
 303      *
 304      * \param buf       A winsys buffer object to unmap.
 305      */
 306     void (*buffer_unmap)(struct radeon_winsys_cs_handle *buf);
 307
 308     /**
 309      * Return TRUE if a buffer object is being used by the GPU.
 310      *
 311      * \param buf       A winsys buffer object.
 312      * \param usage     Only check whether the buffer is busy for the given usage.
 313      */
 314     boolean (*buffer_is_busy)(struct pb_buffer *buf,
 315                               enum radeon_bo_usage usage);
 316
 317     /**
 318      * Wait for a buffer object until it is not used by a GPU. This is
 319      * equivalent to a fence placed after the last command using the buffer,
 320      * and synchronizing to the fence.
 321      *
 322      * \param buf       A winsys buffer object to wait for.
 323      * \param usage     Only wait until the buffer is idle for the given usage,
 324      *                  but may still be busy for some other usage.
 325      */
 326     void (*buffer_wait)(struct pb_buffer *buf, enum radeon_bo_usage usage);
 327
 328     /**
 329      * Return tiling flags describing a memory layout of a buffer object.
 330      *
 331      * \param buf       A winsys buffer object to get the flags from.
 332      * \param macrotile A pointer to the return value of the microtile flag.
 333      * \param microtile A pointer to the return value of the macrotile flag.
 334      *
 335      * \note microtile and macrotile are not bitmasks!
 336      */
 337     void (*buffer_get_tiling)(struct pb_buffer *buf,
 338                               enum radeon_bo_layout *microtile,
 339                               enum radeon_bo_layout *macrotile,
 340                               unsigned *bankw, unsigned *bankh,
 341                               unsigned *tile_split,
 342                               unsigned *stencil_tile_split,
 343                               unsigned *mtilea,
 344                               bool *scanout);
 345
 346     /**
 347      * Set tiling flags describing a memory layout of a buffer object.
 348      *
 349      * \param buf       A winsys buffer object to set the flags for.
 350      * \param cs        A command stream to flush if the buffer is referenced by it.
 351      * \param macrotile A macrotile flag.
 352      * \param microtile A microtile flag.
 353      * \param stride    A stride of the buffer in bytes, for texturing.
 354      *
 355      * \note microtile and macrotile are not bitmasks!
 356      */
 357     void (*buffer_set_tiling)(struct pb_buffer *buf,
 358                               struct radeon_winsys_cs *rcs,
 359                               enum radeon_bo_layout microtile,
 360                               enum radeon_bo_layout macrotile,
 361                               unsigned bankw, unsigned bankh,
 362                               unsigned tile_split,
 363                               unsigned stencil_tile_split,
 364                               unsigned mtilea,
 365                               unsigned stride,
 366                               bool scanout);
 367
 368     /**
 369      * Get a winsys buffer from a winsys handle. The internal structure
 370      * of the handle is platform-specific and only a winsys should access it.
 371      *
 372      * \param ws        The winsys this function is called from.
 373      * \param whandle   A winsys handle pointer as was received from a state
 374      *                  tracker.
 375      * \param stride    The returned buffer stride in bytes.
 376      */
 377     struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws,
 378                                             struct winsys_handle *whandle,
 379                                             unsigned *stride);
 380
 381     /**
 382      * Get a winsys handle from a winsys buffer. The internal structure
 383      * of the handle is platform-specific and only a winsys should access it.
 384      *
 385      * \param buf       A winsys buffer object to get the handle from.
 386      * \param whandle   A winsys handle pointer.
 387      * \param stride    A stride of the buffer in bytes, for texturing.
 388      * \return          TRUE on success.
 389      */
 390     boolean (*buffer_get_handle)(struct pb_buffer *buf,
 391                                  unsigned stride,
 392                                  struct winsys_handle *whandle);
 393
 394     /**
 395      * Return the virtual address of a buffer.
 396      *
 397      * \param buf       A winsys buffer object
 398      * \return          virtual address
 399      */
 400     uint64_t (*buffer_get_virtual_address)(struct radeon_winsys_cs_handle *buf);
 401
 402     /**
 403      * Query the initial placement of the buffer from the kernel driver.
 404      */
 405     enum radeon_bo_domain (*buffer_get_initial_domain)(struct radeon_winsys_cs_handle *buf);
 406
 407     /**************************************************************************
 408      * Command submission.
 409      *
 410      * Each pipe context should create its own command stream and submit
 411      * commands independently of other contexts.
 412      *************************************************************************/
 413
 414     /**
 415      * Create a command stream.
 416      *
 417      * \param ws        The winsys this function is called from.
 418      * \param ring_type The ring type (GFX, DMA, UVD)
 419      * \param trace_buf Trace buffer when tracing is enabled
 420      */
 421     struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys *ws,
 422                                           enum ring_type ring_type,
 423                                           struct radeon_winsys_cs_handle *trace_buf);
 424
 425     /**
 426      * Destroy a command stream.
 427      *
 428      * \param cs        A command stream to destroy.
 429      */
 430     void (*cs_destroy)(struct radeon_winsys_cs *cs);
 431
 432     /**
 433      * Add a new buffer relocation. Every relocation must first be added
 434      * before it can be written.
 435      *
 436      * \param cs  A command stream to add buffer for validation against.
 437      * \param buf A winsys buffer to validate.
 438      * \param usage   Whether the buffer is used for read and/or write.
 439      * \param domain  Bitmask of the RADEON_DOMAIN_* flags.
 440      * \param priority  A higher number means a greater chance of being
 441      *                  placed in the requested domain. 15 is the maximum.
 442      * \return Relocation index.
 443      */
 444     unsigned (*cs_add_reloc)(struct radeon_winsys_cs *cs,
 445                              struct radeon_winsys_cs_handle *buf,
 446                              enum radeon_bo_usage usage,
 447                              enum radeon_bo_domain domain,
 448                              enum radeon_bo_priority priority);
 449
 450     /**
 451      * Return TRUE if there is enough memory in VRAM and GTT for the relocs
 452      * added so far. If the validation fails, all the relocations which have
 453      * been added since the last call of cs_validate will be removed and
 454      * the CS will be flushed (provided there are still any relocations).
 455      *
 456      * \param cs        A command stream to validate.
 457      */
 458     boolean (*cs_validate)(struct radeon_winsys_cs *cs);
 459
 460     /**
 461      * Return TRUE if there is enough memory in VRAM and GTT for the relocs
 462      * added so far.
 463      *
 464      * \param cs        A command stream to validate.
 465      * \param vram      VRAM memory size pending to be use
 466      * \param gtt       GTT memory size pending to be use
 467      */
 468     boolean (*cs_memory_below_limit)(struct radeon_winsys_cs *cs, uint64_t vram, uint64_t gtt);
 469
 470     /**
 471      * Write a relocated dword to a command buffer.
 472      *
 473      * \param cs        A command stream the relocation is written to.
 474      * \param buf       A winsys buffer to write the relocation for.
 475      */
 476     void (*cs_write_reloc)(struct radeon_winsys_cs *cs,
 477                            struct radeon_winsys_cs_handle *buf);
 478
 479     /**
 480      * Flush a command stream.
 481      *
 482      * \param cs          A command stream to flush.
 483      * \param flags,      RADEON_FLUSH_ASYNC or 0.
 484      * \param cs_trace_id A unique identifiant for the cs
 485      */
 486     void (*cs_flush)(struct radeon_winsys_cs *cs, unsigned flags, uint32_t cs_trace_id);
 487
 488     /**
 489      * Set a flush callback which is called from winsys when flush is
 490      * required.
 491      *
 492      * \param cs        A command stream to set the callback for.
 493      * \param flush     A flush callback function associated with the command stream.
 494      * \param user      A user pointer that will be passed to the flush callback.
 495      */
 496     void (*cs_set_flush_callback)(struct radeon_winsys_cs *cs,
 497                                   void (*flush)(void *ctx, unsigned flags),
 498                                   void *ctx);
 499
 500     /**
 501      * Return TRUE if a buffer is referenced by a command stream.
 502      *
 503      * \param cs        A command stream.
 504      * \param buf       A winsys buffer.
 505      */
 506     boolean (*cs_is_buffer_referenced)(struct radeon_winsys_cs *cs,
 507                                        struct radeon_winsys_cs_handle *buf,
 508                                        enum radeon_bo_usage usage);
 509
 510     /**
 511      * Request access to a feature for a command stream.
 512      *
 513      * \param cs        A command stream.
 514      * \param fid       Feature ID, one of RADEON_FID_*
 515      * \param enable    Whether to enable or disable the feature.
 516      */
 517     boolean (*cs_request_feature)(struct radeon_winsys_cs *cs,
 518                                   enum radeon_feature_id fid,
 519                                   boolean enable);
 520      /**
 521       * Make sure all asynchronous flush of the cs have completed
 522       *
 523       * \param cs        A command stream.
 524       */
 525     void (*cs_sync_flush)(struct radeon_winsys_cs *cs);
 526
 527     /**
 528      * Return a fence associated with the CS. The fence will be signalled
 529      * once the CS is flushed and all commands in the CS are completed
 530      * by the GPU.
 531      */
 532     struct pipe_fence_handle *(*cs_create_fence)(struct radeon_winsys_cs *cs);
 533
 534     /**
 535      * Wait for the fence and return true if the fence has been signalled.
 536      * The timeout of 0 will only return the status.
 537      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
 538      * is signalled.
 539      */
 540     bool (*fence_wait)(struct radeon_winsys *ws,
 541                        struct pipe_fence_handle *fence,
 542                        uint64_t timeout);
 543
 544     /**
 545      * Reference counting for fences.
 546      */
 547     void (*fence_reference)(struct pipe_fence_handle **dst,
 548                             struct pipe_fence_handle *src);
 549
 550     /**
 551      * Initialize surface
 552      *
 553      * \param ws        The winsys this function is called from.
 554      * \param surf      Surface structure ptr
 555      */
 556     int (*surface_init)(struct radeon_winsys *ws,
 557                         struct radeon_surface *surf);
 558
 559     /**
 560      * Find best values for a surface
 561      *
 562      * \param ws        The winsys this function is called from.
 563      * \param surf      Surface structure ptr
 564      */
 565     int (*surface_best)(struct radeon_winsys *ws,
 566                         struct radeon_surface *surf);
 567
 568     uint64_t (*query_value)(struct radeon_winsys *ws,
 569                             enum radeon_value_id value);
 570 };
 571
 572 /**
 573  * Decrement the winsys reference count.
 574  *
 575  * \param ws The winsys this function is called for.
 576  */
 577 static INLINE boolean radeon_winsys_unref(struct radeon_winsys *ws)
 578 {
 579    return pipe_reference(&ws->reference, NULL);
 580 }
 581
 582 static INLINE void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 583 {
 584     cs->buf[cs->cdw++] = value;
 585 }
 586
 587 static INLINE void radeon_emit_array(struct radeon_winsys_cs *cs,
 588                                      const uint32_t *values, unsigned count)
 589 {
 590     memcpy(cs->buf+cs->cdw, values, count * 4);
 591     cs->cdw += count;
 592 }
 593
 594 #endif