3d486c7d0b097e039b29985b9964db677490f9b7
1 from nmigen
import Module
, Signal
, Mux
, Const
, Elaboratable
2 from nmigen
.hdl
.rec
import Record
, Layout
, DIR_NONE
3 from nmigen
.compat
.sim
import run_simulation
4 from nmigen
.cli
import verilog
, rtlil
5 from nmigen
.compat
.fhdl
.bitcontainer
import value_bits_sign
6 from nmutil
.singlepipe
import cat
, RecordObject
12 self
.r1
= RecordObject()
13 self
.r1
.sig1
= Signal(16)
14 self
.r1
.r2
= RecordObject()
15 self
.r1
.r2
.sig2
= Signal(16)
16 self
.r1
.r3
= RecordObject()
17 self
.r1
.r3
.sig3
= Signal(16)
18 self
.sig123
= Signal(48)
20 def elaborate(self
, platform
):
24 m
.d
.comb
+= sig1
.eq(self
.r1
.sig1
)
26 m
.d
.comb
+= sig2
.eq(self
.r1
.r2
.sig2
)
28 print (self
.r1
.fields
)
29 print (self
.r1
.shape())
30 print ("width", len(self
.r1
))
31 m
.d
.comb
+= self
.sig123
.eq(cat(self
.r1
))
37 yield dut
.r1
.sig1
.eq(5)
38 yield dut
.r1
.r2
.sig2
.eq(10)
39 yield dut
.r1
.r3
.sig3
.eq(1)
41 sig1
= yield dut
.r1
.sig1
43 sig2
= yield dut
.r1
.r2
.sig2
48 sig123
= yield dut
.sig123
49 print ("sig123", hex(sig123
))
50 assert sig123
== 0x1000a0005
54 class RecordTest2(Elaboratable
):
57 self
.r1
= RecordObject()
58 self
.r1
.sig1
= Signal(16)
59 self
.r1
.r2
= RecordObject()
60 self
.r1
.r2
.sig2
= Signal(16)
61 self
.r1
.r3
= RecordObject()
62 self
.r1
.r3
.sig3
= Signal(16)
63 self
.sig123
= Signal(48)
65 def elaborate(self
, platform
):
68 m
.d
.comb
+= cat(self
.r1
).eq(self
.sig123
)
75 sig123
= yield dut
.sig123
.eq(0x1000a0005)
79 sig1
= yield dut
.r1
.sig1
81 sig2
= yield dut
.r1
.r2
.sig2
83 sig3
= yield dut
.r1
.r3
.sig3
88 ######################################################################
90 ######################################################################
92 if __name__
== '__main__':
95 run_simulation(dut
, testbench(dut
), vcd_name
="test_record1.vcd")
96 vl
= rtlil
.convert(dut
, ports
=[dut
.sig123
, dut
.r1
.sig1
, dut
.r1
.r2
.sig2
])
97 with
open("test_record1.il", "w") as f
:
102 run_simulation(dut
, testbench2(dut
), vcd_name
="test_record2.vcd")
103 vl
= rtlil
.convert(dut
, ports
=[dut
.sig123
, dut
.r1
.sig1
, dut
.r1
.r2
.sig2
])
104 with
open("test_record2.il", "w") as f
: