c3300a60410d659a9307638312cfbe175f69222e
1 """IEEE754 Floating Point Adder Pipeline
3 Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
7 from nmigen
import Module
, Signal
, Cat
, Mux
8 from nmigen
.cli
import main
, verilog
10 from nmutil
.pipemodbase
import PipeModBase
12 from ieee754
.fpcommon
.denorm
import FPSCData
13 from ieee754
.fpcommon
.getop
import FPPipeContext
14 from ieee754
.fpadd
.datastruct
import FPAddStage0Data
17 class FPAddStage0Mod(PipeModBase
):
19 def __init__(self
, pspec
):
20 super().__init
__(pspec
, "add0")
23 return FPSCData(self
.pspec
, True)
26 return FPAddStage0Data(self
.pspec
)
28 def elaborate(self
, platform
):
32 # store intermediate tests (and zero-extended mantissas)
33 seq
= Signal(reset_less
=True)
34 mge
= Signal(reset_less
=True)
35 am0
= Signal(len(self
.i
.a
.m
)+1, reset_less
=True)
36 bm0
= Signal(len(self
.i
.b
.m
)+1, reset_less
=True)
37 # same-sign (both negative or both positive) add mantissas
38 comb
+= [seq
.eq(self
.i
.a
.s
== self
.i
.b
.s
),
39 mge
.eq(self
.i
.a
.m
>= self
.i
.b
.m
),
40 am0
.eq(Cat(self
.i
.a
.m
, 0)),
41 bm0
.eq(Cat(self
.i
.b
.m
, 0))
43 comb
+= self
.o
.z
.e
.eq(self
.i
.a
.e
)
44 comb
+= self
.o
.z
.s
.eq(Mux(seq | mge
, self
.i
.a
.s
, self
.i
.b
.s
))
47 self
.o
.tot
.eq(am0
+ bm0
),
49 # a mantissa greater than b, use a
52 self
.o
.tot
.eq(am0
- bm0
),
54 # b mantissa greater than a, use b
57 self
.o
.tot
.eq(bm0
- am0
),
60 # pass-through context
61 comb
+= self
.o
.oz
.eq(self
.i
.oz
)
62 comb
+= self
.o
.out_do_z
.eq(self
.i
.out_do_z
)
63 comb
+= self
.o
.ctx
.eq(self
.i
.ctx
)