6792a20c9ee27b0e8fb0232ed620b9206fffb7ef
1 """IEEE Floating Point Adder Pipeline
3 Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=75
7 * scnorm - FPMulSpecialCasesDeNorm
8 * addalign - FPAddAlignSingleAdd
9 * normpack - FPNormToPack
11 scnorm - FPDIVSpecialCasesDeNorm ispec FPADDBaseData
14 StageChain: FPMULSpecialCasesMod,
18 addalign - FPAddAlignSingleAdd ispec FPSCData
19 -------- ospec FPAddStage1Data
21 StageChain: FPAddAlignSingleMod
25 normpack - FPNormToPack ispec FPAddStage1Data
26 -------- ospec FPPackData
28 StageChain: Norm1ModSingle,
33 This pipeline has a 3 clock latency, and, with the separation into
34 separate "modules", it is quite clear how to create longer-latency
35 pipelines (if needed) - just create a new, longer top-level (FPADDBasePipe
36 alternative) and construct shorter pipe stages using the building blocks,
37 RoundMod, FPAddStage0Mod etc.
41 from nmigen
import Module
42 from nmigen
.cli
import main
, verilog
44 from nmutil
.singlepipe
import ControlBase
45 from nmutil
.multipipe
import CombMuxOutPipe
46 from nmutil
.multipipe
import PriorityCombMuxInPipe
47 from nmutil
.concurrentunit
import ReservationStations
, num_bits
49 from ieee754
.fpcommon
.getop
import FPADDBaseData
50 from ieee754
.fpcommon
.denorm
import FPSCData
51 from ieee754
.fpcommon
.pack
import FPPackData
52 from ieee754
.fpcommon
.normtopack
import FPNormToPack
53 from ieee754
.fpadd
.specialcases
import FPAddSpecialCasesDeNorm
54 from ieee754
.fpadd
.addstages
import FPAddAlignSingleAdd
55 from ieee754
.pipeline
import PipelineSpec
58 class FPADDBasePipe(ControlBase
):
59 def __init__(self
, pspec
):
60 ControlBase
.__init
__(self
)
61 self
.pipe1
= FPAddSpecialCasesDeNorm(pspec
)
62 self
.pipe2
= FPAddAlignSingleAdd(pspec
)
63 self
.pipe3
= FPNormToPack(pspec
)
65 self
._eqs
= self
.connect([self
.pipe1
, self
.pipe2
, self
.pipe3
])
67 def elaborate(self
, platform
):
68 m
= ControlBase
.elaborate(self
, platform
)
69 m
.submodules
.scnorm
= self
.pipe1
70 m
.submodules
.addalign
= self
.pipe2
71 m
.submodules
.normpack
= self
.pipe3
76 class FPADDMuxInOut(ReservationStations
):
77 """ Reservation-Station version of FPADD pipeline.
79 * fan-in on inputs (an array of FPADDBaseData: a,b,mid)
80 * 3-stage adder pipeline
81 * fan-out on outputs (an array of FPPackData: z,mid)
83 Fan-in and Fan-out are combinatorial.
86 def __init__(self
, width
, num_rows
, op_wid
=None):
87 self
.id_wid
= num_bits(num_rows
)
89 self
.pspec
= PipelineSpec(width
, self
.id_wid
, op_wid
)
90 self
.alu
= FPADDBasePipe(self
.pspec
)
91 ReservationStations
.__init
__(self
, num_rows
)
94 return FPADDBaseData(self
.pspec
)
97 return FPPackData(self
.pspec
)