32d0d17cc8e38b2193400734fc4f9502bb2f27c2
1 """IEEE754 Floating Point Divider
3 Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
6 from nmigen
import Module
, Signal
, Cat
, Elaboratable
, Const
7 from nmigen
.cli
import main
, verilog
9 from ieee754
.fpcommon
.fpbase
import (FPNumBaseRecord
, Overflow
)
10 from ieee754
.fpcommon
.fpbase
import FPState
11 from ieee754
.fpcommon
.denorm
import FPSCData
12 from ieee754
.fpcommon
.getop
import FPPipeContext
13 from ieee754
.div_rem_sqrt_rsqrt
.div_pipe
import DivPipeInputData
16 class FPDivStage0Mod(Elaboratable
):
18 def __init__(self
, pspec
):
24 return FPSCData(self
.pspec
, False)
27 return DivPipeInputData(self
.pspec
)
32 def setup(self
, m
, i
):
33 """ links module to inputs and outputs
35 m
.submodules
.div0
= self
36 m
.d
.comb
+= self
.i
.eq(i
)
38 def elaborate(self
, platform
):
41 # XXX TODO, actual DIV code here. this class would be
42 # "step one" which takes the pre-normalised data (see ispec) and
43 # *begins* the processing phase (enters the massive DIV
44 # pipeline chain) - see ospec.
46 # INPUT SPEC: FPSCData
47 # OUTPUT SPEC: DivPipeInputData
49 # NOTE: this stage does *NOT* do *ACTUAL* DIV processing,
50 # it is PURELY the *ENTRY* point into the chain, performing
53 with m
.If(~self
.i
.out_do_z
):
54 # do conversion here, of both self.i.a and self.i.b,
55 # into DivPipeInputData dividend and divisor.
57 # XXX *sigh* magic constants...
58 if self
.pspec
.width
== 16:
59 if self
.pspec
.log2_radix
== 1:
61 elif self
.pspec
.log2_radix
== 3:
65 elif self
.pspec
.width
== 32:
66 if self
.pspec
.log2_radix
== 1:
70 elif self
.pspec
.width
== 64:
71 if self
.pspec
.log2_radix
== 1:
73 elif self
.pspec
.log2_radix
== 3:
78 # the mantissas, having been de-normalised (and containing
79 # a "1" in the MSB) represent numbers in the range 0.5 to
80 # 0.9999999-recurring. the min and max range of the
81 # result is therefore 0.4999999 (0.5/0.99999) and 1.9999998
85 with m
.If(self
.i
.ctx
.op
== 0):
86 am0
= Signal(len(self
.i
.a
.m
)+3, reset_less
=True)
87 bm0
= Signal(len(self
.i
.b
.m
)+3, reset_less
=True)
89 am0
.eq(Cat(0,0,0,self
.i
.a
.m
, 0)),
90 bm0
.eq(Cat(0,0,0,self
.i
.b
.m
, 0)),
93 # zero-extend the mantissas (room for sticky/round/guard)
95 m
.d
.comb
+= [self
.o
.z
.e
.eq(self
.i
.a
.e
- self
.i
.b
.e
+ 1),
96 self
.o
.z
.s
.eq(self
.i
.a
.s ^ self
.i
.b
.s
),
97 self
.o
.dividend
[len(self
.i
.a
.m
)+extra
:].eq(am0
),
98 self
.o
.divisor_radicand
.eq(bm0
),
99 self
.o
.operation
.eq(Const(0)) # XXX DIV operation
103 with m
.Elif(self
.i
.ctx
.op
== 1):
104 am0
= Signal(len(self
.i
.a
.m
)+3, reset_less
=True)
105 with m
.If(self
.i
.a
.e
[0]):
106 m
.d
.comb
+= am0
.eq(Cat(self
.i
.a
.m
, 0)<<(extra
-2))
107 m
.d
.comb
+= self
.o
.z
.e
.eq(((self
.i
.a
.e
+1) >> 1)+1)
109 m
.d
.comb
+= am0
.eq(Cat(0, self
.i
.a
.m
)<<(extra
-2))
110 m
.d
.comb
+= self
.o
.z
.e
.eq((self
.i
.a
.e
>> 1)+1)
112 m
.d
.comb
+= [self
.o
.z
.s
.eq(self
.i
.a
.s
),
113 self
.o
.divisor_radicand
.eq(am0
),
114 self
.o
.operation
.eq(Const(1)) # XXX SQRT operation
117 # these are required and must not be touched
118 m
.d
.comb
+= self
.o
.oz
.eq(self
.i
.oz
)
119 m
.d
.comb
+= self
.o
.out_do_z
.eq(self
.i
.out_do_z
)
120 m
.d
.comb
+= self
.o
.ctx
.eq(self
.i
.ctx
)
125 class FPDivStage0(FPState
):
126 """ First stage of div.
129 def __init__(self
, pspec
):
130 FPState
.__init
__(self
, "divider_0")
131 self
.mod
= FPDivStage0Mod(pspec
)
132 self
.o
= self
.mod
.ospec()
134 def setup(self
, m
, i
):
135 """ links module to inputs and outputs
139 # NOTE: these could be done as combinatorial (merge div0+div1)
140 m
.d
.sync
+= self
.o
.eq(self
.mod
.o
)