1 # SPDX-License-Identifier: LGPL-2.1-or-later
2 # See Notices.txt for copyright information
3 """Integer Multiplication."""
5 from nmigen
import Signal
, Module
, Value
, Elaboratable
, Cat
, C
, Mux
, Repl
6 from nmigen
.hdl
.ast
import Assign
7 from abc
import ABCMeta
, abstractmethod
8 from nmigen
.cli
import main
9 from functools
import reduce
10 from operator
import or_
12 class PartitionPoints(dict):
13 """Partition points and corresponding ``Value``s.
15 The points at where an ALU is partitioned along with ``Value``s that
16 specify if the corresponding partition points are enabled.
18 For example: ``{1: True, 5: True, 10: True}`` with
19 ``width == 16`` specifies that the ALU is split into 4 sections:
22 * bits 5 <= ``i`` < 10
23 * bits 10 <= ``i`` < 16
25 If the partition_points were instead ``{1: True, 5: a, 10: True}``
26 where ``a`` is a 1-bit ``Signal``:
27 * If ``a`` is asserted:
30 * bits 5 <= ``i`` < 10
31 * bits 10 <= ``i`` < 16
34 * bits 1 <= ``i`` < 10
35 * bits 10 <= ``i`` < 16
38 def __init__(self
, partition_points
=None):
39 """Create a new ``PartitionPoints``.
41 :param partition_points: the input partition points to values mapping.
44 if partition_points
is not None:
45 for point
, enabled
in partition_points
.items():
46 if not isinstance(point
, int):
47 raise TypeError("point must be a non-negative integer")
49 raise ValueError("point must be a non-negative integer")
50 self
[point
] = Value
.wrap(enabled
)
52 def like(self
, name
=None, src_loc_at
=0):
53 """Create a new ``PartitionPoints`` with ``Signal``s for all values.
55 :param name: the base name for the new ``Signal``s.
58 name
= Signal(src_loc_at
=1+src_loc_at
).name
# get variable name
59 retval
= PartitionPoints()
60 for point
, enabled
in self
.items():
61 retval
[point
] = Signal(enabled
.shape(), name
=f
"{name}_{point}")
65 """Assign ``PartitionPoints`` using ``Signal.eq``."""
66 if set(self
.keys()) != set(rhs
.keys()):
67 raise ValueError("incompatible point set")
68 for point
, enabled
in self
.items():
69 yield enabled
.eq(rhs
[point
])
71 def as_mask(self
, width
):
72 """Create a bit-mask from `self`.
74 Each bit in the returned mask is clear only if the partition point at
75 the same bit-index is enabled.
77 :param width: the bit width of the resulting mask
80 for i
in range(width
):
87 def get_max_partition_count(self
, width
):
88 """Get the maximum number of partitions.
90 Gets the number of partitions when all partition points are enabled.
93 for point
in self
.keys():
98 def fits_in_width(self
, width
):
99 """Check if all partition points are smaller than `width`."""
100 for point
in self
.keys():
106 class FullAdder(Elaboratable
):
109 :attribute in0: the first input
110 :attribute in1: the second input
111 :attribute in2: the third input
112 :attribute sum: the sum output
113 :attribute carry: the carry output
116 def __init__(self
, width
):
117 """Create a ``FullAdder``.
119 :param width: the bit width of the input and output
121 self
.in0
= Signal(width
)
122 self
.in1
= Signal(width
)
123 self
.in2
= Signal(width
)
124 self
.sum = Signal(width
)
125 self
.carry
= Signal(width
)
127 def elaborate(self
, platform
):
128 """Elaborate this module."""
130 m
.d
.comb
+= self
.sum.eq(self
.in0 ^ self
.in1 ^ self
.in2
)
131 m
.d
.comb
+= self
.carry
.eq((self
.in0
& self
.in1
)
132 |
(self
.in1
& self
.in2
)
133 |
(self
.in2
& self
.in0
))
137 class PartitionedAdder(Elaboratable
):
138 """Partitioned Adder.
140 :attribute width: the bit width of the input and output. Read-only.
141 :attribute a: the first input to the adder
142 :attribute b: the second input to the adder
143 :attribute output: the sum output
144 :attribute partition_points: the input partition points. Modification not
145 supported, except for by ``Signal.eq``.
148 def __init__(self
, width
, partition_points
):
149 """Create a ``PartitionedAdder``.
151 :param width: the bit width of the input and output
152 :param partition_points: the input partition points
155 self
.a
= Signal(width
)
156 self
.b
= Signal(width
)
157 self
.output
= Signal(width
)
158 self
.partition_points
= PartitionPoints(partition_points
)
159 if not self
.partition_points
.fits_in_width(width
):
160 raise ValueError("partition_points doesn't fit in width")
162 for i
in range(self
.width
):
163 if i
in self
.partition_points
:
166 self
._expanded
_width
= expanded_width
167 self
._expanded
_a
= Signal(expanded_width
)
168 self
._expanded
_b
= Signal(expanded_width
)
169 self
._expanded
_output
= Signal(expanded_width
)
171 def elaborate(self
, platform
):
172 """Elaborate this module."""
175 # store bits in a list, use Cat later. graphviz is much cleaner
182 # partition points are "breaks" (extra zeros) in what would otherwise
183 # be a massive long add.
184 for i
in range(self
.width
):
185 if i
in self
.partition_points
:
186 # add extra bit set to 0 + 0 for enabled partition points
187 # and 1 + 0 for disabled partition points
188 ea
.append(self
._expanded
_a
[expanded_index
])
189 al
.append(~self
.partition_points
[i
])
190 eb
.append(self
._expanded
_b
[expanded_index
])
193 ea
.append(self
._expanded
_a
[expanded_index
])
195 eb
.append(self
._expanded
_b
[expanded_index
])
197 eo
.append(self
._expanded
_output
[expanded_index
])
198 ol
.append(self
.output
[i
])
200 # combine above using Cat
201 m
.d
.comb
+= Cat(*ea
).eq(Cat(*al
))
202 m
.d
.comb
+= Cat(*eb
).eq(Cat(*bl
))
203 m
.d
.comb
+= Cat(*ol
).eq(Cat(*eo
))
204 # use only one addition to take advantage of look-ahead carry and
205 # special hardware on FPGAs
206 m
.d
.comb
+= self
._expanded
_output
.eq(
207 self
._expanded
_a
+ self
._expanded
_b
)
211 FULL_ADDER_INPUT_COUNT
= 3
214 class AddReduce(Elaboratable
):
215 """Add list of numbers together.
217 :attribute inputs: input ``Signal``s to be summed. Modification not
218 supported, except for by ``Signal.eq``.
219 :attribute register_levels: List of nesting levels that should have
221 :attribute output: output sum.
222 :attribute partition_points: the input partition points. Modification not
223 supported, except for by ``Signal.eq``.
226 def __init__(self
, inputs
, output_width
, register_levels
, partition_points
):
227 """Create an ``AddReduce``.
229 :param inputs: input ``Signal``s to be summed.
230 :param output_width: bit-width of ``output``.
231 :param register_levels: List of nesting levels that should have
233 :param partition_points: the input partition points.
235 self
.inputs
= list(inputs
)
236 self
._resized
_inputs
= [
237 Signal(output_width
, name
=f
"resized_inputs[{i}]")
238 for i
in range(len(self
.inputs
))]
239 self
.register_levels
= list(register_levels
)
240 self
.output
= Signal(output_width
)
241 self
.partition_points
= PartitionPoints(partition_points
)
242 if not self
.partition_points
.fits_in_width(output_width
):
243 raise ValueError("partition_points doesn't fit in output_width")
244 self
._reg
_partition
_points
= self
.partition_points
.like()
245 max_level
= AddReduce
.get_max_level(len(self
.inputs
))
246 for level
in self
.register_levels
:
247 if level
> max_level
:
249 "not enough adder levels for specified register levels")
252 def get_max_level(input_count
):
253 """Get the maximum level.
255 All ``register_levels`` must be less than or equal to the maximum
260 groups
= AddReduce
.full_adder_groups(input_count
)
263 input_count
%= FULL_ADDER_INPUT_COUNT
264 input_count
+= 2 * len(groups
)
267 def next_register_levels(self
):
268 """``Iterable`` of ``register_levels`` for next recursive level."""
269 for level
in self
.register_levels
:
274 def full_adder_groups(input_count
):
275 """Get ``inputs`` indices for which a full adder should be built."""
277 input_count
- FULL_ADDER_INPUT_COUNT
+ 1,
278 FULL_ADDER_INPUT_COUNT
)
280 def elaborate(self
, platform
):
281 """Elaborate this module."""
284 # resize inputs to correct bit-width and optionally add in
286 resized_input_assignments
= [self
._resized
_inputs
[i
].eq(self
.inputs
[i
])
287 for i
in range(len(self
.inputs
))]
288 if 0 in self
.register_levels
:
289 m
.d
.sync
+= resized_input_assignments
290 m
.d
.sync
+= self
._reg
_partition
_points
.eq(self
.partition_points
)
292 m
.d
.comb
+= resized_input_assignments
293 m
.d
.comb
+= self
._reg
_partition
_points
.eq(self
.partition_points
)
295 groups
= AddReduce
.full_adder_groups(len(self
.inputs
))
296 # if there are no full adders to create, then we handle the base cases
297 # and return, otherwise we go on to the recursive case
299 if len(self
.inputs
) == 0:
300 # use 0 as the default output value
301 m
.d
.comb
+= self
.output
.eq(0)
302 elif len(self
.inputs
) == 1:
303 # handle single input
304 m
.d
.comb
+= self
.output
.eq(self
._resized
_inputs
[0])
306 # base case for adding 2 or more inputs, which get recursively
307 # reduced to 2 inputs
308 assert len(self
.inputs
) == 2
309 adder
= PartitionedAdder(len(self
.output
),
310 self
._reg
_partition
_points
)
311 m
.submodules
.final_adder
= adder
312 m
.d
.comb
+= adder
.a
.eq(self
._resized
_inputs
[0])
313 m
.d
.comb
+= adder
.b
.eq(self
._resized
_inputs
[1])
314 m
.d
.comb
+= self
.output
.eq(adder
.output
)
316 # go on to handle recursive case
317 intermediate_terms
= []
319 def add_intermediate_term(value
):
320 intermediate_term
= Signal(
322 name
=f
"intermediate_terms[{len(intermediate_terms)}]")
323 intermediate_terms
.append(intermediate_term
)
324 m
.d
.comb
+= intermediate_term
.eq(value
)
326 # store mask in intermediary (simplifies graph)
327 part_mask
= Signal(len(self
.output
), reset_less
=True)
328 mask
= self
._reg
_partition
_points
.as_mask(len(self
.output
))
329 m
.d
.comb
+= part_mask
.eq(mask
)
331 # create full adders for this recursive level.
332 # this shrinks N terms to 2 * (N // 3) plus the remainder
334 adder_i
= FullAdder(len(self
.output
))
335 setattr(m
.submodules
, f
"adder_{i}", adder_i
)
336 m
.d
.comb
+= adder_i
.in0
.eq(self
._resized
_inputs
[i
])
337 m
.d
.comb
+= adder_i
.in1
.eq(self
._resized
_inputs
[i
+ 1])
338 m
.d
.comb
+= adder_i
.in2
.eq(self
._resized
_inputs
[i
+ 2])
339 add_intermediate_term(adder_i
.sum)
340 shifted_carry
= adder_i
.carry
<< 1
341 # mask out carry bits to prevent carries between partitions
342 add_intermediate_term((adder_i
.carry
<< 1) & part_mask
)
343 # handle the remaining inputs.
344 if len(self
.inputs
) % FULL_ADDER_INPUT_COUNT
== 1:
345 add_intermediate_term(self
._resized
_inputs
[-1])
346 elif len(self
.inputs
) % FULL_ADDER_INPUT_COUNT
== 2:
347 # Just pass the terms to the next layer, since we wouldn't gain
348 # anything by using a half adder since there would still be 2 terms
349 # and just passing the terms to the next layer saves gates.
350 add_intermediate_term(self
._resized
_inputs
[-2])
351 add_intermediate_term(self
._resized
_inputs
[-1])
353 assert len(self
.inputs
) % FULL_ADDER_INPUT_COUNT
== 0
354 # recursive invocation of ``AddReduce``
355 next_level
= AddReduce(intermediate_terms
,
357 self
.next_register_levels(),
358 self
._reg
_partition
_points
)
359 m
.submodules
.next_level
= next_level
360 m
.d
.comb
+= self
.output
.eq(next_level
.output
)
365 OP_MUL_SIGNED_HIGH
= 1
366 OP_MUL_SIGNED_UNSIGNED_HIGH
= 2 # a is signed, b is unsigned
367 OP_MUL_UNSIGNED_HIGH
= 3
370 def get_term(value
, shift
=0, enabled
=None):
371 if enabled
is not None:
372 value
= Mux(enabled
, value
, 0)
374 value
= Cat(Repl(C(0, 1), shift
), value
)
380 class Term(Elaboratable
):
381 def __init__(self
, width
, twidth
, shift
=0, enabled
=None):
384 self
.enabled
= enabled
385 self
.ti
= Signal(width
, reset_less
=True)
386 self
.term
= Signal(twidth
, reset_less
=True)
388 def elaborate(self
, platform
):
391 m
.d
.comb
+= self
.term
.eq(get_term(self
.ti
, self
.shift
, self
.enabled
))
396 class ProductTerm(Elaboratable
):
397 def __init__(self
, width
, twidth
, pbwid
, a_index
, b_index
):
398 self
.a_index
= a_index
399 self
.b_index
= b_index
400 shift
= 8 * (self
.a_index
+ self
.b_index
)
402 self
.a
= Signal(twidth
//2, reset_less
=True)
403 self
.b
= Signal(twidth
//2, reset_less
=True)
404 self
.pb_en
= Signal(pbwid
, reset_less
=True)
407 min_index
= min(self
.a_index
, self
.b_index
)
408 max_index
= max(self
.a_index
, self
.b_index
)
409 for i
in range(min_index
, max_index
):
410 tl
.append(self
.pb_en
[i
])
411 name
= "te_%d_%d" % (self
.a_index
, self
.b_index
)
413 term_enabled
= Signal(name
=name
, reset_less
=True)
417 Term
.__init
__(self
, width
*2, twidth
, shift
, term_enabled
)
418 self
.term
.name
= "term_%d_%d" % (a_index
, b_index
) # rename
420 def elaborate(self
, platform
):
422 m
= Term
.elaborate(self
, platform
)
423 if self
.enabled
is not None:
424 m
.d
.comb
+= self
.enabled
.eq(~
(Cat(*self
.tl
).bool()))
426 bsa
= Signal(self
.width
, reset_less
=True)
427 bsb
= Signal(self
.width
, reset_less
=True)
428 a_index
, b_index
= self
.a_index
, self
.b_index
430 m
.d
.comb
+= bsa
.eq(self
.a
.bit_select(a_index
* pwidth
, pwidth
))
431 m
.d
.comb
+= bsb
.eq(self
.b
.bit_select(b_index
* pwidth
, pwidth
))
432 m
.d
.comb
+= self
.ti
.eq(bsa
* bsb
)
437 class ProductTerms(Elaboratable
):
439 def __init__(self
, width
, twidth
, pbwid
, a_index
, blen
):
440 self
.a_index
= a_index
445 self
.a
= Signal(twidth
//2, reset_less
=True)
446 self
.b
= Signal(twidth
//2, reset_less
=True)
447 self
.pb_en
= Signal(pbwid
, reset_less
=True)
448 self
.terms
= [Signal(twidth
, name
="term%d"%i, reset_less
=True) \
449 for i
in range(blen
)]
451 def elaborate(self
, platform
):
455 for b_index
in range(self
.blen
):
456 t
= ProductTerm(self
.pwidth
, self
.twidth
, self
.pbwid
,
457 self
.a_index
, b_index
)
458 setattr(m
.submodules
, "term_%d" % b_index
, t
)
460 m
.d
.comb
+= t
.a
.eq(self
.a
)
461 m
.d
.comb
+= t
.b
.eq(self
.b
)
462 m
.d
.comb
+= t
.pb_en
.eq(self
.pb_en
)
464 m
.d
.comb
+= self
.terms
[b_index
].eq(t
.term
)
469 class Part(Elaboratable
):
470 def __init__(self
, width
, n_parts
, n_levels
, pbwid
):
475 self
._a
_signed
= [Signal(name
=f
"_a_signed_{i}") for i
in range(8)]
476 self
._b
_signed
= [Signal(name
=f
"_b_signed_{i}") for i
in range(8)]
477 self
.pbs
= Signal(pbwid
, reset_less
=True)
480 self
.parts
= [Signal(name
=f
"part_{i}") for i
in range(n_parts
)]
481 self
.delayed_parts
= [
482 [Signal(name
=f
"delayed_part_8_{delay}_{i}")
483 for i
in range(n_parts
)]
484 for delay
in range(n_levels
)]
486 self
.not_a_term
= Signal(width
)
487 self
.neg_lsb_a_term
= Signal(width
)
488 self
.not_b_term
= Signal(width
)
489 self
.neg_lsb_b_term
= Signal(width
)
491 def elaborate(self
, platform
):
494 pbs
, parts
, delayed_parts
= self
.pbs
, self
.parts
, self
.delayed_parts
495 byte_count
= 8 // len(parts
)
496 for i
in range(len(parts
)):
498 pbl
.append(~pbs
[i
* byte_count
- 1])
499 for j
in range(i
* byte_count
, (i
+ 1) * byte_count
- 1):
501 pbl
.append(~pbs
[(i
+ 1) * byte_count
- 1])
502 value
= Signal(len(pbl
), reset_less
=True)
503 m
.d
.comb
+= value
.eq(Cat(*pbl
))
504 m
.d
.comb
+= parts
[i
].eq(~
(value
).bool())
505 m
.d
.comb
+= delayed_parts
[0][i
].eq(parts
[i
])
506 m
.d
.sync
+= [delayed_parts
[j
+ 1][i
].eq(delayed_parts
[j
][i
])
507 for j
in range(len(delayed_parts
)-1)]
509 not_a_term
, neg_lsb_a_term
, not_b_term
, neg_lsb_b_term
= \
510 self
.not_a_term
, self
.neg_lsb_a_term
, \
511 self
.not_b_term
, self
.neg_lsb_b_term
513 byte_width
= 8 // len(parts
)
514 bit_width
= 8 * byte_width
515 nat
, nbt
, nla
, nlb
= [], [], [], []
516 for i
in range(len(parts
)):
517 be
= parts
[i
] & self
.a
[(i
+ 1) * bit_width
- 1] \
518 & self
._a
_signed
[i
* byte_width
]
519 ae
= parts
[i
] & self
.b
[(i
+ 1) * bit_width
- 1] \
520 & self
._b
_signed
[i
* byte_width
]
521 a_enabled
= Signal(name
="a_en_%d" % i
, reset_less
=True)
522 b_enabled
= Signal(name
="b_en_%d" % i
, reset_less
=True)
523 m
.d
.comb
+= a_enabled
.eq(ae
)
524 m
.d
.comb
+= b_enabled
.eq(be
)
526 # for 8-bit values: form a * 0xFF00 by using -a * 0x100, the
527 # negation operation is split into a bitwise not and a +1.
528 # likewise for 16, 32, and 64-bit values.
529 nat
.append(Mux(a_enabled
,
530 Cat(Repl(0, bit_width
),
531 ~self
.a
.bit_select(bit_width
* i
, bit_width
)),
534 nla
.append(Cat(Repl(0, bit_width
), a_enabled
,
535 Repl(0, bit_width
-1)))
537 nbt
.append(Mux(b_enabled
,
538 Cat(Repl(0, bit_width
),
539 ~self
.b
.bit_select(bit_width
* i
, bit_width
)),
542 nlb
.append(Cat(Repl(0, bit_width
), b_enabled
,
543 Repl(0, bit_width
-1)))
545 m
.d
.comb
+= [not_a_term
.eq(Cat(*nat
)),
546 not_b_term
.eq(Cat(*nbt
)),
547 neg_lsb_a_term
.eq(Cat(*nla
)),
548 neg_lsb_b_term
.eq(Cat(*nlb
)),
554 class IntermediateOut(Elaboratable
):
555 def __init__(self
, width
, out_wid
, n_parts
):
557 self
.n_parts
= n_parts
558 self
.delayed_part_ops
= [Signal(2, name
="dpop%d" % i
, reset_less
=True)
560 self
.intermed
= Signal(out_wid
, reset_less
=True)
561 self
.output
= Signal(out_wid
//2, reset_less
=True)
563 def elaborate(self
, platform
):
569 for i
in range(self
.n_parts
):
570 op
= Signal(w
, reset_less
=True, name
="op32_%d" % i
)
572 Mux(self
.delayed_part_ops
[sel
* i
] == OP_MUL_LOW
,
573 self
.intermed
.bit_select(i
* w
*2, w
),
574 self
.intermed
.bit_select(i
* w
*2 + w
, w
)))
576 m
.d
.comb
+= self
.output
.eq(Cat(*ol
))
580 class OrMod(Elaboratable
):
581 def __init__(self
, wid
):
583 self
.orin
= [Signal(wid
, name
="orin%d" % i
, reset_less
=True)
585 self
.orout
= Signal(wid
, reset_less
=True)
587 def elaborate(self
, platform
):
589 or1
= Signal(self
.wid
, reset_less
=True)
590 or2
= Signal(self
.wid
, reset_less
=True)
591 m
.d
.comb
+= or1
.eq(self
.orin
[0] | self
.orin
[1])
592 m
.d
.comb
+= or2
.eq(self
.orin
[2] | self
.orin
[3])
593 m
.d
.comb
+= self
.orout
.eq(or1 | or2
)
598 class Mul8_16_32_64(Elaboratable
):
599 """Signed/Unsigned 8/16/32/64-bit partitioned integer multiplier.
601 Supports partitioning into any combination of 8, 16, 32, and 64-bit
602 partitions on naturally-aligned boundaries. Supports the operation being
603 set for each partition independently.
605 :attribute part_pts: the input partition points. Has a partition point at
606 multiples of 8 in 0 < i < 64. Each partition point's associated
607 ``Value`` is a ``Signal``. Modification not supported, except for by
609 :attribute part_ops: the operation for each byte. The operation for a
610 particular partition is selected by assigning the selected operation
611 code to each byte in the partition. The allowed operation codes are:
613 :attribute OP_MUL_LOW: the LSB half of the product. Equivalent to
614 RISC-V's `mul` instruction.
615 :attribute OP_MUL_SIGNED_HIGH: the MSB half of the product where both
616 ``a`` and ``b`` are signed. Equivalent to RISC-V's `mulh`
618 :attribute OP_MUL_SIGNED_UNSIGNED_HIGH: the MSB half of the product
619 where ``a`` is signed and ``b`` is unsigned. Equivalent to RISC-V's
620 `mulhsu` instruction.
621 :attribute OP_MUL_UNSIGNED_HIGH: the MSB half of the product where both
622 ``a`` and ``b`` are unsigned. Equivalent to RISC-V's `mulhu`
626 def __init__(self
, register_levels
= ()):
627 self
.part_pts
= PartitionPoints()
628 for i
in range(8, 64, 8):
629 self
.part_pts
[i
] = Signal(name
=f
"part_pts_{i}")
630 self
.part_ops
= [Signal(2, name
=f
"part_ops_{i}") for i
in range(8)]
633 self
.output
= Signal(64)
634 self
.register_levels
= list(register_levels
)
635 self
._intermediate
_output
= Signal(128)
636 self
._output
_64 = Signal(64)
637 self
._output
_32 = Signal(64)
638 self
._output
_16 = Signal(64)
639 self
._output
_8 = Signal(64)
640 self
._a
_signed
= [Signal(name
=f
"_a_signed_{i}") for i
in range(8)]
641 self
._b
_signed
= [Signal(name
=f
"_b_signed_{i}") for i
in range(8)]
643 def _part_byte(self
, index
):
644 if index
== -1 or index
== 7:
646 assert index
>= 0 and index
< 8
647 return self
.part_pts
[index
* 8 + 8]
649 def elaborate(self
, platform
):
653 pbs
= Signal(8, reset_less
=True)
656 pb
= Signal(name
="pb%d" % i
, reset_less
=True)
657 m
.d
.comb
+= pb
.eq(self
._part
_byte
(i
))
659 m
.d
.comb
+= pbs
.eq(Cat(*tl
))
662 [Signal(2, name
=f
"_delayed_part_ops_{delay}_{i}")
664 for delay
in range(1 + len(self
.register_levels
))]
665 for i
in range(len(self
.part_ops
)):
666 m
.d
.comb
+= delayed_part_ops
[0][i
].eq(self
.part_ops
[i
])
667 m
.d
.sync
+= [delayed_part_ops
[j
+ 1][i
].eq(delayed_part_ops
[j
][i
])
668 for j
in range(len(self
.register_levels
))]
670 n_levels
= len(self
.register_levels
)+1
671 m
.submodules
.part_8
= part_8
= Part(128, 8, n_levels
, 8)
672 m
.submodules
.part_16
= part_16
= Part(128, 4, n_levels
, 8)
673 m
.submodules
.part_32
= part_32
= Part(128, 2, n_levels
, 8)
674 m
.submodules
.part_64
= part_64
= Part(128, 1, n_levels
, 8)
675 nat_l
, nbt_l
, nla_l
, nlb_l
= [], [], [], []
676 for mod
in [part_8
, part_16
, part_32
, part_64
]:
677 m
.d
.comb
+= mod
.a
.eq(self
.a
)
678 m
.d
.comb
+= mod
.b
.eq(self
.b
)
679 for i
in range(len(self
._a
_signed
)):
680 m
.d
.comb
+= mod
._a
_signed
[i
].eq(self
._a
_signed
[i
])
681 for i
in range(len(self
._b
_signed
)):
682 m
.d
.comb
+= mod
._b
_signed
[i
].eq(self
._b
_signed
[i
])
683 m
.d
.comb
+= mod
.pbs
.eq(pbs
)
684 nat_l
.append(mod
.not_a_term
)
685 nbt_l
.append(mod
.not_b_term
)
686 nla_l
.append(mod
.neg_lsb_a_term
)
687 nlb_l
.append(mod
.neg_lsb_b_term
)
691 for a_index
in range(8):
692 t
= ProductTerms(8, 128, 8, a_index
, 8)
693 setattr(m
.submodules
, "terms_%d" % a_index
, t
)
695 m
.d
.comb
+= t
.a
.eq(self
.a
)
696 m
.d
.comb
+= t
.b
.eq(self
.b
)
697 m
.d
.comb
+= t
.pb_en
.eq(pbs
)
703 a_signed
= self
.part_ops
[i
] != OP_MUL_UNSIGNED_HIGH
704 b_signed
= (self
.part_ops
[i
] == OP_MUL_LOW
) \
705 |
(self
.part_ops
[i
] == OP_MUL_SIGNED_HIGH
)
706 m
.d
.comb
+= self
._a
_signed
[i
].eq(a_signed
)
707 m
.d
.comb
+= self
._b
_signed
[i
].eq(b_signed
)
709 # it's fine to bitwise-or data together since they are never enabled
711 m
.submodules
.nat_or
= nat_or
= OrMod(128)
712 m
.submodules
.nbt_or
= nbt_or
= OrMod(128)
713 m
.submodules
.nla_or
= nla_or
= OrMod(128)
714 m
.submodules
.nlb_or
= nlb_or
= OrMod(128)
715 for l
, mod
in [(nat_l
, nat_or
),
719 for i
in range(len(l
)):
720 m
.d
.comb
+= mod
.orin
[i
].eq(l
[i
])
721 terms
.append(mod
.orout
)
723 expanded_part_pts
= PartitionPoints()
724 for i
, v
in self
.part_pts
.items():
725 signal
= Signal(name
=f
"expanded_part_pts_{i*2}", reset_less
=True)
726 expanded_part_pts
[i
* 2] = signal
727 m
.d
.comb
+= signal
.eq(v
)
729 add_reduce
= AddReduce(terms
,
731 self
.register_levels
,
733 m
.submodules
.add_reduce
= add_reduce
734 m
.d
.comb
+= self
._intermediate
_output
.eq(add_reduce
.output
)
736 m
.submodules
.io64
= io64
= IntermediateOut(64, 128, 1)
737 m
.d
.comb
+= io64
.intermed
.eq(self
._intermediate
_output
)
739 m
.d
.comb
+= io64
.delayed_part_ops
[i
].eq(delayed_part_ops
[-1][i
])
740 m
.d
.comb
+= self
._output
_64.eq(io64
.output
)
743 m
.submodules
.io32
= io32
= IntermediateOut(32, 128, 2)
744 m
.d
.comb
+= io32
.intermed
.eq(self
._intermediate
_output
)
746 m
.d
.comb
+= io32
.delayed_part_ops
[i
].eq(delayed_part_ops
[-1][i
])
747 m
.d
.comb
+= self
._output
_32.eq(io32
.output
)
750 m
.submodules
.io16
= io16
= IntermediateOut(16, 128, 4)
751 m
.d
.comb
+= io16
.intermed
.eq(self
._intermediate
_output
)
753 m
.d
.comb
+= io16
.delayed_part_ops
[i
].eq(delayed_part_ops
[-1][i
])
754 m
.d
.comb
+= self
._output
_16.eq(io16
.output
)
757 m
.submodules
.io8
= io8
= IntermediateOut(8, 128, 8)
758 m
.d
.comb
+= io8
.intermed
.eq(self
._intermediate
_output
)
760 m
.d
.comb
+= io8
.delayed_part_ops
[i
].eq(delayed_part_ops
[-1][i
])
761 m
.d
.comb
+= self
._output
_8.eq(io8
.output
)
766 op
= Signal(8, reset_less
=True, name
="op%d" % i
)
768 Mux(part_8
.delayed_parts
[-1][i
]
769 | part_16
.delayed_parts
[-1][i
// 2],
770 Mux(part_8
.delayed_parts
[-1][i
],
771 self
._output
_8.bit_select(i
* 8, 8),
772 self
._output
_16.bit_select(i
* 8, 8)),
773 Mux(part_32
.delayed_parts
[-1][i
// 4],
774 self
._output
_32.bit_select(i
* 8, 8),
775 self
._output
_64.bit_select(i
* 8, 8))))
777 m
.d
.comb
+= self
.output
.eq(Cat(*ol
))
781 if __name__
== "__main__":
785 m
._intermediate
_output
,
788 *m
.part_pts
.values()])