2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "program/prog_instruction.h"
28 #include "blorp_priv.h"
29 #include "compiler/brw_compiler.h"
30 #include "compiler/brw_nir.h"
33 blorp_init(struct blorp_context
*blorp
, void *driver_ctx
,
34 struct isl_device
*isl_dev
)
36 blorp
->driver_ctx
= driver_ctx
;
37 blorp
->isl_dev
= isl_dev
;
41 blorp_finish(struct blorp_context
*blorp
)
43 blorp
->driver_ctx
= NULL
;
47 blorp_batch_init(struct blorp_context
*blorp
,
48 struct blorp_batch
*batch
, void *driver_batch
,
49 enum blorp_batch_flags flags
)
52 batch
->driver_batch
= driver_batch
;
57 blorp_batch_finish(struct blorp_batch
*batch
)
63 brw_blorp_surface_info_init(struct blorp_context
*blorp
,
64 struct brw_blorp_surface_info
*info
,
65 const struct blorp_surf
*surf
,
66 unsigned int level
, unsigned int layer
,
67 enum isl_format format
, bool is_render_target
)
69 memset(info
, 0, sizeof(*info
));
70 assert(level
< surf
->surf
->levels
);
71 assert(layer
< MAX2(surf
->surf
->logical_level0_px
.depth
>> level
,
72 surf
->surf
->logical_level0_px
.array_len
));
76 if (format
== ISL_FORMAT_UNSUPPORTED
)
77 format
= surf
->surf
->format
;
79 info
->surf
= *surf
->surf
;
80 info
->addr
= surf
->addr
;
82 info
->aux_usage
= surf
->aux_usage
;
83 if (info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
84 info
->aux_surf
= *surf
->aux_surf
;
85 info
->aux_addr
= surf
->aux_addr
;
88 info
->clear_color
= surf
->clear_color
;
89 info
->clear_color_addr
= surf
->clear_color_addr
;
91 info
->view
= (struct isl_view
) {
92 .usage
= is_render_target
? ISL_SURF_USAGE_RENDER_TARGET_BIT
:
93 ISL_SURF_USAGE_TEXTURE_BIT
,
97 .swizzle
= ISL_SWIZZLE_IDENTITY
,
100 info
->view
.array_len
= MAX2(info
->surf
.logical_level0_px
.depth
,
101 info
->surf
.logical_level0_px
.array_len
);
103 if (!is_render_target
&&
104 (info
->surf
.dim
== ISL_SURF_DIM_3D
||
105 info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
)) {
106 /* 3-D textures don't support base_array layer and neither do 2-D
107 * multisampled textures on IVB so we need to pass it through the
108 * sampler in those cases. These are also two cases where we are
109 * guaranteed that we won't be doing any funny surface hacks.
111 info
->view
.base_array_layer
= 0;
112 info
->z_offset
= layer
;
114 info
->view
.base_array_layer
= layer
;
116 assert(info
->view
.array_len
>= info
->view
.base_array_layer
);
117 info
->view
.array_len
-= info
->view
.base_array_layer
;
121 /* Sandy Bridge and earlier have a limit of a maximum of 512 layers for
124 if (is_render_target
&& blorp
->isl_dev
->info
->gen
<= 6)
125 info
->view
.array_len
= MIN2(info
->view
.array_len
, 512);
127 if (surf
->tile_x_sa
|| surf
->tile_y_sa
) {
128 /* This is only allowed on simple 2D surfaces without MSAA */
129 assert(info
->surf
.dim
== ISL_SURF_DIM_2D
);
130 assert(info
->surf
.samples
== 1);
131 assert(info
->surf
.levels
== 1);
132 assert(info
->surf
.logical_level0_px
.array_len
== 1);
133 assert(info
->aux_usage
== ISL_AUX_USAGE_NONE
);
135 info
->tile_x_sa
= surf
->tile_x_sa
;
136 info
->tile_y_sa
= surf
->tile_y_sa
;
138 /* Instead of using the X/Y Offset fields in RENDER_SURFACE_STATE, we
139 * place the image at the tile boundary and offset our sampling or
140 * rendering. For this reason, we need to grow the image by the offset
141 * to ensure that the hardware doesn't think we've gone past the edge.
143 info
->surf
.logical_level0_px
.w
+= surf
->tile_x_sa
;
144 info
->surf
.logical_level0_px
.h
+= surf
->tile_y_sa
;
145 info
->surf
.phys_level0_sa
.w
+= surf
->tile_x_sa
;
146 info
->surf
.phys_level0_sa
.h
+= surf
->tile_y_sa
;
152 blorp_params_init(struct blorp_params
*params
)
154 memset(params
, 0, sizeof(*params
));
155 params
->num_samples
= 1;
156 params
->num_draw_buffers
= 1;
157 params
->num_layers
= 1;
161 brw_blorp_init_wm_prog_key(struct brw_wm_prog_key
*wm_key
)
163 memset(wm_key
, 0, sizeof(*wm_key
));
164 wm_key
->nr_color_regions
= 1;
165 for (int i
= 0; i
< MAX_SAMPLERS
; i
++)
166 wm_key
->base
.tex
.swizzles
[i
] = SWIZZLE_XYZW
;
170 blorp_compile_fs(struct blorp_context
*blorp
, void *mem_ctx
,
171 struct nir_shader
*nir
,
172 struct brw_wm_prog_key
*wm_key
,
174 struct brw_wm_prog_data
*wm_prog_data
)
176 const struct brw_compiler
*compiler
= blorp
->compiler
;
179 compiler
->glsl_compiler_options
[MESA_SHADER_FRAGMENT
].NirOptions
;
181 memset(wm_prog_data
, 0, sizeof(*wm_prog_data
));
183 wm_prog_data
->base
.nr_params
= 0;
184 wm_prog_data
->base
.param
= NULL
;
186 /* BLORP always uses the first two binding table entries:
187 * - Surface 0 is the render target (which always start from 0)
188 * - Surface 1 is the source texture
190 wm_prog_data
->base
.binding_table
.texture_start
= BLORP_TEXTURE_BT_INDEX
;
192 brw_preprocess_nir(compiler
, nir
, NULL
);
193 nir_remove_dead_variables(nir
, nir_var_shader_in
, NULL
);
194 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
196 if (blorp
->compiler
->devinfo
->gen
< 6) {
197 if (nir
->info
.fs
.uses_discard
)
198 wm_key
->iz_lookup
|= BRW_WM_IZ_PS_KILL_ALPHATEST_BIT
;
200 wm_key
->input_slots_valid
= nir
->info
.inputs_read
| VARYING_BIT_POS
;
203 const unsigned *program
=
204 brw_compile_fs(compiler
, blorp
->driver_ctx
, mem_ctx
, wm_key
,
205 wm_prog_data
, nir
, -1, -1, -1, false, use_repclear
,
212 blorp_compile_vs(struct blorp_context
*blorp
, void *mem_ctx
,
213 struct nir_shader
*nir
,
214 struct brw_vs_prog_data
*vs_prog_data
)
216 const struct brw_compiler
*compiler
= blorp
->compiler
;
219 compiler
->glsl_compiler_options
[MESA_SHADER_VERTEX
].NirOptions
;
221 brw_preprocess_nir(compiler
, nir
, NULL
);
222 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
224 vs_prog_data
->inputs_read
= nir
->info
.inputs_read
;
226 brw_compute_vue_map(compiler
->devinfo
,
227 &vs_prog_data
->base
.vue_map
,
228 nir
->info
.outputs_written
,
229 nir
->info
.separate_shader
,
232 struct brw_vs_prog_key vs_key
= { 0, };
234 const unsigned *program
=
235 brw_compile_vs(compiler
, blorp
->driver_ctx
, mem_ctx
,
236 &vs_key
, vs_prog_data
, nir
, -1, NULL
, NULL
);
241 struct blorp_sf_key
{
242 enum blorp_shader_type shader_type
; /* Must be BLORP_SHADER_TYPE_GEN4_SF */
244 struct brw_sf_prog_key key
;
248 blorp_ensure_sf_program(struct blorp_batch
*batch
,
249 struct blorp_params
*params
)
251 struct blorp_context
*blorp
= batch
->blorp
;
252 const struct brw_wm_prog_data
*wm_prog_data
= params
->wm_prog_data
;
253 assert(params
->wm_prog_data
);
255 /* Gen6+ doesn't need a strips and fans program */
256 if (blorp
->compiler
->devinfo
->gen
>= 6)
259 struct blorp_sf_key key
= {
260 .shader_type
= BLORP_SHADER_TYPE_GEN4_SF
,
263 /* Everything gets compacted in vertex setup, so we just need a
264 * pass-through for the correct number of input varyings.
266 const uint64_t slots_valid
= VARYING_BIT_POS
|
267 ((1ull << wm_prog_data
->num_varying_inputs
) - 1) << VARYING_SLOT_VAR0
;
269 key
.key
.attrs
= slots_valid
;
270 key
.key
.primitive
= BRW_SF_PRIM_TRIANGLES
;
271 key
.key
.contains_flat_varying
= wm_prog_data
->contains_flat_varying
;
273 STATIC_ASSERT(sizeof(key
.key
.interp_mode
) ==
274 sizeof(wm_prog_data
->interp_mode
));
275 memcpy(key
.key
.interp_mode
, wm_prog_data
->interp_mode
,
276 sizeof(key
.key
.interp_mode
));
278 if (blorp
->lookup_shader(batch
, &key
, sizeof(key
),
279 ¶ms
->sf_prog_kernel
, ¶ms
->sf_prog_data
))
282 void *mem_ctx
= ralloc_context(NULL
);
284 const unsigned *program
;
285 unsigned program_size
;
287 struct brw_vue_map vue_map
;
288 brw_compute_vue_map(blorp
->compiler
->devinfo
, &vue_map
, slots_valid
, false, 1);
290 struct brw_sf_prog_data prog_data_tmp
;
291 program
= brw_compile_sf(blorp
->compiler
, mem_ctx
, &key
.key
,
292 &prog_data_tmp
, &vue_map
, &program_size
);
295 blorp
->upload_shader(batch
, MESA_SHADER_NONE
,
296 &key
, sizeof(key
), program
, program_size
,
297 (void *)&prog_data_tmp
, sizeof(prog_data_tmp
),
298 ¶ms
->sf_prog_kernel
, ¶ms
->sf_prog_data
);
300 ralloc_free(mem_ctx
);
306 blorp_hiz_op(struct blorp_batch
*batch
, struct blorp_surf
*surf
,
307 uint32_t level
, uint32_t start_layer
, uint32_t num_layers
,
310 struct blorp_params params
;
311 blorp_params_init(¶ms
);
314 params
.full_surface_hiz_op
= true;
316 for (uint32_t a
= 0; a
< num_layers
; a
++) {
317 const uint32_t layer
= start_layer
+ a
;
319 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.depth
, surf
, level
,
320 layer
, surf
->surf
->format
, true);
322 /* Align the rectangle primitive to 8x4 pixels.
324 * During fast depth clears, the emitted rectangle primitive must be
325 * aligned to 8x4 pixels. From the Ivybridge PRM, Vol 2 Part 1 Section
326 * 11.5.3.1 Depth Buffer Clear (and the matching section in the
329 * If Number of Multisamples is NUMSAMPLES_1, the rectangle must be
330 * aligned to an 8x4 pixel block relative to the upper left corner
331 * of the depth buffer [...]
333 * For hiz resolves, the rectangle must also be 8x4 aligned. Item
334 * WaHizAmbiguate8x4Aligned from the Haswell workarounds page and the
335 * Ivybridge simulator require the alignment.
337 * To be safe, let's just align the rect for all hiz operations and all
338 * hardware generations.
340 * However, for some miptree slices of a Z24 texture, emitting an 8x4
341 * aligned rectangle that covers the slice may clobber adjacent slices
342 * if we strictly adhered to the texture alignments specified in the
343 * PRM. The Ivybridge PRM, Section "Alignment Unit Size", states that
344 * SURFACE_STATE.Surface_Horizontal_Alignment should be 4 for Z24
345 * surfaces, not 8. But commit 1f112cc increased the alignment from 4 to
346 * 8, which prevents the clobbering.
348 params
.x1
= minify(params
.depth
.surf
.logical_level0_px
.width
,
349 params
.depth
.view
.base_level
);
350 params
.y1
= minify(params
.depth
.surf
.logical_level0_px
.height
,
351 params
.depth
.view
.base_level
);
352 params
.x1
= ALIGN(params
.x1
, 8);
353 params
.y1
= ALIGN(params
.y1
, 4);
355 if (params
.depth
.view
.base_level
== 0) {
356 /* TODO: What about MSAA? */
357 params
.depth
.surf
.logical_level0_px
.width
= params
.x1
;
358 params
.depth
.surf
.logical_level0_px
.height
= params
.y1
;
361 params
.dst
.surf
.samples
= params
.depth
.surf
.samples
;
362 params
.dst
.surf
.logical_level0_px
= params
.depth
.surf
.logical_level0_px
;
363 params
.depth_format
=
364 isl_format_get_depth_format(surf
->surf
->format
, false);
365 params
.num_samples
= params
.depth
.surf
.samples
;
367 batch
->blorp
->exec(batch
, ¶ms
);
372 blorp_hiz_stencil_op(struct blorp_batch
*batch
, struct blorp_surf
*stencil
,
373 uint32_t level
, uint32_t start_layer
,
374 uint32_t num_layers
, enum isl_aux_op op
)
376 struct blorp_params params
;
377 blorp_params_init(¶ms
);
380 params
.full_surface_hiz_op
= true;
382 for (uint32_t a
= 0; a
< num_layers
; a
++) {
383 const uint32_t layer
= start_layer
+ a
;
385 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.stencil
, stencil
, level
,
386 layer
, stencil
->surf
->format
, true);
387 params
.x1
= minify(params
.stencil
.surf
.logical_level0_px
.width
,
388 params
.stencil
.view
.base_level
);
389 params
.y1
= minify(params
.stencil
.surf
.logical_level0_px
.height
,
390 params
.stencil
.view
.base_level
);
391 params
.dst
.surf
.samples
= params
.stencil
.surf
.samples
;
392 params
.dst
.surf
.logical_level0_px
=
393 params
.stencil
.surf
.logical_level0_px
;
394 params
.dst
.view
= params
.stencil
.view
;
395 params
.num_samples
= params
.stencil
.surf
.samples
;
397 batch
->blorp
->exec(batch
, ¶ms
);