2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #ifndef BLORP_GENX_EXEC_H
25 #define BLORP_GENX_EXEC_H
27 #include "blorp_priv.h"
28 #include "dev/gen_device_info.h"
29 #include "common/gen_sample_positions.h"
30 #include "genxml/gen_macros.h"
33 * This file provides the blorp pipeline setup and execution functionality.
34 * It defines the following function:
37 * blorp_exec(struct blorp_context *blorp, void *batch_data,
38 * const struct blorp_params *params);
40 * It is the job of whoever includes this header to wrap this in something
41 * to get an externally visible symbol.
43 * In order for the blorp_exec function to work, the driver must provide
44 * implementations of the following static helper functions.
48 blorp_emit_dwords(struct blorp_batch
*batch
, unsigned n
);
51 blorp_emit_reloc(struct blorp_batch
*batch
,
52 void *location
, struct blorp_address address
, uint32_t delta
);
55 blorp_alloc_dynamic_state(struct blorp_batch
*batch
,
60 blorp_alloc_vertex_buffer(struct blorp_batch
*batch
, uint32_t size
,
61 struct blorp_address
*addr
);
63 blorp_vf_invalidate_for_vb_48b_transitions(struct blorp_batch
*batch
,
64 const struct blorp_address
*addrs
,
69 static struct blorp_address
70 blorp_get_workaround_page(struct blorp_batch
*batch
);
74 blorp_alloc_binding_table(struct blorp_batch
*batch
, unsigned num_entries
,
75 unsigned state_size
, unsigned state_alignment
,
76 uint32_t *bt_offset
, uint32_t *surface_offsets
,
80 blorp_flush_range(struct blorp_batch
*batch
, void *start
, size_t size
);
83 blorp_surface_reloc(struct blorp_batch
*batch
, uint32_t ss_offset
,
84 struct blorp_address address
, uint32_t delta
);
87 blorp_get_surface_address(struct blorp_batch
*batch
,
88 struct blorp_address address
);
90 #if GEN_GEN >= 7 && GEN_GEN < 10
91 static struct blorp_address
92 blorp_get_surface_base_address(struct blorp_batch
*batch
);
96 blorp_emit_urb_config(struct blorp_batch
*batch
,
97 unsigned vs_entry_size
, unsigned sf_entry_size
);
100 blorp_emit_pipeline(struct blorp_batch
*batch
,
101 const struct blorp_params
*params
);
103 /***** BEGIN blorp_exec implementation ******/
106 _blorp_combine_address(struct blorp_batch
*batch
, void *location
,
107 struct blorp_address address
, uint32_t delta
)
109 if (address
.buffer
== NULL
) {
110 return address
.offset
+ delta
;
112 return blorp_emit_reloc(batch
, location
, address
, delta
);
116 #define __gen_address_type struct blorp_address
117 #define __gen_user_data struct blorp_batch
118 #define __gen_combine_address _blorp_combine_address
120 #include "genxml/genX_pack.h"
122 #define _blorp_cmd_length(cmd) cmd ## _length
123 #define _blorp_cmd_length_bias(cmd) cmd ## _length_bias
124 #define _blorp_cmd_header(cmd) cmd ## _header
125 #define _blorp_cmd_pack(cmd) cmd ## _pack
127 #define blorp_emit(batch, cmd, name) \
128 for (struct cmd name = { _blorp_cmd_header(cmd) }, \
129 *_dst = blorp_emit_dwords(batch, _blorp_cmd_length(cmd)); \
130 __builtin_expect(_dst != NULL, 1); \
131 _blorp_cmd_pack(cmd)(batch, (void *)_dst, &name), \
134 #define blorp_emitn(batch, cmd, n, ...) ({ \
135 uint32_t *_dw = blorp_emit_dwords(batch, n); \
137 struct cmd template = { \
138 _blorp_cmd_header(cmd), \
139 .DWordLength = n - _blorp_cmd_length_bias(cmd), \
142 _blorp_cmd_pack(cmd)(batch, _dw, &template); \
144 _dw ? _dw + 1 : NULL; /* Array starts at dw[1] */ \
147 #define STRUCT_ZERO(S) ({ struct S t; memset(&t, 0, sizeof(t)); t; })
149 #define blorp_emit_dynamic(batch, state, name, align, offset) \
150 for (struct state name = STRUCT_ZERO(state), \
151 *_dst = blorp_alloc_dynamic_state(batch, \
152 _blorp_cmd_length(state) * 4, \
154 __builtin_expect(_dst != NULL, 1); \
155 _blorp_cmd_pack(state)(batch, (void *)_dst, &name), \
156 blorp_flush_range(batch, _dst, _blorp_cmd_length(state) * 4), \
165 * Assign the entire URB to the VS. Even though the VS disabled, URB space
166 * is still needed because the clipper loads the VUE's from the URB. From
167 * the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE,
168 * Dword 1.15:0 "VS Number of URB Entries":
169 * This field is always used (even if VS Function Enable is DISABLED).
171 * The warning below appears in the PRM (Section 3DSTATE_URB), but we can
172 * safely ignore it because this batch contains only one draw call.
173 * Because of URB corruption caused by allocating a previous GS unit
174 * URB entry to the VS unit, software is required to send a “GS NULL
175 * Fence” (Send URB fence with VS URB size == 1 and GS URB size == 0)
176 * plus a dummy DRAW call before any case where VS will be taking over
179 * If the 3DSTATE_URB_VS is emitted, than the others must be also.
180 * From the Ivybridge PRM, Volume 2 Part 1, section 1.7.1 3DSTATE_URB_VS:
182 * 3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
183 * programmed in order for the programming of this state to be
187 emit_urb_config(struct blorp_batch
*batch
,
188 const struct blorp_params
*params
)
190 /* Once vertex fetcher has written full VUE entries with complete
191 * header the space requirement is as follows per vertex (in bytes):
193 * Header Position Program constants
194 * +--------+------------+-------------------+
195 * | 16 | 16 | n x 16 |
196 * +--------+------------+-------------------+
198 * where 'n' stands for number of varying inputs expressed as vec4s.
200 const unsigned num_varyings
=
201 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
202 const unsigned total_needed
= 16 + 16 + num_varyings
* 16;
204 /* The URB size is expressed in units of 64 bytes (512 bits) */
205 const unsigned vs_entry_size
= DIV_ROUND_UP(total_needed
, 64);
207 const unsigned sf_entry_size
=
208 params
->sf_prog_data
? params
->sf_prog_data
->urb_entry_size
: 0;
210 blorp_emit_urb_config(batch
, vs_entry_size
, sf_entry_size
);
215 blorp_emit_memcpy(struct blorp_batch
*batch
,
216 struct blorp_address dst
,
217 struct blorp_address src
,
222 blorp_emit_vertex_data(struct blorp_batch
*batch
,
223 const struct blorp_params
*params
,
224 struct blorp_address
*addr
,
227 const float vertices
[] = {
228 /* v0 */ (float)params
->x1
, (float)params
->y1
, params
->z
,
229 /* v1 */ (float)params
->x0
, (float)params
->y1
, params
->z
,
230 /* v2 */ (float)params
->x0
, (float)params
->y0
, params
->z
,
233 void *data
= blorp_alloc_vertex_buffer(batch
, sizeof(vertices
), addr
);
234 memcpy(data
, vertices
, sizeof(vertices
));
235 *size
= sizeof(vertices
);
236 blorp_flush_range(batch
, data
, *size
);
240 blorp_emit_input_varying_data(struct blorp_batch
*batch
,
241 const struct blorp_params
*params
,
242 struct blorp_address
*addr
,
245 const unsigned vec4_size_in_bytes
= 4 * sizeof(float);
246 const unsigned max_num_varyings
=
247 DIV_ROUND_UP(sizeof(params
->wm_inputs
), vec4_size_in_bytes
);
248 const unsigned num_varyings
=
249 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
251 *size
= 16 + num_varyings
* vec4_size_in_bytes
;
253 const uint32_t *const inputs_src
= (const uint32_t *)¶ms
->wm_inputs
;
254 void *data
= blorp_alloc_vertex_buffer(batch
, *size
, addr
);
255 uint32_t *inputs
= data
;
257 /* Copy in the VS inputs */
258 assert(sizeof(params
->vs_inputs
) == 16);
259 memcpy(inputs
, ¶ms
->vs_inputs
, sizeof(params
->vs_inputs
));
262 if (params
->wm_prog_data
) {
263 /* Walk over the attribute slots, determine if the attribute is used by
264 * the program and when necessary copy the values from the input storage
265 * to the vertex data buffer.
267 for (unsigned i
= 0; i
< max_num_varyings
; i
++) {
268 const gl_varying_slot attr
= VARYING_SLOT_VAR0
+ i
;
270 const int input_index
= params
->wm_prog_data
->urb_setup
[attr
];
274 memcpy(inputs
, inputs_src
+ i
* 4, vec4_size_in_bytes
);
280 blorp_flush_range(batch
, data
, *size
);
282 if (params
->dst_clear_color_as_input
) {
284 /* In this case, the clear color isn't known statically and instead
285 * comes in through an indirect which we have to copy into the vertex
286 * buffer before we execute the 3DPRIMITIVE. We already copied the
287 * value of params->wm_inputs.clear_color into the vertex buffer in the
288 * loop above. Now we emit code to stomp it from the GPU with the
289 * actual clear color value.
291 assert(num_varyings
== 1);
293 /* The clear color is the first thing after the header */
294 struct blorp_address clear_color_input_addr
= *addr
;
295 clear_color_input_addr
.offset
+= 16;
297 const unsigned clear_color_size
=
298 GEN_GEN
< 10 ? batch
->blorp
->isl_dev
->ss
.clear_value_size
: 4 * 4;
299 blorp_emit_memcpy(batch
, clear_color_input_addr
,
300 params
->dst
.clear_color_addr
,
303 unreachable("MCS partial resolve is not a thing on SNB and earlier");
309 blorp_fill_vertex_buffer_state(struct blorp_batch
*batch
,
310 struct GENX(VERTEX_BUFFER_STATE
) *vb
,
312 struct blorp_address addr
, uint32_t size
,
315 vb
[idx
].VertexBufferIndex
= idx
;
316 vb
[idx
].BufferStartingAddress
= addr
;
317 vb
[idx
].BufferPitch
= stride
;
320 vb
[idx
].MOCS
= addr
.mocs
;
324 vb
[idx
].AddressModifyEnable
= true;
328 vb
[idx
].BufferSize
= size
;
330 vb
[idx
].BufferAccessType
= stride
> 0 ? VERTEXDATA
: INSTANCEDATA
;
331 vb
[idx
].EndAddress
= vb
[idx
].BufferStartingAddress
;
332 vb
[idx
].EndAddress
.offset
+= size
- 1;
334 vb
[idx
].BufferAccessType
= stride
> 0 ? VERTEXDATA
: INSTANCEDATA
;
335 vb
[idx
].MaxIndex
= stride
> 0 ? size
/ stride
: 0;
340 blorp_emit_vertex_buffers(struct blorp_batch
*batch
,
341 const struct blorp_params
*params
)
343 struct GENX(VERTEX_BUFFER_STATE
) vb
[3];
344 uint32_t num_vbs
= 2;
345 memset(vb
, 0, sizeof(vb
));
347 struct blorp_address addrs
[2] = {};
349 blorp_emit_vertex_data(batch
, params
, &addrs
[0], &sizes
[0]);
350 blorp_fill_vertex_buffer_state(batch
, vb
, 0, addrs
[0], sizes
[0],
353 blorp_emit_input_varying_data(batch
, params
, &addrs
[1], &sizes
[1]);
354 blorp_fill_vertex_buffer_state(batch
, vb
, 1, addrs
[1], sizes
[1], 0);
356 blorp_vf_invalidate_for_vb_48b_transitions(batch
, addrs
, sizes
, num_vbs
);
358 const unsigned num_dwords
= 1 + num_vbs
* GENX(VERTEX_BUFFER_STATE_length
);
359 uint32_t *dw
= blorp_emitn(batch
, GENX(3DSTATE_VERTEX_BUFFERS
), num_dwords
);
363 for (unsigned i
= 0; i
< num_vbs
; i
++) {
364 GENX(VERTEX_BUFFER_STATE_pack
)(batch
, dw
, &vb
[i
]);
365 dw
+= GENX(VERTEX_BUFFER_STATE_length
);
370 blorp_emit_vertex_elements(struct blorp_batch
*batch
,
371 const struct blorp_params
*params
)
373 const unsigned num_varyings
=
374 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
375 bool need_ndc
= batch
->blorp
->compiler
->devinfo
->gen
<= 5;
376 const unsigned num_elements
= 2 + need_ndc
+ num_varyings
;
378 struct GENX(VERTEX_ELEMENT_STATE
) ve
[num_elements
];
379 memset(ve
, 0, num_elements
* sizeof(*ve
));
381 /* Setup VBO for the rectangle primitive..
383 * A rectangle primitive (3DPRIM_RECTLIST) consists of only three
384 * vertices. The vertices reside in screen space with DirectX
385 * coordinates (that is, (0, 0) is the upper left corner).
392 * Since the VS is disabled, the clipper loads each VUE directly from
393 * the URB. This is controlled by the 3DSTATE_VERTEX_BUFFERS and
394 * 3DSTATE_VERTEX_ELEMENTS packets below. The VUE contents are as follows:
395 * dw0: Reserved, MBZ.
396 * dw1: Render Target Array Index. Below vertex fetcher gets programmed
397 * to assign this with primitive instance identifier which will be
398 * used for layered clears. All other renders have only one instance
399 * and therefore the value will be effectively zero.
400 * dw2: Viewport Index. The HiZ op disables viewport mapping and
401 * scissoring, so set the dword to 0.
402 * dw3: Point Width: The HiZ op does not emit the POINTLIST primitive,
403 * so set the dword to 0.
404 * dw4: Vertex Position X.
405 * dw5: Vertex Position Y.
406 * dw6: Vertex Position Z.
407 * dw7: Vertex Position W.
409 * dw8: Flat vertex input 0
410 * dw9: Flat vertex input 1
412 * dwn: Flat vertex input n - 8
414 * For details, see the Sandybridge PRM, Volume 2, Part 1, Section 1.5.1
415 * "Vertex URB Entry (VUE) Formats".
417 * Only vertex position X and Y are going to be variable, Z is fixed to
418 * zero and W to one. Header words dw0,2,3 are zero. There is no need to
419 * include the fixed values in the vertex buffer. Vertex fetcher can be
420 * instructed to fill vertex elements with constant values of one and zero
421 * instead of reading them from the buffer.
422 * Flat inputs are program constants that are not interpolated. Moreover
423 * their values will be the same between vertices.
425 * See the vertex element setup below.
429 ve
[slot
] = (struct GENX(VERTEX_ELEMENT_STATE
)) {
430 .VertexBufferIndex
= 1,
432 .SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
,
433 .SourceElementOffset
= 0,
434 .Component0Control
= VFCOMP_STORE_SRC
,
436 /* From Gen8 onwards hardware is no more instructed to overwrite
437 * components using an element specifier. Instead one has separate
438 * 3DSTATE_VF_SGVS (System Generated Value Setup) state packet for it.
441 .Component1Control
= VFCOMP_STORE_0
,
443 .Component1Control
= VFCOMP_STORE_IID
,
445 .Component1Control
= VFCOMP_STORE_0
,
447 .Component2Control
= VFCOMP_STORE_0
,
448 .Component3Control
= VFCOMP_STORE_0
,
450 .DestinationElementOffset
= slot
* 4,
456 /* On Iron Lake and earlier, a native device coordinates version of the
457 * position goes right after the normal VUE header and before position.
458 * Since w == 1 for all of our coordinates, this is just a copy of the
461 ve
[slot
] = (struct GENX(VERTEX_ELEMENT_STATE
)) {
462 .VertexBufferIndex
= 0,
464 .SourceElementFormat
= ISL_FORMAT_R32G32B32_FLOAT
,
465 .SourceElementOffset
= 0,
466 .Component0Control
= VFCOMP_STORE_SRC
,
467 .Component1Control
= VFCOMP_STORE_SRC
,
468 .Component2Control
= VFCOMP_STORE_SRC
,
469 .Component3Control
= VFCOMP_STORE_1_FP
,
470 .DestinationElementOffset
= slot
* 4,
475 ve
[slot
] = (struct GENX(VERTEX_ELEMENT_STATE
)) {
476 .VertexBufferIndex
= 0,
478 .SourceElementFormat
= ISL_FORMAT_R32G32B32_FLOAT
,
479 .SourceElementOffset
= 0,
480 .Component0Control
= VFCOMP_STORE_SRC
,
481 .Component1Control
= VFCOMP_STORE_SRC
,
482 .Component2Control
= VFCOMP_STORE_SRC
,
483 .Component3Control
= VFCOMP_STORE_1_FP
,
485 .DestinationElementOffset
= slot
* 4,
490 for (unsigned i
= 0; i
< num_varyings
; ++i
) {
491 ve
[slot
] = (struct GENX(VERTEX_ELEMENT_STATE
)) {
492 .VertexBufferIndex
= 1,
494 .SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
,
495 .SourceElementOffset
= 16 + i
* 4 * sizeof(float),
496 .Component0Control
= VFCOMP_STORE_SRC
,
497 .Component1Control
= VFCOMP_STORE_SRC
,
498 .Component2Control
= VFCOMP_STORE_SRC
,
499 .Component3Control
= VFCOMP_STORE_SRC
,
501 .DestinationElementOffset
= slot
* 4,
507 const unsigned num_dwords
=
508 1 + GENX(VERTEX_ELEMENT_STATE_length
) * num_elements
;
509 uint32_t *dw
= blorp_emitn(batch
, GENX(3DSTATE_VERTEX_ELEMENTS
), num_dwords
);
513 for (unsigned i
= 0; i
< num_elements
; i
++) {
514 GENX(VERTEX_ELEMENT_STATE_pack
)(batch
, dw
, &ve
[i
]);
515 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
518 blorp_emit(batch
, GENX(3DSTATE_VF_STATISTICS
), vf
) {
519 vf
.StatisticsEnable
= false;
523 /* Overwrite Render Target Array Index (2nd dword) in the VUE header with
524 * primitive instance identifier. This is used for layered clears.
526 blorp_emit(batch
, GENX(3DSTATE_VF_SGVS
), sgvs
) {
527 sgvs
.InstanceIDEnable
= true;
528 sgvs
.InstanceIDComponentNumber
= COMP_1
;
529 sgvs
.InstanceIDElementOffset
= 0;
532 for (unsigned i
= 0; i
< num_elements
; i
++) {
533 blorp_emit(batch
, GENX(3DSTATE_VF_INSTANCING
), vf
) {
534 vf
.VertexElementIndex
= i
;
535 vf
.InstancingEnable
= false;
539 blorp_emit(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
540 topo
.PrimitiveTopologyType
= _3DPRIM_RECTLIST
;
545 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
547 blorp_emit_cc_viewport(struct blorp_batch
*batch
)
549 uint32_t cc_vp_offset
;
550 blorp_emit_dynamic(batch
, GENX(CC_VIEWPORT
), vp
, 32, &cc_vp_offset
) {
551 vp
.MinimumDepth
= 0.0;
552 vp
.MaximumDepth
= 1.0;
556 blorp_emit(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), vsp
) {
557 vsp
.CCViewportPointer
= cc_vp_offset
;
560 blorp_emit(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vsp
) {
561 vsp
.CCViewportStateChange
= true;
562 vsp
.PointertoCC_VIEWPORT
= cc_vp_offset
;
570 blorp_emit_sampler_state(struct blorp_batch
*batch
)
573 blorp_emit_dynamic(batch
, GENX(SAMPLER_STATE
), sampler
, 32, &offset
) {
574 sampler
.MipModeFilter
= MIPFILTER_NONE
;
575 sampler
.MagModeFilter
= MAPFILTER_LINEAR
;
576 sampler
.MinModeFilter
= MAPFILTER_LINEAR
;
579 sampler
.TCXAddressControlMode
= TCM_CLAMP
;
580 sampler
.TCYAddressControlMode
= TCM_CLAMP
;
581 sampler
.TCZAddressControlMode
= TCM_CLAMP
;
582 sampler
.MaximumAnisotropy
= RATIO21
;
583 sampler
.RAddressMinFilterRoundingEnable
= true;
584 sampler
.RAddressMagFilterRoundingEnable
= true;
585 sampler
.VAddressMinFilterRoundingEnable
= true;
586 sampler
.VAddressMagFilterRoundingEnable
= true;
587 sampler
.UAddressMinFilterRoundingEnable
= true;
588 sampler
.UAddressMagFilterRoundingEnable
= true;
590 sampler
.NonnormalizedCoordinateEnable
= true;
595 blorp_emit(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_PS
), ssp
) {
596 ssp
.PointertoPSSamplerState
= offset
;
599 blorp_emit(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS
), ssp
) {
600 ssp
.VSSamplerStateChange
= true;
601 ssp
.GSSamplerStateChange
= true;
602 ssp
.PSSamplerStateChange
= true;
603 ssp
.PointertoPSSamplerState
= offset
;
610 /* What follows is the code for setting up a "pipeline" on Sandy Bridge and
611 * later hardware. This file will be included by i965 for gen4-5 as well, so
612 * this code is guarded by GEN_GEN >= 6.
617 blorp_emit_vs_config(struct blorp_batch
*batch
,
618 const struct blorp_params
*params
)
620 struct brw_vs_prog_data
*vs_prog_data
= params
->vs_prog_data
;
621 assert(!vs_prog_data
|| GEN_GEN
< 11 ||
622 vs_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
);
624 blorp_emit(batch
, GENX(3DSTATE_VS
), vs
) {
628 vs
.KernelStartPointer
= params
->vs_prog_kernel
;
630 vs
.DispatchGRFStartRegisterForURBData
=
631 vs_prog_data
->base
.base
.dispatch_grf_start_reg
;
632 vs
.VertexURBEntryReadLength
=
633 vs_prog_data
->base
.urb_read_length
;
634 vs
.VertexURBEntryReadOffset
= 0;
636 vs
.MaximumNumberofThreads
=
637 batch
->blorp
->isl_dev
->info
->max_vs_threads
- 1;
640 vs
.SIMD8DispatchEnable
=
641 vs_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
;
648 blorp_emit_sf_config(struct blorp_batch
*batch
,
649 const struct blorp_params
*params
)
651 const struct brw_wm_prog_data
*prog_data
= params
->wm_prog_data
;
655 * Disable ViewportTransformEnable (dw2.1)
657 * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
658 * Primitives Overview":
659 * RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
660 * use of screen- space coordinates).
662 * A solid rectangle must be rendered, so set FrontFaceFillMode (dw2.4:3)
663 * and BackFaceFillMode (dw2.5:6) to SOLID(0).
665 * From the Sandy Bridge PRM, Volume 2, Part 1, Section
666 * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
667 * SOLID: Any triangle or rectangle object found to be front-facing
668 * is rendered as a solid object. This setting is required when
669 * (rendering rectangle (RECTLIST) objects.
674 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
);
676 blorp_emit(batch
, GENX(3DSTATE_RASTER
), raster
) {
677 raster
.CullMode
= CULLMODE_NONE
;
680 blorp_emit(batch
, GENX(3DSTATE_SBE
), sbe
) {
681 sbe
.VertexURBEntryReadOffset
= 1;
683 sbe
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
684 sbe
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
685 sbe
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
687 sbe
.NumberofSFOutputAttributes
= 0;
688 sbe
.VertexURBEntryReadLength
= 1;
690 sbe
.ForceVertexURBEntryReadLength
= true;
691 sbe
.ForceVertexURBEntryReadOffset
= true;
694 for (unsigned i
= 0; i
< 32; i
++)
695 sbe
.AttributeActiveComponentFormat
[i
] = ACF_XYZW
;
701 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
) {
702 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
703 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
705 sf
.MultisampleRasterizationMode
= params
->num_samples
> 1 ?
706 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
709 sf
.DepthBufferSurfaceFormat
= params
->depth_format
;
713 blorp_emit(batch
, GENX(3DSTATE_SBE
), sbe
) {
714 sbe
.VertexURBEntryReadOffset
= 1;
716 sbe
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
717 sbe
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
718 sbe
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
720 sbe
.NumberofSFOutputAttributes
= 0;
721 sbe
.VertexURBEntryReadLength
= 1;
725 #else /* GEN_GEN <= 6 */
727 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
) {
728 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
729 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
731 sf
.MultisampleRasterizationMode
= params
->num_samples
> 1 ?
732 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
734 sf
.VertexURBEntryReadOffset
= 1;
736 sf
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
737 sf
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
738 sf
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
740 sf
.NumberofSFOutputAttributes
= 0;
741 sf
.VertexURBEntryReadLength
= 1;
749 blorp_emit_ps_config(struct blorp_batch
*batch
,
750 const struct blorp_params
*params
)
752 const struct brw_wm_prog_data
*prog_data
= params
->wm_prog_data
;
754 /* Even when thread dispatch is disabled, max threads (dw5.25:31) must be
755 * nonzero to prevent the GPU from hanging. While the documentation doesn't
756 * mention this explicitly, it notes that the valid range for the field is
757 * [1,39] = [2,40] threads, which excludes zero.
759 * To be safe (and to minimize extraneous code) we go ahead and fully
760 * configure the WM state whether or not there is a WM program.
765 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
);
767 blorp_emit(batch
, GENX(3DSTATE_PS
), ps
) {
768 if (params
->src
.enabled
) {
769 ps
.SamplerCount
= 1; /* Up to 4 samplers */
770 ps
.BindingTableEntryCount
= 2;
772 ps
.BindingTableEntryCount
= 1;
775 /* SAMPLER_STATE prefetching is broken on Gen11 - WA_1606682166 */
780 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
781 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
782 ps
._32PixelDispatchEnable
= prog_data
->dispatch_32
;
784 /* From the Sky Lake PRM 3DSTATE_PS::32 Pixel Dispatch Enable:
786 * "When NUM_MULTISAMPLES = 16 or FORCE_SAMPLE_COUNT = 16, SIMD32
787 * Dispatch must not be enabled for PER_PIXEL dispatch mode."
789 * Since 16x MSAA is first introduced on SKL, we don't need to apply
790 * the workaround on any older hardware.
792 if (GEN_GEN
>= 9 && !prog_data
->persample_dispatch
&&
793 params
->num_samples
== 16) {
794 assert(ps
._8PixelDispatchEnable
|| ps
._16PixelDispatchEnable
);
795 ps
._32PixelDispatchEnable
= false;
798 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
799 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, ps
, 0);
800 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
801 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, ps
, 1);
802 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
803 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, ps
, 2);
805 ps
.KernelStartPointer0
= params
->wm_prog_kernel
+
806 brw_wm_prog_data_prog_offset(prog_data
, ps
, 0);
807 ps
.KernelStartPointer1
= params
->wm_prog_kernel
+
808 brw_wm_prog_data_prog_offset(prog_data
, ps
, 1);
809 ps
.KernelStartPointer2
= params
->wm_prog_kernel
+
810 brw_wm_prog_data_prog_offset(prog_data
, ps
, 2);
813 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64
814 * for pre Gen11 and 128 for gen11+; On gen11+ If a programmed value is
815 * k, it implies 2(k+1) threads. It implicitly scales for different GT
816 * levels (which have some # of PSDs).
818 * In Gen8 the format is U8-2 whereas in Gen9+ it is U9-1.
821 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
823 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
825 switch (params
->fast_clear_op
) {
826 case ISL_AUX_OP_NONE
:
829 case ISL_AUX_OP_AMBIGUATE
:
830 ps
.RenderTargetFastClearEnable
= true;
831 ps
.RenderTargetResolveType
= FAST_CLEAR_0
;
835 case ISL_AUX_OP_PARTIAL_RESOLVE
:
836 ps
.RenderTargetResolveType
= RESOLVE_PARTIAL
;
838 case ISL_AUX_OP_FULL_RESOLVE
:
839 ps
.RenderTargetResolveType
= RESOLVE_FULL
;
842 case ISL_AUX_OP_FULL_RESOLVE
:
843 ps
.RenderTargetResolveEnable
= true;
846 case ISL_AUX_OP_FAST_CLEAR
:
847 ps
.RenderTargetFastClearEnable
= true;
850 unreachable("Invalid fast clear op");
854 blorp_emit(batch
, GENX(3DSTATE_PS_EXTRA
), psx
) {
856 psx
.PixelShaderValid
= true;
857 psx
.AttributeEnable
= prog_data
->num_varying_inputs
> 0;
858 psx
.PixelShaderIsPerSample
= prog_data
->persample_dispatch
;
861 if (params
->src
.enabled
)
862 psx
.PixelShaderKillsPixel
= true;
867 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
) {
868 switch (params
->hiz_op
) {
869 case ISL_AUX_OP_FAST_CLEAR
:
870 wm
.DepthBufferClear
= true;
872 case ISL_AUX_OP_FULL_RESOLVE
:
873 wm
.DepthBufferResolveEnable
= true;
875 case ISL_AUX_OP_AMBIGUATE
:
876 wm
.HierarchicalDepthBufferResolveEnable
= true;
878 case ISL_AUX_OP_NONE
:
881 unreachable("not reached");
885 wm
.ThreadDispatchEnable
= true;
887 if (params
->src
.enabled
)
888 wm
.PixelShaderKillsPixel
= true;
890 if (params
->num_samples
> 1) {
891 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
892 wm
.MultisampleDispatchMode
=
893 (prog_data
&& prog_data
->persample_dispatch
) ?
894 MSDISPMODE_PERSAMPLE
: MSDISPMODE_PERPIXEL
;
896 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
897 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
901 blorp_emit(batch
, GENX(3DSTATE_PS
), ps
) {
902 ps
.MaximumNumberofThreads
=
903 batch
->blorp
->isl_dev
->info
->max_wm_threads
- 1;
910 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
911 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
912 ps
._32PixelDispatchEnable
= prog_data
->dispatch_32
;
914 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
915 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, ps
, 0);
916 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
917 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, ps
, 1);
918 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
919 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, ps
, 2);
921 ps
.KernelStartPointer0
= params
->wm_prog_kernel
+
922 brw_wm_prog_data_prog_offset(prog_data
, ps
, 0);
923 ps
.KernelStartPointer1
= params
->wm_prog_kernel
+
924 brw_wm_prog_data_prog_offset(prog_data
, ps
, 1);
925 ps
.KernelStartPointer2
= params
->wm_prog_kernel
+
926 brw_wm_prog_data_prog_offset(prog_data
, ps
, 2);
928 ps
.AttributeEnable
= prog_data
->num_varying_inputs
> 0;
930 /* Gen7 hardware gets angry if we don't enable at least one dispatch
931 * mode, so just enable 16-pixel dispatch if we don't have a program.
933 ps
._16PixelDispatchEnable
= true;
936 if (params
->src
.enabled
)
937 ps
.SamplerCount
= 1; /* Up to 4 samplers */
939 switch (params
->fast_clear_op
) {
940 case ISL_AUX_OP_NONE
:
942 case ISL_AUX_OP_FULL_RESOLVE
:
943 ps
.RenderTargetResolveEnable
= true;
945 case ISL_AUX_OP_FAST_CLEAR
:
946 ps
.RenderTargetFastClearEnable
= true;
949 unreachable("Invalid fast clear op");
953 #else /* GEN_GEN <= 6 */
955 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
) {
956 wm
.MaximumNumberofThreads
=
957 batch
->blorp
->isl_dev
->info
->max_wm_threads
- 1;
959 switch (params
->hiz_op
) {
960 case ISL_AUX_OP_FAST_CLEAR
:
961 wm
.DepthBufferClear
= true;
963 case ISL_AUX_OP_FULL_RESOLVE
:
964 wm
.DepthBufferResolveEnable
= true;
966 case ISL_AUX_OP_AMBIGUATE
:
967 wm
.HierarchicalDepthBufferResolveEnable
= true;
969 case ISL_AUX_OP_NONE
:
972 unreachable("not reached");
976 wm
.ThreadDispatchEnable
= true;
978 wm
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
979 wm
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
980 wm
._32PixelDispatchEnable
= prog_data
->dispatch_32
;
982 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
983 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, wm
, 0);
984 wm
.DispatchGRFStartRegisterForConstantSetupData1
=
985 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, wm
, 1);
986 wm
.DispatchGRFStartRegisterForConstantSetupData2
=
987 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, wm
, 2);
989 wm
.KernelStartPointer0
= params
->wm_prog_kernel
+
990 brw_wm_prog_data_prog_offset(prog_data
, wm
, 0);
991 wm
.KernelStartPointer1
= params
->wm_prog_kernel
+
992 brw_wm_prog_data_prog_offset(prog_data
, wm
, 1);
993 wm
.KernelStartPointer2
= params
->wm_prog_kernel
+
994 brw_wm_prog_data_prog_offset(prog_data
, wm
, 2);
996 wm
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
999 if (params
->src
.enabled
) {
1000 wm
.SamplerCount
= 1; /* Up to 4 samplers */
1001 wm
.PixelShaderKillsPixel
= true; /* TODO: temporarily smash on */
1004 if (params
->num_samples
> 1) {
1005 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1006 wm
.MultisampleDispatchMode
=
1007 (prog_data
&& prog_data
->persample_dispatch
) ?
1008 MSDISPMODE_PERSAMPLE
: MSDISPMODE_PERPIXEL
;
1010 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1011 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1015 #endif /* GEN_GEN */
1019 blorp_emit_blend_state(struct blorp_batch
*batch
,
1020 const struct blorp_params
*params
)
1022 struct GENX(BLEND_STATE
) blend
;
1023 memset(&blend
, 0, sizeof(blend
));
1026 int size
= GENX(BLEND_STATE_length
) * 4;
1027 size
+= GENX(BLEND_STATE_ENTRY_length
) * 4 * params
->num_draw_buffers
;
1028 uint32_t *state
= blorp_alloc_dynamic_state(batch
, size
, 64, &offset
);
1029 uint32_t *pos
= state
;
1031 GENX(BLEND_STATE_pack
)(NULL
, pos
, &blend
);
1032 pos
+= GENX(BLEND_STATE_length
);
1034 for (unsigned i
= 0; i
< params
->num_draw_buffers
; ++i
) {
1035 struct GENX(BLEND_STATE_ENTRY
) entry
= {
1036 .PreBlendColorClampEnable
= true,
1037 .PostBlendColorClampEnable
= true,
1038 .ColorClampRange
= COLORCLAMP_RTFORMAT
,
1040 .WriteDisableRed
= params
->color_write_disable
[0],
1041 .WriteDisableGreen
= params
->color_write_disable
[1],
1042 .WriteDisableBlue
= params
->color_write_disable
[2],
1043 .WriteDisableAlpha
= params
->color_write_disable
[3],
1045 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, pos
, &entry
);
1046 pos
+= GENX(BLEND_STATE_ENTRY_length
);
1049 blorp_flush_range(batch
, state
, size
);
1052 blorp_emit(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), sp
) {
1053 sp
.BlendStatePointer
= offset
;
1055 sp
.BlendStatePointerValid
= true;
1061 blorp_emit(batch
, GENX(3DSTATE_PS_BLEND
), ps_blend
) {
1062 ps_blend
.HasWriteableRT
= true;
1070 blorp_emit_color_calc_state(struct blorp_batch
*batch
,
1071 UNUSED
const struct blorp_params
*params
)
1074 blorp_emit_dynamic(batch
, GENX(COLOR_CALC_STATE
), cc
, 64, &offset
) {
1076 cc
.StencilReferenceValue
= params
->stencil_ref
;
1081 blorp_emit(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), sp
) {
1082 sp
.ColorCalcStatePointer
= offset
;
1084 sp
.ColorCalcStatePointerValid
= true;
1093 blorp_emit_depth_stencil_state(struct blorp_batch
*batch
,
1094 const struct blorp_params
*params
)
1097 struct GENX(3DSTATE_WM_DEPTH_STENCIL
) ds
= {
1098 GENX(3DSTATE_WM_DEPTH_STENCIL_header
),
1101 struct GENX(DEPTH_STENCIL_STATE
) ds
= { 0 };
1104 if (params
->depth
.enabled
) {
1105 ds
.DepthBufferWriteEnable
= true;
1107 switch (params
->hiz_op
) {
1108 /* See the following sections of the Sandy Bridge PRM, Volume 2, Part1:
1109 * - 7.5.3.1 Depth Buffer Clear
1110 * - 7.5.3.2 Depth Buffer Resolve
1111 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
1113 case ISL_AUX_OP_FULL_RESOLVE
:
1114 ds
.DepthTestEnable
= true;
1115 ds
.DepthTestFunction
= COMPAREFUNCTION_NEVER
;
1118 case ISL_AUX_OP_NONE
:
1119 case ISL_AUX_OP_FAST_CLEAR
:
1120 case ISL_AUX_OP_AMBIGUATE
:
1121 ds
.DepthTestEnable
= false;
1123 case ISL_AUX_OP_PARTIAL_RESOLVE
:
1124 unreachable("Invalid HIZ op");
1128 if (params
->stencil
.enabled
) {
1129 ds
.StencilBufferWriteEnable
= true;
1130 ds
.StencilTestEnable
= true;
1131 ds
.DoubleSidedStencilEnable
= false;
1133 ds
.StencilTestFunction
= COMPAREFUNCTION_ALWAYS
;
1134 ds
.StencilPassDepthPassOp
= STENCILOP_REPLACE
;
1136 ds
.StencilWriteMask
= params
->stencil_mask
;
1138 ds
.StencilReferenceValue
= params
->stencil_ref
;
1143 uint32_t offset
= 0;
1144 uint32_t *dw
= blorp_emit_dwords(batch
,
1145 GENX(3DSTATE_WM_DEPTH_STENCIL_length
));
1149 GENX(3DSTATE_WM_DEPTH_STENCIL_pack
)(NULL
, dw
, &ds
);
1152 void *state
= blorp_alloc_dynamic_state(batch
,
1153 GENX(DEPTH_STENCIL_STATE_length
) * 4,
1155 GENX(DEPTH_STENCIL_STATE_pack
)(NULL
, state
, &ds
);
1156 blorp_flush_range(batch
, state
, GENX(DEPTH_STENCIL_STATE_length
) * 4);
1160 blorp_emit(batch
, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS
), sp
) {
1161 sp
.PointertoDEPTH_STENCIL_STATE
= offset
;
1169 blorp_emit_3dstate_multisample(struct blorp_batch
*batch
,
1170 const struct blorp_params
*params
)
1172 blorp_emit(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
1173 ms
.NumberofMultisamples
= __builtin_ffs(params
->num_samples
) - 1;
1176 /* The PRM says that this bit is valid only for DX9:
1178 * SW can choose to set this bit only for DX9 API. DX10/OGL API's
1179 * should not have any effect by setting or not setting this bit.
1181 ms
.PixelPositionOffsetEnable
= false;
1184 switch (params
->num_samples
) {
1186 GEN_SAMPLE_POS_1X(ms
.Sample
);
1189 GEN_SAMPLE_POS_2X(ms
.Sample
);
1192 GEN_SAMPLE_POS_4X(ms
.Sample
);
1195 GEN_SAMPLE_POS_8X(ms
.Sample
);
1201 GEN_SAMPLE_POS_4X(ms
.Sample
);
1203 ms
.PixelLocation
= CENTER
;
1208 blorp_emit_pipeline(struct blorp_batch
*batch
,
1209 const struct blorp_params
*params
)
1211 uint32_t blend_state_offset
= 0;
1212 uint32_t color_calc_state_offset
;
1213 uint32_t depth_stencil_state_offset
;
1215 emit_urb_config(batch
, params
);
1217 if (params
->wm_prog_data
) {
1218 blend_state_offset
= blorp_emit_blend_state(batch
, params
);
1220 color_calc_state_offset
= blorp_emit_color_calc_state(batch
, params
);
1221 depth_stencil_state_offset
= blorp_emit_depth_stencil_state(batch
, params
);
1224 /* 3DSTATE_CC_STATE_POINTERS
1226 * The pointer offsets are relative to
1227 * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
1229 * The HiZ op doesn't use BLEND_STATE or COLOR_CALC_STATE.
1231 * The dynamic state emit helpers emit their own STATE_POINTERS packets on
1232 * gen7+. However, on gen6 and earlier, they're all lumpped together in
1233 * one CC_STATE_POINTERS packet so we have to emit that here.
1235 blorp_emit(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), cc
) {
1236 cc
.BLEND_STATEChange
= true;
1237 cc
.ColorCalcStatePointerValid
= true;
1238 cc
.DEPTH_STENCIL_STATEChange
= true;
1239 cc
.PointertoBLEND_STATE
= blend_state_offset
;
1240 cc
.ColorCalcStatePointer
= color_calc_state_offset
;
1241 cc
.PointertoDEPTH_STENCIL_STATE
= depth_stencil_state_offset
;
1244 (void)blend_state_offset
;
1245 (void)color_calc_state_offset
;
1246 (void)depth_stencil_state_offset
;
1250 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_ALL
), pc
) {
1251 /* Update empty push constants for all stages (bitmask = 11111b) */
1252 pc
.ShaderUpdateEnable
= 0x1f;
1255 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_VS
), vs
);
1257 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_HS
), hs
);
1258 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_DS
), DS
);
1260 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_GS
), gs
);
1261 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_PS
), ps
);
1264 if (params
->src
.enabled
)
1265 blorp_emit_sampler_state(batch
);
1267 blorp_emit_3dstate_multisample(batch
, params
);
1269 blorp_emit(batch
, GENX(3DSTATE_SAMPLE_MASK
), mask
) {
1270 mask
.SampleMask
= (1 << params
->num_samples
) - 1;
1273 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
1274 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
1276 * [DevSNB] A pipeline flush must be programmed prior to a
1277 * 3DSTATE_VS command that causes the VS Function Enable to
1278 * toggle. Pipeline flush can be executed by sending a PIPE_CONTROL
1279 * command with CS stall bit set and a post sync operation.
1281 * We've already done one at the start of the BLORP operation.
1283 blorp_emit_vs_config(batch
, params
);
1285 blorp_emit(batch
, GENX(3DSTATE_HS
), hs
);
1286 blorp_emit(batch
, GENX(3DSTATE_TE
), te
);
1287 blorp_emit(batch
, GENX(3DSTATE_DS
), DS
);
1288 blorp_emit(batch
, GENX(3DSTATE_STREAMOUT
), so
);
1290 blorp_emit(batch
, GENX(3DSTATE_GS
), gs
);
1292 blorp_emit(batch
, GENX(3DSTATE_CLIP
), clip
) {
1293 clip
.PerspectiveDivideDisable
= true;
1296 blorp_emit_sf_config(batch
, params
);
1297 blorp_emit_ps_config(batch
, params
);
1299 blorp_emit_cc_viewport(batch
);
1302 /******** This is the end of the pipeline setup code ********/
1304 #endif /* GEN_GEN >= 6 */
1308 blorp_emit_memcpy(struct blorp_batch
*batch
,
1309 struct blorp_address dst
,
1310 struct blorp_address src
,
1313 assert(size
% 4 == 0);
1315 for (unsigned dw
= 0; dw
< size
; dw
+= 4) {
1317 blorp_emit(batch
, GENX(MI_COPY_MEM_MEM
), cp
) {
1318 cp
.DestinationMemoryAddress
= dst
;
1319 cp
.SourceMemoryAddress
= src
;
1322 /* IVB does not have a general purpose register for command streamer
1323 * commands. Therefore, we use an alternate temporary register.
1325 #define BLORP_TEMP_REG 0x2440 /* GEN7_3DPRIM_BASE_VERTEX */
1326 blorp_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), load
) {
1327 load
.RegisterAddress
= BLORP_TEMP_REG
;
1328 load
.MemoryAddress
= src
;
1330 blorp_emit(batch
, GENX(MI_STORE_REGISTER_MEM
), store
) {
1331 store
.RegisterAddress
= BLORP_TEMP_REG
;
1332 store
.MemoryAddress
= dst
;
1334 #undef BLORP_TEMP_REG
1343 blorp_emit_surface_state(struct blorp_batch
*batch
,
1344 const struct brw_blorp_surface_info
*surface
,
1345 enum isl_aux_op aux_op
,
1346 void *state
, uint32_t state_offset
,
1347 const bool color_write_disables
[4],
1348 bool is_render_target
)
1350 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
1351 struct isl_surf surf
= surface
->surf
;
1353 if (surf
.dim
== ISL_SURF_DIM_1D
&&
1354 surf
.dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
) {
1355 assert(surf
.logical_level0_px
.height
== 1);
1356 surf
.dim
= ISL_SURF_DIM_2D
;
1359 if (isl_aux_usage_has_hiz(surface
->aux_usage
)) {
1360 /* BLORP doesn't render with depth so we can't use HiZ */
1361 assert(!is_render_target
);
1362 /* We can't reinterpret HiZ */
1363 assert(surface
->surf
.format
== surface
->view
.format
);
1365 enum isl_aux_usage aux_usage
= surface
->aux_usage
;
1367 isl_channel_mask_t write_disable_mask
= 0;
1368 if (is_render_target
&& GEN_GEN
<= 5) {
1369 if (color_write_disables
[0])
1370 write_disable_mask
|= ISL_CHANNEL_RED_BIT
;
1371 if (color_write_disables
[1])
1372 write_disable_mask
|= ISL_CHANNEL_GREEN_BIT
;
1373 if (color_write_disables
[2])
1374 write_disable_mask
|= ISL_CHANNEL_BLUE_BIT
;
1375 if (color_write_disables
[3])
1376 write_disable_mask
|= ISL_CHANNEL_ALPHA_BIT
;
1379 const bool use_clear_address
=
1380 GEN_GEN
>= 10 && (surface
->clear_color_addr
.buffer
!= NULL
);
1382 isl_surf_fill_state(batch
->blorp
->isl_dev
, state
,
1383 .surf
= &surf
, .view
= &surface
->view
,
1384 .aux_surf
= &surface
->aux_surf
, .aux_usage
= aux_usage
,
1386 blorp_get_surface_address(batch
, surface
->addr
),
1387 .aux_address
= aux_usage
== ISL_AUX_USAGE_NONE
? 0 :
1388 blorp_get_surface_address(batch
, surface
->aux_addr
),
1389 .clear_address
= !use_clear_address
? 0 :
1390 blorp_get_surface_address(batch
,
1391 surface
->clear_color_addr
),
1392 .mocs
= surface
->addr
.mocs
,
1393 .clear_color
= surface
->clear_color
,
1394 .use_clear_address
= use_clear_address
,
1395 .write_disables
= write_disable_mask
);
1397 blorp_surface_reloc(batch
, state_offset
+ isl_dev
->ss
.addr_offset
,
1400 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
1401 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
1402 * used to store other information. This should be ok, however, because
1403 * surface buffer addresses are always 4K page alinged.
1405 assert((surface
->aux_addr
.offset
& 0xfff) == 0);
1406 uint32_t *aux_addr
= state
+ isl_dev
->ss
.aux_addr_offset
;
1407 blorp_surface_reloc(batch
, state_offset
+ isl_dev
->ss
.aux_addr_offset
,
1408 surface
->aux_addr
, *aux_addr
);
1411 if (aux_usage
!= ISL_AUX_USAGE_NONE
&& surface
->clear_color_addr
.buffer
) {
1413 assert((surface
->clear_color_addr
.offset
& 0x3f) == 0);
1414 uint32_t *clear_addr
= state
+ isl_dev
->ss
.clear_color_state_offset
;
1415 blorp_surface_reloc(batch
, state_offset
+
1416 isl_dev
->ss
.clear_color_state_offset
,
1417 surface
->clear_color_addr
, *clear_addr
);
1419 /* Fast clears just whack the AUX surface and don't actually use the
1420 * clear color for anything. We can avoid the MI memcpy on that case.
1422 if (aux_op
!= ISL_AUX_OP_FAST_CLEAR
) {
1423 struct blorp_address dst_addr
= blorp_get_surface_base_address(batch
);
1424 dst_addr
.offset
+= state_offset
+ isl_dev
->ss
.clear_value_offset
;
1425 blorp_emit_memcpy(batch
, dst_addr
, surface
->clear_color_addr
,
1426 isl_dev
->ss
.clear_value_size
);
1429 unreachable("Fast clears are only supported on gen7+");
1433 blorp_flush_range(batch
, state
, GENX(RENDER_SURFACE_STATE_length
) * 4);
1437 blorp_emit_null_surface_state(struct blorp_batch
*batch
,
1438 const struct brw_blorp_surface_info
*surface
,
1441 struct GENX(RENDER_SURFACE_STATE
) ss
= {
1442 .SurfaceType
= SURFTYPE_NULL
,
1443 .SurfaceFormat
= ISL_FORMAT_R8G8B8A8_UNORM
,
1444 .Width
= surface
->surf
.logical_level0_px
.width
- 1,
1445 .Height
= surface
->surf
.logical_level0_px
.height
- 1,
1446 .MIPCountLOD
= surface
->view
.base_level
,
1447 .MinimumArrayElement
= surface
->view
.base_array_layer
,
1448 .Depth
= surface
->view
.array_len
- 1,
1449 .RenderTargetViewExtent
= surface
->view
.array_len
- 1,
1451 .NumberofMultisamples
= ffs(surface
->surf
.samples
) - 1,
1455 .SurfaceArray
= surface
->surf
.dim
!= ISL_SURF_DIM_3D
,
1461 .TiledSurface
= true,
1465 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
, &ss
);
1467 blorp_flush_range(batch
, state
, GENX(RENDER_SURFACE_STATE_length
) * 4);
1471 blorp_emit_surface_states(struct blorp_batch
*batch
,
1472 const struct blorp_params
*params
)
1474 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
1475 uint32_t bind_offset
= 0, surface_offsets
[2];
1476 void *surface_maps
[2];
1478 UNUSED
bool has_indirect_clear_color
= false;
1479 if (params
->use_pre_baked_binding_table
) {
1480 bind_offset
= params
->pre_baked_binding_table_offset
;
1482 unsigned num_surfaces
= 1 + params
->src
.enabled
;
1483 blorp_alloc_binding_table(batch
, num_surfaces
,
1484 isl_dev
->ss
.size
, isl_dev
->ss
.align
,
1485 &bind_offset
, surface_offsets
, surface_maps
);
1487 if (params
->dst
.enabled
) {
1488 blorp_emit_surface_state(batch
, ¶ms
->dst
,
1489 params
->fast_clear_op
,
1490 surface_maps
[BLORP_RENDERBUFFER_BT_INDEX
],
1491 surface_offsets
[BLORP_RENDERBUFFER_BT_INDEX
],
1492 params
->color_write_disable
, true);
1493 if (params
->dst
.clear_color_addr
.buffer
!= NULL
)
1494 has_indirect_clear_color
= true;
1496 assert(params
->depth
.enabled
|| params
->stencil
.enabled
);
1497 const struct brw_blorp_surface_info
*surface
=
1498 params
->depth
.enabled
? ¶ms
->depth
: ¶ms
->stencil
;
1499 blorp_emit_null_surface_state(batch
, surface
,
1500 surface_maps
[BLORP_RENDERBUFFER_BT_INDEX
]);
1503 if (params
->src
.enabled
) {
1504 blorp_emit_surface_state(batch
, ¶ms
->src
,
1505 params
->fast_clear_op
,
1506 surface_maps
[BLORP_TEXTURE_BT_INDEX
],
1507 surface_offsets
[BLORP_TEXTURE_BT_INDEX
],
1509 if (params
->src
.clear_color_addr
.buffer
!= NULL
)
1510 has_indirect_clear_color
= true;
1515 if (has_indirect_clear_color
) {
1516 /* Updating a surface state object may require that the state cache be
1517 * invalidated. From the SKL PRM, Shared Functions -> State -> State
1520 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
1521 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
1522 * modified [...], the L1 state cache must be invalidated to ensure
1523 * the new surface or sampler state is fetched from system memory.
1525 blorp_emit(batch
, GENX(PIPE_CONTROL
), pipe
) {
1526 pipe
.StateCacheInvalidationEnable
= true;
1528 pipe
.TileCacheFlushEnable
= true;
1535 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), bt
);
1536 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_HS
), bt
);
1537 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_DS
), bt
);
1538 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_GS
), bt
);
1540 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_PS
), bt
) {
1541 bt
.PointertoPSBindingTable
= bind_offset
;
1544 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS
), bt
) {
1545 bt
.PSBindingTableChange
= true;
1546 bt
.PointertoPSBindingTable
= bind_offset
;
1549 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS
), bt
) {
1550 bt
.PointertoPSBindingTable
= bind_offset
;
1556 blorp_emit_depth_stencil_config(struct blorp_batch
*batch
,
1557 const struct blorp_params
*params
)
1559 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
1561 uint32_t *dw
= blorp_emit_dwords(batch
, isl_dev
->ds
.size
/ 4);
1565 struct isl_depth_stencil_hiz_emit_info info
= { };
1567 if (params
->depth
.enabled
) {
1568 info
.view
= ¶ms
->depth
.view
;
1569 info
.mocs
= params
->depth
.addr
.mocs
;
1570 } else if (params
->stencil
.enabled
) {
1571 info
.view
= ¶ms
->stencil
.view
;
1572 info
.mocs
= params
->stencil
.addr
.mocs
;
1575 if (params
->depth
.enabled
) {
1576 info
.depth_surf
= ¶ms
->depth
.surf
;
1578 info
.depth_address
=
1579 blorp_emit_reloc(batch
, dw
+ isl_dev
->ds
.depth_offset
/ 4,
1580 params
->depth
.addr
, 0);
1582 info
.hiz_usage
= params
->depth
.aux_usage
;
1583 if (isl_aux_usage_has_hiz(info
.hiz_usage
)) {
1584 info
.hiz_surf
= ¶ms
->depth
.aux_surf
;
1586 struct blorp_address hiz_address
= params
->depth
.aux_addr
;
1588 /* Sandy bridge hardware does not technically support mipmapped HiZ.
1589 * However, we have a special layout that allows us to make it work
1590 * anyway by manually offsetting to the specified miplevel.
1592 assert(info
.hiz_surf
->dim_layout
== ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
);
1594 isl_surf_get_image_offset_B_tile_sa(info
.hiz_surf
,
1595 info
.view
->base_level
, 0, 0,
1596 &offset_B
, NULL
, NULL
);
1597 hiz_address
.offset
+= offset_B
;
1601 blorp_emit_reloc(batch
, dw
+ isl_dev
->ds
.hiz_offset
/ 4,
1604 info
.depth_clear_value
= params
->depth
.clear_color
.f32
[0];
1608 if (params
->stencil
.enabled
) {
1609 info
.stencil_surf
= ¶ms
->stencil
.surf
;
1611 info
.stencil_aux_usage
= params
->stencil
.aux_usage
;
1612 struct blorp_address stencil_address
= params
->stencil
.addr
;
1614 /* Sandy bridge hardware does not technically support mipmapped stencil.
1615 * However, we have a special layout that allows us to make it work
1616 * anyway by manually offsetting to the specified miplevel.
1618 assert(info
.stencil_surf
->dim_layout
== ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
);
1620 isl_surf_get_image_offset_B_tile_sa(info
.stencil_surf
,
1621 info
.view
->base_level
, 0, 0,
1622 &offset_B
, NULL
, NULL
);
1623 stencil_address
.offset
+= offset_B
;
1626 info
.stencil_address
=
1627 blorp_emit_reloc(batch
, dw
+ isl_dev
->ds
.stencil_offset
/ 4,
1628 stencil_address
, 0);
1631 isl_emit_depth_stencil_hiz_s(isl_dev
, dw
, &info
);
1634 /* GEN:BUG:1408224581
1636 * Workaround: Gen12LP Astep only An additional pipe control with
1637 * post-sync = store dword operation would be required.( w/a is to
1638 * have an additional pipe control after the stencil state whenever
1639 * the surface state bits of this state is changing).
1641 blorp_emit(batch
, GENX(PIPE_CONTROL
), pc
) {
1642 pc
.PostSyncOperation
= WriteImmediateData
;
1643 pc
.Address
= blorp_get_workaround_page(batch
);
1649 /* Emits the Optimized HiZ sequence specified in the BDW+ PRMs. The
1650 * depth/stencil buffer extents are ignored to handle APIs which perform
1651 * clearing operations without such information.
1654 blorp_emit_gen8_hiz_op(struct blorp_batch
*batch
,
1655 const struct blorp_params
*params
)
1657 /* We should be performing an operation on a depth or stencil buffer.
1659 assert(params
->depth
.enabled
|| params
->stencil
.enabled
);
1661 /* The stencil buffer should only be enabled on GEN == 12, if a fast clear
1662 * or full resolve operation is requested. On rest of the GEN, if a fast
1663 * clear operation is requested.
1665 if (params
->stencil
.enabled
) {
1667 assert(params
->hiz_op
== ISL_AUX_OP_FAST_CLEAR
||
1668 params
->hiz_op
== ISL_AUX_OP_FULL_RESOLVE
);
1670 assert(params
->hiz_op
== ISL_AUX_OP_FAST_CLEAR
);
1674 /* From the BDW PRM Volume 2, 3DSTATE_WM_HZ_OP:
1676 * 3DSTATE_MULTISAMPLE packet must be used prior to this packet to change
1677 * the Number of Multisamples. This packet must not be used to change
1678 * Number of Multisamples in a rendering sequence.
1680 * Since HIZ may be the first thing in a batch buffer, play safe and always
1681 * emit 3DSTATE_MULTISAMPLE.
1683 blorp_emit_3dstate_multisample(batch
, params
);
1685 /* From the BDW PRM Volume 7, Depth Buffer Clear:
1687 * The clear value must be between the min and max depth values
1688 * (inclusive) defined in the CC_VIEWPORT. If the depth buffer format is
1689 * D32_FLOAT, then +/-DENORM values are also allowed.
1691 * Set the bounds to match our hardware limits, [0.0, 1.0].
1693 if (params
->depth
.enabled
&& params
->hiz_op
== ISL_AUX_OP_FAST_CLEAR
) {
1694 assert(params
->depth
.clear_color
.f32
[0] >= 0.0f
);
1695 assert(params
->depth
.clear_color
.f32
[0] <= 1.0f
);
1696 blorp_emit_cc_viewport(batch
);
1699 /* According to the SKL PRM formula for WM_INT::ThreadDispatchEnable, the
1700 * 3DSTATE_WM::ForceThreadDispatchEnable field can force WM thread dispatch
1701 * even when WM_HZ_OP is active. However, WM thread dispatch is normally
1702 * disabled for HiZ ops and it appears that force-enabling it can lead to
1703 * GPU hangs on at least Skylake. Since we don't know the current state of
1704 * the 3DSTATE_WM packet, just emit a dummy one prior to 3DSTATE_WM_HZ_OP.
1706 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
);
1708 /* If we can't alter the depth stencil config and multiple layers are
1709 * involved, the HiZ op will fail. This is because the op requires that a
1710 * new config is emitted for each additional layer.
1712 if (batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
) {
1713 assert(params
->num_layers
<= 1);
1715 blorp_emit_depth_stencil_config(batch
, params
);
1718 blorp_emit(batch
, GENX(3DSTATE_WM_HZ_OP
), hzp
) {
1719 switch (params
->hiz_op
) {
1720 case ISL_AUX_OP_FAST_CLEAR
:
1721 hzp
.StencilBufferClearEnable
= params
->stencil
.enabled
;
1722 hzp
.DepthBufferClearEnable
= params
->depth
.enabled
;
1723 hzp
.StencilClearValue
= params
->stencil_ref
;
1724 hzp
.FullSurfaceDepthandStencilClear
= params
->full_surface_hiz_op
;
1726 case ISL_AUX_OP_FULL_RESOLVE
:
1727 assert(params
->full_surface_hiz_op
);
1728 hzp
.DepthBufferResolveEnable
= params
->depth
.enabled
;
1730 if (params
->stencil
.enabled
) {
1731 assert(params
->stencil
.aux_usage
== ISL_AUX_USAGE_CCS_E
);
1732 hzp
.StencilBufferResolveEnable
= true;
1736 case ISL_AUX_OP_AMBIGUATE
:
1737 assert(params
->full_surface_hiz_op
);
1738 hzp
.HierarchicalDepthBufferResolveEnable
= true;
1740 case ISL_AUX_OP_PARTIAL_RESOLVE
:
1741 case ISL_AUX_OP_NONE
:
1742 unreachable("Invalid HIZ op");
1745 hzp
.NumberofMultisamples
= ffs(params
->num_samples
) - 1;
1746 hzp
.SampleMask
= 0xFFFF;
1748 /* Due to a hardware issue, this bit MBZ */
1749 assert(hzp
.ScissorRectangleEnable
== false);
1751 /* Contrary to the HW docs both fields are inclusive */
1752 hzp
.ClearRectangleXMin
= params
->x0
;
1753 hzp
.ClearRectangleYMin
= params
->y0
;
1755 /* Contrary to the HW docs both fields are exclusive */
1756 hzp
.ClearRectangleXMax
= params
->x1
;
1757 hzp
.ClearRectangleYMax
= params
->y1
;
1760 /* PIPE_CONTROL w/ all bits clear except for “Post-Sync Operation” must set
1761 * to “Write Immediate Data” enabled.
1763 blorp_emit(batch
, GENX(PIPE_CONTROL
), pc
) {
1764 pc
.PostSyncOperation
= WriteImmediateData
;
1765 pc
.Address
= blorp_get_workaround_page(batch
);
1768 blorp_emit(batch
, GENX(3DSTATE_WM_HZ_OP
), hzp
);
1773 blorp_update_clear_color(struct blorp_batch
*batch
,
1774 const struct brw_blorp_surface_info
*info
,
1777 if (info
->clear_color_addr
.buffer
&& op
== ISL_AUX_OP_FAST_CLEAR
) {
1779 blorp_emit(batch
, GENX(PIPE_CONTROL
), pipe
) {
1780 pipe
.CommandStreamerStallEnable
= true;
1784 const unsigned inlinedata_dw
= 2 * 2;
1785 const unsigned num_dwords
= GENX(MI_ATOMIC_length
) + inlinedata_dw
;
1787 struct blorp_address clear_addr
= info
->clear_color_addr
;
1788 uint32_t *dw
= blorp_emitn(batch
, GENX(MI_ATOMIC
), num_dwords
,
1789 .DataSize
= MI_ATOMIC_QWORD
,
1790 .ATOMICOPCODE
= MI_ATOMIC_OP_MOVE8B
,
1792 .MemoryAddress
= clear_addr
);
1793 /* dw starts at dword 1, but we need to fill dwords 3 and 5 */
1794 dw
[2] = info
->clear_color
.u32
[0];
1796 dw
[4] = info
->clear_color
.u32
[1];
1799 clear_addr
.offset
+= 8;
1800 dw
= blorp_emitn(batch
, GENX(MI_ATOMIC
), num_dwords
,
1801 .DataSize
= MI_ATOMIC_QWORD
,
1802 .ATOMICOPCODE
= MI_ATOMIC_OP_MOVE8B
,
1804 .ReturnDataControl
= true,
1806 .MemoryAddress
= clear_addr
);
1807 /* dw starts at dword 1, but we need to fill dwords 3 and 5 */
1808 dw
[2] = info
->clear_color
.u32
[2];
1810 dw
[4] = info
->clear_color
.u32
[3];
1813 blorp_emit(batch
, GENX(PIPE_CONTROL
), pipe
) {
1814 pipe
.StateCacheInvalidationEnable
= true;
1815 pipe
.TextureCacheInvalidationEnable
= true;
1819 /* According to GEN:BUG:2201730850, in the Clear Color Programming Note
1820 * under the Red channel, "Software shall write the converted Depth
1821 * Clear to this dword." The only depth formats listed under the red
1822 * channel are IEEE_FP and UNORM24_X8. These two requirements are
1823 * incompatible with the UNORM16 depth format, so just ignore that case
1824 * and simply perform the conversion for all depth formats.
1826 union isl_color_value fixed_color
= info
->clear_color
;
1827 if (GEN_GEN
== 12 && isl_surf_usage_is_depth(info
->surf
.usage
)) {
1828 isl_color_value_pack(&info
->clear_color
, info
->surf
.format
,
1832 for (int i
= 0; i
< 4; i
++) {
1833 blorp_emit(batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
1834 sdi
.Address
= info
->clear_color_addr
;
1835 sdi
.Address
.offset
+= i
* 4;
1836 sdi
.ImmediateData
= fixed_color
.u32
[i
];
1839 sdi
.ForceWriteCompletionCheck
= true;
1844 /* The RENDER_SURFACE_STATE::ClearColor field states that software should
1845 * write the converted depth value 16B after the clear address:
1847 * 3D Sampler will always fetch clear depth from the location 16-bytes
1848 * above this address, where the clear depth, converted to native
1849 * surface format by software, will be stored.
1853 if (isl_surf_usage_is_depth(info
->surf
.usage
)) {
1854 blorp_emit(batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
1855 sdi
.Address
= info
->clear_color_addr
;
1856 sdi
.Address
.offset
+= 4 * 4;
1857 sdi
.ImmediateData
= fixed_color
.u32
[0];
1858 sdi
.ForceWriteCompletionCheck
= true;
1864 blorp_emit(batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
1865 sdi
.Address
= info
->clear_color_addr
;
1866 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
1867 ISL_CHANNEL_SELECT_GREEN
<< 22 |
1868 ISL_CHANNEL_SELECT_BLUE
<< 19 |
1869 ISL_CHANNEL_SELECT_ALPHA
<< 16;
1870 if (isl_format_has_int_channel(info
->view
.format
)) {
1871 for (unsigned i
= 0; i
< 4; i
++) {
1872 assert(info
->clear_color
.u32
[i
] == 0 ||
1873 info
->clear_color
.u32
[i
] == 1);
1875 sdi
.ImmediateData
|= (info
->clear_color
.u32
[0] != 0) << 31;
1876 sdi
.ImmediateData
|= (info
->clear_color
.u32
[1] != 0) << 30;
1877 sdi
.ImmediateData
|= (info
->clear_color
.u32
[2] != 0) << 29;
1878 sdi
.ImmediateData
|= (info
->clear_color
.u32
[3] != 0) << 28;
1880 for (unsigned i
= 0; i
< 4; i
++) {
1881 assert(info
->clear_color
.f32
[i
] == 0.0f
||
1882 info
->clear_color
.f32
[i
] == 1.0f
);
1884 sdi
.ImmediateData
|= (info
->clear_color
.f32
[0] != 0.0f
) << 31;
1885 sdi
.ImmediateData
|= (info
->clear_color
.f32
[1] != 0.0f
) << 30;
1886 sdi
.ImmediateData
|= (info
->clear_color
.f32
[2] != 0.0f
) << 29;
1887 sdi
.ImmediateData
|= (info
->clear_color
.f32
[3] != 0.0f
) << 28;
1895 * \brief Execute a blit or render pass operation.
1897 * To execute the operation, this function manually constructs and emits a
1898 * batch to draw a rectangle primitive. The batchbuffer is flushed before
1899 * constructing and after emitting the batch.
1901 * This function alters no GL state.
1904 blorp_exec(struct blorp_batch
*batch
, const struct blorp_params
*params
)
1906 if (!(batch
->flags
& BLORP_BATCH_NO_UPDATE_CLEAR_COLOR
)) {
1907 blorp_update_clear_color(batch
, ¶ms
->dst
, params
->fast_clear_op
);
1908 blorp_update_clear_color(batch
, ¶ms
->depth
, params
->hiz_op
);
1912 if (params
->hiz_op
!= ISL_AUX_OP_NONE
) {
1913 blorp_emit_gen8_hiz_op(batch
, params
);
1918 blorp_emit_vertex_buffers(batch
, params
);
1919 blorp_emit_vertex_elements(batch
, params
);
1921 blorp_emit_pipeline(batch
, params
);
1923 blorp_emit_surface_states(batch
, params
);
1925 if (!(batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
))
1926 blorp_emit_depth_stencil_config(batch
, params
);
1928 blorp_emit(batch
, GENX(3DPRIMITIVE
), prim
) {
1929 prim
.VertexAccessType
= SEQUENTIAL
;
1930 prim
.PrimitiveTopologyType
= _3DPRIM_RECTLIST
;
1932 prim
.PredicateEnable
= batch
->flags
& BLORP_BATCH_PREDICATE_ENABLE
;
1934 prim
.VertexCountPerInstance
= 3;
1935 prim
.InstanceCount
= params
->num_layers
;
1939 #endif /* BLORP_GENX_EXEC_H */