2 * Copyright © 2010 - 2015 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #ifndef BRW_COMPILER_H
25 #define BRW_COMPILER_H
28 #include "dev/gen_device_info.h"
29 #include "main/macros.h"
30 #include "main/mtypes.h"
31 #include "util/ralloc.h"
42 const struct gen_device_info
*devinfo
;
48 * Array of the ra classes for the unaligned contiguous register
54 * Mapping for register-allocated objects in *regs to the first
55 * GRF for that object.
57 uint8_t *ra_reg_to_grf
;
64 * Array of the ra classes for the unaligned contiguous register
65 * block sizes used, indexed by register size.
70 * Mapping from classes to ra_reg ranges. Each of the per-size
71 * classes corresponds to a range of ra_reg nodes. This array stores
72 * those ranges in the form of first ra_reg in each class and the
73 * total number of ra_reg elements in the last array element. This
74 * way the range of the i'th class is given by:
75 * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] )
77 int class_to_ra_reg_range
[17];
80 * Mapping for register-allocated objects in *regs to the first
81 * GRF for that object.
83 uint8_t *ra_reg_to_grf
;
86 * ra class for the aligned pairs we use for PLN, which doesn't
89 int aligned_pairs_class
;
92 void (*shader_debug_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
93 void (*shader_perf_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
95 bool scalar_stage
[MESA_SHADER_STAGES
];
96 struct gl_shader_compiler_options glsl_compiler_options
[MESA_SHADER_STAGES
];
99 * Apply workarounds for SIN and COS output range problems.
100 * This can negatively impact performance.
105 * Is 3DSTATE_CONSTANT_*'s Constant Buffer 0 relative to Dynamic State
106 * Base Address? (If not, it's a normal GPU address.)
108 bool constant_buffer_0_is_relative
;
111 * Whether or not the driver supports pull constants. If not, the compiler
112 * will attempt to push everything.
114 bool supports_pull_constants
;
117 * Whether or not the driver supports NIR shader constants. This controls
118 * whether nir_opt_large_constants will be run.
120 bool supports_shader_constants
;
124 * We use a constant subgroup size of 32. It really only needs to be a
125 * maximum and, since we do SIMD32 for compute shaders in some cases, it
126 * needs to be at least 32. SIMD8 and SIMD16 shaders will still claim a
127 * subgroup size of 32 but will act as if 16 or 24 of those channels are
130 #define BRW_SUBGROUP_SIZE 32
133 * Program key structures.
135 * When drawing, we look for the currently bound shaders in the program
136 * cache. This is essentially a hash table lookup, and these are the keys.
138 * Sometimes OpenGL features specified as state need to be simulated via
139 * shader code, due to a mismatch between the API and the hardware. This
140 * is often referred to as "non-orthagonal state" or "NOS". We store NOS
141 * in the program key so it's considered when searching for a program. If
142 * we haven't seen a particular combination before, we have to recompile a
143 * new specialized version.
145 * Shader compilation should not look up state in gl_context directly, but
146 * instead use the copy in the program key. This guarantees recompiles will
152 enum PACKED gen6_gather_sampler_wa
{
153 WA_SIGN
= 1, /* whether we need to sign extend */
154 WA_8BIT
= 2, /* if we have an 8bit format needing wa */
155 WA_16BIT
= 4, /* if we have a 16bit format needing wa */
159 * Sampler information needed by VS, WM, and GS program cache keys.
161 struct brw_sampler_prog_key_data
{
163 * EXT_texture_swizzle and DEPTH_TEXTURE_MODE swizzles.
165 uint16_t swizzles
[MAX_SAMPLERS
];
167 uint32_t gl_clamp_mask
[3];
170 * For RG32F, gather4's channel select is broken.
172 uint32_t gather_channel_quirk_mask
;
175 * Whether this sampler uses the compressed multisample surface layout.
177 uint32_t compressed_multisample_layout_mask
;
180 * Whether this sampler is using 16x multisampling. If so fetching from
181 * this sampler will be handled with a different instruction, ld2dms_w
187 * For Sandybridge, which shader w/a we need for gather quirks.
189 enum gen6_gather_sampler_wa gen6_gather_wa
[MAX_SAMPLERS
];
192 * Texture units that have a YUV image bound.
194 uint32_t y_u_v_image_mask
;
195 uint32_t y_uv_image_mask
;
196 uint32_t yx_xuxv_image_mask
;
197 uint32_t xy_uxvx_image_mask
;
198 uint32_t ayuv_image_mask
;
202 * The VF can't natively handle certain types of attributes, such as GL_FIXED
203 * or most 10_10_10_2 types. These flags enable various VS workarounds to
204 * "fix" attributes at the beginning of shaders.
206 #define BRW_ATTRIB_WA_COMPONENT_MASK 7 /* mask for GL_FIXED scale channel count */
207 #define BRW_ATTRIB_WA_NORMALIZE 8 /* normalize in shader */
208 #define BRW_ATTRIB_WA_BGRA 16 /* swap r/b channels in shader */
209 #define BRW_ATTRIB_WA_SIGN 32 /* interpret as signed in shader */
210 #define BRW_ATTRIB_WA_SCALE 64 /* interpret as scaled in shader */
213 * OpenGL attribute slots fall in [0, VERT_ATTRIB_MAX - 1] with the range
214 * [VERT_ATTRIB_GENERIC0, VERT_ATTRIB_MAX - 1] reserved for up to 16 user
215 * input vertex attributes. In Vulkan, we expose up to 28 user vertex input
216 * attributes that are mapped to slots also starting at VERT_ATTRIB_GENERIC0.
218 #define MAX_GL_VERT_ATTRIB VERT_ATTRIB_MAX
219 #define MAX_VK_VERT_ATTRIB (VERT_ATTRIB_GENERIC0 + 28)
221 /** The program key for Vertex Shaders. */
222 struct brw_vs_prog_key
{
223 unsigned program_string_id
;
226 * Per-attribute workaround flags
228 * For each attribute, a combination of BRW_ATTRIB_WA_*.
230 * For OpenGL, where we expose a maximum of 16 user input atttributes
231 * we only need up to VERT_ATTRIB_MAX slots, however, in Vulkan
232 * slots preceding VERT_ATTRIB_GENERIC0 are unused and we can
233 * expose up to 28 user input vertex attributes that are mapped to slots
234 * starting at VERT_ATTRIB_GENERIC0, so this array needs to be large
235 * enough to hold this many slots.
237 uint8_t gl_attrib_wa_flags
[MAX2(MAX_GL_VERT_ATTRIB
, MAX_VK_VERT_ATTRIB
)];
239 bool copy_edgeflag
:1;
241 bool clamp_vertex_color
:1;
244 * How many user clipping planes are being uploaded to the vertex shader as
247 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
250 unsigned nr_userclip_plane_consts
:4;
253 * For pre-Gen6 hardware, a bitfield indicating which texture coordinates
254 * are going to be replaced with point coordinates (as a consequence of a
255 * call to glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)). Because
256 * our SF thread requires exact matching between VS outputs and FS inputs,
257 * these texture coordinates will need to be unconditionally included in
258 * the VUE, even if they aren't written by the vertex shader.
260 uint8_t point_coord_replace
;
262 struct brw_sampler_prog_key_data tex
;
265 /** The program key for Tessellation Control Shaders. */
266 struct brw_tcs_prog_key
268 unsigned program_string_id
;
270 GLenum tes_primitive_mode
;
272 unsigned input_vertices
;
274 /** A bitfield of per-patch outputs written. */
275 uint32_t patch_outputs_written
;
277 /** A bitfield of per-vertex outputs written. */
278 uint64_t outputs_written
;
280 bool quads_workaround
;
282 struct brw_sampler_prog_key_data tex
;
285 /** The program key for Tessellation Evaluation Shaders. */
286 struct brw_tes_prog_key
288 unsigned program_string_id
;
290 /** A bitfield of per-patch inputs read. */
291 uint32_t patch_inputs_read
;
293 /** A bitfield of per-vertex inputs read. */
294 uint64_t inputs_read
;
296 struct brw_sampler_prog_key_data tex
;
299 /** The program key for Geometry Shaders. */
300 struct brw_gs_prog_key
302 unsigned program_string_id
;
304 struct brw_sampler_prog_key_data tex
;
307 enum brw_sf_primitive
{
308 BRW_SF_PRIM_POINTS
= 0,
309 BRW_SF_PRIM_LINES
= 1,
310 BRW_SF_PRIM_TRIANGLES
= 2,
311 BRW_SF_PRIM_UNFILLED_TRIS
= 3,
314 struct brw_sf_prog_key
{
316 bool contains_flat_varying
;
317 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
318 uint8_t point_sprite_coord_replace
;
319 enum brw_sf_primitive primitive
:2;
320 bool do_twoside_color
:1;
321 bool frontface_ccw
:1;
322 bool do_point_sprite
:1;
323 bool do_point_coord
:1;
324 bool sprite_origin_lower_left
:1;
325 bool userclip_active
:1;
329 BRW_CLIP_MODE_NORMAL
= 0,
330 BRW_CLIP_MODE_CLIP_ALL
= 1,
331 BRW_CLIP_MODE_CLIP_NON_REJECTED
= 2,
332 BRW_CLIP_MODE_REJECT_ALL
= 3,
333 BRW_CLIP_MODE_ACCEPT_ALL
= 4,
334 BRW_CLIP_MODE_KERNEL_CLIP
= 5,
337 enum brw_clip_fill_mode
{
338 BRW_CLIP_FILL_MODE_LINE
= 0,
339 BRW_CLIP_FILL_MODE_POINT
= 1,
340 BRW_CLIP_FILL_MODE_FILL
= 2,
341 BRW_CLIP_FILL_MODE_CULL
= 3,
344 /* Note that if unfilled primitives are being emitted, we have to fix
345 * up polygon offset and flatshading at this point:
347 struct brw_clip_prog_key
{
349 bool contains_flat_varying
;
350 bool contains_noperspective_varying
;
351 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
352 unsigned primitive
:4;
353 unsigned nr_userclip
:4;
356 enum brw_clip_fill_mode fill_cw
:2; /* includes cull information */
357 enum brw_clip_fill_mode fill_ccw
:2; /* includes cull information */
362 enum brw_clip_mode clip_mode
:3;
369 /* A big lookup table is used to figure out which and how many
370 * additional regs will inserted before the main payload in the WM
371 * program execution. These mainly relate to depth and stencil
372 * processing and the early-depth-test optimization.
374 enum brw_wm_iz_bits
{
375 BRW_WM_IZ_PS_KILL_ALPHATEST_BIT
= 0x1,
376 BRW_WM_IZ_PS_COMPUTES_DEPTH_BIT
= 0x2,
377 BRW_WM_IZ_DEPTH_WRITE_ENABLE_BIT
= 0x4,
378 BRW_WM_IZ_DEPTH_TEST_ENABLE_BIT
= 0x8,
379 BRW_WM_IZ_STENCIL_WRITE_ENABLE_BIT
= 0x10,
380 BRW_WM_IZ_STENCIL_TEST_ENABLE_BIT
= 0x20,
381 BRW_WM_IZ_BIT_MAX
= 0x40
384 enum brw_wm_aa_enable
{
390 /** The program key for Fragment/Pixel Shaders. */
391 struct brw_wm_prog_key
{
392 /* Some collection of BRW_WM_IZ_* */
396 unsigned nr_color_regions
:5;
397 bool replicate_alpha
:1;
398 bool clamp_fragment_color
:1;
399 bool persample_interp
:1;
400 bool multisample_fbo
:1;
401 bool frag_coord_adds_sample_pos
:1;
402 enum brw_wm_aa_enable line_aa
:2;
403 bool high_quality_derivatives
:1;
404 bool force_dual_color_blend
:1;
405 bool coherent_fb_fetch
:1;
407 uint8_t color_outputs_valid
;
408 uint64_t input_slots_valid
;
409 unsigned program_string_id
;
410 GLenum alpha_test_func
; /* < For Gen4/5 MRT alpha test */
411 float alpha_test_ref
;
413 struct brw_sampler_prog_key_data tex
;
416 struct brw_cs_prog_key
{
417 uint32_t program_string_id
;
418 struct brw_sampler_prog_key_data tex
;
421 /* brw_any_prog_key is any of the keys that map to an API stage */
422 union brw_any_prog_key
{
423 struct brw_vs_prog_key vs
;
424 struct brw_tcs_prog_key tcs
;
425 struct brw_tes_prog_key tes
;
426 struct brw_gs_prog_key gs
;
427 struct brw_wm_prog_key wm
;
428 struct brw_cs_prog_key cs
;
432 * Image metadata structure as laid out in the shader parameter
433 * buffer. Entries have to be 16B-aligned for the vec4 back-end to be
434 * able to use them. That's okay because the padding and any unused
435 * entries [most of them except when we're doing untyped surface
436 * access] will be removed by the uniform packing pass.
438 #define BRW_IMAGE_PARAM_OFFSET_OFFSET 0
439 #define BRW_IMAGE_PARAM_SIZE_OFFSET 4
440 #define BRW_IMAGE_PARAM_STRIDE_OFFSET 8
441 #define BRW_IMAGE_PARAM_TILING_OFFSET 12
442 #define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 16
443 #define BRW_IMAGE_PARAM_SIZE 20
445 struct brw_image_param
{
446 /** Offset applied to the X and Y surface coordinates. */
449 /** Surface X, Y and Z dimensions. */
452 /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
453 * pixels, vertical slice stride in pixels.
457 /** Log2 of the tiling modulus in the X, Y and Z dimension. */
461 * Right shift to apply for bit 6 address swizzling. Two different
462 * swizzles can be specified and will be applied one after the other. The
463 * resulting address will be:
465 * addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
466 * (addr >> swizzling[1])))
468 * Use \c 0xff if any of the swizzles is not required.
470 uint32_t swizzling
[2];
473 /** Max number of render targets in a shader */
474 #define BRW_MAX_DRAW_BUFFERS 8
477 * Max number of binding table entries used for stream output.
479 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
480 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
482 * On Gen6, the size of transform feedback data is limited not by the number
483 * of components but by the number of binding table entries we set aside. We
484 * use one binding table entry for a float, one entry for a vector, and one
485 * entry per matrix column. Since the only way we can communicate our
486 * transform feedback capabilities to the client is via
487 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
488 * worst case, in which all the varyings are floats, so we use up one binding
489 * table entry per component. Therefore we need to set aside at least 64
490 * binding table entries for use by transform feedback.
492 * Note: since we don't currently pack varyings, it is currently impossible
493 * for the client to actually use up all of these binding table entries--if
494 * all of their varyings were floats, they would run out of varying slots and
495 * fail to link. But that's a bug, so it seems prudent to go ahead and
496 * allocate the number of binding table entries we will need once the bug is
499 #define BRW_MAX_SOL_BINDINGS 64
502 * Binding table index for the first gen6 SOL binding.
504 #define BRW_GEN6_SOL_BINDING_START 0
507 * Stride in bytes between shader_time entries.
509 * We separate entries by a cacheline to reduce traffic between EUs writing to
512 #define BRW_SHADER_TIME_STRIDE 64
521 /* We reserve the first 2^16 values for builtins */
522 #define BRW_PARAM_IS_BUILTIN(param) (((param) & 0xffff0000) == 0)
524 enum brw_param_builtin
{
525 BRW_PARAM_BUILTIN_ZERO
,
527 BRW_PARAM_BUILTIN_CLIP_PLANE_0_X
,
528 BRW_PARAM_BUILTIN_CLIP_PLANE_0_Y
,
529 BRW_PARAM_BUILTIN_CLIP_PLANE_0_Z
,
530 BRW_PARAM_BUILTIN_CLIP_PLANE_0_W
,
531 BRW_PARAM_BUILTIN_CLIP_PLANE_1_X
,
532 BRW_PARAM_BUILTIN_CLIP_PLANE_1_Y
,
533 BRW_PARAM_BUILTIN_CLIP_PLANE_1_Z
,
534 BRW_PARAM_BUILTIN_CLIP_PLANE_1_W
,
535 BRW_PARAM_BUILTIN_CLIP_PLANE_2_X
,
536 BRW_PARAM_BUILTIN_CLIP_PLANE_2_Y
,
537 BRW_PARAM_BUILTIN_CLIP_PLANE_2_Z
,
538 BRW_PARAM_BUILTIN_CLIP_PLANE_2_W
,
539 BRW_PARAM_BUILTIN_CLIP_PLANE_3_X
,
540 BRW_PARAM_BUILTIN_CLIP_PLANE_3_Y
,
541 BRW_PARAM_BUILTIN_CLIP_PLANE_3_Z
,
542 BRW_PARAM_BUILTIN_CLIP_PLANE_3_W
,
543 BRW_PARAM_BUILTIN_CLIP_PLANE_4_X
,
544 BRW_PARAM_BUILTIN_CLIP_PLANE_4_Y
,
545 BRW_PARAM_BUILTIN_CLIP_PLANE_4_Z
,
546 BRW_PARAM_BUILTIN_CLIP_PLANE_4_W
,
547 BRW_PARAM_BUILTIN_CLIP_PLANE_5_X
,
548 BRW_PARAM_BUILTIN_CLIP_PLANE_5_Y
,
549 BRW_PARAM_BUILTIN_CLIP_PLANE_5_Z
,
550 BRW_PARAM_BUILTIN_CLIP_PLANE_5_W
,
551 BRW_PARAM_BUILTIN_CLIP_PLANE_6_X
,
552 BRW_PARAM_BUILTIN_CLIP_PLANE_6_Y
,
553 BRW_PARAM_BUILTIN_CLIP_PLANE_6_Z
,
554 BRW_PARAM_BUILTIN_CLIP_PLANE_6_W
,
555 BRW_PARAM_BUILTIN_CLIP_PLANE_7_X
,
556 BRW_PARAM_BUILTIN_CLIP_PLANE_7_Y
,
557 BRW_PARAM_BUILTIN_CLIP_PLANE_7_Z
,
558 BRW_PARAM_BUILTIN_CLIP_PLANE_7_W
,
560 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
,
561 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Y
,
562 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Z
,
563 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_W
,
564 BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
,
565 BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y
,
567 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_X
,
568 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Y
,
569 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Z
,
570 BRW_PARAM_BUILTIN_SUBGROUP_ID
,
573 #define BRW_PARAM_BUILTIN_CLIP_PLANE(idx, comp) \
574 (BRW_PARAM_BUILTIN_CLIP_PLANE_0_X + ((idx) << 2) + (comp))
576 #define BRW_PARAM_BUILTIN_IS_CLIP_PLANE(param) \
577 ((param) >= BRW_PARAM_BUILTIN_CLIP_PLANE_0_X && \
578 (param) <= BRW_PARAM_BUILTIN_CLIP_PLANE_7_W)
580 #define BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(param) \
581 (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) >> 2)
583 #define BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(param) \
584 (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) & 0x3)
586 struct brw_stage_prog_data
{
588 /** size of our binding table. */
592 * surface indices for the various groups of surfaces
594 uint32_t pull_constants_start
;
595 uint32_t texture_start
;
596 uint32_t gather_texture_start
;
599 uint32_t image_start
;
600 uint32_t shader_time_start
;
601 uint32_t plane_start
[3];
605 struct brw_ubo_range ubo_ranges
[4];
607 GLuint nr_params
; /**< number of float params/constants */
608 GLuint nr_pull_params
;
610 unsigned curb_read_length
;
611 unsigned total_scratch
;
612 unsigned total_shared
;
614 unsigned program_size
;
617 * Register where the thread expects to find input data from the URB
618 * (typically uniforms, followed by vertex or fragment attributes).
620 unsigned dispatch_grf_start_reg
;
622 bool use_alt_mode
; /**< Use ALT floating point mode? Otherwise, IEEE. */
624 /* 32-bit identifiers for all push/pull parameters. These can be anything
625 * the driver wishes them to be; the core of the back-end compiler simply
626 * re-arranges them. The one restriction is that the bottom 2^16 values
627 * are reserved for builtins defined in the brw_param_builtin enum defined
631 uint32_t *pull_param
;
634 static inline uint32_t *
635 brw_stage_prog_data_add_params(struct brw_stage_prog_data
*prog_data
,
636 unsigned nr_new_params
)
638 unsigned old_nr_params
= prog_data
->nr_params
;
639 prog_data
->nr_params
+= nr_new_params
;
640 prog_data
->param
= reralloc(ralloc_parent(prog_data
->param
),
641 prog_data
->param
, uint32_t,
642 prog_data
->nr_params
);
643 return prog_data
->param
+ old_nr_params
;
647 brw_mark_surface_used(struct brw_stage_prog_data
*prog_data
,
650 /* A binding table index is 8 bits and the top 3 values are reserved for
651 * special things (stateless and SLM).
653 assert(surf_index
<= 252);
655 prog_data
->binding_table
.size_bytes
=
656 MAX2(prog_data
->binding_table
.size_bytes
, (surf_index
+ 1) * 4);
659 enum brw_barycentric_mode
{
660 BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
= 0,
661 BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
= 1,
662 BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
= 2,
663 BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL
= 3,
664 BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
= 4,
665 BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE
= 5,
666 BRW_BARYCENTRIC_MODE_COUNT
= 6
668 #define BRW_BARYCENTRIC_NONPERSPECTIVE_BITS \
669 ((1 << BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL) | \
670 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID) | \
671 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE))
673 enum brw_pixel_shader_computed_depth_mode
{
674 BRW_PSCDEPTH_OFF
= 0, /* PS does not compute depth */
675 BRW_PSCDEPTH_ON
= 1, /* PS computes depth; no guarantee about value */
676 BRW_PSCDEPTH_ON_GE
= 2, /* PS guarantees output depth >= source depth */
677 BRW_PSCDEPTH_ON_LE
= 3, /* PS guarantees output depth <= source depth */
680 /* Data about a particular attempt to compile a program. Note that
681 * there can be many of these, each in a different GL state
682 * corresponding to a different brw_wm_prog_key struct, with different
685 struct brw_wm_prog_data
{
686 struct brw_stage_prog_data base
;
688 GLuint num_varying_inputs
;
690 uint8_t reg_blocks_8
;
691 uint8_t reg_blocks_16
;
692 uint8_t reg_blocks_32
;
694 uint8_t dispatch_grf_start_reg_16
;
695 uint8_t dispatch_grf_start_reg_32
;
696 uint32_t prog_offset_16
;
697 uint32_t prog_offset_32
;
701 * surface indices the WM-specific surfaces
703 uint32_t render_target_read_start
;
707 uint8_t computed_depth_mode
;
708 bool computed_stencil
;
710 bool early_fragment_tests
;
711 bool post_depth_coverage
;
717 bool persample_dispatch
;
718 bool uses_pos_offset
;
723 bool uses_sample_mask
;
724 bool has_render_target_reads
;
725 bool has_side_effects
;
728 bool contains_flat_varying
;
729 bool contains_noperspective_varying
;
732 * Mask of which interpolation modes are required by the fragment shader.
733 * Used in hardware setup on gen6+.
735 uint32_t barycentric_interp_modes
;
738 * Mask of which FS inputs are marked flat by the shader source. This is
739 * needed for setting up 3DSTATE_SF/SBE.
741 uint32_t flat_inputs
;
743 /* Mapping of VUE slots to interpolation modes.
744 * Used by the Gen4-5 clip/sf/wm stages.
746 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
749 * Map from gl_varying_slot to the position within the FS setup data
750 * payload where the varying's attribute vertex deltas should be delivered.
751 * For varying slots that are not used by the FS, the value is -1.
753 int urb_setup
[VARYING_SLOT_MAX
];
756 /** Returns the SIMD width corresponding to a given KSP index
758 * The "Variable Pixel Dispatch" table in the PRM (which can be found, for
759 * example in Vol. 7 of the SKL PRM) has a mapping from dispatch widths to
760 * kernel start pointer (KSP) indices that is based on what dispatch widths
761 * are enabled. This function provides, effectively, the reverse mapping.
763 * If the given KSP is valid with respect to the SIMD8/16/32 enables, a SIMD
764 * width of 8, 16, or 32 is returned. If the KSP is invalid, 0 is returned.
766 static inline unsigned
767 brw_fs_simd_width_for_ksp(unsigned ksp_idx
, bool simd8_enabled
,
768 bool simd16_enabled
, bool simd32_enabled
)
770 /* This function strictly ignores contiguous dispatch */
773 return simd8_enabled
? 8 :
774 (simd16_enabled
&& !simd32_enabled
) ? 16 :
775 (simd32_enabled
&& !simd16_enabled
) ? 32 : 0;
777 return (simd32_enabled
&& (simd16_enabled
|| simd8_enabled
)) ? 32 : 0;
779 return (simd16_enabled
&& (simd32_enabled
|| simd8_enabled
)) ? 16 : 0;
781 unreachable("Invalid KSP index");
785 #define brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx) \
786 brw_fs_simd_width_for_ksp((ksp_idx), (wm_state)._8PixelDispatchEnable, \
787 (wm_state)._16PixelDispatchEnable, \
788 (wm_state)._32PixelDispatchEnable)
790 #define brw_wm_state_has_ksp(wm_state, ksp_idx) \
791 (brw_wm_state_simd_width_for_ksp((wm_state), (ksp_idx)) != 0)
793 static inline uint32_t
794 _brw_wm_prog_data_prog_offset(const struct brw_wm_prog_data
*prog_data
,
797 switch (simd_width
) {
799 case 16: return prog_data
->prog_offset_16
;
800 case 32: return prog_data
->prog_offset_32
;
805 #define brw_wm_prog_data_prog_offset(prog_data, wm_state, ksp_idx) \
806 _brw_wm_prog_data_prog_offset(prog_data, \
807 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
809 static inline uint8_t
810 _brw_wm_prog_data_dispatch_grf_start_reg(const struct brw_wm_prog_data
*prog_data
,
813 switch (simd_width
) {
814 case 8: return prog_data
->base
.dispatch_grf_start_reg
;
815 case 16: return prog_data
->dispatch_grf_start_reg_16
;
816 case 32: return prog_data
->dispatch_grf_start_reg_32
;
821 #define brw_wm_prog_data_dispatch_grf_start_reg(prog_data, wm_state, ksp_idx) \
822 _brw_wm_prog_data_dispatch_grf_start_reg(prog_data, \
823 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
825 static inline uint8_t
826 _brw_wm_prog_data_reg_blocks(const struct brw_wm_prog_data
*prog_data
,
829 switch (simd_width
) {
830 case 8: return prog_data
->reg_blocks_8
;
831 case 16: return prog_data
->reg_blocks_16
;
832 case 32: return prog_data
->reg_blocks_32
;
837 #define brw_wm_prog_data_reg_blocks(prog_data, wm_state, ksp_idx) \
838 _brw_wm_prog_data_reg_blocks(prog_data, \
839 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
841 struct brw_push_const_block
{
842 unsigned dwords
; /* Dword count, not reg aligned */
844 unsigned size
; /* Bytes, register aligned */
847 struct brw_cs_prog_data
{
848 struct brw_stage_prog_data base
;
850 unsigned local_size
[3];
854 bool uses_num_work_groups
;
857 struct brw_push_const_block cross_thread
;
858 struct brw_push_const_block per_thread
;
859 struct brw_push_const_block total
;
864 * surface indices the CS-specific surfaces
866 uint32_t work_groups_start
;
872 * Enum representing the i965-specific vertex results that don't correspond
873 * exactly to any element of gl_varying_slot. The values of this enum are
874 * assigned such that they don't conflict with gl_varying_slot.
878 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
879 BRW_VARYING_SLOT_PAD
,
881 * Technically this is not a varying but just a placeholder that
882 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
883 * builtin variable to be compiled correctly. see compile_sf_prog() for
886 BRW_VARYING_SLOT_PNTC
,
887 BRW_VARYING_SLOT_COUNT
891 * We always program SF to start reading at an offset of 1 (2 varying slots)
892 * from the start of the vertex URB entry. This causes it to skip:
893 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
894 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
896 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
899 * Bitmask indicating which fragment shader inputs represent varyings (and
900 * hence have to be delivered to the fragment shader by the SF/SBE stage).
902 #define BRW_FS_VARYING_INPUT_MASK \
903 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
904 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
907 * Data structure recording the relationship between the gl_varying_slot enum
908 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
909 * single octaword within the VUE (128 bits).
911 * Note that each BRW register contains 256 bits (2 octawords), so when
912 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
913 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
914 * in a vertex shader), each register corresponds to a single VUE slot, since
915 * it contains data for two separate vertices.
919 * Bitfield representing all varying slots that are (a) stored in this VUE
920 * map, and (b) actually written by the shader. Does not include any of
921 * the additional varying slots defined in brw_varying_slot.
923 uint64_t slots_valid
;
926 * Is this VUE map for a separate shader pipeline?
928 * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched
929 * without the linker having a chance to dead code eliminate unused varyings.
931 * This means that we have to use a fixed slot layout, based on the output's
932 * location field, rather than assigning slots in a compact contiguous block.
937 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
938 * not stored in a slot (because they are not written, or because
939 * additional processing is applied before storing them in the VUE), the
942 signed char varying_to_slot
[VARYING_SLOT_TESS_MAX
];
945 * Map from VUE slot to gl_varying_slot value. For slots that do not
946 * directly correspond to a gl_varying_slot, the value comes from
949 * For slots that are not in use, the value is BRW_VARYING_SLOT_PAD.
951 signed char slot_to_varying
[VARYING_SLOT_TESS_MAX
];
954 * Total number of VUE slots in use
959 * Number of per-patch VUE slots. Only valid for tessellation control
960 * shader outputs and tessellation evaluation shader inputs.
962 int num_per_patch_slots
;
965 * Number of per-vertex VUE slots. Only valid for tessellation control
966 * shader outputs and tessellation evaluation shader inputs.
968 int num_per_vertex_slots
;
971 void brw_print_vue_map(FILE *fp
, const struct brw_vue_map
*vue_map
);
974 * Convert a VUE slot number into a byte offset within the VUE.
976 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
982 * Convert a vertex output (brw_varying_slot) into a byte offset within the
986 GLuint
brw_varying_to_offset(const struct brw_vue_map
*vue_map
, GLuint varying
)
988 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
991 void brw_compute_vue_map(const struct gen_device_info
*devinfo
,
992 struct brw_vue_map
*vue_map
,
993 uint64_t slots_valid
,
994 bool separate_shader
);
996 void brw_compute_tess_vue_map(struct brw_vue_map
*const vue_map
,
997 uint64_t slots_valid
,
1000 /* brw_interpolation_map.c */
1001 void brw_setup_vue_interpolation(struct brw_vue_map
*vue_map
,
1002 struct nir_shader
*nir
,
1003 struct brw_wm_prog_data
*prog_data
,
1004 const struct gen_device_info
*devinfo
);
1006 enum shader_dispatch_mode
{
1007 DISPATCH_MODE_4X1_SINGLE
= 0,
1008 DISPATCH_MODE_4X2_DUAL_INSTANCE
= 1,
1009 DISPATCH_MODE_4X2_DUAL_OBJECT
= 2,
1010 DISPATCH_MODE_SIMD8
= 3,
1014 * @defgroup Tessellator parameter enumerations.
1016 * These correspond to the hardware values in 3DSTATE_TE, and are provided
1017 * as part of the tessellation evaluation shader.
1021 enum brw_tess_partitioning
{
1022 BRW_TESS_PARTITIONING_INTEGER
= 0,
1023 BRW_TESS_PARTITIONING_ODD_FRACTIONAL
= 1,
1024 BRW_TESS_PARTITIONING_EVEN_FRACTIONAL
= 2,
1027 enum brw_tess_output_topology
{
1028 BRW_TESS_OUTPUT_TOPOLOGY_POINT
= 0,
1029 BRW_TESS_OUTPUT_TOPOLOGY_LINE
= 1,
1030 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
= 2,
1031 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW
= 3,
1034 enum brw_tess_domain
{
1035 BRW_TESS_DOMAIN_QUAD
= 0,
1036 BRW_TESS_DOMAIN_TRI
= 1,
1037 BRW_TESS_DOMAIN_ISOLINE
= 2,
1041 struct brw_vue_prog_data
{
1042 struct brw_stage_prog_data base
;
1043 struct brw_vue_map vue_map
;
1045 /** Should the hardware deliver input VUE handles for URB pull loads? */
1046 bool include_vue_handles
;
1048 GLuint urb_read_length
;
1051 uint32_t clip_distance_mask
;
1052 uint32_t cull_distance_mask
;
1054 /* Used for calculating urb partitions. In the VS, this is the size of the
1055 * URB entry used for both input and output to the thread. In the GS, this
1056 * is the size of the URB entry used for output.
1058 GLuint urb_entry_size
;
1060 enum shader_dispatch_mode dispatch_mode
;
1063 struct brw_vs_prog_data
{
1064 struct brw_vue_prog_data base
;
1066 GLbitfield64 inputs_read
;
1067 GLbitfield64 double_inputs_read
;
1069 unsigned nr_attribute_slots
;
1072 bool uses_instanceid
;
1073 bool uses_is_indexed_draw
;
1074 bool uses_firstvertex
;
1075 bool uses_baseinstance
;
1079 struct brw_tcs_prog_data
1081 struct brw_vue_prog_data base
;
1083 /** Number vertices in output patch */
1088 struct brw_tes_prog_data
1090 struct brw_vue_prog_data base
;
1092 enum brw_tess_partitioning partitioning
;
1093 enum brw_tess_output_topology output_topology
;
1094 enum brw_tess_domain domain
;
1097 struct brw_gs_prog_data
1099 struct brw_vue_prog_data base
;
1101 unsigned vertices_in
;
1104 * Size of an output vertex, measured in HWORDS (32 bytes).
1106 unsigned output_vertex_size_hwords
;
1108 unsigned output_topology
;
1111 * Size of the control data (cut bits or StreamID bits), in hwords (32
1112 * bytes). 0 if there is no control data.
1114 unsigned control_data_header_size_hwords
;
1117 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
1118 * if the control data is StreamID bits, or
1119 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
1120 * Ignored if control_data_header_size is 0.
1122 unsigned control_data_format
;
1124 bool include_primitive_id
;
1127 * The number of vertices emitted, if constant - otherwise -1.
1129 int static_vertex_count
;
1134 * Gen6: Provoking vertex convention for odd-numbered triangles
1140 * Gen6: Number of varyings that are output to transform feedback.
1142 GLuint num_transform_feedback_bindings
:7; /* 0-BRW_MAX_SOL_BINDINGS */
1145 * Gen6: Map from the index of a transform feedback binding table entry to the
1146 * gl_varying_slot that should be streamed out through that binding table
1149 unsigned char transform_feedback_bindings
[64 /* BRW_MAX_SOL_BINDINGS */];
1152 * Gen6: Map from the index of a transform feedback binding table entry to the
1153 * swizzles that should be used when streaming out data through that
1154 * binding table entry.
1156 unsigned char transform_feedback_swizzles
[64 /* BRW_MAX_SOL_BINDINGS */];
1159 struct brw_sf_prog_data
{
1160 uint32_t urb_read_length
;
1163 /* Each vertex may have upto 12 attributes, 4 components each,
1164 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
1167 * Actually we use 4 for each, so call it 12 rows.
1169 unsigned urb_entry_size
;
1172 struct brw_clip_prog_data
{
1173 uint32_t curb_read_length
; /* user planes? */
1175 uint32_t urb_read_length
;
1179 /* brw_any_prog_data is prog_data for any stage that maps to an API stage */
1180 union brw_any_prog_data
{
1181 struct brw_stage_prog_data base
;
1182 struct brw_vue_prog_data vue
;
1183 struct brw_vs_prog_data vs
;
1184 struct brw_tcs_prog_data tcs
;
1185 struct brw_tes_prog_data tes
;
1186 struct brw_gs_prog_data gs
;
1187 struct brw_wm_prog_data wm
;
1188 struct brw_cs_prog_data cs
;
1191 #define DEFINE_PROG_DATA_DOWNCAST(stage) \
1192 static inline struct brw_##stage##_prog_data * \
1193 brw_##stage##_prog_data(struct brw_stage_prog_data *prog_data) \
1195 return (struct brw_##stage##_prog_data *) prog_data; \
1197 DEFINE_PROG_DATA_DOWNCAST(vue
)
1198 DEFINE_PROG_DATA_DOWNCAST(vs
)
1199 DEFINE_PROG_DATA_DOWNCAST(tcs
)
1200 DEFINE_PROG_DATA_DOWNCAST(tes
)
1201 DEFINE_PROG_DATA_DOWNCAST(gs
)
1202 DEFINE_PROG_DATA_DOWNCAST(wm
)
1203 DEFINE_PROG_DATA_DOWNCAST(cs
)
1204 DEFINE_PROG_DATA_DOWNCAST(ff_gs
)
1205 DEFINE_PROG_DATA_DOWNCAST(clip
)
1206 DEFINE_PROG_DATA_DOWNCAST(sf
)
1207 #undef DEFINE_PROG_DATA_DOWNCAST
1211 struct brw_compiler
*
1212 brw_compiler_create(void *mem_ctx
, const struct gen_device_info
*devinfo
);
1215 * Returns a compiler configuration for use with disk shader cache
1217 * This value only needs to change for settings that can cause different
1218 * program generation between two runs on the same hardware.
1220 * For example, it doesn't need to be different for gen 8 and gen 9 hardware,
1221 * but it does need to be different if INTEL_DEBUG=nocompact is or isn't used.
1224 brw_get_compiler_config_value(const struct brw_compiler
*compiler
);
1227 brw_prog_data_size(gl_shader_stage stage
);
1230 brw_prog_key_size(gl_shader_stage stage
);
1233 * Compile a vertex shader.
1235 * Returns the final assembly and the program's size.
1238 brw_compile_vs(const struct brw_compiler
*compiler
, void *log_data
,
1240 const struct brw_vs_prog_key
*key
,
1241 struct brw_vs_prog_data
*prog_data
,
1242 struct nir_shader
*shader
,
1243 int shader_time_index
,
1247 * Compile a tessellation control shader.
1249 * Returns the final assembly and the program's size.
1252 brw_compile_tcs(const struct brw_compiler
*compiler
,
1255 const struct brw_tcs_prog_key
*key
,
1256 struct brw_tcs_prog_data
*prog_data
,
1257 struct nir_shader
*nir
,
1258 int shader_time_index
,
1262 * Compile a tessellation evaluation shader.
1264 * Returns the final assembly and the program's size.
1267 brw_compile_tes(const struct brw_compiler
*compiler
, void *log_data
,
1269 const struct brw_tes_prog_key
*key
,
1270 const struct brw_vue_map
*input_vue_map
,
1271 struct brw_tes_prog_data
*prog_data
,
1272 struct nir_shader
*shader
,
1273 struct gl_program
*prog
,
1274 int shader_time_index
,
1278 * Compile a vertex shader.
1280 * Returns the final assembly and the program's size.
1283 brw_compile_gs(const struct brw_compiler
*compiler
, void *log_data
,
1285 const struct brw_gs_prog_key
*key
,
1286 struct brw_gs_prog_data
*prog_data
,
1287 struct nir_shader
*shader
,
1288 struct gl_program
*prog
,
1289 int shader_time_index
,
1293 * Compile a strips and fans shader.
1295 * This is a fixed-function shader determined entirely by the shader key and
1298 * Returns the final assembly and the program's size.
1301 brw_compile_sf(const struct brw_compiler
*compiler
,
1303 const struct brw_sf_prog_key
*key
,
1304 struct brw_sf_prog_data
*prog_data
,
1305 struct brw_vue_map
*vue_map
,
1306 unsigned *final_assembly_size
);
1309 * Compile a clipper shader.
1311 * This is a fixed-function shader determined entirely by the shader key and
1314 * Returns the final assembly and the program's size.
1317 brw_compile_clip(const struct brw_compiler
*compiler
,
1319 const struct brw_clip_prog_key
*key
,
1320 struct brw_clip_prog_data
*prog_data
,
1321 struct brw_vue_map
*vue_map
,
1322 unsigned *final_assembly_size
);
1325 * Compile a fragment shader.
1327 * Returns the final assembly and the program's size.
1330 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
1332 const struct brw_wm_prog_key
*key
,
1333 struct brw_wm_prog_data
*prog_data
,
1334 struct nir_shader
*shader
,
1335 struct gl_program
*prog
,
1336 int shader_time_index8
,
1337 int shader_time_index16
,
1338 int shader_time_index32
,
1339 bool allow_spilling
,
1340 bool use_rep_send
, struct brw_vue_map
*vue_map
,
1344 * Compile a compute shader.
1346 * Returns the final assembly and the program's size.
1349 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
1351 const struct brw_cs_prog_key
*key
,
1352 struct brw_cs_prog_data
*prog_data
,
1353 const struct nir_shader
*shader
,
1354 int shader_time_index
,
1357 static inline uint32_t
1358 encode_slm_size(unsigned gen
, uint32_t bytes
)
1360 uint32_t slm_size
= 0;
1362 /* Shared Local Memory is specified as powers of two, and encoded in
1363 * INTERFACE_DESCRIPTOR_DATA with the following representations:
1365 * Size | 0 kB | 1 kB | 2 kB | 4 kB | 8 kB | 16 kB | 32 kB | 64 kB |
1366 * -------------------------------------------------------------------
1367 * Gen7-8 | 0 | none | none | 1 | 2 | 4 | 8 | 16 |
1368 * -------------------------------------------------------------------
1369 * Gen9+ | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
1371 assert(bytes
<= 64 * 1024);
1374 /* Shared Local Memory Size is specified as powers of two. */
1375 slm_size
= util_next_power_of_two(bytes
);
1378 /* Use a minimum of 1kB; turn an exponent of 10 (1024 kB) into 1. */
1379 slm_size
= ffs(MAX2(slm_size
, 1024)) - 10;
1381 /* Use a minimum of 4kB; convert to the pre-Gen9 representation. */
1382 slm_size
= MAX2(slm_size
, 4096) / 4096;
1390 * Return true if the given shader stage is dispatched contiguously by the
1391 * relevant fixed function starting from channel 0 of the SIMD thread, which
1392 * implies that the dispatch mask of a thread can be assumed to have the form
1393 * '2^n - 1' for some n.
1396 brw_stage_has_packed_dispatch(MAYBE_UNUSED
const struct gen_device_info
*devinfo
,
1397 gl_shader_stage stage
,
1398 const struct brw_stage_prog_data
*prog_data
)
1400 /* The code below makes assumptions about the hardware's thread dispatch
1401 * behavior that could be proven wrong in future generations -- Make sure
1402 * to do a full test run with brw_fs_test_dispatch_packing() hooked up to
1403 * the NIR front-end before changing this assertion.
1405 assert(devinfo
->gen
<= 11);
1408 case MESA_SHADER_FRAGMENT
: {
1409 /* The PSD discards subspans coming in with no lit samples, which in the
1410 * per-pixel shading case implies that each subspan will either be fully
1411 * lit (due to the VMask being used to allow derivative computations),
1412 * or not dispatched at all. In per-sample dispatch mode individual
1413 * samples from the same subspan have a fixed relative location within
1414 * the SIMD thread, so dispatch of unlit samples cannot be avoided in
1415 * general and we should return false.
1417 const struct brw_wm_prog_data
*wm_prog_data
=
1418 (const struct brw_wm_prog_data
*)prog_data
;
1419 return !wm_prog_data
->persample_dispatch
;
1421 case MESA_SHADER_COMPUTE
:
1422 /* Compute shaders will be spawned with either a fully enabled dispatch
1423 * mask or with whatever bottom/right execution mask was given to the
1424 * GPGPU walker command to be used along the workgroup edges -- In both
1425 * cases the dispatch mask is required to be tightly packed for our
1426 * invocation index calculations to work.
1430 /* Most remaining fixed functions are limited to use a packed dispatch
1431 * mask due to the hardware representation of the dispatch mask as a
1432 * single counter representing the number of enabled channels.
1439 * Computes the first varying slot in the URB produced by the previous stage
1440 * that is used in the next stage. We do this by testing the varying slots in
1441 * the previous stage's vue map against the inputs read in the next stage.
1445 * - Each URB offset contains two varying slots and we can only skip a
1446 * full offset if both slots are unused, so the value we return here is always
1447 * rounded down to the closest multiple of two.
1449 * - gl_Layer and gl_ViewportIndex don't have their own varying slots, they are
1450 * part of the vue header, so if these are read we can't skip anything.
1453 brw_compute_first_urb_slot_required(uint64_t inputs_read
,
1454 const struct brw_vue_map
*prev_stage_vue_map
)
1456 if ((inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
)) == 0) {
1457 for (int i
= 0; i
< prev_stage_vue_map
->num_slots
; i
++) {
1458 int varying
= prev_stage_vue_map
->slot_to_varying
[i
];
1459 if (varying
> 0 && (inputs_read
& BITFIELD64_BIT(varying
)) != 0)
1460 return ROUND_DOWN_TO(i
, 2);
1471 #endif /* BRW_COMPILER_H */