2 * Copyright © 2010 - 2015 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #ifndef BRW_COMPILER_H
25 #define BRW_COMPILER_H
28 #include "dev/gen_device_info.h"
29 #include "main/macros.h"
30 #include "main/mtypes.h"
31 #include "util/ralloc.h"
42 const struct gen_device_info
*devinfo
;
48 * Array of the ra classes for the unaligned contiguous register
54 * Mapping for register-allocated objects in *regs to the first
55 * GRF for that object.
57 uint8_t *ra_reg_to_grf
;
64 * Array of the ra classes for the unaligned contiguous register
65 * block sizes used, indexed by register size.
70 * Mapping from classes to ra_reg ranges. Each of the per-size
71 * classes corresponds to a range of ra_reg nodes. This array stores
72 * those ranges in the form of first ra_reg in each class and the
73 * total number of ra_reg elements in the last array element. This
74 * way the range of the i'th class is given by:
75 * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] )
77 int class_to_ra_reg_range
[17];
80 * Mapping for register-allocated objects in *regs to the first
81 * GRF for that object.
83 uint8_t *ra_reg_to_grf
;
86 * ra class for the aligned pairs we use for PLN, which doesn't
89 int aligned_pairs_class
;
92 void (*shader_debug_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
93 void (*shader_perf_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
95 bool scalar_stage
[MESA_SHADER_STAGES
];
97 struct gl_shader_compiler_options glsl_compiler_options
[MESA_SHADER_STAGES
];
100 * Apply workarounds for SIN and COS output range problems.
101 * This can negatively impact performance.
106 * Is 3DSTATE_CONSTANT_*'s Constant Buffer 0 relative to Dynamic State
107 * Base Address? (If not, it's a normal GPU address.)
109 bool constant_buffer_0_is_relative
;
112 * Whether or not the driver supports pull constants. If not, the compiler
113 * will attempt to push everything.
115 bool supports_pull_constants
;
118 * Whether or not the driver supports NIR shader constants. This controls
119 * whether nir_opt_large_constants will be run.
121 bool supports_shader_constants
;
125 * We use a constant subgroup size of 32. It really only needs to be a
126 * maximum and, since we do SIMD32 for compute shaders in some cases, it
127 * needs to be at least 32. SIMD8 and SIMD16 shaders will still claim a
128 * subgroup size of 32 but will act as if 16 or 24 of those channels are
131 #define BRW_SUBGROUP_SIZE 32
134 * Program key structures.
136 * When drawing, we look for the currently bound shaders in the program
137 * cache. This is essentially a hash table lookup, and these are the keys.
139 * Sometimes OpenGL features specified as state need to be simulated via
140 * shader code, due to a mismatch between the API and the hardware. This
141 * is often referred to as "non-orthagonal state" or "NOS". We store NOS
142 * in the program key so it's considered when searching for a program. If
143 * we haven't seen a particular combination before, we have to recompile a
144 * new specialized version.
146 * Shader compilation should not look up state in gl_context directly, but
147 * instead use the copy in the program key. This guarantees recompiles will
153 enum PACKED gen6_gather_sampler_wa
{
154 WA_SIGN
= 1, /* whether we need to sign extend */
155 WA_8BIT
= 2, /* if we have an 8bit format needing wa */
156 WA_16BIT
= 4, /* if we have a 16bit format needing wa */
160 * Sampler information needed by VS, WM, and GS program cache keys.
162 struct brw_sampler_prog_key_data
{
164 * EXT_texture_swizzle and DEPTH_TEXTURE_MODE swizzles.
166 uint16_t swizzles
[MAX_SAMPLERS
];
168 uint32_t gl_clamp_mask
[3];
171 * For RG32F, gather4's channel select is broken.
173 uint32_t gather_channel_quirk_mask
;
176 * Whether this sampler uses the compressed multisample surface layout.
178 uint32_t compressed_multisample_layout_mask
;
181 * Whether this sampler is using 16x multisampling. If so fetching from
182 * this sampler will be handled with a different instruction, ld2dms_w
188 * For Sandybridge, which shader w/a we need for gather quirks.
190 enum gen6_gather_sampler_wa gen6_gather_wa
[MAX_SAMPLERS
];
193 * Texture units that have a YUV image bound.
195 uint32_t y_u_v_image_mask
;
196 uint32_t y_uv_image_mask
;
197 uint32_t yx_xuxv_image_mask
;
198 uint32_t xy_uxvx_image_mask
;
199 uint32_t ayuv_image_mask
;
200 uint32_t xyuv_image_mask
;
202 /* Scale factor for each texture. */
203 float scale_factors
[32];
206 /** An enum representing what kind of input gl_SubgroupSize is. */
207 enum PACKED brw_subgroup_size_type
209 BRW_SUBGROUP_SIZE_API_CONSTANT
, /**< Default Vulkan behavior */
210 BRW_SUBGROUP_SIZE_UNIFORM
, /**< OpenGL behavior */
211 BRW_SUBGROUP_SIZE_VARYING
, /**< VK_EXT_subgroup_size_control */
213 /* These enums are specifically chosen so that the value of the enum is
214 * also the subgroup size. If any new values are added, they must respect
217 BRW_SUBGROUP_SIZE_REQUIRE_8
= 8, /**< VK_EXT_subgroup_size_control */
218 BRW_SUBGROUP_SIZE_REQUIRE_16
= 16, /**< VK_EXT_subgroup_size_control */
219 BRW_SUBGROUP_SIZE_REQUIRE_32
= 32, /**< VK_EXT_subgroup_size_control */
222 struct brw_base_prog_key
{
223 unsigned program_string_id
;
225 enum brw_subgroup_size_type subgroup_size_type
;
227 struct brw_sampler_prog_key_data tex
;
231 * The VF can't natively handle certain types of attributes, such as GL_FIXED
232 * or most 10_10_10_2 types. These flags enable various VS workarounds to
233 * "fix" attributes at the beginning of shaders.
235 #define BRW_ATTRIB_WA_COMPONENT_MASK 7 /* mask for GL_FIXED scale channel count */
236 #define BRW_ATTRIB_WA_NORMALIZE 8 /* normalize in shader */
237 #define BRW_ATTRIB_WA_BGRA 16 /* swap r/b channels in shader */
238 #define BRW_ATTRIB_WA_SIGN 32 /* interpret as signed in shader */
239 #define BRW_ATTRIB_WA_SCALE 64 /* interpret as scaled in shader */
242 * OpenGL attribute slots fall in [0, VERT_ATTRIB_MAX - 1] with the range
243 * [VERT_ATTRIB_GENERIC0, VERT_ATTRIB_MAX - 1] reserved for up to 16 user
244 * input vertex attributes. In Vulkan, we expose up to 28 user vertex input
245 * attributes that are mapped to slots also starting at VERT_ATTRIB_GENERIC0.
247 #define MAX_GL_VERT_ATTRIB VERT_ATTRIB_MAX
248 #define MAX_VK_VERT_ATTRIB (VERT_ATTRIB_GENERIC0 + 28)
250 /** The program key for Vertex Shaders. */
251 struct brw_vs_prog_key
{
252 struct brw_base_prog_key base
;
255 * Per-attribute workaround flags
257 * For each attribute, a combination of BRW_ATTRIB_WA_*.
259 * For OpenGL, where we expose a maximum of 16 user input atttributes
260 * we only need up to VERT_ATTRIB_MAX slots, however, in Vulkan
261 * slots preceding VERT_ATTRIB_GENERIC0 are unused and we can
262 * expose up to 28 user input vertex attributes that are mapped to slots
263 * starting at VERT_ATTRIB_GENERIC0, so this array needs to be large
264 * enough to hold this many slots.
266 uint8_t gl_attrib_wa_flags
[MAX2(MAX_GL_VERT_ATTRIB
, MAX_VK_VERT_ATTRIB
)];
268 bool copy_edgeflag
:1;
270 bool clamp_vertex_color
:1;
273 * How many user clipping planes are being uploaded to the vertex shader as
276 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
279 unsigned nr_userclip_plane_consts
:4;
282 * For pre-Gen6 hardware, a bitfield indicating which texture coordinates
283 * are going to be replaced with point coordinates (as a consequence of a
284 * call to glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)). Because
285 * our SF thread requires exact matching between VS outputs and FS inputs,
286 * these texture coordinates will need to be unconditionally included in
287 * the VUE, even if they aren't written by the vertex shader.
289 uint8_t point_coord_replace
;
292 /** The program key for Tessellation Control Shaders. */
293 struct brw_tcs_prog_key
295 struct brw_base_prog_key base
;
297 GLenum tes_primitive_mode
;
299 unsigned input_vertices
;
301 /** A bitfield of per-patch outputs written. */
302 uint32_t patch_outputs_written
;
304 /** A bitfield of per-vertex outputs written. */
305 uint64_t outputs_written
;
307 bool quads_workaround
;
310 /** The program key for Tessellation Evaluation Shaders. */
311 struct brw_tes_prog_key
313 struct brw_base_prog_key base
;
315 /** A bitfield of per-patch inputs read. */
316 uint32_t patch_inputs_read
;
318 /** A bitfield of per-vertex inputs read. */
319 uint64_t inputs_read
;
322 * How many user clipping planes are being uploaded to the tessellation
323 * evaluation shader as push constants.
325 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
328 unsigned nr_userclip_plane_consts
:4;
331 /** The program key for Geometry Shaders. */
332 struct brw_gs_prog_key
334 struct brw_base_prog_key base
;
337 * How many user clipping planes are being uploaded to the geometry shader
340 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
343 unsigned nr_userclip_plane_consts
:4;
346 enum brw_sf_primitive
{
347 BRW_SF_PRIM_POINTS
= 0,
348 BRW_SF_PRIM_LINES
= 1,
349 BRW_SF_PRIM_TRIANGLES
= 2,
350 BRW_SF_PRIM_UNFILLED_TRIS
= 3,
353 struct brw_sf_prog_key
{
355 bool contains_flat_varying
;
356 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
357 uint8_t point_sprite_coord_replace
;
358 enum brw_sf_primitive primitive
:2;
359 bool do_twoside_color
:1;
360 bool frontface_ccw
:1;
361 bool do_point_sprite
:1;
362 bool do_point_coord
:1;
363 bool sprite_origin_lower_left
:1;
364 bool userclip_active
:1;
368 BRW_CLIP_MODE_NORMAL
= 0,
369 BRW_CLIP_MODE_CLIP_ALL
= 1,
370 BRW_CLIP_MODE_CLIP_NON_REJECTED
= 2,
371 BRW_CLIP_MODE_REJECT_ALL
= 3,
372 BRW_CLIP_MODE_ACCEPT_ALL
= 4,
373 BRW_CLIP_MODE_KERNEL_CLIP
= 5,
376 enum brw_clip_fill_mode
{
377 BRW_CLIP_FILL_MODE_LINE
= 0,
378 BRW_CLIP_FILL_MODE_POINT
= 1,
379 BRW_CLIP_FILL_MODE_FILL
= 2,
380 BRW_CLIP_FILL_MODE_CULL
= 3,
383 /* Note that if unfilled primitives are being emitted, we have to fix
384 * up polygon offset and flatshading at this point:
386 struct brw_clip_prog_key
{
388 bool contains_flat_varying
;
389 bool contains_noperspective_varying
;
390 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
391 unsigned primitive
:4;
392 unsigned nr_userclip
:4;
395 enum brw_clip_fill_mode fill_cw
:2; /* includes cull information */
396 enum brw_clip_fill_mode fill_ccw
:2; /* includes cull information */
401 enum brw_clip_mode clip_mode
:3;
408 /* A big lookup table is used to figure out which and how many
409 * additional regs will inserted before the main payload in the WM
410 * program execution. These mainly relate to depth and stencil
411 * processing and the early-depth-test optimization.
413 enum brw_wm_iz_bits
{
414 BRW_WM_IZ_PS_KILL_ALPHATEST_BIT
= 0x1,
415 BRW_WM_IZ_PS_COMPUTES_DEPTH_BIT
= 0x2,
416 BRW_WM_IZ_DEPTH_WRITE_ENABLE_BIT
= 0x4,
417 BRW_WM_IZ_DEPTH_TEST_ENABLE_BIT
= 0x8,
418 BRW_WM_IZ_STENCIL_WRITE_ENABLE_BIT
= 0x10,
419 BRW_WM_IZ_STENCIL_TEST_ENABLE_BIT
= 0x20,
420 BRW_WM_IZ_BIT_MAX
= 0x40
423 enum brw_wm_aa_enable
{
429 /** The program key for Fragment/Pixel Shaders. */
430 struct brw_wm_prog_key
{
431 struct brw_base_prog_key base
;
433 /* Some collection of BRW_WM_IZ_* */
437 unsigned nr_color_regions
:5;
438 bool alpha_test_replicate_alpha
:1;
439 bool alpha_to_coverage
:1;
440 bool clamp_fragment_color
:1;
441 bool persample_interp
:1;
442 bool multisample_fbo
:1;
443 bool frag_coord_adds_sample_pos
:1;
444 enum brw_wm_aa_enable line_aa
:2;
445 bool high_quality_derivatives
:1;
446 bool force_dual_color_blend
:1;
447 bool coherent_fb_fetch
:1;
449 uint8_t color_outputs_valid
;
450 uint64_t input_slots_valid
;
451 GLenum alpha_test_func
; /* < For Gen4/5 MRT alpha test */
452 float alpha_test_ref
;
455 struct brw_cs_prog_key
{
456 struct brw_base_prog_key base
;
459 /* brw_any_prog_key is any of the keys that map to an API stage */
460 union brw_any_prog_key
{
461 struct brw_base_prog_key base
;
462 struct brw_vs_prog_key vs
;
463 struct brw_tcs_prog_key tcs
;
464 struct brw_tes_prog_key tes
;
465 struct brw_gs_prog_key gs
;
466 struct brw_wm_prog_key wm
;
467 struct brw_cs_prog_key cs
;
471 * Image metadata structure as laid out in the shader parameter
472 * buffer. Entries have to be 16B-aligned for the vec4 back-end to be
473 * able to use them. That's okay because the padding and any unused
474 * entries [most of them except when we're doing untyped surface
475 * access] will be removed by the uniform packing pass.
477 #define BRW_IMAGE_PARAM_OFFSET_OFFSET 0
478 #define BRW_IMAGE_PARAM_SIZE_OFFSET 4
479 #define BRW_IMAGE_PARAM_STRIDE_OFFSET 8
480 #define BRW_IMAGE_PARAM_TILING_OFFSET 12
481 #define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 16
482 #define BRW_IMAGE_PARAM_SIZE 20
484 struct brw_image_param
{
485 /** Offset applied to the X and Y surface coordinates. */
488 /** Surface X, Y and Z dimensions. */
491 /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
492 * pixels, vertical slice stride in pixels.
496 /** Log2 of the tiling modulus in the X, Y and Z dimension. */
500 * Right shift to apply for bit 6 address swizzling. Two different
501 * swizzles can be specified and will be applied one after the other. The
502 * resulting address will be:
504 * addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
505 * (addr >> swizzling[1])))
507 * Use \c 0xff if any of the swizzles is not required.
509 uint32_t swizzling
[2];
512 /** Max number of render targets in a shader */
513 #define BRW_MAX_DRAW_BUFFERS 8
516 * Max number of binding table entries used for stream output.
518 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
519 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
521 * On Gen6, the size of transform feedback data is limited not by the number
522 * of components but by the number of binding table entries we set aside. We
523 * use one binding table entry for a float, one entry for a vector, and one
524 * entry per matrix column. Since the only way we can communicate our
525 * transform feedback capabilities to the client is via
526 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
527 * worst case, in which all the varyings are floats, so we use up one binding
528 * table entry per component. Therefore we need to set aside at least 64
529 * binding table entries for use by transform feedback.
531 * Note: since we don't currently pack varyings, it is currently impossible
532 * for the client to actually use up all of these binding table entries--if
533 * all of their varyings were floats, they would run out of varying slots and
534 * fail to link. But that's a bug, so it seems prudent to go ahead and
535 * allocate the number of binding table entries we will need once the bug is
538 #define BRW_MAX_SOL_BINDINGS 64
541 * Binding table index for the first gen6 SOL binding.
543 #define BRW_GEN6_SOL_BINDING_START 0
546 * Stride in bytes between shader_time entries.
548 * We separate entries by a cacheline to reduce traffic between EUs writing to
551 #define BRW_SHADER_TIME_STRIDE 64
560 /* We reserve the first 2^16 values for builtins */
561 #define BRW_PARAM_IS_BUILTIN(param) (((param) & 0xffff0000) == 0)
563 enum brw_param_builtin
{
564 BRW_PARAM_BUILTIN_ZERO
,
566 BRW_PARAM_BUILTIN_CLIP_PLANE_0_X
,
567 BRW_PARAM_BUILTIN_CLIP_PLANE_0_Y
,
568 BRW_PARAM_BUILTIN_CLIP_PLANE_0_Z
,
569 BRW_PARAM_BUILTIN_CLIP_PLANE_0_W
,
570 BRW_PARAM_BUILTIN_CLIP_PLANE_1_X
,
571 BRW_PARAM_BUILTIN_CLIP_PLANE_1_Y
,
572 BRW_PARAM_BUILTIN_CLIP_PLANE_1_Z
,
573 BRW_PARAM_BUILTIN_CLIP_PLANE_1_W
,
574 BRW_PARAM_BUILTIN_CLIP_PLANE_2_X
,
575 BRW_PARAM_BUILTIN_CLIP_PLANE_2_Y
,
576 BRW_PARAM_BUILTIN_CLIP_PLANE_2_Z
,
577 BRW_PARAM_BUILTIN_CLIP_PLANE_2_W
,
578 BRW_PARAM_BUILTIN_CLIP_PLANE_3_X
,
579 BRW_PARAM_BUILTIN_CLIP_PLANE_3_Y
,
580 BRW_PARAM_BUILTIN_CLIP_PLANE_3_Z
,
581 BRW_PARAM_BUILTIN_CLIP_PLANE_3_W
,
582 BRW_PARAM_BUILTIN_CLIP_PLANE_4_X
,
583 BRW_PARAM_BUILTIN_CLIP_PLANE_4_Y
,
584 BRW_PARAM_BUILTIN_CLIP_PLANE_4_Z
,
585 BRW_PARAM_BUILTIN_CLIP_PLANE_4_W
,
586 BRW_PARAM_BUILTIN_CLIP_PLANE_5_X
,
587 BRW_PARAM_BUILTIN_CLIP_PLANE_5_Y
,
588 BRW_PARAM_BUILTIN_CLIP_PLANE_5_Z
,
589 BRW_PARAM_BUILTIN_CLIP_PLANE_5_W
,
590 BRW_PARAM_BUILTIN_CLIP_PLANE_6_X
,
591 BRW_PARAM_BUILTIN_CLIP_PLANE_6_Y
,
592 BRW_PARAM_BUILTIN_CLIP_PLANE_6_Z
,
593 BRW_PARAM_BUILTIN_CLIP_PLANE_6_W
,
594 BRW_PARAM_BUILTIN_CLIP_PLANE_7_X
,
595 BRW_PARAM_BUILTIN_CLIP_PLANE_7_Y
,
596 BRW_PARAM_BUILTIN_CLIP_PLANE_7_Z
,
597 BRW_PARAM_BUILTIN_CLIP_PLANE_7_W
,
599 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
,
600 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Y
,
601 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Z
,
602 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_W
,
603 BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
,
604 BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y
,
606 BRW_PARAM_BUILTIN_PATCH_VERTICES_IN
,
608 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_X
,
609 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Y
,
610 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Z
,
611 BRW_PARAM_BUILTIN_SUBGROUP_ID
,
614 #define BRW_PARAM_BUILTIN_CLIP_PLANE(idx, comp) \
615 (BRW_PARAM_BUILTIN_CLIP_PLANE_0_X + ((idx) << 2) + (comp))
617 #define BRW_PARAM_BUILTIN_IS_CLIP_PLANE(param) \
618 ((param) >= BRW_PARAM_BUILTIN_CLIP_PLANE_0_X && \
619 (param) <= BRW_PARAM_BUILTIN_CLIP_PLANE_7_W)
621 #define BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(param) \
622 (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) >> 2)
624 #define BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(param) \
625 (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) & 0x3)
627 struct brw_stage_prog_data
{
629 /** size of our binding table. */
633 * surface indices for the various groups of surfaces
635 uint32_t pull_constants_start
;
636 uint32_t texture_start
;
637 uint32_t gather_texture_start
;
640 uint32_t image_start
;
641 uint32_t shader_time_start
;
642 uint32_t plane_start
[3];
646 struct brw_ubo_range ubo_ranges
[4];
648 GLuint nr_params
; /**< number of float params/constants */
649 GLuint nr_pull_params
;
651 unsigned curb_read_length
;
652 unsigned total_scratch
;
653 unsigned total_shared
;
655 unsigned program_size
;
657 /** Does this program pull from any UBO or other constant buffers? */
661 * Register where the thread expects to find input data from the URB
662 * (typically uniforms, followed by vertex or fragment attributes).
664 unsigned dispatch_grf_start_reg
;
666 bool use_alt_mode
; /**< Use ALT floating point mode? Otherwise, IEEE. */
668 /* 32-bit identifiers for all push/pull parameters. These can be anything
669 * the driver wishes them to be; the core of the back-end compiler simply
670 * re-arranges them. The one restriction is that the bottom 2^16 values
671 * are reserved for builtins defined in the brw_param_builtin enum defined
675 uint32_t *pull_param
;
678 static inline uint32_t *
679 brw_stage_prog_data_add_params(struct brw_stage_prog_data
*prog_data
,
680 unsigned nr_new_params
)
682 unsigned old_nr_params
= prog_data
->nr_params
;
683 prog_data
->nr_params
+= nr_new_params
;
684 prog_data
->param
= reralloc(ralloc_parent(prog_data
->param
),
685 prog_data
->param
, uint32_t,
686 prog_data
->nr_params
);
687 return prog_data
->param
+ old_nr_params
;
690 enum brw_barycentric_mode
{
691 BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
= 0,
692 BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
= 1,
693 BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
= 2,
694 BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL
= 3,
695 BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
= 4,
696 BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE
= 5,
697 BRW_BARYCENTRIC_MODE_COUNT
= 6
699 #define BRW_BARYCENTRIC_NONPERSPECTIVE_BITS \
700 ((1 << BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL) | \
701 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID) | \
702 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE))
704 enum brw_pixel_shader_computed_depth_mode
{
705 BRW_PSCDEPTH_OFF
= 0, /* PS does not compute depth */
706 BRW_PSCDEPTH_ON
= 1, /* PS computes depth; no guarantee about value */
707 BRW_PSCDEPTH_ON_GE
= 2, /* PS guarantees output depth >= source depth */
708 BRW_PSCDEPTH_ON_LE
= 3, /* PS guarantees output depth <= source depth */
711 /* Data about a particular attempt to compile a program. Note that
712 * there can be many of these, each in a different GL state
713 * corresponding to a different brw_wm_prog_key struct, with different
716 struct brw_wm_prog_data
{
717 struct brw_stage_prog_data base
;
719 GLuint num_varying_inputs
;
721 uint8_t reg_blocks_8
;
722 uint8_t reg_blocks_16
;
723 uint8_t reg_blocks_32
;
725 uint8_t dispatch_grf_start_reg_16
;
726 uint8_t dispatch_grf_start_reg_32
;
727 uint32_t prog_offset_16
;
728 uint32_t prog_offset_32
;
732 * surface indices the WM-specific surfaces
734 uint32_t render_target_read_start
;
738 uint8_t computed_depth_mode
;
739 bool computed_stencil
;
741 bool early_fragment_tests
;
742 bool post_depth_coverage
;
748 bool replicate_alpha
;
749 bool persample_dispatch
;
750 bool uses_pos_offset
;
755 bool uses_sample_mask
;
756 bool has_render_target_reads
;
757 bool has_side_effects
;
760 bool contains_flat_varying
;
761 bool contains_noperspective_varying
;
764 * Mask of which interpolation modes are required by the fragment shader.
765 * Used in hardware setup on gen6+.
767 uint32_t barycentric_interp_modes
;
770 * Mask of which FS inputs are marked flat by the shader source. This is
771 * needed for setting up 3DSTATE_SF/SBE.
773 uint32_t flat_inputs
;
775 /* Mapping of VUE slots to interpolation modes.
776 * Used by the Gen4-5 clip/sf/wm stages.
778 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
781 * Map from gl_varying_slot to the position within the FS setup data
782 * payload where the varying's attribute vertex deltas should be delivered.
783 * For varying slots that are not used by the FS, the value is -1.
785 int urb_setup
[VARYING_SLOT_MAX
];
788 /** Returns the SIMD width corresponding to a given KSP index
790 * The "Variable Pixel Dispatch" table in the PRM (which can be found, for
791 * example in Vol. 7 of the SKL PRM) has a mapping from dispatch widths to
792 * kernel start pointer (KSP) indices that is based on what dispatch widths
793 * are enabled. This function provides, effectively, the reverse mapping.
795 * If the given KSP is valid with respect to the SIMD8/16/32 enables, a SIMD
796 * width of 8, 16, or 32 is returned. If the KSP is invalid, 0 is returned.
798 static inline unsigned
799 brw_fs_simd_width_for_ksp(unsigned ksp_idx
, bool simd8_enabled
,
800 bool simd16_enabled
, bool simd32_enabled
)
802 /* This function strictly ignores contiguous dispatch */
805 return simd8_enabled
? 8 :
806 (simd16_enabled
&& !simd32_enabled
) ? 16 :
807 (simd32_enabled
&& !simd16_enabled
) ? 32 : 0;
809 return (simd32_enabled
&& (simd16_enabled
|| simd8_enabled
)) ? 32 : 0;
811 return (simd16_enabled
&& (simd32_enabled
|| simd8_enabled
)) ? 16 : 0;
813 unreachable("Invalid KSP index");
817 #define brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx) \
818 brw_fs_simd_width_for_ksp((ksp_idx), (wm_state)._8PixelDispatchEnable, \
819 (wm_state)._16PixelDispatchEnable, \
820 (wm_state)._32PixelDispatchEnable)
822 #define brw_wm_state_has_ksp(wm_state, ksp_idx) \
823 (brw_wm_state_simd_width_for_ksp((wm_state), (ksp_idx)) != 0)
825 static inline uint32_t
826 _brw_wm_prog_data_prog_offset(const struct brw_wm_prog_data
*prog_data
,
829 switch (simd_width
) {
831 case 16: return prog_data
->prog_offset_16
;
832 case 32: return prog_data
->prog_offset_32
;
837 #define brw_wm_prog_data_prog_offset(prog_data, wm_state, ksp_idx) \
838 _brw_wm_prog_data_prog_offset(prog_data, \
839 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
841 static inline uint8_t
842 _brw_wm_prog_data_dispatch_grf_start_reg(const struct brw_wm_prog_data
*prog_data
,
845 switch (simd_width
) {
846 case 8: return prog_data
->base
.dispatch_grf_start_reg
;
847 case 16: return prog_data
->dispatch_grf_start_reg_16
;
848 case 32: return prog_data
->dispatch_grf_start_reg_32
;
853 #define brw_wm_prog_data_dispatch_grf_start_reg(prog_data, wm_state, ksp_idx) \
854 _brw_wm_prog_data_dispatch_grf_start_reg(prog_data, \
855 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
857 static inline uint8_t
858 _brw_wm_prog_data_reg_blocks(const struct brw_wm_prog_data
*prog_data
,
861 switch (simd_width
) {
862 case 8: return prog_data
->reg_blocks_8
;
863 case 16: return prog_data
->reg_blocks_16
;
864 case 32: return prog_data
->reg_blocks_32
;
869 #define brw_wm_prog_data_reg_blocks(prog_data, wm_state, ksp_idx) \
870 _brw_wm_prog_data_reg_blocks(prog_data, \
871 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
873 struct brw_push_const_block
{
874 unsigned dwords
; /* Dword count, not reg aligned */
876 unsigned size
; /* Bytes, register aligned */
879 struct brw_cs_prog_data
{
880 struct brw_stage_prog_data base
;
882 unsigned local_size
[3];
887 bool uses_num_work_groups
;
890 struct brw_push_const_block cross_thread
;
891 struct brw_push_const_block per_thread
;
892 struct brw_push_const_block total
;
897 * surface indices the CS-specific surfaces
899 uint32_t work_groups_start
;
905 * Enum representing the i965-specific vertex results that don't correspond
906 * exactly to any element of gl_varying_slot. The values of this enum are
907 * assigned such that they don't conflict with gl_varying_slot.
911 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
912 BRW_VARYING_SLOT_PAD
,
914 * Technically this is not a varying but just a placeholder that
915 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
916 * builtin variable to be compiled correctly. see compile_sf_prog() for
919 BRW_VARYING_SLOT_PNTC
,
920 BRW_VARYING_SLOT_COUNT
924 * We always program SF to start reading at an offset of 1 (2 varying slots)
925 * from the start of the vertex URB entry. This causes it to skip:
926 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
927 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
929 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
932 * Bitmask indicating which fragment shader inputs represent varyings (and
933 * hence have to be delivered to the fragment shader by the SF/SBE stage).
935 #define BRW_FS_VARYING_INPUT_MASK \
936 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
937 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
940 * Data structure recording the relationship between the gl_varying_slot enum
941 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
942 * single octaword within the VUE (128 bits).
944 * Note that each BRW register contains 256 bits (2 octawords), so when
945 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
946 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
947 * in a vertex shader), each register corresponds to a single VUE slot, since
948 * it contains data for two separate vertices.
952 * Bitfield representing all varying slots that are (a) stored in this VUE
953 * map, and (b) actually written by the shader. Does not include any of
954 * the additional varying slots defined in brw_varying_slot.
956 uint64_t slots_valid
;
959 * Is this VUE map for a separate shader pipeline?
961 * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched
962 * without the linker having a chance to dead code eliminate unused varyings.
964 * This means that we have to use a fixed slot layout, based on the output's
965 * location field, rather than assigning slots in a compact contiguous block.
970 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
971 * not stored in a slot (because they are not written, or because
972 * additional processing is applied before storing them in the VUE), the
975 signed char varying_to_slot
[VARYING_SLOT_TESS_MAX
];
978 * Map from VUE slot to gl_varying_slot value. For slots that do not
979 * directly correspond to a gl_varying_slot, the value comes from
982 * For slots that are not in use, the value is BRW_VARYING_SLOT_PAD.
984 signed char slot_to_varying
[VARYING_SLOT_TESS_MAX
];
987 * Total number of VUE slots in use
992 * Number of per-patch VUE slots. Only valid for tessellation control
993 * shader outputs and tessellation evaluation shader inputs.
995 int num_per_patch_slots
;
998 * Number of per-vertex VUE slots. Only valid for tessellation control
999 * shader outputs and tessellation evaluation shader inputs.
1001 int num_per_vertex_slots
;
1004 void brw_print_vue_map(FILE *fp
, const struct brw_vue_map
*vue_map
);
1007 * Convert a VUE slot number into a byte offset within the VUE.
1009 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
1015 * Convert a vertex output (brw_varying_slot) into a byte offset within the
1019 GLuint
brw_varying_to_offset(const struct brw_vue_map
*vue_map
, GLuint varying
)
1021 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
1024 void brw_compute_vue_map(const struct gen_device_info
*devinfo
,
1025 struct brw_vue_map
*vue_map
,
1026 uint64_t slots_valid
,
1027 bool separate_shader
);
1029 void brw_compute_tess_vue_map(struct brw_vue_map
*const vue_map
,
1030 uint64_t slots_valid
,
1033 /* brw_interpolation_map.c */
1034 void brw_setup_vue_interpolation(struct brw_vue_map
*vue_map
,
1035 struct nir_shader
*nir
,
1036 struct brw_wm_prog_data
*prog_data
);
1038 enum shader_dispatch_mode
{
1039 DISPATCH_MODE_4X1_SINGLE
= 0,
1040 DISPATCH_MODE_4X2_DUAL_INSTANCE
= 1,
1041 DISPATCH_MODE_4X2_DUAL_OBJECT
= 2,
1042 DISPATCH_MODE_SIMD8
= 3,
1044 DISPATCH_MODE_TCS_SINGLE_PATCH
= 0,
1045 DISPATCH_MODE_TCS_8_PATCH
= 2,
1049 * @defgroup Tessellator parameter enumerations.
1051 * These correspond to the hardware values in 3DSTATE_TE, and are provided
1052 * as part of the tessellation evaluation shader.
1056 enum brw_tess_partitioning
{
1057 BRW_TESS_PARTITIONING_INTEGER
= 0,
1058 BRW_TESS_PARTITIONING_ODD_FRACTIONAL
= 1,
1059 BRW_TESS_PARTITIONING_EVEN_FRACTIONAL
= 2,
1062 enum brw_tess_output_topology
{
1063 BRW_TESS_OUTPUT_TOPOLOGY_POINT
= 0,
1064 BRW_TESS_OUTPUT_TOPOLOGY_LINE
= 1,
1065 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
= 2,
1066 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW
= 3,
1069 enum brw_tess_domain
{
1070 BRW_TESS_DOMAIN_QUAD
= 0,
1071 BRW_TESS_DOMAIN_TRI
= 1,
1072 BRW_TESS_DOMAIN_ISOLINE
= 2,
1076 struct brw_vue_prog_data
{
1077 struct brw_stage_prog_data base
;
1078 struct brw_vue_map vue_map
;
1080 /** Should the hardware deliver input VUE handles for URB pull loads? */
1081 bool include_vue_handles
;
1083 GLuint urb_read_length
;
1086 uint32_t clip_distance_mask
;
1087 uint32_t cull_distance_mask
;
1089 /* Used for calculating urb partitions. In the VS, this is the size of the
1090 * URB entry used for both input and output to the thread. In the GS, this
1091 * is the size of the URB entry used for output.
1093 GLuint urb_entry_size
;
1095 enum shader_dispatch_mode dispatch_mode
;
1098 struct brw_vs_prog_data
{
1099 struct brw_vue_prog_data base
;
1101 GLbitfield64 inputs_read
;
1102 GLbitfield64 double_inputs_read
;
1104 unsigned nr_attribute_slots
;
1107 bool uses_instanceid
;
1108 bool uses_is_indexed_draw
;
1109 bool uses_firstvertex
;
1110 bool uses_baseinstance
;
1114 struct brw_tcs_prog_data
1116 struct brw_vue_prog_data base
;
1118 /** Should the non-SINGLE_PATCH payload provide primitive ID? */
1119 bool include_primitive_id
;
1121 /** Number vertices in output patch */
1126 struct brw_tes_prog_data
1128 struct brw_vue_prog_data base
;
1130 enum brw_tess_partitioning partitioning
;
1131 enum brw_tess_output_topology output_topology
;
1132 enum brw_tess_domain domain
;
1135 struct brw_gs_prog_data
1137 struct brw_vue_prog_data base
;
1139 unsigned vertices_in
;
1142 * Size of an output vertex, measured in HWORDS (32 bytes).
1144 unsigned output_vertex_size_hwords
;
1146 unsigned output_topology
;
1149 * Size of the control data (cut bits or StreamID bits), in hwords (32
1150 * bytes). 0 if there is no control data.
1152 unsigned control_data_header_size_hwords
;
1155 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
1156 * if the control data is StreamID bits, or
1157 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
1158 * Ignored if control_data_header_size is 0.
1160 unsigned control_data_format
;
1162 bool include_primitive_id
;
1165 * The number of vertices emitted, if constant - otherwise -1.
1167 int static_vertex_count
;
1172 * Gen6: Provoking vertex convention for odd-numbered triangles
1178 * Gen6: Number of varyings that are output to transform feedback.
1180 GLuint num_transform_feedback_bindings
:7; /* 0-BRW_MAX_SOL_BINDINGS */
1183 * Gen6: Map from the index of a transform feedback binding table entry to the
1184 * gl_varying_slot that should be streamed out through that binding table
1187 unsigned char transform_feedback_bindings
[64 /* BRW_MAX_SOL_BINDINGS */];
1190 * Gen6: Map from the index of a transform feedback binding table entry to the
1191 * swizzles that should be used when streaming out data through that
1192 * binding table entry.
1194 unsigned char transform_feedback_swizzles
[64 /* BRW_MAX_SOL_BINDINGS */];
1197 struct brw_sf_prog_data
{
1198 uint32_t urb_read_length
;
1201 /* Each vertex may have upto 12 attributes, 4 components each,
1202 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
1205 * Actually we use 4 for each, so call it 12 rows.
1207 unsigned urb_entry_size
;
1210 struct brw_clip_prog_data
{
1211 uint32_t curb_read_length
; /* user planes? */
1213 uint32_t urb_read_length
;
1217 /* brw_any_prog_data is prog_data for any stage that maps to an API stage */
1218 union brw_any_prog_data
{
1219 struct brw_stage_prog_data base
;
1220 struct brw_vue_prog_data vue
;
1221 struct brw_vs_prog_data vs
;
1222 struct brw_tcs_prog_data tcs
;
1223 struct brw_tes_prog_data tes
;
1224 struct brw_gs_prog_data gs
;
1225 struct brw_wm_prog_data wm
;
1226 struct brw_cs_prog_data cs
;
1229 #define DEFINE_PROG_DATA_DOWNCAST(stage) \
1230 static inline struct brw_##stage##_prog_data * \
1231 brw_##stage##_prog_data(struct brw_stage_prog_data *prog_data) \
1233 return (struct brw_##stage##_prog_data *) prog_data; \
1235 DEFINE_PROG_DATA_DOWNCAST(vue
)
1236 DEFINE_PROG_DATA_DOWNCAST(vs
)
1237 DEFINE_PROG_DATA_DOWNCAST(tcs
)
1238 DEFINE_PROG_DATA_DOWNCAST(tes
)
1239 DEFINE_PROG_DATA_DOWNCAST(gs
)
1240 DEFINE_PROG_DATA_DOWNCAST(wm
)
1241 DEFINE_PROG_DATA_DOWNCAST(cs
)
1242 DEFINE_PROG_DATA_DOWNCAST(ff_gs
)
1243 DEFINE_PROG_DATA_DOWNCAST(clip
)
1244 DEFINE_PROG_DATA_DOWNCAST(sf
)
1245 #undef DEFINE_PROG_DATA_DOWNCAST
1247 struct brw_compile_stats
{
1248 uint32_t dispatch_width
; /**< 0 for vec4 */
1249 uint32_t instructions
;
1258 struct brw_compiler
*
1259 brw_compiler_create(void *mem_ctx
, const struct gen_device_info
*devinfo
);
1262 * Returns a compiler configuration for use with disk shader cache
1264 * This value only needs to change for settings that can cause different
1265 * program generation between two runs on the same hardware.
1267 * For example, it doesn't need to be different for gen 8 and gen 9 hardware,
1268 * but it does need to be different if INTEL_DEBUG=nocompact is or isn't used.
1271 brw_get_compiler_config_value(const struct brw_compiler
*compiler
);
1274 brw_prog_data_size(gl_shader_stage stage
);
1277 brw_prog_key_size(gl_shader_stage stage
);
1280 brw_prog_key_set_id(union brw_any_prog_key
*key
, gl_shader_stage
, unsigned id
);
1283 * Compile a vertex shader.
1285 * Returns the final assembly and the program's size.
1288 brw_compile_vs(const struct brw_compiler
*compiler
, void *log_data
,
1290 const struct brw_vs_prog_key
*key
,
1291 struct brw_vs_prog_data
*prog_data
,
1292 struct nir_shader
*shader
,
1293 int shader_time_index
,
1294 struct brw_compile_stats
*stats
,
1298 * Compile a tessellation control shader.
1300 * Returns the final assembly and the program's size.
1303 brw_compile_tcs(const struct brw_compiler
*compiler
,
1306 const struct brw_tcs_prog_key
*key
,
1307 struct brw_tcs_prog_data
*prog_data
,
1308 struct nir_shader
*nir
,
1309 int shader_time_index
,
1310 struct brw_compile_stats
*stats
,
1314 * Compile a tessellation evaluation shader.
1316 * Returns the final assembly and the program's size.
1319 brw_compile_tes(const struct brw_compiler
*compiler
, void *log_data
,
1321 const struct brw_tes_prog_key
*key
,
1322 const struct brw_vue_map
*input_vue_map
,
1323 struct brw_tes_prog_data
*prog_data
,
1324 struct nir_shader
*shader
,
1325 int shader_time_index
,
1326 struct brw_compile_stats
*stats
,
1330 * Compile a vertex shader.
1332 * Returns the final assembly and the program's size.
1335 brw_compile_gs(const struct brw_compiler
*compiler
, void *log_data
,
1337 const struct brw_gs_prog_key
*key
,
1338 struct brw_gs_prog_data
*prog_data
,
1339 struct nir_shader
*shader
,
1340 struct gl_program
*prog
,
1341 int shader_time_index
,
1342 struct brw_compile_stats
*stats
,
1346 * Compile a strips and fans shader.
1348 * This is a fixed-function shader determined entirely by the shader key and
1351 * Returns the final assembly and the program's size.
1354 brw_compile_sf(const struct brw_compiler
*compiler
,
1356 const struct brw_sf_prog_key
*key
,
1357 struct brw_sf_prog_data
*prog_data
,
1358 struct brw_vue_map
*vue_map
,
1359 unsigned *final_assembly_size
);
1362 * Compile a clipper shader.
1364 * This is a fixed-function shader determined entirely by the shader key and
1367 * Returns the final assembly and the program's size.
1370 brw_compile_clip(const struct brw_compiler
*compiler
,
1372 const struct brw_clip_prog_key
*key
,
1373 struct brw_clip_prog_data
*prog_data
,
1374 struct brw_vue_map
*vue_map
,
1375 unsigned *final_assembly_size
);
1378 * Compile a fragment shader.
1380 * Returns the final assembly and the program's size.
1383 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
1385 const struct brw_wm_prog_key
*key
,
1386 struct brw_wm_prog_data
*prog_data
,
1387 struct nir_shader
*shader
,
1388 int shader_time_index8
,
1389 int shader_time_index16
,
1390 int shader_time_index32
,
1391 bool allow_spilling
,
1392 bool use_rep_send
, struct brw_vue_map
*vue_map
,
1393 struct brw_compile_stats
*stats
, /**< Array of three stats */
1397 * Compile a compute shader.
1399 * Returns the final assembly and the program's size.
1402 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
1404 const struct brw_cs_prog_key
*key
,
1405 struct brw_cs_prog_data
*prog_data
,
1406 const struct nir_shader
*shader
,
1407 int shader_time_index
,
1408 struct brw_compile_stats
*stats
,
1411 void brw_debug_key_recompile(const struct brw_compiler
*c
, void *log
,
1412 gl_shader_stage stage
,
1413 const struct brw_base_prog_key
*old_key
,
1414 const struct brw_base_prog_key
*key
);
1416 static inline uint32_t
1417 encode_slm_size(unsigned gen
, uint32_t bytes
)
1419 uint32_t slm_size
= 0;
1421 /* Shared Local Memory is specified as powers of two, and encoded in
1422 * INTERFACE_DESCRIPTOR_DATA with the following representations:
1424 * Size | 0 kB | 1 kB | 2 kB | 4 kB | 8 kB | 16 kB | 32 kB | 64 kB |
1425 * -------------------------------------------------------------------
1426 * Gen7-8 | 0 | none | none | 1 | 2 | 4 | 8 | 16 |
1427 * -------------------------------------------------------------------
1428 * Gen9+ | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
1430 assert(bytes
<= 64 * 1024);
1433 /* Shared Local Memory Size is specified as powers of two. */
1434 slm_size
= util_next_power_of_two(bytes
);
1437 /* Use a minimum of 1kB; turn an exponent of 10 (1024 kB) into 1. */
1438 slm_size
= ffs(MAX2(slm_size
, 1024)) - 10;
1440 /* Use a minimum of 4kB; convert to the pre-Gen9 representation. */
1441 slm_size
= MAX2(slm_size
, 4096) / 4096;
1449 * Return true if the given shader stage is dispatched contiguously by the
1450 * relevant fixed function starting from channel 0 of the SIMD thread, which
1451 * implies that the dispatch mask of a thread can be assumed to have the form
1452 * '2^n - 1' for some n.
1455 brw_stage_has_packed_dispatch(ASSERTED
const struct gen_device_info
*devinfo
,
1456 gl_shader_stage stage
,
1457 const struct brw_stage_prog_data
*prog_data
)
1459 /* The code below makes assumptions about the hardware's thread dispatch
1460 * behavior that could be proven wrong in future generations -- Make sure
1461 * to do a full test run with brw_fs_test_dispatch_packing() hooked up to
1462 * the NIR front-end before changing this assertion.
1464 assert(devinfo
->gen
<= 11);
1467 case MESA_SHADER_FRAGMENT
: {
1468 /* The PSD discards subspans coming in with no lit samples, which in the
1469 * per-pixel shading case implies that each subspan will either be fully
1470 * lit (due to the VMask being used to allow derivative computations),
1471 * or not dispatched at all. In per-sample dispatch mode individual
1472 * samples from the same subspan have a fixed relative location within
1473 * the SIMD thread, so dispatch of unlit samples cannot be avoided in
1474 * general and we should return false.
1476 const struct brw_wm_prog_data
*wm_prog_data
=
1477 (const struct brw_wm_prog_data
*)prog_data
;
1478 return !wm_prog_data
->persample_dispatch
;
1480 case MESA_SHADER_COMPUTE
:
1481 /* Compute shaders will be spawned with either a fully enabled dispatch
1482 * mask or with whatever bottom/right execution mask was given to the
1483 * GPGPU walker command to be used along the workgroup edges -- In both
1484 * cases the dispatch mask is required to be tightly packed for our
1485 * invocation index calculations to work.
1489 /* Most remaining fixed functions are limited to use a packed dispatch
1490 * mask due to the hardware representation of the dispatch mask as a
1491 * single counter representing the number of enabled channels.
1498 * Computes the first varying slot in the URB produced by the previous stage
1499 * that is used in the next stage. We do this by testing the varying slots in
1500 * the previous stage's vue map against the inputs read in the next stage.
1504 * - Each URB offset contains two varying slots and we can only skip a
1505 * full offset if both slots are unused, so the value we return here is always
1506 * rounded down to the closest multiple of two.
1508 * - gl_Layer and gl_ViewportIndex don't have their own varying slots, they are
1509 * part of the vue header, so if these are read we can't skip anything.
1512 brw_compute_first_urb_slot_required(uint64_t inputs_read
,
1513 const struct brw_vue_map
*prev_stage_vue_map
)
1515 if ((inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
)) == 0) {
1516 for (int i
= 0; i
< prev_stage_vue_map
->num_slots
; i
++) {
1517 int varying
= prev_stage_vue_map
->slot_to_varying
[i
];
1518 if (varying
> 0 && (inputs_read
& BITFIELD64_BIT(varying
)) != 0)
1519 return ROUND_DOWN_TO(i
, 2);
1530 #endif /* BRW_COMPILER_H */