2 * Copyright © 2010 - 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #ifndef BRW_COMPILER_H
25 #define BRW_COMPILER_H
28 #include "dev/gen_device_info.h"
29 #include "main/macros.h"
30 #include "main/mtypes.h"
31 #include "util/ralloc.h"
42 const struct gen_device_info
*devinfo
;
48 * Array of the ra classes for the unaligned contiguous register
54 * Mapping for register-allocated objects in *regs to the first
55 * GRF for that object.
57 uint8_t *ra_reg_to_grf
;
64 * Array of the ra classes for the unaligned contiguous register
65 * block sizes used, indexed by register size.
70 * Mapping from classes to ra_reg ranges. Each of the per-size
71 * classes corresponds to a range of ra_reg nodes. This array stores
72 * those ranges in the form of first ra_reg in each class and the
73 * total number of ra_reg elements in the last array element. This
74 * way the range of the i'th class is given by:
75 * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] )
77 int class_to_ra_reg_range
[17];
80 * Mapping for register-allocated objects in *regs to the first
81 * GRF for that object.
83 uint8_t *ra_reg_to_grf
;
86 * ra class for the aligned barycentrics we use for PLN, which doesn't
89 int aligned_bary_class
;
92 void (*shader_debug_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
93 void (*shader_perf_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
95 bool scalar_stage
[MESA_SHADER_STAGES
];
97 struct gl_shader_compiler_options glsl_compiler_options
[MESA_SHADER_STAGES
];
100 * Apply workarounds for SIN and COS output range problems.
101 * This can negatively impact performance.
106 * Is 3DSTATE_CONSTANT_*'s Constant Buffer 0 relative to Dynamic State
107 * Base Address? (If not, it's a normal GPU address.)
109 bool constant_buffer_0_is_relative
;
112 * Whether or not the driver supports pull constants. If not, the compiler
113 * will attempt to push everything.
115 bool supports_pull_constants
;
118 * Whether or not the driver supports NIR shader constants. This controls
119 * whether nir_opt_large_constants will be run.
121 bool supports_shader_constants
;
124 * Whether or not the driver wants uniform params to be compacted by the
131 * We use a constant subgroup size of 32. It really only needs to be a
132 * maximum and, since we do SIMD32 for compute shaders in some cases, it
133 * needs to be at least 32. SIMD8 and SIMD16 shaders will still claim a
134 * subgroup size of 32 but will act as if 16 or 24 of those channels are
137 #define BRW_SUBGROUP_SIZE 32
140 * Program key structures.
142 * When drawing, we look for the currently bound shaders in the program
143 * cache. This is essentially a hash table lookup, and these are the keys.
145 * Sometimes OpenGL features specified as state need to be simulated via
146 * shader code, due to a mismatch between the API and the hardware. This
147 * is often referred to as "non-orthagonal state" or "NOS". We store NOS
148 * in the program key so it's considered when searching for a program. If
149 * we haven't seen a particular combination before, we have to recompile a
150 * new specialized version.
152 * Shader compilation should not look up state in gl_context directly, but
153 * instead use the copy in the program key. This guarantees recompiles will
159 enum PACKED gen6_gather_sampler_wa
{
160 WA_SIGN
= 1, /* whether we need to sign extend */
161 WA_8BIT
= 2, /* if we have an 8bit format needing wa */
162 WA_16BIT
= 4, /* if we have a 16bit format needing wa */
166 * Sampler information needed by VS, WM, and GS program cache keys.
168 struct brw_sampler_prog_key_data
{
170 * EXT_texture_swizzle and DEPTH_TEXTURE_MODE swizzles.
172 uint16_t swizzles
[MAX_SAMPLERS
];
174 uint32_t gl_clamp_mask
[3];
177 * For RG32F, gather4's channel select is broken.
179 uint32_t gather_channel_quirk_mask
;
182 * Whether this sampler uses the compressed multisample surface layout.
184 uint32_t compressed_multisample_layout_mask
;
187 * Whether this sampler is using 16x multisampling. If so fetching from
188 * this sampler will be handled with a different instruction, ld2dms_w
194 * For Sandybridge, which shader w/a we need for gather quirks.
196 enum gen6_gather_sampler_wa gen6_gather_wa
[MAX_SAMPLERS
];
199 * Texture units that have a YUV image bound.
201 uint32_t y_u_v_image_mask
;
202 uint32_t y_uv_image_mask
;
203 uint32_t yx_xuxv_image_mask
;
204 uint32_t xy_uxvx_image_mask
;
205 uint32_t ayuv_image_mask
;
206 uint32_t xyuv_image_mask
;
208 /* Scale factor for each texture. */
209 float scale_factors
[32];
212 /** An enum representing what kind of input gl_SubgroupSize is. */
213 enum PACKED brw_subgroup_size_type
215 BRW_SUBGROUP_SIZE_API_CONSTANT
, /**< Default Vulkan behavior */
216 BRW_SUBGROUP_SIZE_UNIFORM
, /**< OpenGL behavior */
217 BRW_SUBGROUP_SIZE_VARYING
, /**< VK_EXT_subgroup_size_control */
219 /* These enums are specifically chosen so that the value of the enum is
220 * also the subgroup size. If any new values are added, they must respect
223 BRW_SUBGROUP_SIZE_REQUIRE_8
= 8, /**< VK_EXT_subgroup_size_control */
224 BRW_SUBGROUP_SIZE_REQUIRE_16
= 16, /**< VK_EXT_subgroup_size_control */
225 BRW_SUBGROUP_SIZE_REQUIRE_32
= 32, /**< VK_EXT_subgroup_size_control */
228 struct brw_base_prog_key
{
229 unsigned program_string_id
;
231 enum brw_subgroup_size_type subgroup_size_type
;
233 struct brw_sampler_prog_key_data tex
;
237 * The VF can't natively handle certain types of attributes, such as GL_FIXED
238 * or most 10_10_10_2 types. These flags enable various VS workarounds to
239 * "fix" attributes at the beginning of shaders.
241 #define BRW_ATTRIB_WA_COMPONENT_MASK 7 /* mask for GL_FIXED scale channel count */
242 #define BRW_ATTRIB_WA_NORMALIZE 8 /* normalize in shader */
243 #define BRW_ATTRIB_WA_BGRA 16 /* swap r/b channels in shader */
244 #define BRW_ATTRIB_WA_SIGN 32 /* interpret as signed in shader */
245 #define BRW_ATTRIB_WA_SCALE 64 /* interpret as scaled in shader */
248 * OpenGL attribute slots fall in [0, VERT_ATTRIB_MAX - 1] with the range
249 * [VERT_ATTRIB_GENERIC0, VERT_ATTRIB_MAX - 1] reserved for up to 16 user
250 * input vertex attributes. In Vulkan, we expose up to 28 user vertex input
251 * attributes that are mapped to slots also starting at VERT_ATTRIB_GENERIC0.
253 #define MAX_GL_VERT_ATTRIB VERT_ATTRIB_MAX
254 #define MAX_VK_VERT_ATTRIB (VERT_ATTRIB_GENERIC0 + 28)
256 /** The program key for Vertex Shaders. */
257 struct brw_vs_prog_key
{
258 struct brw_base_prog_key base
;
261 * Per-attribute workaround flags
263 * For each attribute, a combination of BRW_ATTRIB_WA_*.
265 * For OpenGL, where we expose a maximum of 16 user input atttributes
266 * we only need up to VERT_ATTRIB_MAX slots, however, in Vulkan
267 * slots preceding VERT_ATTRIB_GENERIC0 are unused and we can
268 * expose up to 28 user input vertex attributes that are mapped to slots
269 * starting at VERT_ATTRIB_GENERIC0, so this array needs to be large
270 * enough to hold this many slots.
272 uint8_t gl_attrib_wa_flags
[MAX2(MAX_GL_VERT_ATTRIB
, MAX_VK_VERT_ATTRIB
)];
274 bool copy_edgeflag
:1;
276 bool clamp_vertex_color
:1;
279 * How many user clipping planes are being uploaded to the vertex shader as
282 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
285 unsigned nr_userclip_plane_consts
:4;
288 * For pre-Gen6 hardware, a bitfield indicating which texture coordinates
289 * are going to be replaced with point coordinates (as a consequence of a
290 * call to glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)). Because
291 * our SF thread requires exact matching between VS outputs and FS inputs,
292 * these texture coordinates will need to be unconditionally included in
293 * the VUE, even if they aren't written by the vertex shader.
295 uint8_t point_coord_replace
;
298 /** The program key for Tessellation Control Shaders. */
299 struct brw_tcs_prog_key
301 struct brw_base_prog_key base
;
303 GLenum tes_primitive_mode
;
305 unsigned input_vertices
;
307 /** A bitfield of per-patch outputs written. */
308 uint32_t patch_outputs_written
;
310 /** A bitfield of per-vertex outputs written. */
311 uint64_t outputs_written
;
313 bool quads_workaround
;
316 /** The program key for Tessellation Evaluation Shaders. */
317 struct brw_tes_prog_key
319 struct brw_base_prog_key base
;
321 /** A bitfield of per-patch inputs read. */
322 uint32_t patch_inputs_read
;
324 /** A bitfield of per-vertex inputs read. */
325 uint64_t inputs_read
;
328 * How many user clipping planes are being uploaded to the tessellation
329 * evaluation shader as push constants.
331 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
334 unsigned nr_userclip_plane_consts
:4;
337 /** The program key for Geometry Shaders. */
338 struct brw_gs_prog_key
340 struct brw_base_prog_key base
;
343 * How many user clipping planes are being uploaded to the geometry shader
346 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
349 unsigned nr_userclip_plane_consts
:4;
352 enum brw_sf_primitive
{
353 BRW_SF_PRIM_POINTS
= 0,
354 BRW_SF_PRIM_LINES
= 1,
355 BRW_SF_PRIM_TRIANGLES
= 2,
356 BRW_SF_PRIM_UNFILLED_TRIS
= 3,
359 struct brw_sf_prog_key
{
361 bool contains_flat_varying
;
362 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
363 uint8_t point_sprite_coord_replace
;
364 enum brw_sf_primitive primitive
:2;
365 bool do_twoside_color
:1;
366 bool frontface_ccw
:1;
367 bool do_point_sprite
:1;
368 bool do_point_coord
:1;
369 bool sprite_origin_lower_left
:1;
370 bool userclip_active
:1;
374 BRW_CLIP_MODE_NORMAL
= 0,
375 BRW_CLIP_MODE_CLIP_ALL
= 1,
376 BRW_CLIP_MODE_CLIP_NON_REJECTED
= 2,
377 BRW_CLIP_MODE_REJECT_ALL
= 3,
378 BRW_CLIP_MODE_ACCEPT_ALL
= 4,
379 BRW_CLIP_MODE_KERNEL_CLIP
= 5,
382 enum brw_clip_fill_mode
{
383 BRW_CLIP_FILL_MODE_LINE
= 0,
384 BRW_CLIP_FILL_MODE_POINT
= 1,
385 BRW_CLIP_FILL_MODE_FILL
= 2,
386 BRW_CLIP_FILL_MODE_CULL
= 3,
389 /* Note that if unfilled primitives are being emitted, we have to fix
390 * up polygon offset and flatshading at this point:
392 struct brw_clip_prog_key
{
394 bool contains_flat_varying
;
395 bool contains_noperspective_varying
;
396 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
397 unsigned primitive
:4;
398 unsigned nr_userclip
:4;
401 enum brw_clip_fill_mode fill_cw
:2; /* includes cull information */
402 enum brw_clip_fill_mode fill_ccw
:2; /* includes cull information */
407 enum brw_clip_mode clip_mode
:3;
414 /* A big lookup table is used to figure out which and how many
415 * additional regs will inserted before the main payload in the WM
416 * program execution. These mainly relate to depth and stencil
417 * processing and the early-depth-test optimization.
419 enum brw_wm_iz_bits
{
420 BRW_WM_IZ_PS_KILL_ALPHATEST_BIT
= 0x1,
421 BRW_WM_IZ_PS_COMPUTES_DEPTH_BIT
= 0x2,
422 BRW_WM_IZ_DEPTH_WRITE_ENABLE_BIT
= 0x4,
423 BRW_WM_IZ_DEPTH_TEST_ENABLE_BIT
= 0x8,
424 BRW_WM_IZ_STENCIL_WRITE_ENABLE_BIT
= 0x10,
425 BRW_WM_IZ_STENCIL_TEST_ENABLE_BIT
= 0x20,
426 BRW_WM_IZ_BIT_MAX
= 0x40
429 enum brw_wm_aa_enable
{
435 /** The program key for Fragment/Pixel Shaders. */
436 struct brw_wm_prog_key
{
437 struct brw_base_prog_key base
;
439 /* Some collection of BRW_WM_IZ_* */
443 unsigned nr_color_regions
:5;
444 bool alpha_test_replicate_alpha
:1;
445 bool alpha_to_coverage
:1;
446 bool clamp_fragment_color
:1;
447 bool persample_interp
:1;
448 bool multisample_fbo
:1;
449 bool frag_coord_adds_sample_pos
:1;
450 enum brw_wm_aa_enable line_aa
:2;
451 bool high_quality_derivatives
:1;
452 bool force_dual_color_blend
:1;
453 bool coherent_fb_fetch
:1;
455 uint8_t color_outputs_valid
;
456 uint64_t input_slots_valid
;
457 GLenum alpha_test_func
; /* < For Gen4/5 MRT alpha test */
458 float alpha_test_ref
;
461 struct brw_cs_prog_key
{
462 struct brw_base_prog_key base
;
465 /* brw_any_prog_key is any of the keys that map to an API stage */
466 union brw_any_prog_key
{
467 struct brw_base_prog_key base
;
468 struct brw_vs_prog_key vs
;
469 struct brw_tcs_prog_key tcs
;
470 struct brw_tes_prog_key tes
;
471 struct brw_gs_prog_key gs
;
472 struct brw_wm_prog_key wm
;
473 struct brw_cs_prog_key cs
;
477 * Image metadata structure as laid out in the shader parameter
478 * buffer. Entries have to be 16B-aligned for the vec4 back-end to be
479 * able to use them. That's okay because the padding and any unused
480 * entries [most of them except when we're doing untyped surface
481 * access] will be removed by the uniform packing pass.
483 #define BRW_IMAGE_PARAM_OFFSET_OFFSET 0
484 #define BRW_IMAGE_PARAM_SIZE_OFFSET 4
485 #define BRW_IMAGE_PARAM_STRIDE_OFFSET 8
486 #define BRW_IMAGE_PARAM_TILING_OFFSET 12
487 #define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 16
488 #define BRW_IMAGE_PARAM_SIZE 20
490 struct brw_image_param
{
491 /** Offset applied to the X and Y surface coordinates. */
494 /** Surface X, Y and Z dimensions. */
497 /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
498 * pixels, vertical slice stride in pixels.
502 /** Log2 of the tiling modulus in the X, Y and Z dimension. */
506 * Right shift to apply for bit 6 address swizzling. Two different
507 * swizzles can be specified and will be applied one after the other. The
508 * resulting address will be:
510 * addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
511 * (addr >> swizzling[1])))
513 * Use \c 0xff if any of the swizzles is not required.
515 uint32_t swizzling
[2];
518 /** Max number of render targets in a shader */
519 #define BRW_MAX_DRAW_BUFFERS 8
522 * Max number of binding table entries used for stream output.
524 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
525 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
527 * On Gen6, the size of transform feedback data is limited not by the number
528 * of components but by the number of binding table entries we set aside. We
529 * use one binding table entry for a float, one entry for a vector, and one
530 * entry per matrix column. Since the only way we can communicate our
531 * transform feedback capabilities to the client is via
532 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
533 * worst case, in which all the varyings are floats, so we use up one binding
534 * table entry per component. Therefore we need to set aside at least 64
535 * binding table entries for use by transform feedback.
537 * Note: since we don't currently pack varyings, it is currently impossible
538 * for the client to actually use up all of these binding table entries--if
539 * all of their varyings were floats, they would run out of varying slots and
540 * fail to link. But that's a bug, so it seems prudent to go ahead and
541 * allocate the number of binding table entries we will need once the bug is
544 #define BRW_MAX_SOL_BINDINGS 64
547 * Binding table index for the first gen6 SOL binding.
549 #define BRW_GEN6_SOL_BINDING_START 0
552 * Stride in bytes between shader_time entries.
554 * We separate entries by a cacheline to reduce traffic between EUs writing to
557 #define BRW_SHADER_TIME_STRIDE 64
566 /* We reserve the first 2^16 values for builtins */
567 #define BRW_PARAM_IS_BUILTIN(param) (((param) & 0xffff0000) == 0)
569 enum brw_param_builtin
{
570 BRW_PARAM_BUILTIN_ZERO
,
572 BRW_PARAM_BUILTIN_CLIP_PLANE_0_X
,
573 BRW_PARAM_BUILTIN_CLIP_PLANE_0_Y
,
574 BRW_PARAM_BUILTIN_CLIP_PLANE_0_Z
,
575 BRW_PARAM_BUILTIN_CLIP_PLANE_0_W
,
576 BRW_PARAM_BUILTIN_CLIP_PLANE_1_X
,
577 BRW_PARAM_BUILTIN_CLIP_PLANE_1_Y
,
578 BRW_PARAM_BUILTIN_CLIP_PLANE_1_Z
,
579 BRW_PARAM_BUILTIN_CLIP_PLANE_1_W
,
580 BRW_PARAM_BUILTIN_CLIP_PLANE_2_X
,
581 BRW_PARAM_BUILTIN_CLIP_PLANE_2_Y
,
582 BRW_PARAM_BUILTIN_CLIP_PLANE_2_Z
,
583 BRW_PARAM_BUILTIN_CLIP_PLANE_2_W
,
584 BRW_PARAM_BUILTIN_CLIP_PLANE_3_X
,
585 BRW_PARAM_BUILTIN_CLIP_PLANE_3_Y
,
586 BRW_PARAM_BUILTIN_CLIP_PLANE_3_Z
,
587 BRW_PARAM_BUILTIN_CLIP_PLANE_3_W
,
588 BRW_PARAM_BUILTIN_CLIP_PLANE_4_X
,
589 BRW_PARAM_BUILTIN_CLIP_PLANE_4_Y
,
590 BRW_PARAM_BUILTIN_CLIP_PLANE_4_Z
,
591 BRW_PARAM_BUILTIN_CLIP_PLANE_4_W
,
592 BRW_PARAM_BUILTIN_CLIP_PLANE_5_X
,
593 BRW_PARAM_BUILTIN_CLIP_PLANE_5_Y
,
594 BRW_PARAM_BUILTIN_CLIP_PLANE_5_Z
,
595 BRW_PARAM_BUILTIN_CLIP_PLANE_5_W
,
596 BRW_PARAM_BUILTIN_CLIP_PLANE_6_X
,
597 BRW_PARAM_BUILTIN_CLIP_PLANE_6_Y
,
598 BRW_PARAM_BUILTIN_CLIP_PLANE_6_Z
,
599 BRW_PARAM_BUILTIN_CLIP_PLANE_6_W
,
600 BRW_PARAM_BUILTIN_CLIP_PLANE_7_X
,
601 BRW_PARAM_BUILTIN_CLIP_PLANE_7_Y
,
602 BRW_PARAM_BUILTIN_CLIP_PLANE_7_Z
,
603 BRW_PARAM_BUILTIN_CLIP_PLANE_7_W
,
605 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
,
606 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Y
,
607 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Z
,
608 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_W
,
609 BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
,
610 BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y
,
612 BRW_PARAM_BUILTIN_PATCH_VERTICES_IN
,
614 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_X
,
615 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Y
,
616 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Z
,
617 BRW_PARAM_BUILTIN_SUBGROUP_ID
,
620 #define BRW_PARAM_BUILTIN_CLIP_PLANE(idx, comp) \
621 (BRW_PARAM_BUILTIN_CLIP_PLANE_0_X + ((idx) << 2) + (comp))
623 #define BRW_PARAM_BUILTIN_IS_CLIP_PLANE(param) \
624 ((param) >= BRW_PARAM_BUILTIN_CLIP_PLANE_0_X && \
625 (param) <= BRW_PARAM_BUILTIN_CLIP_PLANE_7_W)
627 #define BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(param) \
628 (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) >> 2)
630 #define BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(param) \
631 (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) & 0x3)
633 struct brw_stage_prog_data
{
635 /** size of our binding table. */
639 * surface indices for the various groups of surfaces
641 uint32_t pull_constants_start
;
642 uint32_t texture_start
;
643 uint32_t gather_texture_start
;
646 uint32_t image_start
;
647 uint32_t shader_time_start
;
648 uint32_t plane_start
[3];
652 struct brw_ubo_range ubo_ranges
[4];
654 GLuint nr_params
; /**< number of float params/constants */
655 GLuint nr_pull_params
;
657 unsigned curb_read_length
;
658 unsigned total_scratch
;
659 unsigned total_shared
;
661 unsigned program_size
;
663 /** Does this program pull from any UBO or other constant buffers? */
667 * Register where the thread expects to find input data from the URB
668 * (typically uniforms, followed by vertex or fragment attributes).
670 unsigned dispatch_grf_start_reg
;
672 bool use_alt_mode
; /**< Use ALT floating point mode? Otherwise, IEEE. */
674 /* 32-bit identifiers for all push/pull parameters. These can be anything
675 * the driver wishes them to be; the core of the back-end compiler simply
676 * re-arranges them. The one restriction is that the bottom 2^16 values
677 * are reserved for builtins defined in the brw_param_builtin enum defined
681 uint32_t *pull_param
;
683 /* Whether shader uses atomic operations. */
684 bool uses_atomic_load_store
;
687 static inline uint32_t *
688 brw_stage_prog_data_add_params(struct brw_stage_prog_data
*prog_data
,
689 unsigned nr_new_params
)
691 unsigned old_nr_params
= prog_data
->nr_params
;
692 prog_data
->nr_params
+= nr_new_params
;
693 prog_data
->param
= reralloc(ralloc_parent(prog_data
->param
),
694 prog_data
->param
, uint32_t,
695 prog_data
->nr_params
);
696 return prog_data
->param
+ old_nr_params
;
699 enum brw_barycentric_mode
{
700 BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
= 0,
701 BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
= 1,
702 BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
= 2,
703 BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL
= 3,
704 BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
= 4,
705 BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE
= 5,
706 BRW_BARYCENTRIC_MODE_COUNT
= 6
708 #define BRW_BARYCENTRIC_NONPERSPECTIVE_BITS \
709 ((1 << BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL) | \
710 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID) | \
711 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE))
713 enum brw_pixel_shader_computed_depth_mode
{
714 BRW_PSCDEPTH_OFF
= 0, /* PS does not compute depth */
715 BRW_PSCDEPTH_ON
= 1, /* PS computes depth; no guarantee about value */
716 BRW_PSCDEPTH_ON_GE
= 2, /* PS guarantees output depth >= source depth */
717 BRW_PSCDEPTH_ON_LE
= 3, /* PS guarantees output depth <= source depth */
720 /* Data about a particular attempt to compile a program. Note that
721 * there can be many of these, each in a different GL state
722 * corresponding to a different brw_wm_prog_key struct, with different
725 struct brw_wm_prog_data
{
726 struct brw_stage_prog_data base
;
728 GLuint num_varying_inputs
;
730 uint8_t reg_blocks_8
;
731 uint8_t reg_blocks_16
;
732 uint8_t reg_blocks_32
;
734 uint8_t dispatch_grf_start_reg_16
;
735 uint8_t dispatch_grf_start_reg_32
;
736 uint32_t prog_offset_16
;
737 uint32_t prog_offset_32
;
741 * surface indices the WM-specific surfaces
743 uint32_t render_target_read_start
;
747 uint8_t computed_depth_mode
;
748 bool computed_stencil
;
750 bool early_fragment_tests
;
751 bool post_depth_coverage
;
757 bool persample_dispatch
;
758 bool uses_pos_offset
;
763 bool uses_sample_mask
;
764 bool has_render_target_reads
;
765 bool has_side_effects
;
768 bool contains_flat_varying
;
769 bool contains_noperspective_varying
;
772 * Mask of which interpolation modes are required by the fragment shader.
773 * Used in hardware setup on gen6+.
775 uint32_t barycentric_interp_modes
;
778 * Mask of which FS inputs are marked flat by the shader source. This is
779 * needed for setting up 3DSTATE_SF/SBE.
781 uint32_t flat_inputs
;
783 /* Mapping of VUE slots to interpolation modes.
784 * Used by the Gen4-5 clip/sf/wm stages.
786 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
789 * Map from gl_varying_slot to the position within the FS setup data
790 * payload where the varying's attribute vertex deltas should be delivered.
791 * For varying slots that are not used by the FS, the value is -1.
793 int urb_setup
[VARYING_SLOT_MAX
];
796 * Cache structure into the urb_setup array above that contains the
797 * attribute numbers of active varyings out of urb_setup.
798 * The actual count is stored in urb_setup_attribs_count.
800 uint8_t urb_setup_attribs
[VARYING_SLOT_MAX
];
801 uint8_t urb_setup_attribs_count
;
804 /** Returns the SIMD width corresponding to a given KSP index
806 * The "Variable Pixel Dispatch" table in the PRM (which can be found, for
807 * example in Vol. 7 of the SKL PRM) has a mapping from dispatch widths to
808 * kernel start pointer (KSP) indices that is based on what dispatch widths
809 * are enabled. This function provides, effectively, the reverse mapping.
811 * If the given KSP is valid with respect to the SIMD8/16/32 enables, a SIMD
812 * width of 8, 16, or 32 is returned. If the KSP is invalid, 0 is returned.
814 static inline unsigned
815 brw_fs_simd_width_for_ksp(unsigned ksp_idx
, bool simd8_enabled
,
816 bool simd16_enabled
, bool simd32_enabled
)
818 /* This function strictly ignores contiguous dispatch */
821 return simd8_enabled
? 8 :
822 (simd16_enabled
&& !simd32_enabled
) ? 16 :
823 (simd32_enabled
&& !simd16_enabled
) ? 32 : 0;
825 return (simd32_enabled
&& (simd16_enabled
|| simd8_enabled
)) ? 32 : 0;
827 return (simd16_enabled
&& (simd32_enabled
|| simd8_enabled
)) ? 16 : 0;
829 unreachable("Invalid KSP index");
833 #define brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx) \
834 brw_fs_simd_width_for_ksp((ksp_idx), (wm_state)._8PixelDispatchEnable, \
835 (wm_state)._16PixelDispatchEnable, \
836 (wm_state)._32PixelDispatchEnable)
838 #define brw_wm_state_has_ksp(wm_state, ksp_idx) \
839 (brw_wm_state_simd_width_for_ksp((wm_state), (ksp_idx)) != 0)
841 static inline uint32_t
842 _brw_wm_prog_data_prog_offset(const struct brw_wm_prog_data
*prog_data
,
845 switch (simd_width
) {
847 case 16: return prog_data
->prog_offset_16
;
848 case 32: return prog_data
->prog_offset_32
;
853 #define brw_wm_prog_data_prog_offset(prog_data, wm_state, ksp_idx) \
854 _brw_wm_prog_data_prog_offset(prog_data, \
855 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
857 static inline uint8_t
858 _brw_wm_prog_data_dispatch_grf_start_reg(const struct brw_wm_prog_data
*prog_data
,
861 switch (simd_width
) {
862 case 8: return prog_data
->base
.dispatch_grf_start_reg
;
863 case 16: return prog_data
->dispatch_grf_start_reg_16
;
864 case 32: return prog_data
->dispatch_grf_start_reg_32
;
869 #define brw_wm_prog_data_dispatch_grf_start_reg(prog_data, wm_state, ksp_idx) \
870 _brw_wm_prog_data_dispatch_grf_start_reg(prog_data, \
871 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
873 static inline uint8_t
874 _brw_wm_prog_data_reg_blocks(const struct brw_wm_prog_data
*prog_data
,
877 switch (simd_width
) {
878 case 8: return prog_data
->reg_blocks_8
;
879 case 16: return prog_data
->reg_blocks_16
;
880 case 32: return prog_data
->reg_blocks_32
;
885 #define brw_wm_prog_data_reg_blocks(prog_data, wm_state, ksp_idx) \
886 _brw_wm_prog_data_reg_blocks(prog_data, \
887 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
889 struct brw_push_const_block
{
890 unsigned dwords
; /* Dword count, not reg aligned */
892 unsigned size
; /* Bytes, register aligned */
895 struct brw_cs_prog_data
{
896 struct brw_stage_prog_data base
;
898 unsigned local_size
[3];
903 bool uses_num_work_groups
;
906 struct brw_push_const_block cross_thread
;
907 struct brw_push_const_block per_thread
;
908 struct brw_push_const_block total
;
913 * surface indices the CS-specific surfaces
915 uint32_t work_groups_start
;
921 * Enum representing the i965-specific vertex results that don't correspond
922 * exactly to any element of gl_varying_slot. The values of this enum are
923 * assigned such that they don't conflict with gl_varying_slot.
927 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
928 BRW_VARYING_SLOT_PAD
,
930 * Technically this is not a varying but just a placeholder that
931 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
932 * builtin variable to be compiled correctly. see compile_sf_prog() for
935 BRW_VARYING_SLOT_PNTC
,
936 BRW_VARYING_SLOT_COUNT
940 * We always program SF to start reading at an offset of 1 (2 varying slots)
941 * from the start of the vertex URB entry. This causes it to skip:
942 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
943 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
945 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
948 * Bitmask indicating which fragment shader inputs represent varyings (and
949 * hence have to be delivered to the fragment shader by the SF/SBE stage).
951 #define BRW_FS_VARYING_INPUT_MASK \
952 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
953 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
956 * Data structure recording the relationship between the gl_varying_slot enum
957 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
958 * single octaword within the VUE (128 bits).
960 * Note that each BRW register contains 256 bits (2 octawords), so when
961 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
962 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
963 * in a vertex shader), each register corresponds to a single VUE slot, since
964 * it contains data for two separate vertices.
968 * Bitfield representing all varying slots that are (a) stored in this VUE
969 * map, and (b) actually written by the shader. Does not include any of
970 * the additional varying slots defined in brw_varying_slot.
972 uint64_t slots_valid
;
975 * Is this VUE map for a separate shader pipeline?
977 * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched
978 * without the linker having a chance to dead code eliminate unused varyings.
980 * This means that we have to use a fixed slot layout, based on the output's
981 * location field, rather than assigning slots in a compact contiguous block.
986 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
987 * not stored in a slot (because they are not written, or because
988 * additional processing is applied before storing them in the VUE), the
991 signed char varying_to_slot
[VARYING_SLOT_TESS_MAX
];
994 * Map from VUE slot to gl_varying_slot value. For slots that do not
995 * directly correspond to a gl_varying_slot, the value comes from
998 * For slots that are not in use, the value is BRW_VARYING_SLOT_PAD.
1000 signed char slot_to_varying
[VARYING_SLOT_TESS_MAX
];
1003 * Total number of VUE slots in use
1008 * Number of per-patch VUE slots. Only valid for tessellation control
1009 * shader outputs and tessellation evaluation shader inputs.
1011 int num_per_patch_slots
;
1014 * Number of per-vertex VUE slots. Only valid for tessellation control
1015 * shader outputs and tessellation evaluation shader inputs.
1017 int num_per_vertex_slots
;
1020 void brw_print_vue_map(FILE *fp
, const struct brw_vue_map
*vue_map
);
1023 * Convert a VUE slot number into a byte offset within the VUE.
1025 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
1031 * Convert a vertex output (brw_varying_slot) into a byte offset within the
1035 GLuint
brw_varying_to_offset(const struct brw_vue_map
*vue_map
, GLuint varying
)
1037 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
1040 void brw_compute_vue_map(const struct gen_device_info
*devinfo
,
1041 struct brw_vue_map
*vue_map
,
1042 uint64_t slots_valid
,
1043 bool separate_shader
);
1045 void brw_compute_tess_vue_map(struct brw_vue_map
*const vue_map
,
1046 uint64_t slots_valid
,
1049 /* brw_interpolation_map.c */
1050 void brw_setup_vue_interpolation(struct brw_vue_map
*vue_map
,
1051 struct nir_shader
*nir
,
1052 struct brw_wm_prog_data
*prog_data
);
1054 enum shader_dispatch_mode
{
1055 DISPATCH_MODE_4X1_SINGLE
= 0,
1056 DISPATCH_MODE_4X2_DUAL_INSTANCE
= 1,
1057 DISPATCH_MODE_4X2_DUAL_OBJECT
= 2,
1058 DISPATCH_MODE_SIMD8
= 3,
1060 DISPATCH_MODE_TCS_SINGLE_PATCH
= 0,
1061 DISPATCH_MODE_TCS_8_PATCH
= 2,
1065 * @defgroup Tessellator parameter enumerations.
1067 * These correspond to the hardware values in 3DSTATE_TE, and are provided
1068 * as part of the tessellation evaluation shader.
1072 enum brw_tess_partitioning
{
1073 BRW_TESS_PARTITIONING_INTEGER
= 0,
1074 BRW_TESS_PARTITIONING_ODD_FRACTIONAL
= 1,
1075 BRW_TESS_PARTITIONING_EVEN_FRACTIONAL
= 2,
1078 enum brw_tess_output_topology
{
1079 BRW_TESS_OUTPUT_TOPOLOGY_POINT
= 0,
1080 BRW_TESS_OUTPUT_TOPOLOGY_LINE
= 1,
1081 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
= 2,
1082 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW
= 3,
1085 enum brw_tess_domain
{
1086 BRW_TESS_DOMAIN_QUAD
= 0,
1087 BRW_TESS_DOMAIN_TRI
= 1,
1088 BRW_TESS_DOMAIN_ISOLINE
= 2,
1092 struct brw_vue_prog_data
{
1093 struct brw_stage_prog_data base
;
1094 struct brw_vue_map vue_map
;
1096 /** Should the hardware deliver input VUE handles for URB pull loads? */
1097 bool include_vue_handles
;
1099 GLuint urb_read_length
;
1102 uint32_t clip_distance_mask
;
1103 uint32_t cull_distance_mask
;
1105 /* Used for calculating urb partitions. In the VS, this is the size of the
1106 * URB entry used for both input and output to the thread. In the GS, this
1107 * is the size of the URB entry used for output.
1109 GLuint urb_entry_size
;
1111 enum shader_dispatch_mode dispatch_mode
;
1114 struct brw_vs_prog_data
{
1115 struct brw_vue_prog_data base
;
1117 GLbitfield64 inputs_read
;
1118 GLbitfield64 double_inputs_read
;
1120 unsigned nr_attribute_slots
;
1123 bool uses_instanceid
;
1124 bool uses_is_indexed_draw
;
1125 bool uses_firstvertex
;
1126 bool uses_baseinstance
;
1130 struct brw_tcs_prog_data
1132 struct brw_vue_prog_data base
;
1134 /** Should the non-SINGLE_PATCH payload provide primitive ID? */
1135 bool include_primitive_id
;
1137 /** Number vertices in output patch */
1140 /** Track patch count threshold */
1141 int patch_count_threshold
;
1145 struct brw_tes_prog_data
1147 struct brw_vue_prog_data base
;
1149 enum brw_tess_partitioning partitioning
;
1150 enum brw_tess_output_topology output_topology
;
1151 enum brw_tess_domain domain
;
1154 struct brw_gs_prog_data
1156 struct brw_vue_prog_data base
;
1158 unsigned vertices_in
;
1161 * Size of an output vertex, measured in HWORDS (32 bytes).
1163 unsigned output_vertex_size_hwords
;
1165 unsigned output_topology
;
1168 * Size of the control data (cut bits or StreamID bits), in hwords (32
1169 * bytes). 0 if there is no control data.
1171 unsigned control_data_header_size_hwords
;
1174 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
1175 * if the control data is StreamID bits, or
1176 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
1177 * Ignored if control_data_header_size is 0.
1179 unsigned control_data_format
;
1181 bool include_primitive_id
;
1184 * The number of vertices emitted, if constant - otherwise -1.
1186 int static_vertex_count
;
1191 * Gen6: Provoking vertex convention for odd-numbered triangles
1197 * Gen6: Number of varyings that are output to transform feedback.
1199 GLuint num_transform_feedback_bindings
:7; /* 0-BRW_MAX_SOL_BINDINGS */
1202 * Gen6: Map from the index of a transform feedback binding table entry to the
1203 * gl_varying_slot that should be streamed out through that binding table
1206 unsigned char transform_feedback_bindings
[64 /* BRW_MAX_SOL_BINDINGS */];
1209 * Gen6: Map from the index of a transform feedback binding table entry to the
1210 * swizzles that should be used when streaming out data through that
1211 * binding table entry.
1213 unsigned char transform_feedback_swizzles
[64 /* BRW_MAX_SOL_BINDINGS */];
1216 struct brw_sf_prog_data
{
1217 uint32_t urb_read_length
;
1220 /* Each vertex may have upto 12 attributes, 4 components each,
1221 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
1224 * Actually we use 4 for each, so call it 12 rows.
1226 unsigned urb_entry_size
;
1229 struct brw_clip_prog_data
{
1230 uint32_t curb_read_length
; /* user planes? */
1232 uint32_t urb_read_length
;
1236 /* brw_any_prog_data is prog_data for any stage that maps to an API stage */
1237 union brw_any_prog_data
{
1238 struct brw_stage_prog_data base
;
1239 struct brw_vue_prog_data vue
;
1240 struct brw_vs_prog_data vs
;
1241 struct brw_tcs_prog_data tcs
;
1242 struct brw_tes_prog_data tes
;
1243 struct brw_gs_prog_data gs
;
1244 struct brw_wm_prog_data wm
;
1245 struct brw_cs_prog_data cs
;
1248 #define DEFINE_PROG_DATA_DOWNCAST(stage) \
1249 static inline struct brw_##stage##_prog_data * \
1250 brw_##stage##_prog_data(struct brw_stage_prog_data *prog_data) \
1252 return (struct brw_##stage##_prog_data *) prog_data; \
1254 DEFINE_PROG_DATA_DOWNCAST(vue
)
1255 DEFINE_PROG_DATA_DOWNCAST(vs
)
1256 DEFINE_PROG_DATA_DOWNCAST(tcs
)
1257 DEFINE_PROG_DATA_DOWNCAST(tes
)
1258 DEFINE_PROG_DATA_DOWNCAST(gs
)
1259 DEFINE_PROG_DATA_DOWNCAST(wm
)
1260 DEFINE_PROG_DATA_DOWNCAST(cs
)
1261 DEFINE_PROG_DATA_DOWNCAST(ff_gs
)
1262 DEFINE_PROG_DATA_DOWNCAST(clip
)
1263 DEFINE_PROG_DATA_DOWNCAST(sf
)
1264 #undef DEFINE_PROG_DATA_DOWNCAST
1266 struct brw_compile_stats
{
1267 uint32_t dispatch_width
; /**< 0 for vec4 */
1268 uint32_t instructions
;
1277 struct brw_compiler
*
1278 brw_compiler_create(void *mem_ctx
, const struct gen_device_info
*devinfo
);
1281 * Returns a compiler configuration for use with disk shader cache
1283 * This value only needs to change for settings that can cause different
1284 * program generation between two runs on the same hardware.
1286 * For example, it doesn't need to be different for gen 8 and gen 9 hardware,
1287 * but it does need to be different if INTEL_DEBUG=nocompact is or isn't used.
1290 brw_get_compiler_config_value(const struct brw_compiler
*compiler
);
1293 brw_prog_data_size(gl_shader_stage stage
);
1296 brw_prog_key_size(gl_shader_stage stage
);
1299 brw_prog_key_set_id(union brw_any_prog_key
*key
, gl_shader_stage
, unsigned id
);
1302 * Compile a vertex shader.
1304 * Returns the final assembly and the program's size.
1307 brw_compile_vs(const struct brw_compiler
*compiler
, void *log_data
,
1309 const struct brw_vs_prog_key
*key
,
1310 struct brw_vs_prog_data
*prog_data
,
1311 struct nir_shader
*shader
,
1312 int shader_time_index
,
1313 struct brw_compile_stats
*stats
,
1317 * Compile a tessellation control shader.
1319 * Returns the final assembly and the program's size.
1322 brw_compile_tcs(const struct brw_compiler
*compiler
,
1325 const struct brw_tcs_prog_key
*key
,
1326 struct brw_tcs_prog_data
*prog_data
,
1327 struct nir_shader
*nir
,
1328 int shader_time_index
,
1329 struct brw_compile_stats
*stats
,
1333 * Compile a tessellation evaluation shader.
1335 * Returns the final assembly and the program's size.
1338 brw_compile_tes(const struct brw_compiler
*compiler
, void *log_data
,
1340 const struct brw_tes_prog_key
*key
,
1341 const struct brw_vue_map
*input_vue_map
,
1342 struct brw_tes_prog_data
*prog_data
,
1343 struct nir_shader
*shader
,
1344 int shader_time_index
,
1345 struct brw_compile_stats
*stats
,
1349 * Compile a vertex shader.
1351 * Returns the final assembly and the program's size.
1354 brw_compile_gs(const struct brw_compiler
*compiler
, void *log_data
,
1356 const struct brw_gs_prog_key
*key
,
1357 struct brw_gs_prog_data
*prog_data
,
1358 struct nir_shader
*shader
,
1359 struct gl_program
*prog
,
1360 int shader_time_index
,
1361 struct brw_compile_stats
*stats
,
1365 * Compile a strips and fans shader.
1367 * This is a fixed-function shader determined entirely by the shader key and
1370 * Returns the final assembly and the program's size.
1373 brw_compile_sf(const struct brw_compiler
*compiler
,
1375 const struct brw_sf_prog_key
*key
,
1376 struct brw_sf_prog_data
*prog_data
,
1377 struct brw_vue_map
*vue_map
,
1378 unsigned *final_assembly_size
);
1381 * Compile a clipper shader.
1383 * This is a fixed-function shader determined entirely by the shader key and
1386 * Returns the final assembly and the program's size.
1389 brw_compile_clip(const struct brw_compiler
*compiler
,
1391 const struct brw_clip_prog_key
*key
,
1392 struct brw_clip_prog_data
*prog_data
,
1393 struct brw_vue_map
*vue_map
,
1394 unsigned *final_assembly_size
);
1397 * Compile a fragment shader.
1399 * Returns the final assembly and the program's size.
1402 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
1404 const struct brw_wm_prog_key
*key
,
1405 struct brw_wm_prog_data
*prog_data
,
1406 struct nir_shader
*shader
,
1407 int shader_time_index8
,
1408 int shader_time_index16
,
1409 int shader_time_index32
,
1410 bool allow_spilling
,
1411 bool use_rep_send
, struct brw_vue_map
*vue_map
,
1412 struct brw_compile_stats
*stats
, /**< Array of three stats */
1416 * Compile a compute shader.
1418 * Returns the final assembly and the program's size.
1421 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
1423 const struct brw_cs_prog_key
*key
,
1424 struct brw_cs_prog_data
*prog_data
,
1425 const struct nir_shader
*shader
,
1426 int shader_time_index
,
1427 struct brw_compile_stats
*stats
,
1430 void brw_debug_key_recompile(const struct brw_compiler
*c
, void *log
,
1431 gl_shader_stage stage
,
1432 const struct brw_base_prog_key
*old_key
,
1433 const struct brw_base_prog_key
*key
);
1435 static inline uint32_t
1436 encode_slm_size(unsigned gen
, uint32_t bytes
)
1438 uint32_t slm_size
= 0;
1440 /* Shared Local Memory is specified as powers of two, and encoded in
1441 * INTERFACE_DESCRIPTOR_DATA with the following representations:
1443 * Size | 0 kB | 1 kB | 2 kB | 4 kB | 8 kB | 16 kB | 32 kB | 64 kB |
1444 * -------------------------------------------------------------------
1445 * Gen7-8 | 0 | none | none | 1 | 2 | 4 | 8 | 16 |
1446 * -------------------------------------------------------------------
1447 * Gen9+ | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
1449 assert(bytes
<= 64 * 1024);
1452 /* Shared Local Memory Size is specified as powers of two. */
1453 slm_size
= util_next_power_of_two(bytes
);
1456 /* Use a minimum of 1kB; turn an exponent of 10 (1024 kB) into 1. */
1457 slm_size
= ffs(MAX2(slm_size
, 1024)) - 10;
1459 /* Use a minimum of 4kB; convert to the pre-Gen9 representation. */
1460 slm_size
= MAX2(slm_size
, 4096) / 4096;
1468 * Return true if the given shader stage is dispatched contiguously by the
1469 * relevant fixed function starting from channel 0 of the SIMD thread, which
1470 * implies that the dispatch mask of a thread can be assumed to have the form
1471 * '2^n - 1' for some n.
1474 brw_stage_has_packed_dispatch(ASSERTED
const struct gen_device_info
*devinfo
,
1475 gl_shader_stage stage
,
1476 const struct brw_stage_prog_data
*prog_data
)
1478 /* The code below makes assumptions about the hardware's thread dispatch
1479 * behavior that could be proven wrong in future generations -- Make sure
1480 * to do a full test run with brw_fs_test_dispatch_packing() hooked up to
1481 * the NIR front-end before changing this assertion.
1483 assert(devinfo
->gen
<= 12);
1486 case MESA_SHADER_FRAGMENT
: {
1487 /* The PSD discards subspans coming in with no lit samples, which in the
1488 * per-pixel shading case implies that each subspan will either be fully
1489 * lit (due to the VMask being used to allow derivative computations),
1490 * or not dispatched at all. In per-sample dispatch mode individual
1491 * samples from the same subspan have a fixed relative location within
1492 * the SIMD thread, so dispatch of unlit samples cannot be avoided in
1493 * general and we should return false.
1495 const struct brw_wm_prog_data
*wm_prog_data
=
1496 (const struct brw_wm_prog_data
*)prog_data
;
1497 return !wm_prog_data
->persample_dispatch
;
1499 case MESA_SHADER_COMPUTE
:
1500 /* Compute shaders will be spawned with either a fully enabled dispatch
1501 * mask or with whatever bottom/right execution mask was given to the
1502 * GPGPU walker command to be used along the workgroup edges -- In both
1503 * cases the dispatch mask is required to be tightly packed for our
1504 * invocation index calculations to work.
1508 /* Most remaining fixed functions are limited to use a packed dispatch
1509 * mask due to the hardware representation of the dispatch mask as a
1510 * single counter representing the number of enabled channels.
1517 * Computes the first varying slot in the URB produced by the previous stage
1518 * that is used in the next stage. We do this by testing the varying slots in
1519 * the previous stage's vue map against the inputs read in the next stage.
1523 * - Each URB offset contains two varying slots and we can only skip a
1524 * full offset if both slots are unused, so the value we return here is always
1525 * rounded down to the closest multiple of two.
1527 * - gl_Layer and gl_ViewportIndex don't have their own varying slots, they are
1528 * part of the vue header, so if these are read we can't skip anything.
1531 brw_compute_first_urb_slot_required(uint64_t inputs_read
,
1532 const struct brw_vue_map
*prev_stage_vue_map
)
1534 if ((inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
)) == 0) {
1535 for (int i
= 0; i
< prev_stage_vue_map
->num_slots
; i
++) {
1536 int varying
= prev_stage_vue_map
->slot_to_varying
[i
];
1537 if (varying
> 0 && (inputs_read
& BITFIELD64_BIT(varying
)) != 0)
1538 return ROUND_DOWN_TO(i
, 2);
1549 #endif /* BRW_COMPILER_H */