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24 #ifndef BRW_COMPILER_H
25 #define BRW_COMPILER_H
28 #include "common/gen_device_info.h"
29 #include "main/mtypes.h"
30 #include "main/macros.h"
39 union gl_constant_value
;
42 const struct gen_device_info
*devinfo
;
48 * Array of the ra classes for the unaligned contiguous register
54 * Mapping for register-allocated objects in *regs to the first
55 * GRF for that object.
57 uint8_t *ra_reg_to_grf
;
64 * Array of the ra classes for the unaligned contiguous register
65 * block sizes used, indexed by register size.
70 * Mapping from classes to ra_reg ranges. Each of the per-size
71 * classes corresponds to a range of ra_reg nodes. This array stores
72 * those ranges in the form of first ra_reg in each class and the
73 * total number of ra_reg elements in the last array element. This
74 * way the range of the i'th class is given by:
75 * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] )
77 int class_to_ra_reg_range
[17];
80 * Mapping for register-allocated objects in *regs to the first
81 * GRF for that object.
83 uint8_t *ra_reg_to_grf
;
86 * ra class for the aligned pairs we use for PLN, which doesn't
89 int aligned_pairs_class
;
92 void (*shader_debug_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
93 void (*shader_perf_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
95 bool scalar_stage
[MESA_SHADER_STAGES
];
96 struct gl_shader_compiler_options glsl_compiler_options
[MESA_SHADER_STAGES
];
99 * Apply workarounds for SIN and COS output range problems.
100 * This can negatively impact performance.
105 * Is 3DSTATE_CONSTANT_*'s Constant Buffer 0 relative to Dynamic State
106 * Base Address? (If not, it's a normal GPU address.)
108 bool constant_buffer_0_is_relative
;
113 * Program key structures.
115 * When drawing, we look for the currently bound shaders in the program
116 * cache. This is essentially a hash table lookup, and these are the keys.
118 * Sometimes OpenGL features specified as state need to be simulated via
119 * shader code, due to a mismatch between the API and the hardware. This
120 * is often referred to as "non-orthagonal state" or "NOS". We store NOS
121 * in the program key so it's considered when searching for a program. If
122 * we haven't seen a particular combination before, we have to recompile a
123 * new specialized version.
125 * Shader compilation should not look up state in gl_context directly, but
126 * instead use the copy in the program key. This guarantees recompiles will
132 enum PACKED gen6_gather_sampler_wa
{
133 WA_SIGN
= 1, /* whether we need to sign extend */
134 WA_8BIT
= 2, /* if we have an 8bit format needing wa */
135 WA_16BIT
= 4, /* if we have a 16bit format needing wa */
139 * Sampler information needed by VS, WM, and GS program cache keys.
141 struct brw_sampler_prog_key_data
{
143 * EXT_texture_swizzle and DEPTH_TEXTURE_MODE swizzles.
145 uint16_t swizzles
[MAX_SAMPLERS
];
147 uint32_t gl_clamp_mask
[3];
150 * For RG32F, gather4's channel select is broken.
152 uint32_t gather_channel_quirk_mask
;
155 * Whether this sampler uses the compressed multisample surface layout.
157 uint32_t compressed_multisample_layout_mask
;
160 * Whether this sampler is using 16x multisampling. If so fetching from
161 * this sampler will be handled with a different instruction, ld2dms_w
167 * For Sandybridge, which shader w/a we need for gather quirks.
169 enum gen6_gather_sampler_wa gen6_gather_wa
[MAX_SAMPLERS
];
172 * Texture units that have a YUV image bound.
174 uint32_t y_u_v_image_mask
;
175 uint32_t y_uv_image_mask
;
176 uint32_t yx_xuxv_image_mask
;
177 uint32_t xy_uxvx_image_mask
;
181 * The VF can't natively handle certain types of attributes, such as GL_FIXED
182 * or most 10_10_10_2 types. These flags enable various VS workarounds to
183 * "fix" attributes at the beginning of shaders.
185 #define BRW_ATTRIB_WA_COMPONENT_MASK 7 /* mask for GL_FIXED scale channel count */
186 #define BRW_ATTRIB_WA_NORMALIZE 8 /* normalize in shader */
187 #define BRW_ATTRIB_WA_BGRA 16 /* swap r/b channels in shader */
188 #define BRW_ATTRIB_WA_SIGN 32 /* interpret as signed in shader */
189 #define BRW_ATTRIB_WA_SCALE 64 /* interpret as scaled in shader */
192 * OpenGL attribute slots fall in [0, VERT_ATTRIB_MAX - 1] with the range
193 * [VERT_ATTRIB_GENERIC0, VERT_ATTRIB_MAX - 1] reserved for up to 16 user
194 * input vertex attributes. In Vulkan, we expose up to 28 user vertex input
195 * attributes that are mapped to slots also starting at VERT_ATTRIB_GENERIC0.
197 #define MAX_GL_VERT_ATTRIB VERT_ATTRIB_MAX
198 #define MAX_VK_VERT_ATTRIB (VERT_ATTRIB_GENERIC0 + 28)
200 /** The program key for Vertex Shaders. */
201 struct brw_vs_prog_key
{
202 unsigned program_string_id
;
205 * Per-attribute workaround flags
207 * For each attribute, a combination of BRW_ATTRIB_WA_*.
209 * For OpenGL, where we expose a maximum of 16 user input atttributes
210 * we only need up to VERT_ATTRIB_MAX slots, however, in Vulkan
211 * slots preceding VERT_ATTRIB_GENERIC0 are unused and we can
212 * expose up to 28 user input vertex attributes that are mapped to slots
213 * starting at VERT_ATTRIB_GENERIC0, so this array needs to be large
214 * enough to hold this many slots.
216 uint8_t gl_attrib_wa_flags
[MAX2(MAX_GL_VERT_ATTRIB
, MAX_VK_VERT_ATTRIB
)];
218 bool copy_edgeflag
:1;
220 bool clamp_vertex_color
:1;
223 * How many user clipping planes are being uploaded to the vertex shader as
226 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
229 unsigned nr_userclip_plane_consts
:4;
232 * For pre-Gen6 hardware, a bitfield indicating which texture coordinates
233 * are going to be replaced with point coordinates (as a consequence of a
234 * call to glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)). Because
235 * our SF thread requires exact matching between VS outputs and FS inputs,
236 * these texture coordinates will need to be unconditionally included in
237 * the VUE, even if they aren't written by the vertex shader.
239 uint8_t point_coord_replace
;
241 struct brw_sampler_prog_key_data tex
;
244 /** The program key for Tessellation Control Shaders. */
245 struct brw_tcs_prog_key
247 unsigned program_string_id
;
249 GLenum tes_primitive_mode
;
251 unsigned input_vertices
;
253 /** A bitfield of per-patch outputs written. */
254 uint32_t patch_outputs_written
;
256 /** A bitfield of per-vertex outputs written. */
257 uint64_t outputs_written
;
259 bool quads_workaround
;
261 struct brw_sampler_prog_key_data tex
;
264 /** The program key for Tessellation Evaluation Shaders. */
265 struct brw_tes_prog_key
267 unsigned program_string_id
;
269 /** A bitfield of per-patch inputs read. */
270 uint32_t patch_inputs_read
;
272 /** A bitfield of per-vertex inputs read. */
273 uint64_t inputs_read
;
275 struct brw_sampler_prog_key_data tex
;
278 /** The program key for Geometry Shaders. */
279 struct brw_gs_prog_key
281 unsigned program_string_id
;
283 struct brw_sampler_prog_key_data tex
;
286 enum brw_sf_primitive
{
287 BRW_SF_PRIM_POINTS
= 0,
288 BRW_SF_PRIM_LINES
= 1,
289 BRW_SF_PRIM_TRIANGLES
= 2,
290 BRW_SF_PRIM_UNFILLED_TRIS
= 3,
293 struct brw_sf_prog_key
{
295 bool contains_flat_varying
;
296 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
297 uint8_t point_sprite_coord_replace
;
298 enum brw_sf_primitive primitive
:2;
299 bool do_twoside_color
:1;
300 bool frontface_ccw
:1;
301 bool do_point_sprite
:1;
302 bool do_point_coord
:1;
303 bool sprite_origin_lower_left
:1;
304 bool userclip_active
:1;
308 BRW_CLIP_MODE_NORMAL
= 0,
309 BRW_CLIP_MODE_CLIP_ALL
= 1,
310 BRW_CLIP_MODE_CLIP_NON_REJECTED
= 2,
311 BRW_CLIP_MODE_REJECT_ALL
= 3,
312 BRW_CLIP_MODE_ACCEPT_ALL
= 4,
313 BRW_CLIP_MODE_KERNEL_CLIP
= 5,
316 enum brw_clip_fill_mode
{
317 BRW_CLIP_FILL_MODE_LINE
= 0,
318 BRW_CLIP_FILL_MODE_POINT
= 1,
319 BRW_CLIP_FILL_MODE_FILL
= 2,
320 BRW_CLIP_FILL_MODE_CULL
= 3,
323 /* Note that if unfilled primitives are being emitted, we have to fix
324 * up polygon offset and flatshading at this point:
326 struct brw_clip_prog_key
{
328 bool contains_flat_varying
;
329 bool contains_noperspective_varying
;
330 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
331 unsigned primitive
:4;
332 unsigned nr_userclip
:4;
335 enum brw_clip_fill_mode fill_cw
:2; /* includes cull information */
336 enum brw_clip_fill_mode fill_ccw
:2; /* includes cull information */
341 enum brw_clip_mode clip_mode
:3;
348 /* A big lookup table is used to figure out which and how many
349 * additional regs will inserted before the main payload in the WM
350 * program execution. These mainly relate to depth and stencil
351 * processing and the early-depth-test optimization.
353 enum brw_wm_iz_bits
{
354 BRW_WM_IZ_PS_KILL_ALPHATEST_BIT
= 0x1,
355 BRW_WM_IZ_PS_COMPUTES_DEPTH_BIT
= 0x2,
356 BRW_WM_IZ_DEPTH_WRITE_ENABLE_BIT
= 0x4,
357 BRW_WM_IZ_DEPTH_TEST_ENABLE_BIT
= 0x8,
358 BRW_WM_IZ_STENCIL_WRITE_ENABLE_BIT
= 0x10,
359 BRW_WM_IZ_STENCIL_TEST_ENABLE_BIT
= 0x20,
360 BRW_WM_IZ_BIT_MAX
= 0x40
363 enum brw_wm_aa_enable
{
369 /** The program key for Fragment/Pixel Shaders. */
370 struct brw_wm_prog_key
{
371 /* Some collection of BRW_WM_IZ_* */
375 unsigned nr_color_regions
:5;
376 bool replicate_alpha
:1;
377 bool clamp_fragment_color
:1;
378 bool persample_interp
:1;
379 bool multisample_fbo
:1;
380 bool frag_coord_adds_sample_pos
:1;
381 enum brw_wm_aa_enable line_aa
:2;
382 bool high_quality_derivatives
:1;
383 bool force_dual_color_blend
:1;
384 bool coherent_fb_fetch
:1;
386 uint16_t drawable_height
;
387 uint64_t input_slots_valid
;
388 unsigned program_string_id
;
389 GLenum alpha_test_func
; /* < For Gen4/5 MRT alpha test */
390 float alpha_test_ref
;
392 struct brw_sampler_prog_key_data tex
;
395 struct brw_cs_prog_key
{
396 uint32_t program_string_id
;
397 struct brw_sampler_prog_key_data tex
;
401 * Image metadata structure as laid out in the shader parameter
402 * buffer. Entries have to be 16B-aligned for the vec4 back-end to be
403 * able to use them. That's okay because the padding and any unused
404 * entries [most of them except when we're doing untyped surface
405 * access] will be removed by the uniform packing pass.
407 #define BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET 0
408 #define BRW_IMAGE_PARAM_OFFSET_OFFSET 4
409 #define BRW_IMAGE_PARAM_SIZE_OFFSET 8
410 #define BRW_IMAGE_PARAM_STRIDE_OFFSET 12
411 #define BRW_IMAGE_PARAM_TILING_OFFSET 16
412 #define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 20
413 #define BRW_IMAGE_PARAM_SIZE 24
415 struct brw_image_param
{
416 /** Surface binding table index. */
417 uint32_t surface_idx
;
419 /** Offset applied to the X and Y surface coordinates. */
422 /** Surface X, Y and Z dimensions. */
425 /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
426 * pixels, vertical slice stride in pixels.
430 /** Log2 of the tiling modulus in the X, Y and Z dimension. */
434 * Right shift to apply for bit 6 address swizzling. Two different
435 * swizzles can be specified and will be applied one after the other. The
436 * resulting address will be:
438 * addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
439 * (addr >> swizzling[1])))
441 * Use \c 0xff if any of the swizzles is not required.
443 uint32_t swizzling
[2];
446 /** Max number of render targets in a shader */
447 #define BRW_MAX_DRAW_BUFFERS 8
450 * Max number of binding table entries used for stream output.
452 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
453 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
455 * On Gen6, the size of transform feedback data is limited not by the number
456 * of components but by the number of binding table entries we set aside. We
457 * use one binding table entry for a float, one entry for a vector, and one
458 * entry per matrix column. Since the only way we can communicate our
459 * transform feedback capabilities to the client is via
460 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
461 * worst case, in which all the varyings are floats, so we use up one binding
462 * table entry per component. Therefore we need to set aside at least 64
463 * binding table entries for use by transform feedback.
465 * Note: since we don't currently pack varyings, it is currently impossible
466 * for the client to actually use up all of these binding table entries--if
467 * all of their varyings were floats, they would run out of varying slots and
468 * fail to link. But that's a bug, so it seems prudent to go ahead and
469 * allocate the number of binding table entries we will need once the bug is
472 #define BRW_MAX_SOL_BINDINGS 64
475 * Binding table index for the first gen6 SOL binding.
477 #define BRW_GEN6_SOL_BINDING_START 0
480 * Stride in bytes between shader_time entries.
482 * We separate entries by a cacheline to reduce traffic between EUs writing to
485 #define BRW_SHADER_TIME_STRIDE 64
494 struct brw_stage_prog_data
{
496 /** size of our binding table. */
500 * surface indices for the various groups of surfaces
502 uint32_t pull_constants_start
;
503 uint32_t texture_start
;
504 uint32_t gather_texture_start
;
508 uint32_t image_start
;
509 uint32_t shader_time_start
;
510 uint32_t plane_start
[3];
514 struct brw_ubo_range ubo_ranges
[4];
516 GLuint nr_params
; /**< number of float params/constants */
517 GLuint nr_pull_params
;
518 unsigned nr_image_params
;
520 unsigned curb_read_length
;
521 unsigned total_scratch
;
522 unsigned total_shared
;
525 * Register where the thread expects to find input data from the URB
526 * (typically uniforms, followed by vertex or fragment attributes).
528 unsigned dispatch_grf_start_reg
;
530 bool use_alt_mode
; /**< Use ALT floating point mode? Otherwise, IEEE. */
532 /* Pointers to tracked values (only valid once
533 * _mesa_load_state_parameters has been called at runtime).
535 const union gl_constant_value
**param
;
536 const union gl_constant_value
**pull_param
;
538 /** Image metadata passed to the shader as uniforms. */
539 struct brw_image_param
*image_param
;
543 brw_mark_surface_used(struct brw_stage_prog_data
*prog_data
,
546 /* A binding table index is 8 bits and the top 3 values are reserved for
547 * special things (stateless and SLM).
549 assert(surf_index
<= 252);
551 prog_data
->binding_table
.size_bytes
=
552 MAX2(prog_data
->binding_table
.size_bytes
, (surf_index
+ 1) * 4);
555 enum brw_barycentric_mode
{
556 BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
= 0,
557 BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
= 1,
558 BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
= 2,
559 BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL
= 3,
560 BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
= 4,
561 BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE
= 5,
562 BRW_BARYCENTRIC_MODE_COUNT
= 6
564 #define BRW_BARYCENTRIC_NONPERSPECTIVE_BITS \
565 ((1 << BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL) | \
566 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID) | \
567 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE))
569 enum brw_pixel_shader_computed_depth_mode
{
570 BRW_PSCDEPTH_OFF
= 0, /* PS does not compute depth */
571 BRW_PSCDEPTH_ON
= 1, /* PS computes depth; no guarantee about value */
572 BRW_PSCDEPTH_ON_GE
= 2, /* PS guarantees output depth >= source depth */
573 BRW_PSCDEPTH_ON_LE
= 3, /* PS guarantees output depth <= source depth */
576 /* Data about a particular attempt to compile a program. Note that
577 * there can be many of these, each in a different GL state
578 * corresponding to a different brw_wm_prog_key struct, with different
581 struct brw_wm_prog_data
{
582 struct brw_stage_prog_data base
;
584 GLuint num_varying_inputs
;
586 uint8_t reg_blocks_0
;
587 uint8_t reg_blocks_2
;
589 uint8_t dispatch_grf_start_reg_2
;
590 uint32_t prog_offset_2
;
594 * surface indices the WM-specific surfaces
596 uint32_t render_target_start
;
597 uint32_t render_target_read_start
;
601 uint8_t computed_depth_mode
;
602 bool computed_stencil
;
604 bool early_fragment_tests
;
605 bool post_depth_coverage
;
610 bool persample_dispatch
;
611 bool uses_pos_offset
;
616 bool uses_sample_mask
;
617 bool has_render_target_reads
;
618 bool has_side_effects
;
621 bool contains_flat_varying
;
622 bool contains_noperspective_varying
;
625 * Mask of which interpolation modes are required by the fragment shader.
626 * Used in hardware setup on gen6+.
628 uint32_t barycentric_interp_modes
;
631 * Mask of which FS inputs are marked flat by the shader source. This is
632 * needed for setting up 3DSTATE_SF/SBE.
634 uint32_t flat_inputs
;
636 /* Mapping of VUE slots to interpolation modes.
637 * Used by the Gen4-5 clip/sf/wm stages.
639 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
642 * Map from gl_varying_slot to the position within the FS setup data
643 * payload where the varying's attribute vertex deltas should be delivered.
644 * For varying slots that are not used by the FS, the value is -1.
646 int urb_setup
[VARYING_SLOT_MAX
];
649 struct brw_push_const_block
{
650 unsigned dwords
; /* Dword count, not reg aligned */
652 unsigned size
; /* Bytes, register aligned */
655 struct brw_cs_prog_data
{
656 struct brw_stage_prog_data base
;
658 GLuint dispatch_grf_start_reg_16
;
659 unsigned local_size
[3];
663 bool uses_num_work_groups
;
664 int thread_local_id_index
;
667 struct brw_push_const_block cross_thread
;
668 struct brw_push_const_block per_thread
;
669 struct brw_push_const_block total
;
674 * surface indices the CS-specific surfaces
676 uint32_t work_groups_start
;
682 * Enum representing the i965-specific vertex results that don't correspond
683 * exactly to any element of gl_varying_slot. The values of this enum are
684 * assigned such that they don't conflict with gl_varying_slot.
688 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
689 BRW_VARYING_SLOT_PAD
,
691 * Technically this is not a varying but just a placeholder that
692 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
693 * builtin variable to be compiled correctly. see compile_sf_prog() for
696 BRW_VARYING_SLOT_PNTC
,
697 BRW_VARYING_SLOT_COUNT
701 * We always program SF to start reading at an offset of 1 (2 varying slots)
702 * from the start of the vertex URB entry. This causes it to skip:
703 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
704 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
706 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
709 * Bitmask indicating which fragment shader inputs represent varyings (and
710 * hence have to be delivered to the fragment shader by the SF/SBE stage).
712 #define BRW_FS_VARYING_INPUT_MASK \
713 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
714 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
717 * Data structure recording the relationship between the gl_varying_slot enum
718 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
719 * single octaword within the VUE (128 bits).
721 * Note that each BRW register contains 256 bits (2 octawords), so when
722 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
723 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
724 * in a vertex shader), each register corresponds to a single VUE slot, since
725 * it contains data for two separate vertices.
729 * Bitfield representing all varying slots that are (a) stored in this VUE
730 * map, and (b) actually written by the shader. Does not include any of
731 * the additional varying slots defined in brw_varying_slot.
733 uint64_t slots_valid
;
736 * Is this VUE map for a separate shader pipeline?
738 * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched
739 * without the linker having a chance to dead code eliminate unused varyings.
741 * This means that we have to use a fixed slot layout, based on the output's
742 * location field, rather than assigning slots in a compact contiguous block.
747 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
748 * not stored in a slot (because they are not written, or because
749 * additional processing is applied before storing them in the VUE), the
752 signed char varying_to_slot
[VARYING_SLOT_TESS_MAX
];
755 * Map from VUE slot to gl_varying_slot value. For slots that do not
756 * directly correspond to a gl_varying_slot, the value comes from
759 * For slots that are not in use, the value is BRW_VARYING_SLOT_PAD.
761 signed char slot_to_varying
[VARYING_SLOT_TESS_MAX
];
764 * Total number of VUE slots in use
769 * Number of per-patch VUE slots. Only valid for tessellation control
770 * shader outputs and tessellation evaluation shader inputs.
772 int num_per_patch_slots
;
775 * Number of per-vertex VUE slots. Only valid for tessellation control
776 * shader outputs and tessellation evaluation shader inputs.
778 int num_per_vertex_slots
;
781 void brw_print_vue_map(FILE *fp
, const struct brw_vue_map
*vue_map
);
784 * Convert a VUE slot number into a byte offset within the VUE.
786 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
792 * Convert a vertex output (brw_varying_slot) into a byte offset within the
796 GLuint
brw_varying_to_offset(const struct brw_vue_map
*vue_map
, GLuint varying
)
798 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
801 void brw_compute_vue_map(const struct gen_device_info
*devinfo
,
802 struct brw_vue_map
*vue_map
,
803 uint64_t slots_valid
,
804 bool separate_shader
);
806 void brw_compute_tess_vue_map(struct brw_vue_map
*const vue_map
,
807 uint64_t slots_valid
,
810 /* brw_interpolation_map.c */
811 void brw_setup_vue_interpolation(struct brw_vue_map
*vue_map
,
812 struct nir_shader
*nir
,
813 struct brw_wm_prog_data
*prog_data
,
814 const struct gen_device_info
*devinfo
);
816 enum shader_dispatch_mode
{
817 DISPATCH_MODE_4X1_SINGLE
= 0,
818 DISPATCH_MODE_4X2_DUAL_INSTANCE
= 1,
819 DISPATCH_MODE_4X2_DUAL_OBJECT
= 2,
820 DISPATCH_MODE_SIMD8
= 3,
824 * @defgroup Tessellator parameter enumerations.
826 * These correspond to the hardware values in 3DSTATE_TE, and are provided
827 * as part of the tessellation evaluation shader.
831 enum brw_tess_partitioning
{
832 BRW_TESS_PARTITIONING_INTEGER
= 0,
833 BRW_TESS_PARTITIONING_ODD_FRACTIONAL
= 1,
834 BRW_TESS_PARTITIONING_EVEN_FRACTIONAL
= 2,
837 enum brw_tess_output_topology
{
838 BRW_TESS_OUTPUT_TOPOLOGY_POINT
= 0,
839 BRW_TESS_OUTPUT_TOPOLOGY_LINE
= 1,
840 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
= 2,
841 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW
= 3,
844 enum brw_tess_domain
{
845 BRW_TESS_DOMAIN_QUAD
= 0,
846 BRW_TESS_DOMAIN_TRI
= 1,
847 BRW_TESS_DOMAIN_ISOLINE
= 2,
851 struct brw_vue_prog_data
{
852 struct brw_stage_prog_data base
;
853 struct brw_vue_map vue_map
;
855 /** Should the hardware deliver input VUE handles for URB pull loads? */
856 bool include_vue_handles
;
858 GLuint urb_read_length
;
861 uint32_t clip_distance_mask
;
862 uint32_t cull_distance_mask
;
864 /* Used for calculating urb partitions. In the VS, this is the size of the
865 * URB entry used for both input and output to the thread. In the GS, this
866 * is the size of the URB entry used for output.
868 GLuint urb_entry_size
;
870 enum shader_dispatch_mode dispatch_mode
;
873 struct brw_vs_prog_data
{
874 struct brw_vue_prog_data base
;
876 GLbitfield64 inputs_read
;
877 GLbitfield64 double_inputs_read
;
879 unsigned nr_attributes
;
880 unsigned nr_attribute_slots
;
883 bool uses_instanceid
;
884 bool uses_basevertex
;
885 bool uses_baseinstance
;
889 struct brw_tcs_prog_data
891 struct brw_vue_prog_data base
;
893 /** Number vertices in output patch */
898 struct brw_tes_prog_data
900 struct brw_vue_prog_data base
;
902 enum brw_tess_partitioning partitioning
;
903 enum brw_tess_output_topology output_topology
;
904 enum brw_tess_domain domain
;
907 struct brw_gs_prog_data
909 struct brw_vue_prog_data base
;
911 unsigned vertices_in
;
914 * Size of an output vertex, measured in HWORDS (32 bytes).
916 unsigned output_vertex_size_hwords
;
918 unsigned output_topology
;
921 * Size of the control data (cut bits or StreamID bits), in hwords (32
922 * bytes). 0 if there is no control data.
924 unsigned control_data_header_size_hwords
;
927 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
928 * if the control data is StreamID bits, or
929 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
930 * Ignored if control_data_header_size is 0.
932 unsigned control_data_format
;
934 bool include_primitive_id
;
937 * The number of vertices emitted, if constant - otherwise -1.
939 int static_vertex_count
;
944 * Gen6: Provoking vertex convention for odd-numbered triangles
950 * Gen6: Number of varyings that are output to transform feedback.
952 GLuint num_transform_feedback_bindings
:7; /* 0-BRW_MAX_SOL_BINDINGS */
955 * Gen6: Map from the index of a transform feedback binding table entry to the
956 * gl_varying_slot that should be streamed out through that binding table
959 unsigned char transform_feedback_bindings
[64 /* BRW_MAX_SOL_BINDINGS */];
962 * Gen6: Map from the index of a transform feedback binding table entry to the
963 * swizzles that should be used when streaming out data through that
964 * binding table entry.
966 unsigned char transform_feedback_swizzles
[64 /* BRW_MAX_SOL_BINDINGS */];
969 struct brw_sf_prog_data
{
970 uint32_t urb_read_length
;
973 /* Each vertex may have upto 12 attributes, 4 components each,
974 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
977 * Actually we use 4 for each, so call it 12 rows.
979 unsigned urb_entry_size
;
982 struct brw_clip_prog_data
{
983 uint32_t curb_read_length
; /* user planes? */
985 uint32_t urb_read_length
;
989 #define DEFINE_PROG_DATA_DOWNCAST(stage) \
990 static inline struct brw_##stage##_prog_data * \
991 brw_##stage##_prog_data(struct brw_stage_prog_data *prog_data) \
993 return (struct brw_##stage##_prog_data *) prog_data; \
995 DEFINE_PROG_DATA_DOWNCAST(vue
)
996 DEFINE_PROG_DATA_DOWNCAST(vs
)
997 DEFINE_PROG_DATA_DOWNCAST(tcs
)
998 DEFINE_PROG_DATA_DOWNCAST(tes
)
999 DEFINE_PROG_DATA_DOWNCAST(gs
)
1000 DEFINE_PROG_DATA_DOWNCAST(wm
)
1001 DEFINE_PROG_DATA_DOWNCAST(cs
)
1002 DEFINE_PROG_DATA_DOWNCAST(ff_gs
)
1003 DEFINE_PROG_DATA_DOWNCAST(clip
)
1004 DEFINE_PROG_DATA_DOWNCAST(sf
)
1005 #undef DEFINE_PROG_DATA_DOWNCAST
1009 struct brw_compiler
*
1010 brw_compiler_create(void *mem_ctx
, const struct gen_device_info
*devinfo
);
1013 * Compile a vertex shader.
1015 * Returns the final assembly and the program's size.
1018 brw_compile_vs(const struct brw_compiler
*compiler
, void *log_data
,
1020 const struct brw_vs_prog_key
*key
,
1021 struct brw_vs_prog_data
*prog_data
,
1022 const struct nir_shader
*shader
,
1023 gl_clip_plane
*clip_planes
,
1024 bool use_legacy_snorm_formula
,
1025 int shader_time_index
,
1026 unsigned *final_assembly_size
,
1030 * Compile a tessellation control shader.
1032 * Returns the final assembly and the program's size.
1035 brw_compile_tcs(const struct brw_compiler
*compiler
,
1038 const struct brw_tcs_prog_key
*key
,
1039 struct brw_tcs_prog_data
*prog_data
,
1040 const struct nir_shader
*nir
,
1041 int shader_time_index
,
1042 unsigned *final_assembly_size
,
1046 * Compile a tessellation evaluation shader.
1048 * Returns the final assembly and the program's size.
1051 brw_compile_tes(const struct brw_compiler
*compiler
, void *log_data
,
1053 const struct brw_tes_prog_key
*key
,
1054 const struct brw_vue_map
*input_vue_map
,
1055 struct brw_tes_prog_data
*prog_data
,
1056 const struct nir_shader
*shader
,
1057 struct gl_program
*prog
,
1058 int shader_time_index
,
1059 unsigned *final_assembly_size
,
1063 * Compile a vertex shader.
1065 * Returns the final assembly and the program's size.
1068 brw_compile_gs(const struct brw_compiler
*compiler
, void *log_data
,
1070 const struct brw_gs_prog_key
*key
,
1071 struct brw_gs_prog_data
*prog_data
,
1072 const struct nir_shader
*shader
,
1073 struct gl_program
*prog
,
1074 int shader_time_index
,
1075 unsigned *final_assembly_size
,
1079 * Compile a strips and fans shader.
1081 * This is a fixed-function shader determined entirely by the shader key and
1084 * Returns the final assembly and the program's size.
1087 brw_compile_sf(const struct brw_compiler
*compiler
,
1089 const struct brw_sf_prog_key
*key
,
1090 struct brw_sf_prog_data
*prog_data
,
1091 struct brw_vue_map
*vue_map
,
1092 unsigned *final_assembly_size
);
1095 * Compile a clipper shader.
1097 * This is a fixed-function shader determined entirely by the shader key and
1100 * Returns the final assembly and the program's size.
1103 brw_compile_clip(const struct brw_compiler
*compiler
,
1105 const struct brw_clip_prog_key
*key
,
1106 struct brw_clip_prog_data
*prog_data
,
1107 struct brw_vue_map
*vue_map
,
1108 unsigned *final_assembly_size
);
1111 * Compile a fragment shader.
1113 * Returns the final assembly and the program's size.
1116 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
1118 const struct brw_wm_prog_key
*key
,
1119 struct brw_wm_prog_data
*prog_data
,
1120 const struct nir_shader
*shader
,
1121 struct gl_program
*prog
,
1122 int shader_time_index8
,
1123 int shader_time_index16
,
1124 bool allow_spilling
,
1125 bool use_rep_send
, struct brw_vue_map
*vue_map
,
1126 unsigned *final_assembly_size
,
1130 * Compile a compute shader.
1132 * Returns the final assembly and the program's size.
1135 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
1137 const struct brw_cs_prog_key
*key
,
1138 struct brw_cs_prog_data
*prog_data
,
1139 const struct nir_shader
*shader
,
1140 int shader_time_index
,
1141 unsigned *final_assembly_size
,
1144 static inline uint32_t
1145 encode_slm_size(unsigned gen
, uint32_t bytes
)
1147 uint32_t slm_size
= 0;
1149 /* Shared Local Memory is specified as powers of two, and encoded in
1150 * INTERFACE_DESCRIPTOR_DATA with the following representations:
1152 * Size | 0 kB | 1 kB | 2 kB | 4 kB | 8 kB | 16 kB | 32 kB | 64 kB |
1153 * -------------------------------------------------------------------
1154 * Gen7-8 | 0 | none | none | 1 | 2 | 4 | 8 | 16 |
1155 * -------------------------------------------------------------------
1156 * Gen9+ | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
1158 assert(bytes
<= 64 * 1024);
1161 /* Shared Local Memory Size is specified as powers of two. */
1162 slm_size
= util_next_power_of_two(bytes
);
1165 /* Use a minimum of 1kB; turn an exponent of 10 (1024 kB) into 1. */
1166 slm_size
= ffs(MAX2(slm_size
, 1024)) - 10;
1168 /* Use a minimum of 4kB; convert to the pre-Gen9 representation. */
1169 slm_size
= MAX2(slm_size
, 4096) / 4096;
1177 * Return true if the given shader stage is dispatched contiguously by the
1178 * relevant fixed function starting from channel 0 of the SIMD thread, which
1179 * implies that the dispatch mask of a thread can be assumed to have the form
1180 * '2^n - 1' for some n.
1183 brw_stage_has_packed_dispatch(const struct gen_device_info
*devinfo
,
1184 gl_shader_stage stage
,
1185 const struct brw_stage_prog_data
*prog_data
)
1187 /* The code below makes assumptions about the hardware's thread dispatch
1188 * behavior that could be proven wrong in future generations -- Make sure
1189 * to do a full test run with brw_fs_test_dispatch_packing() hooked up to
1190 * the NIR front-end before changing this assertion.
1192 assert(devinfo
->gen
<= 10);
1195 case MESA_SHADER_FRAGMENT
: {
1196 /* The PSD discards subspans coming in with no lit samples, which in the
1197 * per-pixel shading case implies that each subspan will either be fully
1198 * lit (due to the VMask being used to allow derivative computations),
1199 * or not dispatched at all. In per-sample dispatch mode individual
1200 * samples from the same subspan have a fixed relative location within
1201 * the SIMD thread, so dispatch of unlit samples cannot be avoided in
1202 * general and we should return false.
1204 const struct brw_wm_prog_data
*wm_prog_data
=
1205 (const struct brw_wm_prog_data
*)prog_data
;
1206 return !wm_prog_data
->persample_dispatch
;
1208 case MESA_SHADER_COMPUTE
:
1209 /* Compute shaders will be spawned with either a fully enabled dispatch
1210 * mask or with whatever bottom/right execution mask was given to the
1211 * GPGPU walker command to be used along the workgroup edges -- In both
1212 * cases the dispatch mask is required to be tightly packed for our
1213 * invocation index calculations to work.
1217 /* Most remaining fixed functions are limited to use a packed dispatch
1218 * mask due to the hardware representation of the dispatch mask as a
1219 * single counter representing the number of enabled channels.
1226 * Computes the first varying slot in the URB produced by the previous stage
1227 * that is used in the next stage. We do this by testing the varying slots in
1228 * the previous stage's vue map against the inputs read in the next stage.
1232 * - Each URB offset contains two varying slots and we can only skip a
1233 * full offset if both slots are unused, so the value we return here is always
1234 * rounded down to the closest multiple of two.
1236 * - gl_Layer and gl_ViewportIndex don't have their own varying slots, they are
1237 * part of the vue header, so if these are read we can't skip anything.
1240 brw_compute_first_urb_slot_required(uint64_t inputs_read
,
1241 const struct brw_vue_map
*prev_stage_vue_map
)
1243 if ((inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
)) == 0) {
1244 for (int i
= 0; i
< prev_stage_vue_map
->num_slots
; i
++) {
1245 int varying
= prev_stage_vue_map
->slot_to_varying
[i
];
1246 if (varying
> 0 && (inputs_read
& BITFIELD64_BIT(varying
)) != 0)
1247 return ROUND_DOWN_TO(i
, 2);
1258 #endif /* BRW_COMPILER_H */