2 * Copyright © 2010 - 2015 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #ifndef BRW_COMPILER_H
25 #define BRW_COMPILER_H
28 #include "dev/gen_device_info.h"
29 #include "main/macros.h"
30 #include "main/mtypes.h"
31 #include "util/ralloc.h"
42 const struct gen_device_info
*devinfo
;
48 * Array of the ra classes for the unaligned contiguous register
54 * Mapping for register-allocated objects in *regs to the first
55 * GRF for that object.
57 uint8_t *ra_reg_to_grf
;
64 * Array of the ra classes for the unaligned contiguous register
65 * block sizes used, indexed by register size.
70 * Mapping from classes to ra_reg ranges. Each of the per-size
71 * classes corresponds to a range of ra_reg nodes. This array stores
72 * those ranges in the form of first ra_reg in each class and the
73 * total number of ra_reg elements in the last array element. This
74 * way the range of the i'th class is given by:
75 * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] )
77 int class_to_ra_reg_range
[17];
80 * Mapping for register-allocated objects in *regs to the first
81 * GRF for that object.
83 uint8_t *ra_reg_to_grf
;
86 * ra class for the aligned pairs we use for PLN, which doesn't
89 int aligned_pairs_class
;
92 void (*shader_debug_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
93 void (*shader_perf_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
95 bool scalar_stage
[MESA_SHADER_STAGES
];
96 struct gl_shader_compiler_options glsl_compiler_options
[MESA_SHADER_STAGES
];
99 * Apply workarounds for SIN and COS output range problems.
100 * This can negatively impact performance.
105 * Is 3DSTATE_CONSTANT_*'s Constant Buffer 0 relative to Dynamic State
106 * Base Address? (If not, it's a normal GPU address.)
108 bool constant_buffer_0_is_relative
;
111 * Whether or not the driver supports pull constants. If not, the compiler
112 * will attempt to push everything.
114 bool supports_pull_constants
;
117 * Whether or not the driver supports NIR shader constants. This controls
118 * whether nir_opt_large_constants will be run.
120 bool supports_shader_constants
;
124 * We use a constant subgroup size of 32. It really only needs to be a
125 * maximum and, since we do SIMD32 for compute shaders in some cases, it
126 * needs to be at least 32. SIMD8 and SIMD16 shaders will still claim a
127 * subgroup size of 32 but will act as if 16 or 24 of those channels are
130 #define BRW_SUBGROUP_SIZE 32
133 * Program key structures.
135 * When drawing, we look for the currently bound shaders in the program
136 * cache. This is essentially a hash table lookup, and these are the keys.
138 * Sometimes OpenGL features specified as state need to be simulated via
139 * shader code, due to a mismatch between the API and the hardware. This
140 * is often referred to as "non-orthagonal state" or "NOS". We store NOS
141 * in the program key so it's considered when searching for a program. If
142 * we haven't seen a particular combination before, we have to recompile a
143 * new specialized version.
145 * Shader compilation should not look up state in gl_context directly, but
146 * instead use the copy in the program key. This guarantees recompiles will
152 enum PACKED gen6_gather_sampler_wa
{
153 WA_SIGN
= 1, /* whether we need to sign extend */
154 WA_8BIT
= 2, /* if we have an 8bit format needing wa */
155 WA_16BIT
= 4, /* if we have a 16bit format needing wa */
159 * Sampler information needed by VS, WM, and GS program cache keys.
161 struct brw_sampler_prog_key_data
{
163 * EXT_texture_swizzle and DEPTH_TEXTURE_MODE swizzles.
165 uint16_t swizzles
[MAX_SAMPLERS
];
167 uint32_t gl_clamp_mask
[3];
170 * For RG32F, gather4's channel select is broken.
172 uint32_t gather_channel_quirk_mask
;
175 * Whether this sampler uses the compressed multisample surface layout.
177 uint32_t compressed_multisample_layout_mask
;
180 * Whether this sampler is using 16x multisampling. If so fetching from
181 * this sampler will be handled with a different instruction, ld2dms_w
187 * For Sandybridge, which shader w/a we need for gather quirks.
189 enum gen6_gather_sampler_wa gen6_gather_wa
[MAX_SAMPLERS
];
192 * Texture units that have a YUV image bound.
194 uint32_t y_u_v_image_mask
;
195 uint32_t y_uv_image_mask
;
196 uint32_t yx_xuxv_image_mask
;
197 uint32_t xy_uxvx_image_mask
;
198 uint32_t ayuv_image_mask
;
199 uint32_t xyuv_image_mask
;
201 /* Scale factor for each texture. */
202 float scale_factors
[32];
206 * The VF can't natively handle certain types of attributes, such as GL_FIXED
207 * or most 10_10_10_2 types. These flags enable various VS workarounds to
208 * "fix" attributes at the beginning of shaders.
210 #define BRW_ATTRIB_WA_COMPONENT_MASK 7 /* mask for GL_FIXED scale channel count */
211 #define BRW_ATTRIB_WA_NORMALIZE 8 /* normalize in shader */
212 #define BRW_ATTRIB_WA_BGRA 16 /* swap r/b channels in shader */
213 #define BRW_ATTRIB_WA_SIGN 32 /* interpret as signed in shader */
214 #define BRW_ATTRIB_WA_SCALE 64 /* interpret as scaled in shader */
217 * OpenGL attribute slots fall in [0, VERT_ATTRIB_MAX - 1] with the range
218 * [VERT_ATTRIB_GENERIC0, VERT_ATTRIB_MAX - 1] reserved for up to 16 user
219 * input vertex attributes. In Vulkan, we expose up to 28 user vertex input
220 * attributes that are mapped to slots also starting at VERT_ATTRIB_GENERIC0.
222 #define MAX_GL_VERT_ATTRIB VERT_ATTRIB_MAX
223 #define MAX_VK_VERT_ATTRIB (VERT_ATTRIB_GENERIC0 + 28)
225 /** The program key for Vertex Shaders. */
226 struct brw_vs_prog_key
{
227 unsigned program_string_id
;
230 * Per-attribute workaround flags
232 * For each attribute, a combination of BRW_ATTRIB_WA_*.
234 * For OpenGL, where we expose a maximum of 16 user input atttributes
235 * we only need up to VERT_ATTRIB_MAX slots, however, in Vulkan
236 * slots preceding VERT_ATTRIB_GENERIC0 are unused and we can
237 * expose up to 28 user input vertex attributes that are mapped to slots
238 * starting at VERT_ATTRIB_GENERIC0, so this array needs to be large
239 * enough to hold this many slots.
241 uint8_t gl_attrib_wa_flags
[MAX2(MAX_GL_VERT_ATTRIB
, MAX_VK_VERT_ATTRIB
)];
243 bool copy_edgeflag
:1;
245 bool clamp_vertex_color
:1;
248 * How many user clipping planes are being uploaded to the vertex shader as
251 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
254 unsigned nr_userclip_plane_consts
:4;
257 * For pre-Gen6 hardware, a bitfield indicating which texture coordinates
258 * are going to be replaced with point coordinates (as a consequence of a
259 * call to glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)). Because
260 * our SF thread requires exact matching between VS outputs and FS inputs,
261 * these texture coordinates will need to be unconditionally included in
262 * the VUE, even if they aren't written by the vertex shader.
264 uint8_t point_coord_replace
;
266 struct brw_sampler_prog_key_data tex
;
269 /** The program key for Tessellation Control Shaders. */
270 struct brw_tcs_prog_key
272 unsigned program_string_id
;
274 GLenum tes_primitive_mode
;
276 unsigned input_vertices
;
278 /** A bitfield of per-patch outputs written. */
279 uint32_t patch_outputs_written
;
281 /** A bitfield of per-vertex outputs written. */
282 uint64_t outputs_written
;
284 bool quads_workaround
;
286 struct brw_sampler_prog_key_data tex
;
289 /** The program key for Tessellation Evaluation Shaders. */
290 struct brw_tes_prog_key
292 unsigned program_string_id
;
294 /** A bitfield of per-patch inputs read. */
295 uint32_t patch_inputs_read
;
297 /** A bitfield of per-vertex inputs read. */
298 uint64_t inputs_read
;
300 struct brw_sampler_prog_key_data tex
;
303 /** The program key for Geometry Shaders. */
304 struct brw_gs_prog_key
306 unsigned program_string_id
;
308 struct brw_sampler_prog_key_data tex
;
311 enum brw_sf_primitive
{
312 BRW_SF_PRIM_POINTS
= 0,
313 BRW_SF_PRIM_LINES
= 1,
314 BRW_SF_PRIM_TRIANGLES
= 2,
315 BRW_SF_PRIM_UNFILLED_TRIS
= 3,
318 struct brw_sf_prog_key
{
320 bool contains_flat_varying
;
321 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
322 uint8_t point_sprite_coord_replace
;
323 enum brw_sf_primitive primitive
:2;
324 bool do_twoside_color
:1;
325 bool frontface_ccw
:1;
326 bool do_point_sprite
:1;
327 bool do_point_coord
:1;
328 bool sprite_origin_lower_left
:1;
329 bool userclip_active
:1;
333 BRW_CLIP_MODE_NORMAL
= 0,
334 BRW_CLIP_MODE_CLIP_ALL
= 1,
335 BRW_CLIP_MODE_CLIP_NON_REJECTED
= 2,
336 BRW_CLIP_MODE_REJECT_ALL
= 3,
337 BRW_CLIP_MODE_ACCEPT_ALL
= 4,
338 BRW_CLIP_MODE_KERNEL_CLIP
= 5,
341 enum brw_clip_fill_mode
{
342 BRW_CLIP_FILL_MODE_LINE
= 0,
343 BRW_CLIP_FILL_MODE_POINT
= 1,
344 BRW_CLIP_FILL_MODE_FILL
= 2,
345 BRW_CLIP_FILL_MODE_CULL
= 3,
348 /* Note that if unfilled primitives are being emitted, we have to fix
349 * up polygon offset and flatshading at this point:
351 struct brw_clip_prog_key
{
353 bool contains_flat_varying
;
354 bool contains_noperspective_varying
;
355 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
356 unsigned primitive
:4;
357 unsigned nr_userclip
:4;
360 enum brw_clip_fill_mode fill_cw
:2; /* includes cull information */
361 enum brw_clip_fill_mode fill_ccw
:2; /* includes cull information */
366 enum brw_clip_mode clip_mode
:3;
373 /* A big lookup table is used to figure out which and how many
374 * additional regs will inserted before the main payload in the WM
375 * program execution. These mainly relate to depth and stencil
376 * processing and the early-depth-test optimization.
378 enum brw_wm_iz_bits
{
379 BRW_WM_IZ_PS_KILL_ALPHATEST_BIT
= 0x1,
380 BRW_WM_IZ_PS_COMPUTES_DEPTH_BIT
= 0x2,
381 BRW_WM_IZ_DEPTH_WRITE_ENABLE_BIT
= 0x4,
382 BRW_WM_IZ_DEPTH_TEST_ENABLE_BIT
= 0x8,
383 BRW_WM_IZ_STENCIL_WRITE_ENABLE_BIT
= 0x10,
384 BRW_WM_IZ_STENCIL_TEST_ENABLE_BIT
= 0x20,
385 BRW_WM_IZ_BIT_MAX
= 0x40
388 enum brw_wm_aa_enable
{
394 /** The program key for Fragment/Pixel Shaders. */
395 struct brw_wm_prog_key
{
396 /* Some collection of BRW_WM_IZ_* */
400 unsigned nr_color_regions
:5;
401 bool replicate_alpha
:1;
402 bool clamp_fragment_color
:1;
403 bool persample_interp
:1;
404 bool multisample_fbo
:1;
405 bool frag_coord_adds_sample_pos
:1;
406 enum brw_wm_aa_enable line_aa
:2;
407 bool high_quality_derivatives
:1;
408 bool force_dual_color_blend
:1;
409 bool coherent_fb_fetch
:1;
411 uint8_t color_outputs_valid
;
412 uint64_t input_slots_valid
;
413 unsigned program_string_id
;
414 GLenum alpha_test_func
; /* < For Gen4/5 MRT alpha test */
415 float alpha_test_ref
;
417 struct brw_sampler_prog_key_data tex
;
420 struct brw_cs_prog_key
{
421 uint32_t program_string_id
;
422 struct brw_sampler_prog_key_data tex
;
425 /* brw_any_prog_key is any of the keys that map to an API stage */
426 union brw_any_prog_key
{
427 struct brw_vs_prog_key vs
;
428 struct brw_tcs_prog_key tcs
;
429 struct brw_tes_prog_key tes
;
430 struct brw_gs_prog_key gs
;
431 struct brw_wm_prog_key wm
;
432 struct brw_cs_prog_key cs
;
436 * Image metadata structure as laid out in the shader parameter
437 * buffer. Entries have to be 16B-aligned for the vec4 back-end to be
438 * able to use them. That's okay because the padding and any unused
439 * entries [most of them except when we're doing untyped surface
440 * access] will be removed by the uniform packing pass.
442 #define BRW_IMAGE_PARAM_OFFSET_OFFSET 0
443 #define BRW_IMAGE_PARAM_SIZE_OFFSET 4
444 #define BRW_IMAGE_PARAM_STRIDE_OFFSET 8
445 #define BRW_IMAGE_PARAM_TILING_OFFSET 12
446 #define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 16
447 #define BRW_IMAGE_PARAM_SIZE 20
449 struct brw_image_param
{
450 /** Offset applied to the X and Y surface coordinates. */
453 /** Surface X, Y and Z dimensions. */
456 /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
457 * pixels, vertical slice stride in pixels.
461 /** Log2 of the tiling modulus in the X, Y and Z dimension. */
465 * Right shift to apply for bit 6 address swizzling. Two different
466 * swizzles can be specified and will be applied one after the other. The
467 * resulting address will be:
469 * addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
470 * (addr >> swizzling[1])))
472 * Use \c 0xff if any of the swizzles is not required.
474 uint32_t swizzling
[2];
477 /** Max number of render targets in a shader */
478 #define BRW_MAX_DRAW_BUFFERS 8
481 * Max number of binding table entries used for stream output.
483 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
484 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
486 * On Gen6, the size of transform feedback data is limited not by the number
487 * of components but by the number of binding table entries we set aside. We
488 * use one binding table entry for a float, one entry for a vector, and one
489 * entry per matrix column. Since the only way we can communicate our
490 * transform feedback capabilities to the client is via
491 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
492 * worst case, in which all the varyings are floats, so we use up one binding
493 * table entry per component. Therefore we need to set aside at least 64
494 * binding table entries for use by transform feedback.
496 * Note: since we don't currently pack varyings, it is currently impossible
497 * for the client to actually use up all of these binding table entries--if
498 * all of their varyings were floats, they would run out of varying slots and
499 * fail to link. But that's a bug, so it seems prudent to go ahead and
500 * allocate the number of binding table entries we will need once the bug is
503 #define BRW_MAX_SOL_BINDINGS 64
506 * Binding table index for the first gen6 SOL binding.
508 #define BRW_GEN6_SOL_BINDING_START 0
511 * Stride in bytes between shader_time entries.
513 * We separate entries by a cacheline to reduce traffic between EUs writing to
516 #define BRW_SHADER_TIME_STRIDE 64
525 /* We reserve the first 2^16 values for builtins */
526 #define BRW_PARAM_IS_BUILTIN(param) (((param) & 0xffff0000) == 0)
528 enum brw_param_builtin
{
529 BRW_PARAM_BUILTIN_ZERO
,
531 BRW_PARAM_BUILTIN_CLIP_PLANE_0_X
,
532 BRW_PARAM_BUILTIN_CLIP_PLANE_0_Y
,
533 BRW_PARAM_BUILTIN_CLIP_PLANE_0_Z
,
534 BRW_PARAM_BUILTIN_CLIP_PLANE_0_W
,
535 BRW_PARAM_BUILTIN_CLIP_PLANE_1_X
,
536 BRW_PARAM_BUILTIN_CLIP_PLANE_1_Y
,
537 BRW_PARAM_BUILTIN_CLIP_PLANE_1_Z
,
538 BRW_PARAM_BUILTIN_CLIP_PLANE_1_W
,
539 BRW_PARAM_BUILTIN_CLIP_PLANE_2_X
,
540 BRW_PARAM_BUILTIN_CLIP_PLANE_2_Y
,
541 BRW_PARAM_BUILTIN_CLIP_PLANE_2_Z
,
542 BRW_PARAM_BUILTIN_CLIP_PLANE_2_W
,
543 BRW_PARAM_BUILTIN_CLIP_PLANE_3_X
,
544 BRW_PARAM_BUILTIN_CLIP_PLANE_3_Y
,
545 BRW_PARAM_BUILTIN_CLIP_PLANE_3_Z
,
546 BRW_PARAM_BUILTIN_CLIP_PLANE_3_W
,
547 BRW_PARAM_BUILTIN_CLIP_PLANE_4_X
,
548 BRW_PARAM_BUILTIN_CLIP_PLANE_4_Y
,
549 BRW_PARAM_BUILTIN_CLIP_PLANE_4_Z
,
550 BRW_PARAM_BUILTIN_CLIP_PLANE_4_W
,
551 BRW_PARAM_BUILTIN_CLIP_PLANE_5_X
,
552 BRW_PARAM_BUILTIN_CLIP_PLANE_5_Y
,
553 BRW_PARAM_BUILTIN_CLIP_PLANE_5_Z
,
554 BRW_PARAM_BUILTIN_CLIP_PLANE_5_W
,
555 BRW_PARAM_BUILTIN_CLIP_PLANE_6_X
,
556 BRW_PARAM_BUILTIN_CLIP_PLANE_6_Y
,
557 BRW_PARAM_BUILTIN_CLIP_PLANE_6_Z
,
558 BRW_PARAM_BUILTIN_CLIP_PLANE_6_W
,
559 BRW_PARAM_BUILTIN_CLIP_PLANE_7_X
,
560 BRW_PARAM_BUILTIN_CLIP_PLANE_7_Y
,
561 BRW_PARAM_BUILTIN_CLIP_PLANE_7_Z
,
562 BRW_PARAM_BUILTIN_CLIP_PLANE_7_W
,
564 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
,
565 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Y
,
566 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Z
,
567 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_W
,
568 BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
,
569 BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y
,
571 BRW_PARAM_BUILTIN_PATCH_VERTICES_IN
,
573 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_X
,
574 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Y
,
575 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Z
,
576 BRW_PARAM_BUILTIN_SUBGROUP_ID
,
579 #define BRW_PARAM_BUILTIN_CLIP_PLANE(idx, comp) \
580 (BRW_PARAM_BUILTIN_CLIP_PLANE_0_X + ((idx) << 2) + (comp))
582 #define BRW_PARAM_BUILTIN_IS_CLIP_PLANE(param) \
583 ((param) >= BRW_PARAM_BUILTIN_CLIP_PLANE_0_X && \
584 (param) <= BRW_PARAM_BUILTIN_CLIP_PLANE_7_W)
586 #define BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(param) \
587 (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) >> 2)
589 #define BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(param) \
590 (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) & 0x3)
592 struct brw_stage_prog_data
{
594 /** size of our binding table. */
598 * surface indices for the various groups of surfaces
600 uint32_t pull_constants_start
;
601 uint32_t texture_start
;
602 uint32_t gather_texture_start
;
605 uint32_t image_start
;
606 uint32_t shader_time_start
;
607 uint32_t plane_start
[3];
611 struct brw_ubo_range ubo_ranges
[4];
613 GLuint nr_params
; /**< number of float params/constants */
614 GLuint nr_pull_params
;
616 unsigned curb_read_length
;
617 unsigned total_scratch
;
618 unsigned total_shared
;
620 unsigned program_size
;
623 * Register where the thread expects to find input data from the URB
624 * (typically uniforms, followed by vertex or fragment attributes).
626 unsigned dispatch_grf_start_reg
;
628 bool use_alt_mode
; /**< Use ALT floating point mode? Otherwise, IEEE. */
630 /* 32-bit identifiers for all push/pull parameters. These can be anything
631 * the driver wishes them to be; the core of the back-end compiler simply
632 * re-arranges them. The one restriction is that the bottom 2^16 values
633 * are reserved for builtins defined in the brw_param_builtin enum defined
637 uint32_t *pull_param
;
640 static inline uint32_t *
641 brw_stage_prog_data_add_params(struct brw_stage_prog_data
*prog_data
,
642 unsigned nr_new_params
)
644 unsigned old_nr_params
= prog_data
->nr_params
;
645 prog_data
->nr_params
+= nr_new_params
;
646 prog_data
->param
= reralloc(ralloc_parent(prog_data
->param
),
647 prog_data
->param
, uint32_t,
648 prog_data
->nr_params
);
649 return prog_data
->param
+ old_nr_params
;
652 enum brw_barycentric_mode
{
653 BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
= 0,
654 BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
= 1,
655 BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
= 2,
656 BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL
= 3,
657 BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
= 4,
658 BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE
= 5,
659 BRW_BARYCENTRIC_MODE_COUNT
= 6
661 #define BRW_BARYCENTRIC_NONPERSPECTIVE_BITS \
662 ((1 << BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL) | \
663 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID) | \
664 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE))
666 enum brw_pixel_shader_computed_depth_mode
{
667 BRW_PSCDEPTH_OFF
= 0, /* PS does not compute depth */
668 BRW_PSCDEPTH_ON
= 1, /* PS computes depth; no guarantee about value */
669 BRW_PSCDEPTH_ON_GE
= 2, /* PS guarantees output depth >= source depth */
670 BRW_PSCDEPTH_ON_LE
= 3, /* PS guarantees output depth <= source depth */
673 /* Data about a particular attempt to compile a program. Note that
674 * there can be many of these, each in a different GL state
675 * corresponding to a different brw_wm_prog_key struct, with different
678 struct brw_wm_prog_data
{
679 struct brw_stage_prog_data base
;
681 GLuint num_varying_inputs
;
683 uint8_t reg_blocks_8
;
684 uint8_t reg_blocks_16
;
685 uint8_t reg_blocks_32
;
687 uint8_t dispatch_grf_start_reg_16
;
688 uint8_t dispatch_grf_start_reg_32
;
689 uint32_t prog_offset_16
;
690 uint32_t prog_offset_32
;
694 * surface indices the WM-specific surfaces
696 uint32_t render_target_read_start
;
700 uint8_t computed_depth_mode
;
701 bool computed_stencil
;
703 bool early_fragment_tests
;
704 bool post_depth_coverage
;
710 bool persample_dispatch
;
711 bool uses_pos_offset
;
716 bool uses_sample_mask
;
717 bool has_render_target_reads
;
718 bool has_side_effects
;
721 bool contains_flat_varying
;
722 bool contains_noperspective_varying
;
725 * Mask of which interpolation modes are required by the fragment shader.
726 * Used in hardware setup on gen6+.
728 uint32_t barycentric_interp_modes
;
731 * Mask of which FS inputs are marked flat by the shader source. This is
732 * needed for setting up 3DSTATE_SF/SBE.
734 uint32_t flat_inputs
;
736 /* Mapping of VUE slots to interpolation modes.
737 * Used by the Gen4-5 clip/sf/wm stages.
739 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
742 * Map from gl_varying_slot to the position within the FS setup data
743 * payload where the varying's attribute vertex deltas should be delivered.
744 * For varying slots that are not used by the FS, the value is -1.
746 int urb_setup
[VARYING_SLOT_MAX
];
749 /** Returns the SIMD width corresponding to a given KSP index
751 * The "Variable Pixel Dispatch" table in the PRM (which can be found, for
752 * example in Vol. 7 of the SKL PRM) has a mapping from dispatch widths to
753 * kernel start pointer (KSP) indices that is based on what dispatch widths
754 * are enabled. This function provides, effectively, the reverse mapping.
756 * If the given KSP is valid with respect to the SIMD8/16/32 enables, a SIMD
757 * width of 8, 16, or 32 is returned. If the KSP is invalid, 0 is returned.
759 static inline unsigned
760 brw_fs_simd_width_for_ksp(unsigned ksp_idx
, bool simd8_enabled
,
761 bool simd16_enabled
, bool simd32_enabled
)
763 /* This function strictly ignores contiguous dispatch */
766 return simd8_enabled
? 8 :
767 (simd16_enabled
&& !simd32_enabled
) ? 16 :
768 (simd32_enabled
&& !simd16_enabled
) ? 32 : 0;
770 return (simd32_enabled
&& (simd16_enabled
|| simd8_enabled
)) ? 32 : 0;
772 return (simd16_enabled
&& (simd32_enabled
|| simd8_enabled
)) ? 16 : 0;
774 unreachable("Invalid KSP index");
778 #define brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx) \
779 brw_fs_simd_width_for_ksp((ksp_idx), (wm_state)._8PixelDispatchEnable, \
780 (wm_state)._16PixelDispatchEnable, \
781 (wm_state)._32PixelDispatchEnable)
783 #define brw_wm_state_has_ksp(wm_state, ksp_idx) \
784 (brw_wm_state_simd_width_for_ksp((wm_state), (ksp_idx)) != 0)
786 static inline uint32_t
787 _brw_wm_prog_data_prog_offset(const struct brw_wm_prog_data
*prog_data
,
790 switch (simd_width
) {
792 case 16: return prog_data
->prog_offset_16
;
793 case 32: return prog_data
->prog_offset_32
;
798 #define brw_wm_prog_data_prog_offset(prog_data, wm_state, ksp_idx) \
799 _brw_wm_prog_data_prog_offset(prog_data, \
800 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
802 static inline uint8_t
803 _brw_wm_prog_data_dispatch_grf_start_reg(const struct brw_wm_prog_data
*prog_data
,
806 switch (simd_width
) {
807 case 8: return prog_data
->base
.dispatch_grf_start_reg
;
808 case 16: return prog_data
->dispatch_grf_start_reg_16
;
809 case 32: return prog_data
->dispatch_grf_start_reg_32
;
814 #define brw_wm_prog_data_dispatch_grf_start_reg(prog_data, wm_state, ksp_idx) \
815 _brw_wm_prog_data_dispatch_grf_start_reg(prog_data, \
816 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
818 static inline uint8_t
819 _brw_wm_prog_data_reg_blocks(const struct brw_wm_prog_data
*prog_data
,
822 switch (simd_width
) {
823 case 8: return prog_data
->reg_blocks_8
;
824 case 16: return prog_data
->reg_blocks_16
;
825 case 32: return prog_data
->reg_blocks_32
;
830 #define brw_wm_prog_data_reg_blocks(prog_data, wm_state, ksp_idx) \
831 _brw_wm_prog_data_reg_blocks(prog_data, \
832 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
834 struct brw_push_const_block
{
835 unsigned dwords
; /* Dword count, not reg aligned */
837 unsigned size
; /* Bytes, register aligned */
840 struct brw_cs_prog_data
{
841 struct brw_stage_prog_data base
;
843 unsigned local_size
[3];
847 bool uses_num_work_groups
;
850 struct brw_push_const_block cross_thread
;
851 struct brw_push_const_block per_thread
;
852 struct brw_push_const_block total
;
857 * surface indices the CS-specific surfaces
859 uint32_t work_groups_start
;
865 * Enum representing the i965-specific vertex results that don't correspond
866 * exactly to any element of gl_varying_slot. The values of this enum are
867 * assigned such that they don't conflict with gl_varying_slot.
871 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
872 BRW_VARYING_SLOT_PAD
,
874 * Technically this is not a varying but just a placeholder that
875 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
876 * builtin variable to be compiled correctly. see compile_sf_prog() for
879 BRW_VARYING_SLOT_PNTC
,
880 BRW_VARYING_SLOT_COUNT
884 * We always program SF to start reading at an offset of 1 (2 varying slots)
885 * from the start of the vertex URB entry. This causes it to skip:
886 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
887 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
889 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
892 * Bitmask indicating which fragment shader inputs represent varyings (and
893 * hence have to be delivered to the fragment shader by the SF/SBE stage).
895 #define BRW_FS_VARYING_INPUT_MASK \
896 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
897 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
900 * Data structure recording the relationship between the gl_varying_slot enum
901 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
902 * single octaword within the VUE (128 bits).
904 * Note that each BRW register contains 256 bits (2 octawords), so when
905 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
906 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
907 * in a vertex shader), each register corresponds to a single VUE slot, since
908 * it contains data for two separate vertices.
912 * Bitfield representing all varying slots that are (a) stored in this VUE
913 * map, and (b) actually written by the shader. Does not include any of
914 * the additional varying slots defined in brw_varying_slot.
916 uint64_t slots_valid
;
919 * Is this VUE map for a separate shader pipeline?
921 * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched
922 * without the linker having a chance to dead code eliminate unused varyings.
924 * This means that we have to use a fixed slot layout, based on the output's
925 * location field, rather than assigning slots in a compact contiguous block.
930 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
931 * not stored in a slot (because they are not written, or because
932 * additional processing is applied before storing them in the VUE), the
935 signed char varying_to_slot
[VARYING_SLOT_TESS_MAX
];
938 * Map from VUE slot to gl_varying_slot value. For slots that do not
939 * directly correspond to a gl_varying_slot, the value comes from
942 * For slots that are not in use, the value is BRW_VARYING_SLOT_PAD.
944 signed char slot_to_varying
[VARYING_SLOT_TESS_MAX
];
947 * Total number of VUE slots in use
952 * Number of per-patch VUE slots. Only valid for tessellation control
953 * shader outputs and tessellation evaluation shader inputs.
955 int num_per_patch_slots
;
958 * Number of per-vertex VUE slots. Only valid for tessellation control
959 * shader outputs and tessellation evaluation shader inputs.
961 int num_per_vertex_slots
;
964 void brw_print_vue_map(FILE *fp
, const struct brw_vue_map
*vue_map
);
967 * Convert a VUE slot number into a byte offset within the VUE.
969 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
975 * Convert a vertex output (brw_varying_slot) into a byte offset within the
979 GLuint
brw_varying_to_offset(const struct brw_vue_map
*vue_map
, GLuint varying
)
981 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
984 void brw_compute_vue_map(const struct gen_device_info
*devinfo
,
985 struct brw_vue_map
*vue_map
,
986 uint64_t slots_valid
,
987 bool separate_shader
);
989 void brw_compute_tess_vue_map(struct brw_vue_map
*const vue_map
,
990 uint64_t slots_valid
,
993 /* brw_interpolation_map.c */
994 void brw_setup_vue_interpolation(struct brw_vue_map
*vue_map
,
995 struct nir_shader
*nir
,
996 struct brw_wm_prog_data
*prog_data
);
998 enum shader_dispatch_mode
{
999 DISPATCH_MODE_4X1_SINGLE
= 0,
1000 DISPATCH_MODE_4X2_DUAL_INSTANCE
= 1,
1001 DISPATCH_MODE_4X2_DUAL_OBJECT
= 2,
1002 DISPATCH_MODE_SIMD8
= 3,
1006 * @defgroup Tessellator parameter enumerations.
1008 * These correspond to the hardware values in 3DSTATE_TE, and are provided
1009 * as part of the tessellation evaluation shader.
1013 enum brw_tess_partitioning
{
1014 BRW_TESS_PARTITIONING_INTEGER
= 0,
1015 BRW_TESS_PARTITIONING_ODD_FRACTIONAL
= 1,
1016 BRW_TESS_PARTITIONING_EVEN_FRACTIONAL
= 2,
1019 enum brw_tess_output_topology
{
1020 BRW_TESS_OUTPUT_TOPOLOGY_POINT
= 0,
1021 BRW_TESS_OUTPUT_TOPOLOGY_LINE
= 1,
1022 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
= 2,
1023 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW
= 3,
1026 enum brw_tess_domain
{
1027 BRW_TESS_DOMAIN_QUAD
= 0,
1028 BRW_TESS_DOMAIN_TRI
= 1,
1029 BRW_TESS_DOMAIN_ISOLINE
= 2,
1033 struct brw_vue_prog_data
{
1034 struct brw_stage_prog_data base
;
1035 struct brw_vue_map vue_map
;
1037 /** Should the hardware deliver input VUE handles for URB pull loads? */
1038 bool include_vue_handles
;
1040 GLuint urb_read_length
;
1043 uint32_t clip_distance_mask
;
1044 uint32_t cull_distance_mask
;
1046 /* Used for calculating urb partitions. In the VS, this is the size of the
1047 * URB entry used for both input and output to the thread. In the GS, this
1048 * is the size of the URB entry used for output.
1050 GLuint urb_entry_size
;
1052 enum shader_dispatch_mode dispatch_mode
;
1055 struct brw_vs_prog_data
{
1056 struct brw_vue_prog_data base
;
1058 GLbitfield64 inputs_read
;
1059 GLbitfield64 double_inputs_read
;
1061 unsigned nr_attribute_slots
;
1064 bool uses_instanceid
;
1065 bool uses_is_indexed_draw
;
1066 bool uses_firstvertex
;
1067 bool uses_baseinstance
;
1071 struct brw_tcs_prog_data
1073 struct brw_vue_prog_data base
;
1075 /** Number vertices in output patch */
1080 struct brw_tes_prog_data
1082 struct brw_vue_prog_data base
;
1084 enum brw_tess_partitioning partitioning
;
1085 enum brw_tess_output_topology output_topology
;
1086 enum brw_tess_domain domain
;
1089 struct brw_gs_prog_data
1091 struct brw_vue_prog_data base
;
1093 unsigned vertices_in
;
1096 * Size of an output vertex, measured in HWORDS (32 bytes).
1098 unsigned output_vertex_size_hwords
;
1100 unsigned output_topology
;
1103 * Size of the control data (cut bits or StreamID bits), in hwords (32
1104 * bytes). 0 if there is no control data.
1106 unsigned control_data_header_size_hwords
;
1109 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
1110 * if the control data is StreamID bits, or
1111 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
1112 * Ignored if control_data_header_size is 0.
1114 unsigned control_data_format
;
1116 bool include_primitive_id
;
1119 * The number of vertices emitted, if constant - otherwise -1.
1121 int static_vertex_count
;
1126 * Gen6: Provoking vertex convention for odd-numbered triangles
1132 * Gen6: Number of varyings that are output to transform feedback.
1134 GLuint num_transform_feedback_bindings
:7; /* 0-BRW_MAX_SOL_BINDINGS */
1137 * Gen6: Map from the index of a transform feedback binding table entry to the
1138 * gl_varying_slot that should be streamed out through that binding table
1141 unsigned char transform_feedback_bindings
[64 /* BRW_MAX_SOL_BINDINGS */];
1144 * Gen6: Map from the index of a transform feedback binding table entry to the
1145 * swizzles that should be used when streaming out data through that
1146 * binding table entry.
1148 unsigned char transform_feedback_swizzles
[64 /* BRW_MAX_SOL_BINDINGS */];
1151 struct brw_sf_prog_data
{
1152 uint32_t urb_read_length
;
1155 /* Each vertex may have upto 12 attributes, 4 components each,
1156 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
1159 * Actually we use 4 for each, so call it 12 rows.
1161 unsigned urb_entry_size
;
1164 struct brw_clip_prog_data
{
1165 uint32_t curb_read_length
; /* user planes? */
1167 uint32_t urb_read_length
;
1171 /* brw_any_prog_data is prog_data for any stage that maps to an API stage */
1172 union brw_any_prog_data
{
1173 struct brw_stage_prog_data base
;
1174 struct brw_vue_prog_data vue
;
1175 struct brw_vs_prog_data vs
;
1176 struct brw_tcs_prog_data tcs
;
1177 struct brw_tes_prog_data tes
;
1178 struct brw_gs_prog_data gs
;
1179 struct brw_wm_prog_data wm
;
1180 struct brw_cs_prog_data cs
;
1183 #define DEFINE_PROG_DATA_DOWNCAST(stage) \
1184 static inline struct brw_##stage##_prog_data * \
1185 brw_##stage##_prog_data(struct brw_stage_prog_data *prog_data) \
1187 return (struct brw_##stage##_prog_data *) prog_data; \
1189 DEFINE_PROG_DATA_DOWNCAST(vue
)
1190 DEFINE_PROG_DATA_DOWNCAST(vs
)
1191 DEFINE_PROG_DATA_DOWNCAST(tcs
)
1192 DEFINE_PROG_DATA_DOWNCAST(tes
)
1193 DEFINE_PROG_DATA_DOWNCAST(gs
)
1194 DEFINE_PROG_DATA_DOWNCAST(wm
)
1195 DEFINE_PROG_DATA_DOWNCAST(cs
)
1196 DEFINE_PROG_DATA_DOWNCAST(ff_gs
)
1197 DEFINE_PROG_DATA_DOWNCAST(clip
)
1198 DEFINE_PROG_DATA_DOWNCAST(sf
)
1199 #undef DEFINE_PROG_DATA_DOWNCAST
1203 struct brw_compiler
*
1204 brw_compiler_create(void *mem_ctx
, const struct gen_device_info
*devinfo
);
1207 * Returns a compiler configuration for use with disk shader cache
1209 * This value only needs to change for settings that can cause different
1210 * program generation between two runs on the same hardware.
1212 * For example, it doesn't need to be different for gen 8 and gen 9 hardware,
1213 * but it does need to be different if INTEL_DEBUG=nocompact is or isn't used.
1216 brw_get_compiler_config_value(const struct brw_compiler
*compiler
);
1219 brw_prog_data_size(gl_shader_stage stage
);
1222 brw_prog_key_size(gl_shader_stage stage
);
1225 * Compile a vertex shader.
1227 * Returns the final assembly and the program's size.
1230 brw_compile_vs(const struct brw_compiler
*compiler
, void *log_data
,
1232 const struct brw_vs_prog_key
*key
,
1233 struct brw_vs_prog_data
*prog_data
,
1234 struct nir_shader
*shader
,
1235 int shader_time_index
,
1239 * Compile a tessellation control shader.
1241 * Returns the final assembly and the program's size.
1244 brw_compile_tcs(const struct brw_compiler
*compiler
,
1247 const struct brw_tcs_prog_key
*key
,
1248 struct brw_tcs_prog_data
*prog_data
,
1249 struct nir_shader
*nir
,
1250 int shader_time_index
,
1254 * Compile a tessellation evaluation shader.
1256 * Returns the final assembly and the program's size.
1259 brw_compile_tes(const struct brw_compiler
*compiler
, void *log_data
,
1261 const struct brw_tes_prog_key
*key
,
1262 const struct brw_vue_map
*input_vue_map
,
1263 struct brw_tes_prog_data
*prog_data
,
1264 struct nir_shader
*shader
,
1265 struct gl_program
*prog
,
1266 int shader_time_index
,
1270 * Compile a vertex shader.
1272 * Returns the final assembly and the program's size.
1275 brw_compile_gs(const struct brw_compiler
*compiler
, void *log_data
,
1277 const struct brw_gs_prog_key
*key
,
1278 struct brw_gs_prog_data
*prog_data
,
1279 struct nir_shader
*shader
,
1280 struct gl_program
*prog
,
1281 int shader_time_index
,
1285 * Compile a strips and fans shader.
1287 * This is a fixed-function shader determined entirely by the shader key and
1290 * Returns the final assembly and the program's size.
1293 brw_compile_sf(const struct brw_compiler
*compiler
,
1295 const struct brw_sf_prog_key
*key
,
1296 struct brw_sf_prog_data
*prog_data
,
1297 struct brw_vue_map
*vue_map
,
1298 unsigned *final_assembly_size
);
1301 * Compile a clipper shader.
1303 * This is a fixed-function shader determined entirely by the shader key and
1306 * Returns the final assembly and the program's size.
1309 brw_compile_clip(const struct brw_compiler
*compiler
,
1311 const struct brw_clip_prog_key
*key
,
1312 struct brw_clip_prog_data
*prog_data
,
1313 struct brw_vue_map
*vue_map
,
1314 unsigned *final_assembly_size
);
1317 * Compile a fragment shader.
1319 * Returns the final assembly and the program's size.
1322 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
1324 const struct brw_wm_prog_key
*key
,
1325 struct brw_wm_prog_data
*prog_data
,
1326 struct nir_shader
*shader
,
1327 struct gl_program
*prog
,
1328 int shader_time_index8
,
1329 int shader_time_index16
,
1330 int shader_time_index32
,
1331 bool allow_spilling
,
1332 bool use_rep_send
, struct brw_vue_map
*vue_map
,
1336 * Compile a compute shader.
1338 * Returns the final assembly and the program's size.
1341 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
1343 const struct brw_cs_prog_key
*key
,
1344 struct brw_cs_prog_data
*prog_data
,
1345 const struct nir_shader
*shader
,
1346 int shader_time_index
,
1349 static inline uint32_t
1350 encode_slm_size(unsigned gen
, uint32_t bytes
)
1352 uint32_t slm_size
= 0;
1354 /* Shared Local Memory is specified as powers of two, and encoded in
1355 * INTERFACE_DESCRIPTOR_DATA with the following representations:
1357 * Size | 0 kB | 1 kB | 2 kB | 4 kB | 8 kB | 16 kB | 32 kB | 64 kB |
1358 * -------------------------------------------------------------------
1359 * Gen7-8 | 0 | none | none | 1 | 2 | 4 | 8 | 16 |
1360 * -------------------------------------------------------------------
1361 * Gen9+ | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
1363 assert(bytes
<= 64 * 1024);
1366 /* Shared Local Memory Size is specified as powers of two. */
1367 slm_size
= util_next_power_of_two(bytes
);
1370 /* Use a minimum of 1kB; turn an exponent of 10 (1024 kB) into 1. */
1371 slm_size
= ffs(MAX2(slm_size
, 1024)) - 10;
1373 /* Use a minimum of 4kB; convert to the pre-Gen9 representation. */
1374 slm_size
= MAX2(slm_size
, 4096) / 4096;
1382 * Return true if the given shader stage is dispatched contiguously by the
1383 * relevant fixed function starting from channel 0 of the SIMD thread, which
1384 * implies that the dispatch mask of a thread can be assumed to have the form
1385 * '2^n - 1' for some n.
1388 brw_stage_has_packed_dispatch(MAYBE_UNUSED
const struct gen_device_info
*devinfo
,
1389 gl_shader_stage stage
,
1390 const struct brw_stage_prog_data
*prog_data
)
1392 /* The code below makes assumptions about the hardware's thread dispatch
1393 * behavior that could be proven wrong in future generations -- Make sure
1394 * to do a full test run with brw_fs_test_dispatch_packing() hooked up to
1395 * the NIR front-end before changing this assertion.
1397 assert(devinfo
->gen
<= 11);
1400 case MESA_SHADER_FRAGMENT
: {
1401 /* The PSD discards subspans coming in with no lit samples, which in the
1402 * per-pixel shading case implies that each subspan will either be fully
1403 * lit (due to the VMask being used to allow derivative computations),
1404 * or not dispatched at all. In per-sample dispatch mode individual
1405 * samples from the same subspan have a fixed relative location within
1406 * the SIMD thread, so dispatch of unlit samples cannot be avoided in
1407 * general and we should return false.
1409 const struct brw_wm_prog_data
*wm_prog_data
=
1410 (const struct brw_wm_prog_data
*)prog_data
;
1411 return !wm_prog_data
->persample_dispatch
;
1413 case MESA_SHADER_COMPUTE
:
1414 /* Compute shaders will be spawned with either a fully enabled dispatch
1415 * mask or with whatever bottom/right execution mask was given to the
1416 * GPGPU walker command to be used along the workgroup edges -- In both
1417 * cases the dispatch mask is required to be tightly packed for our
1418 * invocation index calculations to work.
1422 /* Most remaining fixed functions are limited to use a packed dispatch
1423 * mask due to the hardware representation of the dispatch mask as a
1424 * single counter representing the number of enabled channels.
1431 * Computes the first varying slot in the URB produced by the previous stage
1432 * that is used in the next stage. We do this by testing the varying slots in
1433 * the previous stage's vue map against the inputs read in the next stage.
1437 * - Each URB offset contains two varying slots and we can only skip a
1438 * full offset if both slots are unused, so the value we return here is always
1439 * rounded down to the closest multiple of two.
1441 * - gl_Layer and gl_ViewportIndex don't have their own varying slots, they are
1442 * part of the vue header, so if these are read we can't skip anything.
1445 brw_compute_first_urb_slot_required(uint64_t inputs_read
,
1446 const struct brw_vue_map
*prev_stage_vue_map
)
1448 if ((inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
)) == 0) {
1449 for (int i
= 0; i
< prev_stage_vue_map
->num_slots
; i
++) {
1450 int varying
= prev_stage_vue_map
->slot_to_varying
[i
];
1451 if (varying
> 0 && (inputs_read
& BITFIELD64_BIT(varying
)) != 0)
1452 return ROUND_DOWN_TO(i
, 2);
1463 #endif /* BRW_COMPILER_H */