2 * Copyright © 2010 - 2015 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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24 #ifndef BRW_COMPILER_H
25 #define BRW_COMPILER_H
28 #include "common/gen_device_info.h"
29 #include "main/mtypes.h"
30 #include "main/macros.h"
31 #include "util/ralloc.h"
42 const struct gen_device_info
*devinfo
;
48 * Array of the ra classes for the unaligned contiguous register
54 * Mapping for register-allocated objects in *regs to the first
55 * GRF for that object.
57 uint8_t *ra_reg_to_grf
;
64 * Array of the ra classes for the unaligned contiguous register
65 * block sizes used, indexed by register size.
70 * Mapping from classes to ra_reg ranges. Each of the per-size
71 * classes corresponds to a range of ra_reg nodes. This array stores
72 * those ranges in the form of first ra_reg in each class and the
73 * total number of ra_reg elements in the last array element. This
74 * way the range of the i'th class is given by:
75 * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] )
77 int class_to_ra_reg_range
[17];
80 * Mapping for register-allocated objects in *regs to the first
81 * GRF for that object.
83 uint8_t *ra_reg_to_grf
;
86 * ra class for the aligned pairs we use for PLN, which doesn't
89 int aligned_pairs_class
;
92 void (*shader_debug_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
93 void (*shader_perf_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
95 bool scalar_stage
[MESA_SHADER_STAGES
];
96 struct gl_shader_compiler_options glsl_compiler_options
[MESA_SHADER_STAGES
];
99 * Apply workarounds for SIN and COS output range problems.
100 * This can negatively impact performance.
105 * Is 3DSTATE_CONSTANT_*'s Constant Buffer 0 relative to Dynamic State
106 * Base Address? (If not, it's a normal GPU address.)
108 bool constant_buffer_0_is_relative
;
111 * Whether or not the driver supports pull constants. If not, the compiler
112 * will attempt to push everything.
114 bool supports_pull_constants
;
119 * Program key structures.
121 * When drawing, we look for the currently bound shaders in the program
122 * cache. This is essentially a hash table lookup, and these are the keys.
124 * Sometimes OpenGL features specified as state need to be simulated via
125 * shader code, due to a mismatch between the API and the hardware. This
126 * is often referred to as "non-orthagonal state" or "NOS". We store NOS
127 * in the program key so it's considered when searching for a program. If
128 * we haven't seen a particular combination before, we have to recompile a
129 * new specialized version.
131 * Shader compilation should not look up state in gl_context directly, but
132 * instead use the copy in the program key. This guarantees recompiles will
138 enum PACKED gen6_gather_sampler_wa
{
139 WA_SIGN
= 1, /* whether we need to sign extend */
140 WA_8BIT
= 2, /* if we have an 8bit format needing wa */
141 WA_16BIT
= 4, /* if we have a 16bit format needing wa */
145 * Sampler information needed by VS, WM, and GS program cache keys.
147 struct brw_sampler_prog_key_data
{
149 * EXT_texture_swizzle and DEPTH_TEXTURE_MODE swizzles.
151 uint16_t swizzles
[MAX_SAMPLERS
];
153 uint32_t gl_clamp_mask
[3];
156 * For RG32F, gather4's channel select is broken.
158 uint32_t gather_channel_quirk_mask
;
161 * Whether this sampler uses the compressed multisample surface layout.
163 uint32_t compressed_multisample_layout_mask
;
166 * Whether this sampler is using 16x multisampling. If so fetching from
167 * this sampler will be handled with a different instruction, ld2dms_w
173 * For Sandybridge, which shader w/a we need for gather quirks.
175 enum gen6_gather_sampler_wa gen6_gather_wa
[MAX_SAMPLERS
];
178 * Texture units that have a YUV image bound.
180 uint32_t y_u_v_image_mask
;
181 uint32_t y_uv_image_mask
;
182 uint32_t yx_xuxv_image_mask
;
183 uint32_t xy_uxvx_image_mask
;
187 * The VF can't natively handle certain types of attributes, such as GL_FIXED
188 * or most 10_10_10_2 types. These flags enable various VS workarounds to
189 * "fix" attributes at the beginning of shaders.
191 #define BRW_ATTRIB_WA_COMPONENT_MASK 7 /* mask for GL_FIXED scale channel count */
192 #define BRW_ATTRIB_WA_NORMALIZE 8 /* normalize in shader */
193 #define BRW_ATTRIB_WA_BGRA 16 /* swap r/b channels in shader */
194 #define BRW_ATTRIB_WA_SIGN 32 /* interpret as signed in shader */
195 #define BRW_ATTRIB_WA_SCALE 64 /* interpret as scaled in shader */
198 * OpenGL attribute slots fall in [0, VERT_ATTRIB_MAX - 1] with the range
199 * [VERT_ATTRIB_GENERIC0, VERT_ATTRIB_MAX - 1] reserved for up to 16 user
200 * input vertex attributes. In Vulkan, we expose up to 28 user vertex input
201 * attributes that are mapped to slots also starting at VERT_ATTRIB_GENERIC0.
203 #define MAX_GL_VERT_ATTRIB VERT_ATTRIB_MAX
204 #define MAX_VK_VERT_ATTRIB (VERT_ATTRIB_GENERIC0 + 28)
206 /** The program key for Vertex Shaders. */
207 struct brw_vs_prog_key
{
208 unsigned program_string_id
;
211 * Per-attribute workaround flags
213 * For each attribute, a combination of BRW_ATTRIB_WA_*.
215 * For OpenGL, where we expose a maximum of 16 user input atttributes
216 * we only need up to VERT_ATTRIB_MAX slots, however, in Vulkan
217 * slots preceding VERT_ATTRIB_GENERIC0 are unused and we can
218 * expose up to 28 user input vertex attributes that are mapped to slots
219 * starting at VERT_ATTRIB_GENERIC0, so this array needs to be large
220 * enough to hold this many slots.
222 uint8_t gl_attrib_wa_flags
[MAX2(MAX_GL_VERT_ATTRIB
, MAX_VK_VERT_ATTRIB
)];
224 bool copy_edgeflag
:1;
226 bool clamp_vertex_color
:1;
229 * How many user clipping planes are being uploaded to the vertex shader as
232 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
235 unsigned nr_userclip_plane_consts
:4;
238 * For pre-Gen6 hardware, a bitfield indicating which texture coordinates
239 * are going to be replaced with point coordinates (as a consequence of a
240 * call to glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)). Because
241 * our SF thread requires exact matching between VS outputs and FS inputs,
242 * these texture coordinates will need to be unconditionally included in
243 * the VUE, even if they aren't written by the vertex shader.
245 uint8_t point_coord_replace
;
247 struct brw_sampler_prog_key_data tex
;
250 /** The program key for Tessellation Control Shaders. */
251 struct brw_tcs_prog_key
253 unsigned program_string_id
;
255 GLenum tes_primitive_mode
;
257 unsigned input_vertices
;
259 /** A bitfield of per-patch outputs written. */
260 uint32_t patch_outputs_written
;
262 /** A bitfield of per-vertex outputs written. */
263 uint64_t outputs_written
;
265 bool quads_workaround
;
267 struct brw_sampler_prog_key_data tex
;
270 /** The program key for Tessellation Evaluation Shaders. */
271 struct brw_tes_prog_key
273 unsigned program_string_id
;
275 /** A bitfield of per-patch inputs read. */
276 uint32_t patch_inputs_read
;
278 /** A bitfield of per-vertex inputs read. */
279 uint64_t inputs_read
;
281 struct brw_sampler_prog_key_data tex
;
284 /** The program key for Geometry Shaders. */
285 struct brw_gs_prog_key
287 unsigned program_string_id
;
289 struct brw_sampler_prog_key_data tex
;
292 enum brw_sf_primitive
{
293 BRW_SF_PRIM_POINTS
= 0,
294 BRW_SF_PRIM_LINES
= 1,
295 BRW_SF_PRIM_TRIANGLES
= 2,
296 BRW_SF_PRIM_UNFILLED_TRIS
= 3,
299 struct brw_sf_prog_key
{
301 bool contains_flat_varying
;
302 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
303 uint8_t point_sprite_coord_replace
;
304 enum brw_sf_primitive primitive
:2;
305 bool do_twoside_color
:1;
306 bool frontface_ccw
:1;
307 bool do_point_sprite
:1;
308 bool do_point_coord
:1;
309 bool sprite_origin_lower_left
:1;
310 bool userclip_active
:1;
314 BRW_CLIP_MODE_NORMAL
= 0,
315 BRW_CLIP_MODE_CLIP_ALL
= 1,
316 BRW_CLIP_MODE_CLIP_NON_REJECTED
= 2,
317 BRW_CLIP_MODE_REJECT_ALL
= 3,
318 BRW_CLIP_MODE_ACCEPT_ALL
= 4,
319 BRW_CLIP_MODE_KERNEL_CLIP
= 5,
322 enum brw_clip_fill_mode
{
323 BRW_CLIP_FILL_MODE_LINE
= 0,
324 BRW_CLIP_FILL_MODE_POINT
= 1,
325 BRW_CLIP_FILL_MODE_FILL
= 2,
326 BRW_CLIP_FILL_MODE_CULL
= 3,
329 /* Note that if unfilled primitives are being emitted, we have to fix
330 * up polygon offset and flatshading at this point:
332 struct brw_clip_prog_key
{
334 bool contains_flat_varying
;
335 bool contains_noperspective_varying
;
336 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
337 unsigned primitive
:4;
338 unsigned nr_userclip
:4;
341 enum brw_clip_fill_mode fill_cw
:2; /* includes cull information */
342 enum brw_clip_fill_mode fill_ccw
:2; /* includes cull information */
347 enum brw_clip_mode clip_mode
:3;
354 /* A big lookup table is used to figure out which and how many
355 * additional regs will inserted before the main payload in the WM
356 * program execution. These mainly relate to depth and stencil
357 * processing and the early-depth-test optimization.
359 enum brw_wm_iz_bits
{
360 BRW_WM_IZ_PS_KILL_ALPHATEST_BIT
= 0x1,
361 BRW_WM_IZ_PS_COMPUTES_DEPTH_BIT
= 0x2,
362 BRW_WM_IZ_DEPTH_WRITE_ENABLE_BIT
= 0x4,
363 BRW_WM_IZ_DEPTH_TEST_ENABLE_BIT
= 0x8,
364 BRW_WM_IZ_STENCIL_WRITE_ENABLE_BIT
= 0x10,
365 BRW_WM_IZ_STENCIL_TEST_ENABLE_BIT
= 0x20,
366 BRW_WM_IZ_BIT_MAX
= 0x40
369 enum brw_wm_aa_enable
{
375 /** The program key for Fragment/Pixel Shaders. */
376 struct brw_wm_prog_key
{
377 /* Some collection of BRW_WM_IZ_* */
381 unsigned nr_color_regions
:5;
382 bool replicate_alpha
:1;
383 bool clamp_fragment_color
:1;
384 bool persample_interp
:1;
385 bool multisample_fbo
:1;
386 bool frag_coord_adds_sample_pos
:1;
387 enum brw_wm_aa_enable line_aa
:2;
388 bool high_quality_derivatives
:1;
389 bool force_dual_color_blend
:1;
390 bool coherent_fb_fetch
:1;
392 uint64_t input_slots_valid
;
393 unsigned program_string_id
;
394 GLenum alpha_test_func
; /* < For Gen4/5 MRT alpha test */
395 float alpha_test_ref
;
397 struct brw_sampler_prog_key_data tex
;
400 struct brw_cs_prog_key
{
401 uint32_t program_string_id
;
402 struct brw_sampler_prog_key_data tex
;
406 * Image metadata structure as laid out in the shader parameter
407 * buffer. Entries have to be 16B-aligned for the vec4 back-end to be
408 * able to use them. That's okay because the padding and any unused
409 * entries [most of them except when we're doing untyped surface
410 * access] will be removed by the uniform packing pass.
412 #define BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET 0
413 #define BRW_IMAGE_PARAM_OFFSET_OFFSET 4
414 #define BRW_IMAGE_PARAM_SIZE_OFFSET 8
415 #define BRW_IMAGE_PARAM_STRIDE_OFFSET 12
416 #define BRW_IMAGE_PARAM_TILING_OFFSET 16
417 #define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 20
418 #define BRW_IMAGE_PARAM_SIZE 24
420 struct brw_image_param
{
421 /** Surface binding table index. */
422 uint32_t surface_idx
;
424 /** Offset applied to the X and Y surface coordinates. */
427 /** Surface X, Y and Z dimensions. */
430 /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
431 * pixels, vertical slice stride in pixels.
435 /** Log2 of the tiling modulus in the X, Y and Z dimension. */
439 * Right shift to apply for bit 6 address swizzling. Two different
440 * swizzles can be specified and will be applied one after the other. The
441 * resulting address will be:
443 * addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
444 * (addr >> swizzling[1])))
446 * Use \c 0xff if any of the swizzles is not required.
448 uint32_t swizzling
[2];
451 /** Max number of render targets in a shader */
452 #define BRW_MAX_DRAW_BUFFERS 8
455 * Max number of binding table entries used for stream output.
457 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
458 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
460 * On Gen6, the size of transform feedback data is limited not by the number
461 * of components but by the number of binding table entries we set aside. We
462 * use one binding table entry for a float, one entry for a vector, and one
463 * entry per matrix column. Since the only way we can communicate our
464 * transform feedback capabilities to the client is via
465 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
466 * worst case, in which all the varyings are floats, so we use up one binding
467 * table entry per component. Therefore we need to set aside at least 64
468 * binding table entries for use by transform feedback.
470 * Note: since we don't currently pack varyings, it is currently impossible
471 * for the client to actually use up all of these binding table entries--if
472 * all of their varyings were floats, they would run out of varying slots and
473 * fail to link. But that's a bug, so it seems prudent to go ahead and
474 * allocate the number of binding table entries we will need once the bug is
477 #define BRW_MAX_SOL_BINDINGS 64
480 * Binding table index for the first gen6 SOL binding.
482 #define BRW_GEN6_SOL_BINDING_START 0
485 * Stride in bytes between shader_time entries.
487 * We separate entries by a cacheline to reduce traffic between EUs writing to
490 #define BRW_SHADER_TIME_STRIDE 64
499 /* We reserve the first 2^16 values for builtins */
500 #define BRW_PARAM_IS_BUILTIN(param) (((param) & 0xffff0000) == 0)
502 enum brw_param_builtin
{
503 BRW_PARAM_BUILTIN_ZERO
,
505 BRW_PARAM_BUILTIN_CLIP_PLANE_0_X
,
506 BRW_PARAM_BUILTIN_CLIP_PLANE_0_Y
,
507 BRW_PARAM_BUILTIN_CLIP_PLANE_0_Z
,
508 BRW_PARAM_BUILTIN_CLIP_PLANE_0_W
,
509 BRW_PARAM_BUILTIN_CLIP_PLANE_1_X
,
510 BRW_PARAM_BUILTIN_CLIP_PLANE_1_Y
,
511 BRW_PARAM_BUILTIN_CLIP_PLANE_1_Z
,
512 BRW_PARAM_BUILTIN_CLIP_PLANE_1_W
,
513 BRW_PARAM_BUILTIN_CLIP_PLANE_2_X
,
514 BRW_PARAM_BUILTIN_CLIP_PLANE_2_Y
,
515 BRW_PARAM_BUILTIN_CLIP_PLANE_2_Z
,
516 BRW_PARAM_BUILTIN_CLIP_PLANE_2_W
,
517 BRW_PARAM_BUILTIN_CLIP_PLANE_3_X
,
518 BRW_PARAM_BUILTIN_CLIP_PLANE_3_Y
,
519 BRW_PARAM_BUILTIN_CLIP_PLANE_3_Z
,
520 BRW_PARAM_BUILTIN_CLIP_PLANE_3_W
,
521 BRW_PARAM_BUILTIN_CLIP_PLANE_4_X
,
522 BRW_PARAM_BUILTIN_CLIP_PLANE_4_Y
,
523 BRW_PARAM_BUILTIN_CLIP_PLANE_4_Z
,
524 BRW_PARAM_BUILTIN_CLIP_PLANE_4_W
,
525 BRW_PARAM_BUILTIN_CLIP_PLANE_5_X
,
526 BRW_PARAM_BUILTIN_CLIP_PLANE_5_Y
,
527 BRW_PARAM_BUILTIN_CLIP_PLANE_5_Z
,
528 BRW_PARAM_BUILTIN_CLIP_PLANE_5_W
,
529 BRW_PARAM_BUILTIN_CLIP_PLANE_6_X
,
530 BRW_PARAM_BUILTIN_CLIP_PLANE_6_Y
,
531 BRW_PARAM_BUILTIN_CLIP_PLANE_6_Z
,
532 BRW_PARAM_BUILTIN_CLIP_PLANE_6_W
,
533 BRW_PARAM_BUILTIN_CLIP_PLANE_7_X
,
534 BRW_PARAM_BUILTIN_CLIP_PLANE_7_Y
,
535 BRW_PARAM_BUILTIN_CLIP_PLANE_7_Z
,
536 BRW_PARAM_BUILTIN_CLIP_PLANE_7_W
,
538 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
,
539 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Y
,
540 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Z
,
541 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_W
,
542 BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
,
543 BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y
,
545 BRW_PARAM_BUILTIN_THREAD_LOCAL_ID
,
548 #define BRW_PARAM_BUILTIN_CLIP_PLANE(idx, comp) \
549 (BRW_PARAM_BUILTIN_CLIP_PLANE_0_X + ((idx) << 2) + (comp))
551 #define BRW_PARAM_BUILTIN_IS_CLIP_PLANE(param) \
552 ((param) >= BRW_PARAM_BUILTIN_CLIP_PLANE_0_X && \
553 (param) <= BRW_PARAM_BUILTIN_CLIP_PLANE_7_W)
555 #define BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(param) \
556 (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) >> 2)
558 #define BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(param) \
559 (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) & 0x3)
561 struct brw_stage_prog_data
{
563 /** size of our binding table. */
567 * surface indices for the various groups of surfaces
569 uint32_t pull_constants_start
;
570 uint32_t texture_start
;
571 uint32_t gather_texture_start
;
575 uint32_t image_start
;
576 uint32_t shader_time_start
;
577 uint32_t plane_start
[3];
581 struct brw_ubo_range ubo_ranges
[4];
583 GLuint nr_params
; /**< number of float params/constants */
584 GLuint nr_pull_params
;
586 unsigned curb_read_length
;
587 unsigned total_scratch
;
588 unsigned total_shared
;
591 * Register where the thread expects to find input data from the URB
592 * (typically uniforms, followed by vertex or fragment attributes).
594 unsigned dispatch_grf_start_reg
;
596 bool use_alt_mode
; /**< Use ALT floating point mode? Otherwise, IEEE. */
598 /* 32-bit identifiers for all push/pull parameters. These can be anything
599 * the driver wishes them to be; the core of the back-end compiler simply
600 * re-arranges them. The one restriction is that the bottom 2^16 values
601 * are reserved for builtins defined in the brw_param_builtin enum defined
605 uint32_t *pull_param
;
608 static inline uint32_t *
609 brw_stage_prog_data_add_params(struct brw_stage_prog_data
*prog_data
,
610 unsigned nr_new_params
)
612 unsigned old_nr_params
= prog_data
->nr_params
;
613 prog_data
->nr_params
+= nr_new_params
;
614 prog_data
->param
= reralloc(ralloc_parent(prog_data
->param
),
615 prog_data
->param
, uint32_t,
616 prog_data
->nr_params
);
617 return prog_data
->param
+ old_nr_params
;
621 brw_mark_surface_used(struct brw_stage_prog_data
*prog_data
,
624 /* A binding table index is 8 bits and the top 3 values are reserved for
625 * special things (stateless and SLM).
627 assert(surf_index
<= 252);
629 prog_data
->binding_table
.size_bytes
=
630 MAX2(prog_data
->binding_table
.size_bytes
, (surf_index
+ 1) * 4);
633 enum brw_barycentric_mode
{
634 BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
= 0,
635 BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
= 1,
636 BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
= 2,
637 BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL
= 3,
638 BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
= 4,
639 BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE
= 5,
640 BRW_BARYCENTRIC_MODE_COUNT
= 6
642 #define BRW_BARYCENTRIC_NONPERSPECTIVE_BITS \
643 ((1 << BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL) | \
644 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID) | \
645 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE))
647 enum brw_pixel_shader_computed_depth_mode
{
648 BRW_PSCDEPTH_OFF
= 0, /* PS does not compute depth */
649 BRW_PSCDEPTH_ON
= 1, /* PS computes depth; no guarantee about value */
650 BRW_PSCDEPTH_ON_GE
= 2, /* PS guarantees output depth >= source depth */
651 BRW_PSCDEPTH_ON_LE
= 3, /* PS guarantees output depth <= source depth */
654 /* Data about a particular attempt to compile a program. Note that
655 * there can be many of these, each in a different GL state
656 * corresponding to a different brw_wm_prog_key struct, with different
659 struct brw_wm_prog_data
{
660 struct brw_stage_prog_data base
;
662 GLuint num_varying_inputs
;
664 uint8_t reg_blocks_0
;
665 uint8_t reg_blocks_2
;
667 uint8_t dispatch_grf_start_reg_2
;
668 uint32_t prog_offset_2
;
672 * surface indices the WM-specific surfaces
674 uint32_t render_target_start
;
675 uint32_t render_target_read_start
;
679 uint8_t computed_depth_mode
;
680 bool computed_stencil
;
682 bool early_fragment_tests
;
683 bool post_depth_coverage
;
688 bool persample_dispatch
;
689 bool uses_pos_offset
;
694 bool uses_sample_mask
;
695 bool has_render_target_reads
;
696 bool has_side_effects
;
699 bool contains_flat_varying
;
700 bool contains_noperspective_varying
;
703 * Mask of which interpolation modes are required by the fragment shader.
704 * Used in hardware setup on gen6+.
706 uint32_t barycentric_interp_modes
;
709 * Mask of which FS inputs are marked flat by the shader source. This is
710 * needed for setting up 3DSTATE_SF/SBE.
712 uint32_t flat_inputs
;
714 /* Mapping of VUE slots to interpolation modes.
715 * Used by the Gen4-5 clip/sf/wm stages.
717 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
720 * Map from gl_varying_slot to the position within the FS setup data
721 * payload where the varying's attribute vertex deltas should be delivered.
722 * For varying slots that are not used by the FS, the value is -1.
724 int urb_setup
[VARYING_SLOT_MAX
];
727 struct brw_push_const_block
{
728 unsigned dwords
; /* Dword count, not reg aligned */
730 unsigned size
; /* Bytes, register aligned */
733 struct brw_cs_prog_data
{
734 struct brw_stage_prog_data base
;
736 GLuint dispatch_grf_start_reg_16
;
737 unsigned local_size
[3];
741 bool uses_num_work_groups
;
744 struct brw_push_const_block cross_thread
;
745 struct brw_push_const_block per_thread
;
746 struct brw_push_const_block total
;
751 * surface indices the CS-specific surfaces
753 uint32_t work_groups_start
;
759 * Enum representing the i965-specific vertex results that don't correspond
760 * exactly to any element of gl_varying_slot. The values of this enum are
761 * assigned such that they don't conflict with gl_varying_slot.
765 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
766 BRW_VARYING_SLOT_PAD
,
768 * Technically this is not a varying but just a placeholder that
769 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
770 * builtin variable to be compiled correctly. see compile_sf_prog() for
773 BRW_VARYING_SLOT_PNTC
,
774 BRW_VARYING_SLOT_COUNT
778 * We always program SF to start reading at an offset of 1 (2 varying slots)
779 * from the start of the vertex URB entry. This causes it to skip:
780 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
781 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
783 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
786 * Bitmask indicating which fragment shader inputs represent varyings (and
787 * hence have to be delivered to the fragment shader by the SF/SBE stage).
789 #define BRW_FS_VARYING_INPUT_MASK \
790 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
791 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
794 * Data structure recording the relationship between the gl_varying_slot enum
795 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
796 * single octaword within the VUE (128 bits).
798 * Note that each BRW register contains 256 bits (2 octawords), so when
799 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
800 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
801 * in a vertex shader), each register corresponds to a single VUE slot, since
802 * it contains data for two separate vertices.
806 * Bitfield representing all varying slots that are (a) stored in this VUE
807 * map, and (b) actually written by the shader. Does not include any of
808 * the additional varying slots defined in brw_varying_slot.
810 uint64_t slots_valid
;
813 * Is this VUE map for a separate shader pipeline?
815 * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched
816 * without the linker having a chance to dead code eliminate unused varyings.
818 * This means that we have to use a fixed slot layout, based on the output's
819 * location field, rather than assigning slots in a compact contiguous block.
824 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
825 * not stored in a slot (because they are not written, or because
826 * additional processing is applied before storing them in the VUE), the
829 signed char varying_to_slot
[VARYING_SLOT_TESS_MAX
];
832 * Map from VUE slot to gl_varying_slot value. For slots that do not
833 * directly correspond to a gl_varying_slot, the value comes from
836 * For slots that are not in use, the value is BRW_VARYING_SLOT_PAD.
838 signed char slot_to_varying
[VARYING_SLOT_TESS_MAX
];
841 * Total number of VUE slots in use
846 * Number of per-patch VUE slots. Only valid for tessellation control
847 * shader outputs and tessellation evaluation shader inputs.
849 int num_per_patch_slots
;
852 * Number of per-vertex VUE slots. Only valid for tessellation control
853 * shader outputs and tessellation evaluation shader inputs.
855 int num_per_vertex_slots
;
858 void brw_print_vue_map(FILE *fp
, const struct brw_vue_map
*vue_map
);
861 * Convert a VUE slot number into a byte offset within the VUE.
863 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
869 * Convert a vertex output (brw_varying_slot) into a byte offset within the
873 GLuint
brw_varying_to_offset(const struct brw_vue_map
*vue_map
, GLuint varying
)
875 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
878 void brw_compute_vue_map(const struct gen_device_info
*devinfo
,
879 struct brw_vue_map
*vue_map
,
880 uint64_t slots_valid
,
881 bool separate_shader
);
883 void brw_compute_tess_vue_map(struct brw_vue_map
*const vue_map
,
884 uint64_t slots_valid
,
887 /* brw_interpolation_map.c */
888 void brw_setup_vue_interpolation(struct brw_vue_map
*vue_map
,
889 struct nir_shader
*nir
,
890 struct brw_wm_prog_data
*prog_data
,
891 const struct gen_device_info
*devinfo
);
893 enum shader_dispatch_mode
{
894 DISPATCH_MODE_4X1_SINGLE
= 0,
895 DISPATCH_MODE_4X2_DUAL_INSTANCE
= 1,
896 DISPATCH_MODE_4X2_DUAL_OBJECT
= 2,
897 DISPATCH_MODE_SIMD8
= 3,
901 * @defgroup Tessellator parameter enumerations.
903 * These correspond to the hardware values in 3DSTATE_TE, and are provided
904 * as part of the tessellation evaluation shader.
908 enum brw_tess_partitioning
{
909 BRW_TESS_PARTITIONING_INTEGER
= 0,
910 BRW_TESS_PARTITIONING_ODD_FRACTIONAL
= 1,
911 BRW_TESS_PARTITIONING_EVEN_FRACTIONAL
= 2,
914 enum brw_tess_output_topology
{
915 BRW_TESS_OUTPUT_TOPOLOGY_POINT
= 0,
916 BRW_TESS_OUTPUT_TOPOLOGY_LINE
= 1,
917 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
= 2,
918 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW
= 3,
921 enum brw_tess_domain
{
922 BRW_TESS_DOMAIN_QUAD
= 0,
923 BRW_TESS_DOMAIN_TRI
= 1,
924 BRW_TESS_DOMAIN_ISOLINE
= 2,
928 struct brw_vue_prog_data
{
929 struct brw_stage_prog_data base
;
930 struct brw_vue_map vue_map
;
932 /** Should the hardware deliver input VUE handles for URB pull loads? */
933 bool include_vue_handles
;
935 GLuint urb_read_length
;
938 uint32_t clip_distance_mask
;
939 uint32_t cull_distance_mask
;
941 /* Used for calculating urb partitions. In the VS, this is the size of the
942 * URB entry used for both input and output to the thread. In the GS, this
943 * is the size of the URB entry used for output.
945 GLuint urb_entry_size
;
947 enum shader_dispatch_mode dispatch_mode
;
950 struct brw_vs_prog_data
{
951 struct brw_vue_prog_data base
;
953 GLbitfield64 inputs_read
;
954 GLbitfield64 double_inputs_read
;
956 unsigned nr_attribute_slots
;
959 bool uses_instanceid
;
960 bool uses_basevertex
;
961 bool uses_baseinstance
;
965 struct brw_tcs_prog_data
967 struct brw_vue_prog_data base
;
969 /** Number vertices in output patch */
974 struct brw_tes_prog_data
976 struct brw_vue_prog_data base
;
978 enum brw_tess_partitioning partitioning
;
979 enum brw_tess_output_topology output_topology
;
980 enum brw_tess_domain domain
;
983 struct brw_gs_prog_data
985 struct brw_vue_prog_data base
;
987 unsigned vertices_in
;
990 * Size of an output vertex, measured in HWORDS (32 bytes).
992 unsigned output_vertex_size_hwords
;
994 unsigned output_topology
;
997 * Size of the control data (cut bits or StreamID bits), in hwords (32
998 * bytes). 0 if there is no control data.
1000 unsigned control_data_header_size_hwords
;
1003 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
1004 * if the control data is StreamID bits, or
1005 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
1006 * Ignored if control_data_header_size is 0.
1008 unsigned control_data_format
;
1010 bool include_primitive_id
;
1013 * The number of vertices emitted, if constant - otherwise -1.
1015 int static_vertex_count
;
1020 * Gen6: Provoking vertex convention for odd-numbered triangles
1026 * Gen6: Number of varyings that are output to transform feedback.
1028 GLuint num_transform_feedback_bindings
:7; /* 0-BRW_MAX_SOL_BINDINGS */
1031 * Gen6: Map from the index of a transform feedback binding table entry to the
1032 * gl_varying_slot that should be streamed out through that binding table
1035 unsigned char transform_feedback_bindings
[64 /* BRW_MAX_SOL_BINDINGS */];
1038 * Gen6: Map from the index of a transform feedback binding table entry to the
1039 * swizzles that should be used when streaming out data through that
1040 * binding table entry.
1042 unsigned char transform_feedback_swizzles
[64 /* BRW_MAX_SOL_BINDINGS */];
1045 struct brw_sf_prog_data
{
1046 uint32_t urb_read_length
;
1049 /* Each vertex may have upto 12 attributes, 4 components each,
1050 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
1053 * Actually we use 4 for each, so call it 12 rows.
1055 unsigned urb_entry_size
;
1058 struct brw_clip_prog_data
{
1059 uint32_t curb_read_length
; /* user planes? */
1061 uint32_t urb_read_length
;
1065 #define DEFINE_PROG_DATA_DOWNCAST(stage) \
1066 static inline struct brw_##stage##_prog_data * \
1067 brw_##stage##_prog_data(struct brw_stage_prog_data *prog_data) \
1069 return (struct brw_##stage##_prog_data *) prog_data; \
1071 DEFINE_PROG_DATA_DOWNCAST(vue
)
1072 DEFINE_PROG_DATA_DOWNCAST(vs
)
1073 DEFINE_PROG_DATA_DOWNCAST(tcs
)
1074 DEFINE_PROG_DATA_DOWNCAST(tes
)
1075 DEFINE_PROG_DATA_DOWNCAST(gs
)
1076 DEFINE_PROG_DATA_DOWNCAST(wm
)
1077 DEFINE_PROG_DATA_DOWNCAST(cs
)
1078 DEFINE_PROG_DATA_DOWNCAST(ff_gs
)
1079 DEFINE_PROG_DATA_DOWNCAST(clip
)
1080 DEFINE_PROG_DATA_DOWNCAST(sf
)
1081 #undef DEFINE_PROG_DATA_DOWNCAST
1085 struct brw_compiler
*
1086 brw_compiler_create(void *mem_ctx
, const struct gen_device_info
*devinfo
);
1089 * Compile a vertex shader.
1091 * Returns the final assembly and the program's size.
1094 brw_compile_vs(const struct brw_compiler
*compiler
, void *log_data
,
1096 const struct brw_vs_prog_key
*key
,
1097 struct brw_vs_prog_data
*prog_data
,
1098 const struct nir_shader
*shader
,
1099 bool use_legacy_snorm_formula
,
1100 int shader_time_index
,
1101 unsigned *final_assembly_size
,
1105 * Compile a tessellation control shader.
1107 * Returns the final assembly and the program's size.
1110 brw_compile_tcs(const struct brw_compiler
*compiler
,
1113 const struct brw_tcs_prog_key
*key
,
1114 struct brw_tcs_prog_data
*prog_data
,
1115 const struct nir_shader
*nir
,
1116 int shader_time_index
,
1117 unsigned *final_assembly_size
,
1121 * Compile a tessellation evaluation shader.
1123 * Returns the final assembly and the program's size.
1126 brw_compile_tes(const struct brw_compiler
*compiler
, void *log_data
,
1128 const struct brw_tes_prog_key
*key
,
1129 const struct brw_vue_map
*input_vue_map
,
1130 struct brw_tes_prog_data
*prog_data
,
1131 const struct nir_shader
*shader
,
1132 struct gl_program
*prog
,
1133 int shader_time_index
,
1134 unsigned *final_assembly_size
,
1138 * Compile a vertex shader.
1140 * Returns the final assembly and the program's size.
1143 brw_compile_gs(const struct brw_compiler
*compiler
, void *log_data
,
1145 const struct brw_gs_prog_key
*key
,
1146 struct brw_gs_prog_data
*prog_data
,
1147 const struct nir_shader
*shader
,
1148 struct gl_program
*prog
,
1149 int shader_time_index
,
1150 unsigned *final_assembly_size
,
1154 * Compile a strips and fans shader.
1156 * This is a fixed-function shader determined entirely by the shader key and
1159 * Returns the final assembly and the program's size.
1162 brw_compile_sf(const struct brw_compiler
*compiler
,
1164 const struct brw_sf_prog_key
*key
,
1165 struct brw_sf_prog_data
*prog_data
,
1166 struct brw_vue_map
*vue_map
,
1167 unsigned *final_assembly_size
);
1170 * Compile a clipper shader.
1172 * This is a fixed-function shader determined entirely by the shader key and
1175 * Returns the final assembly and the program's size.
1178 brw_compile_clip(const struct brw_compiler
*compiler
,
1180 const struct brw_clip_prog_key
*key
,
1181 struct brw_clip_prog_data
*prog_data
,
1182 struct brw_vue_map
*vue_map
,
1183 unsigned *final_assembly_size
);
1186 * Compile a fragment shader.
1188 * Returns the final assembly and the program's size.
1191 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
1193 const struct brw_wm_prog_key
*key
,
1194 struct brw_wm_prog_data
*prog_data
,
1195 const struct nir_shader
*shader
,
1196 struct gl_program
*prog
,
1197 int shader_time_index8
,
1198 int shader_time_index16
,
1199 bool allow_spilling
,
1200 bool use_rep_send
, struct brw_vue_map
*vue_map
,
1201 unsigned *final_assembly_size
,
1205 * Compile a compute shader.
1207 * Returns the final assembly and the program's size.
1210 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
1212 const struct brw_cs_prog_key
*key
,
1213 struct brw_cs_prog_data
*prog_data
,
1214 const struct nir_shader
*shader
,
1215 int shader_time_index
,
1216 unsigned *final_assembly_size
,
1219 static inline uint32_t
1220 encode_slm_size(unsigned gen
, uint32_t bytes
)
1222 uint32_t slm_size
= 0;
1224 /* Shared Local Memory is specified as powers of two, and encoded in
1225 * INTERFACE_DESCRIPTOR_DATA with the following representations:
1227 * Size | 0 kB | 1 kB | 2 kB | 4 kB | 8 kB | 16 kB | 32 kB | 64 kB |
1228 * -------------------------------------------------------------------
1229 * Gen7-8 | 0 | none | none | 1 | 2 | 4 | 8 | 16 |
1230 * -------------------------------------------------------------------
1231 * Gen9+ | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
1233 assert(bytes
<= 64 * 1024);
1236 /* Shared Local Memory Size is specified as powers of two. */
1237 slm_size
= util_next_power_of_two(bytes
);
1240 /* Use a minimum of 1kB; turn an exponent of 10 (1024 kB) into 1. */
1241 slm_size
= ffs(MAX2(slm_size
, 1024)) - 10;
1243 /* Use a minimum of 4kB; convert to the pre-Gen9 representation. */
1244 slm_size
= MAX2(slm_size
, 4096) / 4096;
1252 * Return true if the given shader stage is dispatched contiguously by the
1253 * relevant fixed function starting from channel 0 of the SIMD thread, which
1254 * implies that the dispatch mask of a thread can be assumed to have the form
1255 * '2^n - 1' for some n.
1258 brw_stage_has_packed_dispatch(const struct gen_device_info
*devinfo
,
1259 gl_shader_stage stage
,
1260 const struct brw_stage_prog_data
*prog_data
)
1262 /* The code below makes assumptions about the hardware's thread dispatch
1263 * behavior that could be proven wrong in future generations -- Make sure
1264 * to do a full test run with brw_fs_test_dispatch_packing() hooked up to
1265 * the NIR front-end before changing this assertion.
1267 assert(devinfo
->gen
<= 10);
1270 case MESA_SHADER_FRAGMENT
: {
1271 /* The PSD discards subspans coming in with no lit samples, which in the
1272 * per-pixel shading case implies that each subspan will either be fully
1273 * lit (due to the VMask being used to allow derivative computations),
1274 * or not dispatched at all. In per-sample dispatch mode individual
1275 * samples from the same subspan have a fixed relative location within
1276 * the SIMD thread, so dispatch of unlit samples cannot be avoided in
1277 * general and we should return false.
1279 const struct brw_wm_prog_data
*wm_prog_data
=
1280 (const struct brw_wm_prog_data
*)prog_data
;
1281 return !wm_prog_data
->persample_dispatch
;
1283 case MESA_SHADER_COMPUTE
:
1284 /* Compute shaders will be spawned with either a fully enabled dispatch
1285 * mask or with whatever bottom/right execution mask was given to the
1286 * GPGPU walker command to be used along the workgroup edges -- In both
1287 * cases the dispatch mask is required to be tightly packed for our
1288 * invocation index calculations to work.
1292 /* Most remaining fixed functions are limited to use a packed dispatch
1293 * mask due to the hardware representation of the dispatch mask as a
1294 * single counter representing the number of enabled channels.
1301 * Computes the first varying slot in the URB produced by the previous stage
1302 * that is used in the next stage. We do this by testing the varying slots in
1303 * the previous stage's vue map against the inputs read in the next stage.
1307 * - Each URB offset contains two varying slots and we can only skip a
1308 * full offset if both slots are unused, so the value we return here is always
1309 * rounded down to the closest multiple of two.
1311 * - gl_Layer and gl_ViewportIndex don't have their own varying slots, they are
1312 * part of the vue header, so if these are read we can't skip anything.
1315 brw_compute_first_urb_slot_required(uint64_t inputs_read
,
1316 const struct brw_vue_map
*prev_stage_vue_map
)
1318 if ((inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
)) == 0) {
1319 for (int i
= 0; i
< prev_stage_vue_map
->num_slots
; i
++) {
1320 int varying
= prev_stage_vue_map
->slot_to_varying
[i
];
1321 if (varying
> 0 && (inputs_read
& BITFIELD64_BIT(varying
)) != 0)
1322 return ROUND_DOWN_TO(i
, 2);
1333 #endif /* BRW_COMPILER_H */