2 * Copyright © 2010 - 2015 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #ifndef BRW_COMPILER_H
25 #define BRW_COMPILER_H
28 #include "dev/gen_device_info.h"
29 #include "main/macros.h"
30 #include "main/mtypes.h"
31 #include "util/ralloc.h"
42 const struct gen_device_info
*devinfo
;
48 * Array of the ra classes for the unaligned contiguous register
54 * Mapping for register-allocated objects in *regs to the first
55 * GRF for that object.
57 uint8_t *ra_reg_to_grf
;
64 * Array of the ra classes for the unaligned contiguous register
65 * block sizes used, indexed by register size.
70 * Mapping from classes to ra_reg ranges. Each of the per-size
71 * classes corresponds to a range of ra_reg nodes. This array stores
72 * those ranges in the form of first ra_reg in each class and the
73 * total number of ra_reg elements in the last array element. This
74 * way the range of the i'th class is given by:
75 * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] )
77 int class_to_ra_reg_range
[17];
80 * Mapping for register-allocated objects in *regs to the first
81 * GRF for that object.
83 uint8_t *ra_reg_to_grf
;
86 * ra class for the aligned pairs we use for PLN, which doesn't
89 int aligned_pairs_class
;
92 void (*shader_debug_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
93 void (*shader_perf_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
95 bool scalar_stage
[MESA_SHADER_STAGES
];
96 struct gl_shader_compiler_options glsl_compiler_options
[MESA_SHADER_STAGES
];
99 * Apply workarounds for SIN and COS output range problems.
100 * This can negatively impact performance.
105 * Is 3DSTATE_CONSTANT_*'s Constant Buffer 0 relative to Dynamic State
106 * Base Address? (If not, it's a normal GPU address.)
108 bool constant_buffer_0_is_relative
;
111 * Whether or not the driver supports pull constants. If not, the compiler
112 * will attempt to push everything.
114 bool supports_pull_constants
;
117 * Whether or not the driver supports NIR shader constants. This controls
118 * whether nir_opt_large_constants will be run.
120 bool supports_shader_constants
;
124 * We use a constant subgroup size of 32. It really only needs to be a
125 * maximum and, since we do SIMD32 for compute shaders in some cases, it
126 * needs to be at least 32. SIMD8 and SIMD16 shaders will still claim a
127 * subgroup size of 32 but will act as if 16 or 24 of those channels are
130 #define BRW_SUBGROUP_SIZE 32
133 * Program key structures.
135 * When drawing, we look for the currently bound shaders in the program
136 * cache. This is essentially a hash table lookup, and these are the keys.
138 * Sometimes OpenGL features specified as state need to be simulated via
139 * shader code, due to a mismatch between the API and the hardware. This
140 * is often referred to as "non-orthagonal state" or "NOS". We store NOS
141 * in the program key so it's considered when searching for a program. If
142 * we haven't seen a particular combination before, we have to recompile a
143 * new specialized version.
145 * Shader compilation should not look up state in gl_context directly, but
146 * instead use the copy in the program key. This guarantees recompiles will
152 enum PACKED gen6_gather_sampler_wa
{
153 WA_SIGN
= 1, /* whether we need to sign extend */
154 WA_8BIT
= 2, /* if we have an 8bit format needing wa */
155 WA_16BIT
= 4, /* if we have a 16bit format needing wa */
159 * Sampler information needed by VS, WM, and GS program cache keys.
161 struct brw_sampler_prog_key_data
{
163 * EXT_texture_swizzle and DEPTH_TEXTURE_MODE swizzles.
165 uint16_t swizzles
[MAX_SAMPLERS
];
167 uint32_t gl_clamp_mask
[3];
170 * For RG32F, gather4's channel select is broken.
172 uint32_t gather_channel_quirk_mask
;
175 * Whether this sampler uses the compressed multisample surface layout.
177 uint32_t compressed_multisample_layout_mask
;
180 * Whether this sampler is using 16x multisampling. If so fetching from
181 * this sampler will be handled with a different instruction, ld2dms_w
187 * For Sandybridge, which shader w/a we need for gather quirks.
189 enum gen6_gather_sampler_wa gen6_gather_wa
[MAX_SAMPLERS
];
192 * Texture units that have a YUV image bound.
194 uint32_t y_u_v_image_mask
;
195 uint32_t y_uv_image_mask
;
196 uint32_t yx_xuxv_image_mask
;
197 uint32_t xy_uxvx_image_mask
;
201 * The VF can't natively handle certain types of attributes, such as GL_FIXED
202 * or most 10_10_10_2 types. These flags enable various VS workarounds to
203 * "fix" attributes at the beginning of shaders.
205 #define BRW_ATTRIB_WA_COMPONENT_MASK 7 /* mask for GL_FIXED scale channel count */
206 #define BRW_ATTRIB_WA_NORMALIZE 8 /* normalize in shader */
207 #define BRW_ATTRIB_WA_BGRA 16 /* swap r/b channels in shader */
208 #define BRW_ATTRIB_WA_SIGN 32 /* interpret as signed in shader */
209 #define BRW_ATTRIB_WA_SCALE 64 /* interpret as scaled in shader */
212 * OpenGL attribute slots fall in [0, VERT_ATTRIB_MAX - 1] with the range
213 * [VERT_ATTRIB_GENERIC0, VERT_ATTRIB_MAX - 1] reserved for up to 16 user
214 * input vertex attributes. In Vulkan, we expose up to 28 user vertex input
215 * attributes that are mapped to slots also starting at VERT_ATTRIB_GENERIC0.
217 #define MAX_GL_VERT_ATTRIB VERT_ATTRIB_MAX
218 #define MAX_VK_VERT_ATTRIB (VERT_ATTRIB_GENERIC0 + 28)
220 /** The program key for Vertex Shaders. */
221 struct brw_vs_prog_key
{
222 unsigned program_string_id
;
225 * Per-attribute workaround flags
227 * For each attribute, a combination of BRW_ATTRIB_WA_*.
229 * For OpenGL, where we expose a maximum of 16 user input atttributes
230 * we only need up to VERT_ATTRIB_MAX slots, however, in Vulkan
231 * slots preceding VERT_ATTRIB_GENERIC0 are unused and we can
232 * expose up to 28 user input vertex attributes that are mapped to slots
233 * starting at VERT_ATTRIB_GENERIC0, so this array needs to be large
234 * enough to hold this many slots.
236 uint8_t gl_attrib_wa_flags
[MAX2(MAX_GL_VERT_ATTRIB
, MAX_VK_VERT_ATTRIB
)];
238 bool copy_edgeflag
:1;
240 bool clamp_vertex_color
:1;
243 * How many user clipping planes are being uploaded to the vertex shader as
246 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
249 unsigned nr_userclip_plane_consts
:4;
252 * For pre-Gen6 hardware, a bitfield indicating which texture coordinates
253 * are going to be replaced with point coordinates (as a consequence of a
254 * call to glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)). Because
255 * our SF thread requires exact matching between VS outputs and FS inputs,
256 * these texture coordinates will need to be unconditionally included in
257 * the VUE, even if they aren't written by the vertex shader.
259 uint8_t point_coord_replace
;
261 struct brw_sampler_prog_key_data tex
;
264 /** The program key for Tessellation Control Shaders. */
265 struct brw_tcs_prog_key
267 unsigned program_string_id
;
269 GLenum tes_primitive_mode
;
271 unsigned input_vertices
;
273 /** A bitfield of per-patch outputs written. */
274 uint32_t patch_outputs_written
;
276 /** A bitfield of per-vertex outputs written. */
277 uint64_t outputs_written
;
279 bool quads_workaround
;
281 struct brw_sampler_prog_key_data tex
;
284 /** The program key for Tessellation Evaluation Shaders. */
285 struct brw_tes_prog_key
287 unsigned program_string_id
;
289 /** A bitfield of per-patch inputs read. */
290 uint32_t patch_inputs_read
;
292 /** A bitfield of per-vertex inputs read. */
293 uint64_t inputs_read
;
295 struct brw_sampler_prog_key_data tex
;
298 /** The program key for Geometry Shaders. */
299 struct brw_gs_prog_key
301 unsigned program_string_id
;
303 struct brw_sampler_prog_key_data tex
;
306 enum brw_sf_primitive
{
307 BRW_SF_PRIM_POINTS
= 0,
308 BRW_SF_PRIM_LINES
= 1,
309 BRW_SF_PRIM_TRIANGLES
= 2,
310 BRW_SF_PRIM_UNFILLED_TRIS
= 3,
313 struct brw_sf_prog_key
{
315 bool contains_flat_varying
;
316 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
317 uint8_t point_sprite_coord_replace
;
318 enum brw_sf_primitive primitive
:2;
319 bool do_twoside_color
:1;
320 bool frontface_ccw
:1;
321 bool do_point_sprite
:1;
322 bool do_point_coord
:1;
323 bool sprite_origin_lower_left
:1;
324 bool userclip_active
:1;
328 BRW_CLIP_MODE_NORMAL
= 0,
329 BRW_CLIP_MODE_CLIP_ALL
= 1,
330 BRW_CLIP_MODE_CLIP_NON_REJECTED
= 2,
331 BRW_CLIP_MODE_REJECT_ALL
= 3,
332 BRW_CLIP_MODE_ACCEPT_ALL
= 4,
333 BRW_CLIP_MODE_KERNEL_CLIP
= 5,
336 enum brw_clip_fill_mode
{
337 BRW_CLIP_FILL_MODE_LINE
= 0,
338 BRW_CLIP_FILL_MODE_POINT
= 1,
339 BRW_CLIP_FILL_MODE_FILL
= 2,
340 BRW_CLIP_FILL_MODE_CULL
= 3,
343 /* Note that if unfilled primitives are being emitted, we have to fix
344 * up polygon offset and flatshading at this point:
346 struct brw_clip_prog_key
{
348 bool contains_flat_varying
;
349 bool contains_noperspective_varying
;
350 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
351 unsigned primitive
:4;
352 unsigned nr_userclip
:4;
355 enum brw_clip_fill_mode fill_cw
:2; /* includes cull information */
356 enum brw_clip_fill_mode fill_ccw
:2; /* includes cull information */
361 enum brw_clip_mode clip_mode
:3;
368 /* A big lookup table is used to figure out which and how many
369 * additional regs will inserted before the main payload in the WM
370 * program execution. These mainly relate to depth and stencil
371 * processing and the early-depth-test optimization.
373 enum brw_wm_iz_bits
{
374 BRW_WM_IZ_PS_KILL_ALPHATEST_BIT
= 0x1,
375 BRW_WM_IZ_PS_COMPUTES_DEPTH_BIT
= 0x2,
376 BRW_WM_IZ_DEPTH_WRITE_ENABLE_BIT
= 0x4,
377 BRW_WM_IZ_DEPTH_TEST_ENABLE_BIT
= 0x8,
378 BRW_WM_IZ_STENCIL_WRITE_ENABLE_BIT
= 0x10,
379 BRW_WM_IZ_STENCIL_TEST_ENABLE_BIT
= 0x20,
380 BRW_WM_IZ_BIT_MAX
= 0x40
383 enum brw_wm_aa_enable
{
389 /** The program key for Fragment/Pixel Shaders. */
390 struct brw_wm_prog_key
{
391 /* Some collection of BRW_WM_IZ_* */
395 unsigned nr_color_regions
:5;
396 bool replicate_alpha
:1;
397 bool clamp_fragment_color
:1;
398 bool persample_interp
:1;
399 bool multisample_fbo
:1;
400 bool frag_coord_adds_sample_pos
:1;
401 enum brw_wm_aa_enable line_aa
:2;
402 bool high_quality_derivatives
:1;
403 bool force_dual_color_blend
:1;
404 bool coherent_fb_fetch
:1;
406 uint8_t color_outputs_valid
;
407 uint64_t input_slots_valid
;
408 unsigned program_string_id
;
409 GLenum alpha_test_func
; /* < For Gen4/5 MRT alpha test */
410 float alpha_test_ref
;
412 struct brw_sampler_prog_key_data tex
;
415 struct brw_cs_prog_key
{
416 uint32_t program_string_id
;
417 struct brw_sampler_prog_key_data tex
;
420 /* brw_any_prog_key is any of the keys that map to an API stage */
421 union brw_any_prog_key
{
422 struct brw_vs_prog_key vs
;
423 struct brw_tcs_prog_key tcs
;
424 struct brw_tes_prog_key tes
;
425 struct brw_gs_prog_key gs
;
426 struct brw_wm_prog_key wm
;
427 struct brw_cs_prog_key cs
;
431 * Image metadata structure as laid out in the shader parameter
432 * buffer. Entries have to be 16B-aligned for the vec4 back-end to be
433 * able to use them. That's okay because the padding and any unused
434 * entries [most of them except when we're doing untyped surface
435 * access] will be removed by the uniform packing pass.
437 #define BRW_IMAGE_PARAM_OFFSET_OFFSET 0
438 #define BRW_IMAGE_PARAM_SIZE_OFFSET 4
439 #define BRW_IMAGE_PARAM_STRIDE_OFFSET 8
440 #define BRW_IMAGE_PARAM_TILING_OFFSET 12
441 #define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 16
442 #define BRW_IMAGE_PARAM_SIZE 20
444 struct brw_image_param
{
445 /** Offset applied to the X and Y surface coordinates. */
448 /** Surface X, Y and Z dimensions. */
451 /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
452 * pixels, vertical slice stride in pixels.
456 /** Log2 of the tiling modulus in the X, Y and Z dimension. */
460 * Right shift to apply for bit 6 address swizzling. Two different
461 * swizzles can be specified and will be applied one after the other. The
462 * resulting address will be:
464 * addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
465 * (addr >> swizzling[1])))
467 * Use \c 0xff if any of the swizzles is not required.
469 uint32_t swizzling
[2];
472 /** Max number of render targets in a shader */
473 #define BRW_MAX_DRAW_BUFFERS 8
476 * Max number of binding table entries used for stream output.
478 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
479 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
481 * On Gen6, the size of transform feedback data is limited not by the number
482 * of components but by the number of binding table entries we set aside. We
483 * use one binding table entry for a float, one entry for a vector, and one
484 * entry per matrix column. Since the only way we can communicate our
485 * transform feedback capabilities to the client is via
486 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
487 * worst case, in which all the varyings are floats, so we use up one binding
488 * table entry per component. Therefore we need to set aside at least 64
489 * binding table entries for use by transform feedback.
491 * Note: since we don't currently pack varyings, it is currently impossible
492 * for the client to actually use up all of these binding table entries--if
493 * all of their varyings were floats, they would run out of varying slots and
494 * fail to link. But that's a bug, so it seems prudent to go ahead and
495 * allocate the number of binding table entries we will need once the bug is
498 #define BRW_MAX_SOL_BINDINGS 64
501 * Binding table index for the first gen6 SOL binding.
503 #define BRW_GEN6_SOL_BINDING_START 0
506 * Stride in bytes between shader_time entries.
508 * We separate entries by a cacheline to reduce traffic between EUs writing to
511 #define BRW_SHADER_TIME_STRIDE 64
520 /* We reserve the first 2^16 values for builtins */
521 #define BRW_PARAM_IS_BUILTIN(param) (((param) & 0xffff0000) == 0)
523 enum brw_param_builtin
{
524 BRW_PARAM_BUILTIN_ZERO
,
526 BRW_PARAM_BUILTIN_CLIP_PLANE_0_X
,
527 BRW_PARAM_BUILTIN_CLIP_PLANE_0_Y
,
528 BRW_PARAM_BUILTIN_CLIP_PLANE_0_Z
,
529 BRW_PARAM_BUILTIN_CLIP_PLANE_0_W
,
530 BRW_PARAM_BUILTIN_CLIP_PLANE_1_X
,
531 BRW_PARAM_BUILTIN_CLIP_PLANE_1_Y
,
532 BRW_PARAM_BUILTIN_CLIP_PLANE_1_Z
,
533 BRW_PARAM_BUILTIN_CLIP_PLANE_1_W
,
534 BRW_PARAM_BUILTIN_CLIP_PLANE_2_X
,
535 BRW_PARAM_BUILTIN_CLIP_PLANE_2_Y
,
536 BRW_PARAM_BUILTIN_CLIP_PLANE_2_Z
,
537 BRW_PARAM_BUILTIN_CLIP_PLANE_2_W
,
538 BRW_PARAM_BUILTIN_CLIP_PLANE_3_X
,
539 BRW_PARAM_BUILTIN_CLIP_PLANE_3_Y
,
540 BRW_PARAM_BUILTIN_CLIP_PLANE_3_Z
,
541 BRW_PARAM_BUILTIN_CLIP_PLANE_3_W
,
542 BRW_PARAM_BUILTIN_CLIP_PLANE_4_X
,
543 BRW_PARAM_BUILTIN_CLIP_PLANE_4_Y
,
544 BRW_PARAM_BUILTIN_CLIP_PLANE_4_Z
,
545 BRW_PARAM_BUILTIN_CLIP_PLANE_4_W
,
546 BRW_PARAM_BUILTIN_CLIP_PLANE_5_X
,
547 BRW_PARAM_BUILTIN_CLIP_PLANE_5_Y
,
548 BRW_PARAM_BUILTIN_CLIP_PLANE_5_Z
,
549 BRW_PARAM_BUILTIN_CLIP_PLANE_5_W
,
550 BRW_PARAM_BUILTIN_CLIP_PLANE_6_X
,
551 BRW_PARAM_BUILTIN_CLIP_PLANE_6_Y
,
552 BRW_PARAM_BUILTIN_CLIP_PLANE_6_Z
,
553 BRW_PARAM_BUILTIN_CLIP_PLANE_6_W
,
554 BRW_PARAM_BUILTIN_CLIP_PLANE_7_X
,
555 BRW_PARAM_BUILTIN_CLIP_PLANE_7_Y
,
556 BRW_PARAM_BUILTIN_CLIP_PLANE_7_Z
,
557 BRW_PARAM_BUILTIN_CLIP_PLANE_7_W
,
559 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
,
560 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Y
,
561 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Z
,
562 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_W
,
563 BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
,
564 BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y
,
566 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_X
,
567 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Y
,
568 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Z
,
569 BRW_PARAM_BUILTIN_SUBGROUP_ID
,
572 #define BRW_PARAM_BUILTIN_CLIP_PLANE(idx, comp) \
573 (BRW_PARAM_BUILTIN_CLIP_PLANE_0_X + ((idx) << 2) + (comp))
575 #define BRW_PARAM_BUILTIN_IS_CLIP_PLANE(param) \
576 ((param) >= BRW_PARAM_BUILTIN_CLIP_PLANE_0_X && \
577 (param) <= BRW_PARAM_BUILTIN_CLIP_PLANE_7_W)
579 #define BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(param) \
580 (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) >> 2)
582 #define BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(param) \
583 (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) & 0x3)
585 struct brw_stage_prog_data
{
587 /** size of our binding table. */
591 * surface indices for the various groups of surfaces
593 uint32_t pull_constants_start
;
594 uint32_t texture_start
;
595 uint32_t gather_texture_start
;
598 uint32_t image_start
;
599 uint32_t shader_time_start
;
600 uint32_t plane_start
[3];
604 struct brw_ubo_range ubo_ranges
[4];
606 GLuint nr_params
; /**< number of float params/constants */
607 GLuint nr_pull_params
;
609 unsigned curb_read_length
;
610 unsigned total_scratch
;
611 unsigned total_shared
;
613 unsigned program_size
;
616 * Register where the thread expects to find input data from the URB
617 * (typically uniforms, followed by vertex or fragment attributes).
619 unsigned dispatch_grf_start_reg
;
621 bool use_alt_mode
; /**< Use ALT floating point mode? Otherwise, IEEE. */
623 /* 32-bit identifiers for all push/pull parameters. These can be anything
624 * the driver wishes them to be; the core of the back-end compiler simply
625 * re-arranges them. The one restriction is that the bottom 2^16 values
626 * are reserved for builtins defined in the brw_param_builtin enum defined
630 uint32_t *pull_param
;
633 static inline uint32_t *
634 brw_stage_prog_data_add_params(struct brw_stage_prog_data
*prog_data
,
635 unsigned nr_new_params
)
637 unsigned old_nr_params
= prog_data
->nr_params
;
638 prog_data
->nr_params
+= nr_new_params
;
639 prog_data
->param
= reralloc(ralloc_parent(prog_data
->param
),
640 prog_data
->param
, uint32_t,
641 prog_data
->nr_params
);
642 return prog_data
->param
+ old_nr_params
;
646 brw_mark_surface_used(struct brw_stage_prog_data
*prog_data
,
649 /* A binding table index is 8 bits and the top 3 values are reserved for
650 * special things (stateless and SLM).
652 assert(surf_index
<= 252);
654 prog_data
->binding_table
.size_bytes
=
655 MAX2(prog_data
->binding_table
.size_bytes
, (surf_index
+ 1) * 4);
658 enum brw_barycentric_mode
{
659 BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
= 0,
660 BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
= 1,
661 BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
= 2,
662 BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL
= 3,
663 BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
= 4,
664 BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE
= 5,
665 BRW_BARYCENTRIC_MODE_COUNT
= 6
667 #define BRW_BARYCENTRIC_NONPERSPECTIVE_BITS \
668 ((1 << BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL) | \
669 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID) | \
670 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE))
672 enum brw_pixel_shader_computed_depth_mode
{
673 BRW_PSCDEPTH_OFF
= 0, /* PS does not compute depth */
674 BRW_PSCDEPTH_ON
= 1, /* PS computes depth; no guarantee about value */
675 BRW_PSCDEPTH_ON_GE
= 2, /* PS guarantees output depth >= source depth */
676 BRW_PSCDEPTH_ON_LE
= 3, /* PS guarantees output depth <= source depth */
679 /* Data about a particular attempt to compile a program. Note that
680 * there can be many of these, each in a different GL state
681 * corresponding to a different brw_wm_prog_key struct, with different
684 struct brw_wm_prog_data
{
685 struct brw_stage_prog_data base
;
687 GLuint num_varying_inputs
;
689 uint8_t reg_blocks_8
;
690 uint8_t reg_blocks_16
;
691 uint8_t reg_blocks_32
;
693 uint8_t dispatch_grf_start_reg_16
;
694 uint8_t dispatch_grf_start_reg_32
;
695 uint32_t prog_offset_16
;
696 uint32_t prog_offset_32
;
700 * surface indices the WM-specific surfaces
702 uint32_t render_target_read_start
;
706 uint8_t computed_depth_mode
;
707 bool computed_stencil
;
709 bool early_fragment_tests
;
710 bool post_depth_coverage
;
716 bool persample_dispatch
;
717 bool uses_pos_offset
;
722 bool uses_sample_mask
;
723 bool has_render_target_reads
;
724 bool has_side_effects
;
727 bool contains_flat_varying
;
728 bool contains_noperspective_varying
;
731 * Mask of which interpolation modes are required by the fragment shader.
732 * Used in hardware setup on gen6+.
734 uint32_t barycentric_interp_modes
;
737 * Mask of which FS inputs are marked flat by the shader source. This is
738 * needed for setting up 3DSTATE_SF/SBE.
740 uint32_t flat_inputs
;
742 /* Mapping of VUE slots to interpolation modes.
743 * Used by the Gen4-5 clip/sf/wm stages.
745 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
748 * Map from gl_varying_slot to the position within the FS setup data
749 * payload where the varying's attribute vertex deltas should be delivered.
750 * For varying slots that are not used by the FS, the value is -1.
752 int urb_setup
[VARYING_SLOT_MAX
];
755 /** Returns the SIMD width corresponding to a given KSP index
757 * The "Variable Pixel Dispatch" table in the PRM (which can be found, for
758 * example in Vol. 7 of the SKL PRM) has a mapping from dispatch widths to
759 * kernel start pointer (KSP) indices that is based on what dispatch widths
760 * are enabled. This function provides, effectively, the reverse mapping.
762 * If the given KSP is valid with respect to the SIMD8/16/32 enables, a SIMD
763 * width of 8, 16, or 32 is returned. If the KSP is invalid, 0 is returned.
765 static inline unsigned
766 brw_fs_simd_width_for_ksp(unsigned ksp_idx
, bool simd8_enabled
,
767 bool simd16_enabled
, bool simd32_enabled
)
769 /* This function strictly ignores contiguous dispatch */
772 return simd8_enabled
? 8 :
773 (simd16_enabled
&& !simd32_enabled
) ? 16 :
774 (simd32_enabled
&& !simd16_enabled
) ? 32 : 0;
776 return (simd32_enabled
&& (simd16_enabled
|| simd8_enabled
)) ? 32 : 0;
778 return (simd16_enabled
&& (simd32_enabled
|| simd8_enabled
)) ? 16 : 0;
780 unreachable("Invalid KSP index");
784 #define brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx) \
785 brw_fs_simd_width_for_ksp((ksp_idx), (wm_state)._8PixelDispatchEnable, \
786 (wm_state)._16PixelDispatchEnable, \
787 (wm_state)._32PixelDispatchEnable)
789 #define brw_wm_state_has_ksp(wm_state, ksp_idx) \
790 (brw_wm_state_simd_width_for_ksp((wm_state), (ksp_idx)) != 0)
792 static inline uint32_t
793 _brw_wm_prog_data_prog_offset(const struct brw_wm_prog_data
*prog_data
,
796 switch (simd_width
) {
798 case 16: return prog_data
->prog_offset_16
;
799 case 32: return prog_data
->prog_offset_32
;
804 #define brw_wm_prog_data_prog_offset(prog_data, wm_state, ksp_idx) \
805 _brw_wm_prog_data_prog_offset(prog_data, \
806 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
808 static inline uint8_t
809 _brw_wm_prog_data_dispatch_grf_start_reg(const struct brw_wm_prog_data
*prog_data
,
812 switch (simd_width
) {
813 case 8: return prog_data
->base
.dispatch_grf_start_reg
;
814 case 16: return prog_data
->dispatch_grf_start_reg_16
;
815 case 32: return prog_data
->dispatch_grf_start_reg_32
;
820 #define brw_wm_prog_data_dispatch_grf_start_reg(prog_data, wm_state, ksp_idx) \
821 _brw_wm_prog_data_dispatch_grf_start_reg(prog_data, \
822 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
824 static inline uint8_t
825 _brw_wm_prog_data_reg_blocks(const struct brw_wm_prog_data
*prog_data
,
828 switch (simd_width
) {
829 case 8: return prog_data
->reg_blocks_8
;
830 case 16: return prog_data
->reg_blocks_16
;
831 case 32: return prog_data
->reg_blocks_32
;
836 #define brw_wm_prog_data_reg_blocks(prog_data, wm_state, ksp_idx) \
837 _brw_wm_prog_data_reg_blocks(prog_data, \
838 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
840 struct brw_push_const_block
{
841 unsigned dwords
; /* Dword count, not reg aligned */
843 unsigned size
; /* Bytes, register aligned */
846 struct brw_cs_prog_data
{
847 struct brw_stage_prog_data base
;
849 unsigned local_size
[3];
853 bool uses_num_work_groups
;
856 struct brw_push_const_block cross_thread
;
857 struct brw_push_const_block per_thread
;
858 struct brw_push_const_block total
;
863 * surface indices the CS-specific surfaces
865 uint32_t work_groups_start
;
871 * Enum representing the i965-specific vertex results that don't correspond
872 * exactly to any element of gl_varying_slot. The values of this enum are
873 * assigned such that they don't conflict with gl_varying_slot.
877 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
878 BRW_VARYING_SLOT_PAD
,
880 * Technically this is not a varying but just a placeholder that
881 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
882 * builtin variable to be compiled correctly. see compile_sf_prog() for
885 BRW_VARYING_SLOT_PNTC
,
886 BRW_VARYING_SLOT_COUNT
890 * We always program SF to start reading at an offset of 1 (2 varying slots)
891 * from the start of the vertex URB entry. This causes it to skip:
892 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
893 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
895 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
898 * Bitmask indicating which fragment shader inputs represent varyings (and
899 * hence have to be delivered to the fragment shader by the SF/SBE stage).
901 #define BRW_FS_VARYING_INPUT_MASK \
902 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
903 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
906 * Data structure recording the relationship between the gl_varying_slot enum
907 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
908 * single octaword within the VUE (128 bits).
910 * Note that each BRW register contains 256 bits (2 octawords), so when
911 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
912 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
913 * in a vertex shader), each register corresponds to a single VUE slot, since
914 * it contains data for two separate vertices.
918 * Bitfield representing all varying slots that are (a) stored in this VUE
919 * map, and (b) actually written by the shader. Does not include any of
920 * the additional varying slots defined in brw_varying_slot.
922 uint64_t slots_valid
;
925 * Is this VUE map for a separate shader pipeline?
927 * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched
928 * without the linker having a chance to dead code eliminate unused varyings.
930 * This means that we have to use a fixed slot layout, based on the output's
931 * location field, rather than assigning slots in a compact contiguous block.
936 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
937 * not stored in a slot (because they are not written, or because
938 * additional processing is applied before storing them in the VUE), the
941 signed char varying_to_slot
[VARYING_SLOT_TESS_MAX
];
944 * Map from VUE slot to gl_varying_slot value. For slots that do not
945 * directly correspond to a gl_varying_slot, the value comes from
948 * For slots that are not in use, the value is BRW_VARYING_SLOT_PAD.
950 signed char slot_to_varying
[VARYING_SLOT_TESS_MAX
];
953 * Total number of VUE slots in use
958 * Number of per-patch VUE slots. Only valid for tessellation control
959 * shader outputs and tessellation evaluation shader inputs.
961 int num_per_patch_slots
;
964 * Number of per-vertex VUE slots. Only valid for tessellation control
965 * shader outputs and tessellation evaluation shader inputs.
967 int num_per_vertex_slots
;
970 void brw_print_vue_map(FILE *fp
, const struct brw_vue_map
*vue_map
);
973 * Convert a VUE slot number into a byte offset within the VUE.
975 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
981 * Convert a vertex output (brw_varying_slot) into a byte offset within the
985 GLuint
brw_varying_to_offset(const struct brw_vue_map
*vue_map
, GLuint varying
)
987 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
990 void brw_compute_vue_map(const struct gen_device_info
*devinfo
,
991 struct brw_vue_map
*vue_map
,
992 uint64_t slots_valid
,
993 bool separate_shader
);
995 void brw_compute_tess_vue_map(struct brw_vue_map
*const vue_map
,
996 uint64_t slots_valid
,
999 /* brw_interpolation_map.c */
1000 void brw_setup_vue_interpolation(struct brw_vue_map
*vue_map
,
1001 struct nir_shader
*nir
,
1002 struct brw_wm_prog_data
*prog_data
,
1003 const struct gen_device_info
*devinfo
);
1005 enum shader_dispatch_mode
{
1006 DISPATCH_MODE_4X1_SINGLE
= 0,
1007 DISPATCH_MODE_4X2_DUAL_INSTANCE
= 1,
1008 DISPATCH_MODE_4X2_DUAL_OBJECT
= 2,
1009 DISPATCH_MODE_SIMD8
= 3,
1013 * @defgroup Tessellator parameter enumerations.
1015 * These correspond to the hardware values in 3DSTATE_TE, and are provided
1016 * as part of the tessellation evaluation shader.
1020 enum brw_tess_partitioning
{
1021 BRW_TESS_PARTITIONING_INTEGER
= 0,
1022 BRW_TESS_PARTITIONING_ODD_FRACTIONAL
= 1,
1023 BRW_TESS_PARTITIONING_EVEN_FRACTIONAL
= 2,
1026 enum brw_tess_output_topology
{
1027 BRW_TESS_OUTPUT_TOPOLOGY_POINT
= 0,
1028 BRW_TESS_OUTPUT_TOPOLOGY_LINE
= 1,
1029 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
= 2,
1030 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW
= 3,
1033 enum brw_tess_domain
{
1034 BRW_TESS_DOMAIN_QUAD
= 0,
1035 BRW_TESS_DOMAIN_TRI
= 1,
1036 BRW_TESS_DOMAIN_ISOLINE
= 2,
1040 struct brw_vue_prog_data
{
1041 struct brw_stage_prog_data base
;
1042 struct brw_vue_map vue_map
;
1044 /** Should the hardware deliver input VUE handles for URB pull loads? */
1045 bool include_vue_handles
;
1047 GLuint urb_read_length
;
1050 uint32_t clip_distance_mask
;
1051 uint32_t cull_distance_mask
;
1053 /* Used for calculating urb partitions. In the VS, this is the size of the
1054 * URB entry used for both input and output to the thread. In the GS, this
1055 * is the size of the URB entry used for output.
1057 GLuint urb_entry_size
;
1059 enum shader_dispatch_mode dispatch_mode
;
1062 struct brw_vs_prog_data
{
1063 struct brw_vue_prog_data base
;
1065 GLbitfield64 inputs_read
;
1066 GLbitfield64 double_inputs_read
;
1068 unsigned nr_attribute_slots
;
1071 bool uses_instanceid
;
1072 bool uses_is_indexed_draw
;
1073 bool uses_firstvertex
;
1074 bool uses_baseinstance
;
1078 struct brw_tcs_prog_data
1080 struct brw_vue_prog_data base
;
1082 /** Number vertices in output patch */
1087 struct brw_tes_prog_data
1089 struct brw_vue_prog_data base
;
1091 enum brw_tess_partitioning partitioning
;
1092 enum brw_tess_output_topology output_topology
;
1093 enum brw_tess_domain domain
;
1096 struct brw_gs_prog_data
1098 struct brw_vue_prog_data base
;
1100 unsigned vertices_in
;
1103 * Size of an output vertex, measured in HWORDS (32 bytes).
1105 unsigned output_vertex_size_hwords
;
1107 unsigned output_topology
;
1110 * Size of the control data (cut bits or StreamID bits), in hwords (32
1111 * bytes). 0 if there is no control data.
1113 unsigned control_data_header_size_hwords
;
1116 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
1117 * if the control data is StreamID bits, or
1118 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
1119 * Ignored if control_data_header_size is 0.
1121 unsigned control_data_format
;
1123 bool include_primitive_id
;
1126 * The number of vertices emitted, if constant - otherwise -1.
1128 int static_vertex_count
;
1133 * Gen6: Provoking vertex convention for odd-numbered triangles
1139 * Gen6: Number of varyings that are output to transform feedback.
1141 GLuint num_transform_feedback_bindings
:7; /* 0-BRW_MAX_SOL_BINDINGS */
1144 * Gen6: Map from the index of a transform feedback binding table entry to the
1145 * gl_varying_slot that should be streamed out through that binding table
1148 unsigned char transform_feedback_bindings
[64 /* BRW_MAX_SOL_BINDINGS */];
1151 * Gen6: Map from the index of a transform feedback binding table entry to the
1152 * swizzles that should be used when streaming out data through that
1153 * binding table entry.
1155 unsigned char transform_feedback_swizzles
[64 /* BRW_MAX_SOL_BINDINGS */];
1158 struct brw_sf_prog_data
{
1159 uint32_t urb_read_length
;
1162 /* Each vertex may have upto 12 attributes, 4 components each,
1163 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
1166 * Actually we use 4 for each, so call it 12 rows.
1168 unsigned urb_entry_size
;
1171 struct brw_clip_prog_data
{
1172 uint32_t curb_read_length
; /* user planes? */
1174 uint32_t urb_read_length
;
1178 /* brw_any_prog_data is prog_data for any stage that maps to an API stage */
1179 union brw_any_prog_data
{
1180 struct brw_stage_prog_data base
;
1181 struct brw_vue_prog_data vue
;
1182 struct brw_vs_prog_data vs
;
1183 struct brw_tcs_prog_data tcs
;
1184 struct brw_tes_prog_data tes
;
1185 struct brw_gs_prog_data gs
;
1186 struct brw_wm_prog_data wm
;
1187 struct brw_cs_prog_data cs
;
1190 #define DEFINE_PROG_DATA_DOWNCAST(stage) \
1191 static inline struct brw_##stage##_prog_data * \
1192 brw_##stage##_prog_data(struct brw_stage_prog_data *prog_data) \
1194 return (struct brw_##stage##_prog_data *) prog_data; \
1196 DEFINE_PROG_DATA_DOWNCAST(vue
)
1197 DEFINE_PROG_DATA_DOWNCAST(vs
)
1198 DEFINE_PROG_DATA_DOWNCAST(tcs
)
1199 DEFINE_PROG_DATA_DOWNCAST(tes
)
1200 DEFINE_PROG_DATA_DOWNCAST(gs
)
1201 DEFINE_PROG_DATA_DOWNCAST(wm
)
1202 DEFINE_PROG_DATA_DOWNCAST(cs
)
1203 DEFINE_PROG_DATA_DOWNCAST(ff_gs
)
1204 DEFINE_PROG_DATA_DOWNCAST(clip
)
1205 DEFINE_PROG_DATA_DOWNCAST(sf
)
1206 #undef DEFINE_PROG_DATA_DOWNCAST
1210 struct brw_compiler
*
1211 brw_compiler_create(void *mem_ctx
, const struct gen_device_info
*devinfo
);
1214 * Returns a compiler configuration for use with disk shader cache
1216 * This value only needs to change for settings that can cause different
1217 * program generation between two runs on the same hardware.
1219 * For example, it doesn't need to be different for gen 8 and gen 9 hardware,
1220 * but it does need to be different if INTEL_DEBUG=nocompact is or isn't used.
1223 brw_get_compiler_config_value(const struct brw_compiler
*compiler
);
1226 brw_prog_data_size(gl_shader_stage stage
);
1229 brw_prog_key_size(gl_shader_stage stage
);
1232 * Compile a vertex shader.
1234 * Returns the final assembly and the program's size.
1237 brw_compile_vs(const struct brw_compiler
*compiler
, void *log_data
,
1239 const struct brw_vs_prog_key
*key
,
1240 struct brw_vs_prog_data
*prog_data
,
1241 const struct nir_shader
*shader
,
1242 int shader_time_index
,
1246 * Compile a tessellation control shader.
1248 * Returns the final assembly and the program's size.
1251 brw_compile_tcs(const struct brw_compiler
*compiler
,
1254 const struct brw_tcs_prog_key
*key
,
1255 struct brw_tcs_prog_data
*prog_data
,
1256 const struct nir_shader
*nir
,
1257 int shader_time_index
,
1261 * Compile a tessellation evaluation shader.
1263 * Returns the final assembly and the program's size.
1266 brw_compile_tes(const struct brw_compiler
*compiler
, void *log_data
,
1268 const struct brw_tes_prog_key
*key
,
1269 const struct brw_vue_map
*input_vue_map
,
1270 struct brw_tes_prog_data
*prog_data
,
1271 const struct nir_shader
*shader
,
1272 struct gl_program
*prog
,
1273 int shader_time_index
,
1277 * Compile a vertex shader.
1279 * Returns the final assembly and the program's size.
1282 brw_compile_gs(const struct brw_compiler
*compiler
, void *log_data
,
1284 const struct brw_gs_prog_key
*key
,
1285 struct brw_gs_prog_data
*prog_data
,
1286 const struct nir_shader
*shader
,
1287 struct gl_program
*prog
,
1288 int shader_time_index
,
1292 * Compile a strips and fans shader.
1294 * This is a fixed-function shader determined entirely by the shader key and
1297 * Returns the final assembly and the program's size.
1300 brw_compile_sf(const struct brw_compiler
*compiler
,
1302 const struct brw_sf_prog_key
*key
,
1303 struct brw_sf_prog_data
*prog_data
,
1304 struct brw_vue_map
*vue_map
,
1305 unsigned *final_assembly_size
);
1308 * Compile a clipper shader.
1310 * This is a fixed-function shader determined entirely by the shader key and
1313 * Returns the final assembly and the program's size.
1316 brw_compile_clip(const struct brw_compiler
*compiler
,
1318 const struct brw_clip_prog_key
*key
,
1319 struct brw_clip_prog_data
*prog_data
,
1320 struct brw_vue_map
*vue_map
,
1321 unsigned *final_assembly_size
);
1324 * Compile a fragment shader.
1326 * Returns the final assembly and the program's size.
1329 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
1331 const struct brw_wm_prog_key
*key
,
1332 struct brw_wm_prog_data
*prog_data
,
1333 const struct nir_shader
*shader
,
1334 struct gl_program
*prog
,
1335 int shader_time_index8
,
1336 int shader_time_index16
,
1337 int shader_time_index32
,
1338 bool allow_spilling
,
1339 bool use_rep_send
, struct brw_vue_map
*vue_map
,
1343 * Compile a compute shader.
1345 * Returns the final assembly and the program's size.
1348 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
1350 const struct brw_cs_prog_key
*key
,
1351 struct brw_cs_prog_data
*prog_data
,
1352 const struct nir_shader
*shader
,
1353 int shader_time_index
,
1356 static inline uint32_t
1357 encode_slm_size(unsigned gen
, uint32_t bytes
)
1359 uint32_t slm_size
= 0;
1361 /* Shared Local Memory is specified as powers of two, and encoded in
1362 * INTERFACE_DESCRIPTOR_DATA with the following representations:
1364 * Size | 0 kB | 1 kB | 2 kB | 4 kB | 8 kB | 16 kB | 32 kB | 64 kB |
1365 * -------------------------------------------------------------------
1366 * Gen7-8 | 0 | none | none | 1 | 2 | 4 | 8 | 16 |
1367 * -------------------------------------------------------------------
1368 * Gen9+ | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
1370 assert(bytes
<= 64 * 1024);
1373 /* Shared Local Memory Size is specified as powers of two. */
1374 slm_size
= util_next_power_of_two(bytes
);
1377 /* Use a minimum of 1kB; turn an exponent of 10 (1024 kB) into 1. */
1378 slm_size
= ffs(MAX2(slm_size
, 1024)) - 10;
1380 /* Use a minimum of 4kB; convert to the pre-Gen9 representation. */
1381 slm_size
= MAX2(slm_size
, 4096) / 4096;
1389 * Return true if the given shader stage is dispatched contiguously by the
1390 * relevant fixed function starting from channel 0 of the SIMD thread, which
1391 * implies that the dispatch mask of a thread can be assumed to have the form
1392 * '2^n - 1' for some n.
1395 brw_stage_has_packed_dispatch(MAYBE_UNUSED
const struct gen_device_info
*devinfo
,
1396 gl_shader_stage stage
,
1397 const struct brw_stage_prog_data
*prog_data
)
1399 /* The code below makes assumptions about the hardware's thread dispatch
1400 * behavior that could be proven wrong in future generations -- Make sure
1401 * to do a full test run with brw_fs_test_dispatch_packing() hooked up to
1402 * the NIR front-end before changing this assertion.
1404 assert(devinfo
->gen
<= 11);
1407 case MESA_SHADER_FRAGMENT
: {
1408 /* The PSD discards subspans coming in with no lit samples, which in the
1409 * per-pixel shading case implies that each subspan will either be fully
1410 * lit (due to the VMask being used to allow derivative computations),
1411 * or not dispatched at all. In per-sample dispatch mode individual
1412 * samples from the same subspan have a fixed relative location within
1413 * the SIMD thread, so dispatch of unlit samples cannot be avoided in
1414 * general and we should return false.
1416 const struct brw_wm_prog_data
*wm_prog_data
=
1417 (const struct brw_wm_prog_data
*)prog_data
;
1418 return !wm_prog_data
->persample_dispatch
;
1420 case MESA_SHADER_COMPUTE
:
1421 /* Compute shaders will be spawned with either a fully enabled dispatch
1422 * mask or with whatever bottom/right execution mask was given to the
1423 * GPGPU walker command to be used along the workgroup edges -- In both
1424 * cases the dispatch mask is required to be tightly packed for our
1425 * invocation index calculations to work.
1429 /* Most remaining fixed functions are limited to use a packed dispatch
1430 * mask due to the hardware representation of the dispatch mask as a
1431 * single counter representing the number of enabled channels.
1438 * Computes the first varying slot in the URB produced by the previous stage
1439 * that is used in the next stage. We do this by testing the varying slots in
1440 * the previous stage's vue map against the inputs read in the next stage.
1444 * - Each URB offset contains two varying slots and we can only skip a
1445 * full offset if both slots are unused, so the value we return here is always
1446 * rounded down to the closest multiple of two.
1448 * - gl_Layer and gl_ViewportIndex don't have their own varying slots, they are
1449 * part of the vue header, so if these are read we can't skip anything.
1452 brw_compute_first_urb_slot_required(uint64_t inputs_read
,
1453 const struct brw_vue_map
*prev_stage_vue_map
)
1455 if ((inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
)) == 0) {
1456 for (int i
= 0; i
< prev_stage_vue_map
->num_slots
; i
++) {
1457 int varying
= prev_stage_vue_map
->slot_to_varying
[i
];
1458 if (varying
> 0 && (inputs_read
& BITFIELD64_BIT(varying
)) != 0)
1459 return ROUND_DOWN_TO(i
, 2);
1470 #endif /* BRW_COMPILER_H */