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intel/disasm: Properly disassemble indirect SENDs
[mesa.git] / src / intel / compiler / brw_disasm.c
1 /*
2 * Copyright © 2008 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
23 #include <stdio.h>
24 #include <string.h>
25 #include <stdarg.h>
26
27 #include "brw_eu_defines.h"
28 #include "brw_inst.h"
29 #include "brw_shader.h"
30 #include "brw_reg.h"
31 #include "brw_inst.h"
32 #include "brw_eu.h"
33 #include "util/half_float.h"
34
35 static bool
36 has_jip(const struct gen_device_info *devinfo, enum opcode opcode)
37 {
38 if (devinfo->gen < 6)
39 return false;
40
41 return opcode == BRW_OPCODE_IF ||
42 opcode == BRW_OPCODE_ELSE ||
43 opcode == BRW_OPCODE_ENDIF ||
44 opcode == BRW_OPCODE_WHILE ||
45 opcode == BRW_OPCODE_BREAK ||
46 opcode == BRW_OPCODE_CONTINUE ||
47 opcode == BRW_OPCODE_HALT;
48 }
49
50 static bool
51 has_uip(const struct gen_device_info *devinfo, enum opcode opcode)
52 {
53 if (devinfo->gen < 6)
54 return false;
55
56 return (devinfo->gen >= 7 && opcode == BRW_OPCODE_IF) ||
57 (devinfo->gen >= 8 && opcode == BRW_OPCODE_ELSE) ||
58 opcode == BRW_OPCODE_BREAK ||
59 opcode == BRW_OPCODE_CONTINUE ||
60 opcode == BRW_OPCODE_HALT;
61 }
62
63 static bool
64 has_branch_ctrl(const struct gen_device_info *devinfo, enum opcode opcode)
65 {
66 if (devinfo->gen < 8)
67 return false;
68
69 return opcode == BRW_OPCODE_IF ||
70 opcode == BRW_OPCODE_ELSE;
71 /* opcode == BRW_OPCODE_GOTO; */
72 }
73
74 static bool
75 is_logic_instruction(unsigned opcode)
76 {
77 return opcode == BRW_OPCODE_AND ||
78 opcode == BRW_OPCODE_NOT ||
79 opcode == BRW_OPCODE_OR ||
80 opcode == BRW_OPCODE_XOR;
81 }
82
83 static bool
84 is_send(unsigned opcode)
85 {
86 return opcode == BRW_OPCODE_SEND ||
87 opcode == BRW_OPCODE_SENDC ||
88 opcode == BRW_OPCODE_SENDS ||
89 opcode == BRW_OPCODE_SENDSC;
90 }
91
92 static bool
93 is_split_send(UNUSED const struct gen_device_info *devinfo, unsigned opcode)
94 {
95 if (devinfo->gen >= 12)
96 return is_send(opcode);
97 else
98 return opcode == BRW_OPCODE_SENDS ||
99 opcode == BRW_OPCODE_SENDSC;
100 }
101
102 const char *const conditional_modifier[16] = {
103 [BRW_CONDITIONAL_NONE] = "",
104 [BRW_CONDITIONAL_Z] = ".z",
105 [BRW_CONDITIONAL_NZ] = ".nz",
106 [BRW_CONDITIONAL_G] = ".g",
107 [BRW_CONDITIONAL_GE] = ".ge",
108 [BRW_CONDITIONAL_L] = ".l",
109 [BRW_CONDITIONAL_LE] = ".le",
110 [BRW_CONDITIONAL_R] = ".r",
111 [BRW_CONDITIONAL_O] = ".o",
112 [BRW_CONDITIONAL_U] = ".u",
113 };
114
115 static const char *const m_negate[2] = {
116 [0] = "",
117 [1] = "-",
118 };
119
120 static const char *const _abs[2] = {
121 [0] = "",
122 [1] = "(abs)",
123 };
124
125 static const char *const m_bitnot[2] = { "", "~" };
126
127 static const char *const vert_stride[16] = {
128 [0] = "0",
129 [1] = "1",
130 [2] = "2",
131 [3] = "4",
132 [4] = "8",
133 [5] = "16",
134 [6] = "32",
135 [15] = "VxH",
136 };
137
138 static const char *const width[8] = {
139 [0] = "1",
140 [1] = "2",
141 [2] = "4",
142 [3] = "8",
143 [4] = "16",
144 };
145
146 static const char *const horiz_stride[4] = {
147 [0] = "0",
148 [1] = "1",
149 [2] = "2",
150 [3] = "4"
151 };
152
153 static const char *const chan_sel[4] = {
154 [0] = "x",
155 [1] = "y",
156 [2] = "z",
157 [3] = "w",
158 };
159
160 static const char *const debug_ctrl[2] = {
161 [0] = "",
162 [1] = ".breakpoint"
163 };
164
165 static const char *const saturate[2] = {
166 [0] = "",
167 [1] = ".sat"
168 };
169
170 static const char *const cmpt_ctrl[2] = {
171 [0] = "",
172 [1] = "compacted"
173 };
174
175 static const char *const accwr[2] = {
176 [0] = "",
177 [1] = "AccWrEnable"
178 };
179
180 static const char *const branch_ctrl[2] = {
181 [0] = "",
182 [1] = "BranchCtrl"
183 };
184
185 static const char *const wectrl[2] = {
186 [0] = "",
187 [1] = "WE_all"
188 };
189
190 static const char *const exec_size[8] = {
191 [0] = "1",
192 [1] = "2",
193 [2] = "4",
194 [3] = "8",
195 [4] = "16",
196 [5] = "32"
197 };
198
199 static const char *const pred_inv[2] = {
200 [0] = "+",
201 [1] = "-"
202 };
203
204 const char *const pred_ctrl_align16[16] = {
205 [1] = "",
206 [2] = ".x",
207 [3] = ".y",
208 [4] = ".z",
209 [5] = ".w",
210 [6] = ".any4h",
211 [7] = ".all4h",
212 };
213
214 static const char *const pred_ctrl_align1[16] = {
215 [BRW_PREDICATE_NORMAL] = "",
216 [BRW_PREDICATE_ALIGN1_ANYV] = ".anyv",
217 [BRW_PREDICATE_ALIGN1_ALLV] = ".allv",
218 [BRW_PREDICATE_ALIGN1_ANY2H] = ".any2h",
219 [BRW_PREDICATE_ALIGN1_ALL2H] = ".all2h",
220 [BRW_PREDICATE_ALIGN1_ANY4H] = ".any4h",
221 [BRW_PREDICATE_ALIGN1_ALL4H] = ".all4h",
222 [BRW_PREDICATE_ALIGN1_ANY8H] = ".any8h",
223 [BRW_PREDICATE_ALIGN1_ALL8H] = ".all8h",
224 [BRW_PREDICATE_ALIGN1_ANY16H] = ".any16h",
225 [BRW_PREDICATE_ALIGN1_ALL16H] = ".all16h",
226 [BRW_PREDICATE_ALIGN1_ANY32H] = ".any32h",
227 [BRW_PREDICATE_ALIGN1_ALL32H] = ".all32h",
228 };
229
230 static const char *const thread_ctrl[4] = {
231 [BRW_THREAD_NORMAL] = "",
232 [BRW_THREAD_ATOMIC] = "atomic",
233 [BRW_THREAD_SWITCH] = "switch",
234 };
235
236 static const char *const compr_ctrl[4] = {
237 [0] = "",
238 [1] = "sechalf",
239 [2] = "compr",
240 [3] = "compr4",
241 };
242
243 static const char *const dep_ctrl[4] = {
244 [0] = "",
245 [1] = "NoDDClr",
246 [2] = "NoDDChk",
247 [3] = "NoDDClr,NoDDChk",
248 };
249
250 static const char *const mask_ctrl[4] = {
251 [0] = "",
252 [1] = "nomask",
253 };
254
255 static const char *const access_mode[2] = {
256 [0] = "align1",
257 [1] = "align16",
258 };
259
260 static const char *const reg_file[4] = {
261 [0] = "A",
262 [1] = "g",
263 [2] = "m",
264 [3] = "imm",
265 };
266
267 static const char *const writemask[16] = {
268 [0x0] = ".",
269 [0x1] = ".x",
270 [0x2] = ".y",
271 [0x3] = ".xy",
272 [0x4] = ".z",
273 [0x5] = ".xz",
274 [0x6] = ".yz",
275 [0x7] = ".xyz",
276 [0x8] = ".w",
277 [0x9] = ".xw",
278 [0xa] = ".yw",
279 [0xb] = ".xyw",
280 [0xc] = ".zw",
281 [0xd] = ".xzw",
282 [0xe] = ".yzw",
283 [0xf] = "",
284 };
285
286 static const char *const end_of_thread[2] = {
287 [0] = "",
288 [1] = "EOT"
289 };
290
291 /* SFIDs on Gen4-5 */
292 static const char *const gen4_sfid[16] = {
293 [BRW_SFID_NULL] = "null",
294 [BRW_SFID_MATH] = "math",
295 [BRW_SFID_SAMPLER] = "sampler",
296 [BRW_SFID_MESSAGE_GATEWAY] = "gateway",
297 [BRW_SFID_DATAPORT_READ] = "read",
298 [BRW_SFID_DATAPORT_WRITE] = "write",
299 [BRW_SFID_URB] = "urb",
300 [BRW_SFID_THREAD_SPAWNER] = "thread_spawner",
301 [BRW_SFID_VME] = "vme",
302 };
303
304 static const char *const gen6_sfid[16] = {
305 [BRW_SFID_NULL] = "null",
306 [BRW_SFID_MATH] = "math",
307 [BRW_SFID_SAMPLER] = "sampler",
308 [BRW_SFID_MESSAGE_GATEWAY] = "gateway",
309 [BRW_SFID_URB] = "urb",
310 [BRW_SFID_THREAD_SPAWNER] = "thread_spawner",
311 [GEN6_SFID_DATAPORT_SAMPLER_CACHE] = "dp_sampler",
312 [GEN6_SFID_DATAPORT_RENDER_CACHE] = "render",
313 [GEN6_SFID_DATAPORT_CONSTANT_CACHE] = "const",
314 [GEN7_SFID_DATAPORT_DATA_CACHE] = "data",
315 [GEN7_SFID_PIXEL_INTERPOLATOR] = "pixel interp",
316 [HSW_SFID_DATAPORT_DATA_CACHE_1] = "dp data 1",
317 [HSW_SFID_CRE] = "cre",
318 };
319
320 static const char *const gen7_gateway_subfuncid[8] = {
321 [BRW_MESSAGE_GATEWAY_SFID_OPEN_GATEWAY] = "open",
322 [BRW_MESSAGE_GATEWAY_SFID_CLOSE_GATEWAY] = "close",
323 [BRW_MESSAGE_GATEWAY_SFID_FORWARD_MSG] = "forward msg",
324 [BRW_MESSAGE_GATEWAY_SFID_GET_TIMESTAMP] = "get timestamp",
325 [BRW_MESSAGE_GATEWAY_SFID_BARRIER_MSG] = "barrier msg",
326 [BRW_MESSAGE_GATEWAY_SFID_UPDATE_GATEWAY_STATE] = "update state",
327 [BRW_MESSAGE_GATEWAY_SFID_MMIO_READ_WRITE] = "mmio read/write",
328 };
329
330 static const char *const gen4_dp_read_port_msg_type[4] = {
331 [0b00] = "OWord Block Read",
332 [0b01] = "OWord Dual Block Read",
333 [0b10] = "Media Block Read",
334 [0b11] = "DWord Scattered Read",
335 };
336
337 static const char *const g45_dp_read_port_msg_type[8] = {
338 [0b000] = "OWord Block Read",
339 [0b010] = "OWord Dual Block Read",
340 [0b100] = "Media Block Read",
341 [0b110] = "DWord Scattered Read",
342 [0b001] = "Render Target UNORM Read",
343 [0b011] = "AVC Loop Filter Read",
344 };
345
346 static const char *const dp_write_port_msg_type[8] = {
347 [0b000] = "OWord block write",
348 [0b001] = "OWord dual block write",
349 [0b010] = "media block write",
350 [0b011] = "DWord scattered write",
351 [0b100] = "RT write",
352 [0b101] = "streamed VB write",
353 [0b110] = "RT UNORM write", /* G45+ */
354 [0b111] = "flush render cache",
355 };
356
357 static const char *const dp_rc_msg_type_gen6[16] = {
358 [BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ] = "OWORD block read",
359 [GEN6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ] = "RT UNORM read",
360 [GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ] = "OWORD dual block read",
361 [GEN6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ] = "media block read",
362 [GEN6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ] =
363 "OWORD unaligned block read",
364 [GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ] = "DWORD scattered read",
365 [GEN6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE] = "DWORD atomic write",
366 [GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE] = "OWORD block write",
367 [GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE] =
368 "OWORD dual block write",
369 [GEN6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE] = "media block write",
370 [GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE] =
371 "DWORD scattered write",
372 [GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE] = "RT write",
373 [GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE] = "streamed VB write",
374 [GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE] = "RT UNORM write",
375 };
376
377 static const char *const dp_rc_msg_type_gen7[16] = {
378 [GEN7_DATAPORT_RC_MEDIA_BLOCK_READ] = "media block read",
379 [GEN7_DATAPORT_RC_TYPED_SURFACE_READ] = "typed surface read",
380 [GEN7_DATAPORT_RC_TYPED_ATOMIC_OP] = "typed atomic op",
381 [GEN7_DATAPORT_RC_MEMORY_FENCE] = "memory fence",
382 [GEN7_DATAPORT_RC_MEDIA_BLOCK_WRITE] = "media block write",
383 [GEN7_DATAPORT_RC_RENDER_TARGET_WRITE] = "RT write",
384 [GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE] = "typed surface write"
385 };
386
387 static const char *const dp_rc_msg_type_gen9[16] = {
388 [GEN9_DATAPORT_RC_RENDER_TARGET_WRITE] = "RT write",
389 [GEN9_DATAPORT_RC_RENDER_TARGET_READ] = "RT read"
390 };
391
392 static const char *const *
393 dp_rc_msg_type(const struct gen_device_info *devinfo)
394 {
395 return (devinfo->gen >= 9 ? dp_rc_msg_type_gen9 :
396 devinfo->gen >= 7 ? dp_rc_msg_type_gen7 :
397 devinfo->gen >= 6 ? dp_rc_msg_type_gen6 :
398 dp_write_port_msg_type);
399 }
400
401 static const char *const m_rt_write_subtype[] = {
402 [0b000] = "SIMD16",
403 [0b001] = "SIMD16/RepData",
404 [0b010] = "SIMD8/DualSrcLow",
405 [0b011] = "SIMD8/DualSrcHigh",
406 [0b100] = "SIMD8",
407 [0b101] = "SIMD8/ImageWrite", /* Gen6+ */
408 [0b111] = "SIMD16/RepData-111", /* no idea how this is different than 1 */
409 };
410
411 static const char *const dp_dc0_msg_type_gen7[16] = {
412 [GEN7_DATAPORT_DC_OWORD_BLOCK_READ] = "DC OWORD block read",
413 [GEN7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ] =
414 "DC unaligned OWORD block read",
415 [GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_READ] = "DC OWORD dual block read",
416 [GEN7_DATAPORT_DC_DWORD_SCATTERED_READ] = "DC DWORD scattered read",
417 [GEN7_DATAPORT_DC_BYTE_SCATTERED_READ] = "DC byte scattered read",
418 [GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ] = "DC untyped surface read",
419 [GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP] = "DC untyped atomic",
420 [GEN7_DATAPORT_DC_MEMORY_FENCE] = "DC mfence",
421 [GEN7_DATAPORT_DC_OWORD_BLOCK_WRITE] = "DC OWORD block write",
422 [GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE] = "DC OWORD dual block write",
423 [GEN7_DATAPORT_DC_DWORD_SCATTERED_WRITE] = "DC DWORD scatterd write",
424 [GEN7_DATAPORT_DC_BYTE_SCATTERED_WRITE] = "DC byte scattered write",
425 [GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE] = "DC untyped surface write",
426 };
427
428 static const char *const dp_dc1_msg_type_hsw[32] = {
429 [HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ] = "untyped surface read",
430 [HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP] = "DC untyped atomic op",
431 [HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2] =
432 "DC untyped 4x2 atomic op",
433 [HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_READ] = "DC media block read",
434 [HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ] = "DC typed surface read",
435 [HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP] = "DC typed atomic",
436 [HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2] = "DC typed 4x2 atomic op",
437 [HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE] = "DC untyped surface write",
438 [HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_WRITE] = "DC media block write",
439 [HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP] = "DC atomic counter op",
440 [HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2] =
441 "DC 4x2 atomic counter op",
442 [HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE] = "DC typed surface write",
443 [GEN9_DATAPORT_DC_PORT1_A64_SCATTERED_READ] = "DC A64 scattered read",
444 [GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ] = "DC A64 untyped surface read",
445 [GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP] = "DC A64 untyped atomic op",
446 [GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE] = "DC A64 untyped surface write",
447 [GEN8_DATAPORT_DC_PORT1_A64_SCATTERED_WRITE] = "DC A64 scattered write",
448 [GEN9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP] =
449 "DC untyped atomic float op",
450 [GEN9_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_FLOAT_OP] =
451 "DC A64 untyped atomic float op",
452 };
453
454 static const char *const aop[16] = {
455 [BRW_AOP_AND] = "and",
456 [BRW_AOP_OR] = "or",
457 [BRW_AOP_XOR] = "xor",
458 [BRW_AOP_MOV] = "mov",
459 [BRW_AOP_INC] = "inc",
460 [BRW_AOP_DEC] = "dec",
461 [BRW_AOP_ADD] = "add",
462 [BRW_AOP_SUB] = "sub",
463 [BRW_AOP_REVSUB] = "revsub",
464 [BRW_AOP_IMAX] = "imax",
465 [BRW_AOP_IMIN] = "imin",
466 [BRW_AOP_UMAX] = "umax",
467 [BRW_AOP_UMIN] = "umin",
468 [BRW_AOP_CMPWR] = "cmpwr",
469 [BRW_AOP_PREDEC] = "predec",
470 };
471
472 static const char *const aop_float[4] = {
473 [BRW_AOP_FMAX] = "fmax",
474 [BRW_AOP_FMIN] = "fmin",
475 [BRW_AOP_FCMPWR] = "fcmpwr",
476 };
477
478 static const char * const pixel_interpolator_msg_types[4] = {
479 [GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET] = "per_message_offset",
480 [GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE] = "sample_position",
481 [GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID] = "centroid",
482 [GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET] = "per_slot_offset",
483 };
484
485 static const char *const math_function[16] = {
486 [BRW_MATH_FUNCTION_INV] = "inv",
487 [BRW_MATH_FUNCTION_LOG] = "log",
488 [BRW_MATH_FUNCTION_EXP] = "exp",
489 [BRW_MATH_FUNCTION_SQRT] = "sqrt",
490 [BRW_MATH_FUNCTION_RSQ] = "rsq",
491 [BRW_MATH_FUNCTION_SIN] = "sin",
492 [BRW_MATH_FUNCTION_COS] = "cos",
493 [BRW_MATH_FUNCTION_SINCOS] = "sincos",
494 [BRW_MATH_FUNCTION_FDIV] = "fdiv",
495 [BRW_MATH_FUNCTION_POW] = "pow",
496 [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER] = "intdivmod",
497 [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT] = "intdiv",
498 [BRW_MATH_FUNCTION_INT_DIV_REMAINDER] = "intmod",
499 [GEN8_MATH_FUNCTION_INVM] = "invm",
500 [GEN8_MATH_FUNCTION_RSQRTM] = "rsqrtm",
501 };
502
503 static const char *const sync_function[16] = {
504 [TGL_SYNC_NOP] = "nop",
505 [TGL_SYNC_ALLRD] = "allrd",
506 [TGL_SYNC_ALLWR] = "allwr",
507 [TGL_SYNC_BAR] = "bar",
508 [TGL_SYNC_HOST] = "host",
509 };
510
511 static const char *const math_saturate[2] = {
512 [0] = "",
513 [1] = "sat"
514 };
515
516 static const char *const math_signed[2] = {
517 [0] = "",
518 [1] = "signed"
519 };
520
521 static const char *const math_scalar[2] = {
522 [0] = "",
523 [1] = "scalar"
524 };
525
526 static const char *const math_precision[2] = {
527 [0] = "",
528 [1] = "partial_precision"
529 };
530
531 static const char *const gen5_urb_opcode[] = {
532 [0] = "urb_write",
533 [1] = "ff_sync",
534 };
535
536 static const char *const gen7_urb_opcode[] = {
537 [BRW_URB_OPCODE_WRITE_HWORD] = "write HWord",
538 [BRW_URB_OPCODE_WRITE_OWORD] = "write OWord",
539 [BRW_URB_OPCODE_READ_HWORD] = "read HWord",
540 [BRW_URB_OPCODE_READ_OWORD] = "read OWord",
541 [GEN7_URB_OPCODE_ATOMIC_MOV] = "atomic mov", /* Gen7+ */
542 [GEN7_URB_OPCODE_ATOMIC_INC] = "atomic inc", /* Gen7+ */
543 [GEN8_URB_OPCODE_ATOMIC_ADD] = "atomic add", /* Gen8+ */
544 [GEN8_URB_OPCODE_SIMD8_WRITE] = "SIMD8 write", /* Gen8+ */
545 [GEN8_URB_OPCODE_SIMD8_READ] = "SIMD8 read", /* Gen8+ */
546 /* [9-15] - reserved */
547 };
548
549 static const char *const urb_swizzle[4] = {
550 [BRW_URB_SWIZZLE_NONE] = "",
551 [BRW_URB_SWIZZLE_INTERLEAVE] = "interleave",
552 [BRW_URB_SWIZZLE_TRANSPOSE] = "transpose",
553 };
554
555 static const char *const urb_allocate[2] = {
556 [0] = "",
557 [1] = "allocate"
558 };
559
560 static const char *const urb_used[2] = {
561 [0] = "",
562 [1] = "used"
563 };
564
565 static const char *const urb_complete[2] = {
566 [0] = "",
567 [1] = "complete"
568 };
569
570 static const char *const gen5_sampler_msg_type[] = {
571 [GEN5_SAMPLER_MESSAGE_SAMPLE] = "sample",
572 [GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS] = "sample_b",
573 [GEN5_SAMPLER_MESSAGE_SAMPLE_LOD] = "sample_l",
574 [GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE] = "sample_c",
575 [GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS] = "sample_d",
576 [GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE] = "sample_b_c",
577 [GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE] = "sample_l_c",
578 [GEN5_SAMPLER_MESSAGE_SAMPLE_LD] = "ld",
579 [GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4] = "gather4",
580 [GEN5_SAMPLER_MESSAGE_LOD] = "lod",
581 [GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO] = "resinfo",
582 [GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO] = "sampleinfo",
583 [GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C] = "gather4_c",
584 [GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO] = "gather4_po",
585 [GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C] = "gather4_po_c",
586 [HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE] = "sample_d_c",
587 [GEN9_SAMPLER_MESSAGE_SAMPLE_LZ] = "sample_lz",
588 [GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ] = "sample_c_lz",
589 [GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ] = "ld_lz",
590 [GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W] = "ld2dms_w",
591 [GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS] = "ld_mcs",
592 [GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS] = "ld2dms",
593 [GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS] = "ld2dss",
594 };
595
596 static const char *const gen5_sampler_simd_mode[4] = {
597 [BRW_SAMPLER_SIMD_MODE_SIMD4X2] = "SIMD4x2",
598 [BRW_SAMPLER_SIMD_MODE_SIMD8] = "SIMD8",
599 [BRW_SAMPLER_SIMD_MODE_SIMD16] = "SIMD16",
600 [BRW_SAMPLER_SIMD_MODE_SIMD32_64] = "SIMD32/64",
601 };
602
603 static const char *const sampler_target_format[4] = {
604 [0] = "F",
605 [2] = "UD",
606 [3] = "D"
607 };
608
609
610 static int column;
611
612 static int
613 string(FILE *file, const char *string)
614 {
615 fputs(string, file);
616 column += strlen(string);
617 return 0;
618 }
619
620 static int
621 format(FILE *f, const char *format, ...) PRINTFLIKE(2, 3);
622
623 static int
624 format(FILE *f, const char *format, ...)
625 {
626 char buf[1024];
627 va_list args;
628 va_start(args, format);
629
630 vsnprintf(buf, sizeof(buf) - 1, format, args);
631 va_end(args);
632 string(f, buf);
633 return 0;
634 }
635
636 static int
637 newline(FILE *f)
638 {
639 putc('\n', f);
640 column = 0;
641 return 0;
642 }
643
644 static int
645 pad(FILE *f, int c)
646 {
647 do
648 string(f, " ");
649 while (column < c);
650 return 0;
651 }
652
653 static int
654 control(FILE *file, const char *name, const char *const ctrl[],
655 unsigned id, int *space)
656 {
657 if (!ctrl[id]) {
658 fprintf(file, "*** invalid %s value %d ", name, id);
659 return 1;
660 }
661 if (ctrl[id][0]) {
662 if (space && *space)
663 string(file, " ");
664 string(file, ctrl[id]);
665 if (space)
666 *space = 1;
667 }
668 return 0;
669 }
670
671 static int
672 print_opcode(FILE *file, const struct gen_device_info *devinfo,
673 enum opcode id)
674 {
675 const struct opcode_desc *desc = brw_opcode_desc(devinfo, id);
676 if (!desc) {
677 format(file, "*** invalid opcode value %d ", id);
678 return 1;
679 }
680 string(file, desc->name);
681 return 0;
682 }
683
684 static int
685 reg(FILE *file, unsigned _reg_file, unsigned _reg_nr)
686 {
687 int err = 0;
688
689 /* Clear the Compr4 instruction compression bit. */
690 if (_reg_file == BRW_MESSAGE_REGISTER_FILE)
691 _reg_nr &= ~BRW_MRF_COMPR4;
692
693 if (_reg_file == BRW_ARCHITECTURE_REGISTER_FILE) {
694 switch (_reg_nr & 0xf0) {
695 case BRW_ARF_NULL:
696 string(file, "null");
697 break;
698 case BRW_ARF_ADDRESS:
699 format(file, "a%d", _reg_nr & 0x0f);
700 break;
701 case BRW_ARF_ACCUMULATOR:
702 format(file, "acc%d", _reg_nr & 0x0f);
703 break;
704 case BRW_ARF_FLAG:
705 format(file, "f%d", _reg_nr & 0x0f);
706 break;
707 case BRW_ARF_MASK:
708 format(file, "mask%d", _reg_nr & 0x0f);
709 break;
710 case BRW_ARF_MASK_STACK:
711 format(file, "msd%d", _reg_nr & 0x0f);
712 break;
713 case BRW_ARF_STATE:
714 format(file, "sr%d", _reg_nr & 0x0f);
715 break;
716 case BRW_ARF_CONTROL:
717 format(file, "cr%d", _reg_nr & 0x0f);
718 break;
719 case BRW_ARF_NOTIFICATION_COUNT:
720 format(file, "n%d", _reg_nr & 0x0f);
721 break;
722 case BRW_ARF_IP:
723 string(file, "ip");
724 return -1;
725 break;
726 case BRW_ARF_TDR:
727 format(file, "tdr0");
728 return -1;
729 case BRW_ARF_TIMESTAMP:
730 format(file, "tm%d", _reg_nr & 0x0f);
731 break;
732 default:
733 format(file, "ARF%d", _reg_nr);
734 break;
735 }
736 } else {
737 err |= control(file, "src reg file", reg_file, _reg_file, NULL);
738 format(file, "%d", _reg_nr);
739 }
740 return err;
741 }
742
743 static int
744 dest(FILE *file, const struct gen_device_info *devinfo, const brw_inst *inst)
745 {
746 enum brw_reg_type type = brw_inst_dst_type(devinfo, inst);
747 unsigned elem_size = brw_reg_type_to_size(type);
748 int err = 0;
749
750 if (is_split_send(devinfo, brw_inst_opcode(devinfo, inst))) {
751 /* These are fixed for split sends */
752 type = BRW_REGISTER_TYPE_UD;
753 elem_size = 4;
754 if (devinfo->gen >= 12) {
755 err |= reg(file, brw_inst_send_dst_reg_file(devinfo, inst),
756 brw_inst_dst_da_reg_nr(devinfo, inst));
757 string(file, brw_reg_type_to_letters(type));
758 } else if (brw_inst_dst_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
759 err |= reg(file, brw_inst_send_dst_reg_file(devinfo, inst),
760 brw_inst_dst_da_reg_nr(devinfo, inst));
761 unsigned subreg_nr = brw_inst_dst_da16_subreg_nr(devinfo, inst);
762 if (subreg_nr)
763 format(file, ".%u", subreg_nr);
764 string(file, brw_reg_type_to_letters(type));
765 } else {
766 string(file, "g[a0");
767 if (brw_inst_dst_ia_subreg_nr(devinfo, inst))
768 format(file, ".%"PRIu64, brw_inst_dst_ia_subreg_nr(devinfo, inst) /
769 elem_size);
770 if (brw_inst_send_dst_ia16_addr_imm(devinfo, inst))
771 format(file, " %d", brw_inst_send_dst_ia16_addr_imm(devinfo, inst));
772 string(file, "]<");
773 string(file, brw_reg_type_to_letters(type));
774 }
775 } else if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
776 if (brw_inst_dst_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
777 err |= reg(file, brw_inst_dst_reg_file(devinfo, inst),
778 brw_inst_dst_da_reg_nr(devinfo, inst));
779 if (err == -1)
780 return 0;
781 if (brw_inst_dst_da1_subreg_nr(devinfo, inst))
782 format(file, ".%"PRIu64, brw_inst_dst_da1_subreg_nr(devinfo, inst) /
783 elem_size);
784 string(file, "<");
785 err |= control(file, "horiz stride", horiz_stride,
786 brw_inst_dst_hstride(devinfo, inst), NULL);
787 string(file, ">");
788 string(file, brw_reg_type_to_letters(type));
789 } else {
790 string(file, "g[a0");
791 if (brw_inst_dst_ia_subreg_nr(devinfo, inst))
792 format(file, ".%"PRIu64, brw_inst_dst_ia_subreg_nr(devinfo, inst) /
793 elem_size);
794 if (brw_inst_dst_ia1_addr_imm(devinfo, inst))
795 format(file, " %d", brw_inst_dst_ia1_addr_imm(devinfo, inst));
796 string(file, "]<");
797 err |= control(file, "horiz stride", horiz_stride,
798 brw_inst_dst_hstride(devinfo, inst), NULL);
799 string(file, ">");
800 string(file, brw_reg_type_to_letters(type));
801 }
802 } else {
803 if (brw_inst_dst_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
804 err |= reg(file, brw_inst_dst_reg_file(devinfo, inst),
805 brw_inst_dst_da_reg_nr(devinfo, inst));
806 if (err == -1)
807 return 0;
808 if (brw_inst_dst_da16_subreg_nr(devinfo, inst))
809 format(file, ".%u", 16 / elem_size);
810 string(file, "<1>");
811 err |= control(file, "writemask", writemask,
812 brw_inst_da16_writemask(devinfo, inst), NULL);
813 string(file, brw_reg_type_to_letters(type));
814 } else {
815 err = 1;
816 string(file, "Indirect align16 address mode not supported");
817 }
818 }
819
820 return 0;
821 }
822
823 static int
824 dest_3src(FILE *file, const struct gen_device_info *devinfo, const brw_inst *inst)
825 {
826 bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1;
827 int err = 0;
828 uint32_t reg_file;
829 unsigned subreg_nr;
830 enum brw_reg_type type;
831
832 if (devinfo->gen < 10 && is_align1)
833 return 0;
834
835 if (devinfo->gen == 6 && brw_inst_3src_a16_dst_reg_file(devinfo, inst))
836 reg_file = BRW_MESSAGE_REGISTER_FILE;
837 else if (devinfo->gen >= 12)
838 reg_file = brw_inst_3src_a1_dst_reg_file(devinfo, inst);
839 else if (is_align1 && brw_inst_3src_a1_dst_reg_file(devinfo, inst))
840 reg_file = BRW_ARCHITECTURE_REGISTER_FILE;
841 else
842 reg_file = BRW_GENERAL_REGISTER_FILE;
843
844 err |= reg(file, reg_file, brw_inst_3src_dst_reg_nr(devinfo, inst));
845 if (err == -1)
846 return 0;
847
848 if (is_align1) {
849 type = brw_inst_3src_a1_dst_type(devinfo, inst);
850 subreg_nr = brw_inst_3src_a1_dst_subreg_nr(devinfo, inst);
851 } else {
852 type = brw_inst_3src_a16_dst_type(devinfo, inst);
853 subreg_nr = brw_inst_3src_a16_dst_subreg_nr(devinfo, inst) * 4;
854 }
855 subreg_nr /= brw_reg_type_to_size(type);
856
857 if (subreg_nr)
858 format(file, ".%u", subreg_nr);
859 string(file, "<1>");
860
861 if (!is_align1) {
862 err |= control(file, "writemask", writemask,
863 brw_inst_3src_a16_dst_writemask(devinfo, inst), NULL);
864 }
865 string(file, brw_reg_type_to_letters(type));
866
867 return 0;
868 }
869
870 static int
871 src_align1_region(FILE *file,
872 unsigned _vert_stride, unsigned _width,
873 unsigned _horiz_stride)
874 {
875 int err = 0;
876 string(file, "<");
877 err |= control(file, "vert stride", vert_stride, _vert_stride, NULL);
878 string(file, ",");
879 err |= control(file, "width", width, _width, NULL);
880 string(file, ",");
881 err |= control(file, "horiz_stride", horiz_stride, _horiz_stride, NULL);
882 string(file, ">");
883 return err;
884 }
885
886 static int
887 src_da1(FILE *file,
888 const struct gen_device_info *devinfo,
889 unsigned opcode,
890 enum brw_reg_type type, unsigned _reg_file,
891 unsigned _vert_stride, unsigned _width, unsigned _horiz_stride,
892 unsigned reg_num, unsigned sub_reg_num, unsigned __abs,
893 unsigned _negate)
894 {
895 int err = 0;
896
897 if (devinfo->gen >= 8 && is_logic_instruction(opcode))
898 err |= control(file, "bitnot", m_bitnot, _negate, NULL);
899 else
900 err |= control(file, "negate", m_negate, _negate, NULL);
901
902 err |= control(file, "abs", _abs, __abs, NULL);
903
904 err |= reg(file, _reg_file, reg_num);
905 if (err == -1)
906 return 0;
907 if (sub_reg_num) {
908 unsigned elem_size = brw_reg_type_to_size(type);
909 format(file, ".%d", sub_reg_num / elem_size); /* use formal style like spec */
910 }
911 src_align1_region(file, _vert_stride, _width, _horiz_stride);
912 string(file, brw_reg_type_to_letters(type));
913 return err;
914 }
915
916 static int
917 src_ia1(FILE *file,
918 const struct gen_device_info *devinfo,
919 unsigned opcode,
920 enum brw_reg_type type,
921 int _addr_imm,
922 unsigned _addr_subreg_nr,
923 unsigned _negate,
924 unsigned __abs,
925 unsigned _horiz_stride, unsigned _width, unsigned _vert_stride)
926 {
927 int err = 0;
928
929 if (devinfo->gen >= 8 && is_logic_instruction(opcode))
930 err |= control(file, "bitnot", m_bitnot, _negate, NULL);
931 else
932 err |= control(file, "negate", m_negate, _negate, NULL);
933
934 err |= control(file, "abs", _abs, __abs, NULL);
935
936 string(file, "g[a0");
937 if (_addr_subreg_nr)
938 format(file, ".%d", _addr_subreg_nr);
939 if (_addr_imm)
940 format(file, " %d", _addr_imm);
941 string(file, "]");
942 src_align1_region(file, _vert_stride, _width, _horiz_stride);
943 string(file, brw_reg_type_to_letters(type));
944 return err;
945 }
946
947 static int
948 src_swizzle(FILE *file, unsigned swiz)
949 {
950 unsigned x = BRW_GET_SWZ(swiz, BRW_CHANNEL_X);
951 unsigned y = BRW_GET_SWZ(swiz, BRW_CHANNEL_Y);
952 unsigned z = BRW_GET_SWZ(swiz, BRW_CHANNEL_Z);
953 unsigned w = BRW_GET_SWZ(swiz, BRW_CHANNEL_W);
954 int err = 0;
955
956 if (x == y && x == z && x == w) {
957 string(file, ".");
958 err |= control(file, "channel select", chan_sel, x, NULL);
959 } else if (swiz != BRW_SWIZZLE_XYZW) {
960 string(file, ".");
961 err |= control(file, "channel select", chan_sel, x, NULL);
962 err |= control(file, "channel select", chan_sel, y, NULL);
963 err |= control(file, "channel select", chan_sel, z, NULL);
964 err |= control(file, "channel select", chan_sel, w, NULL);
965 }
966 return err;
967 }
968
969 static int
970 src_da16(FILE *file,
971 const struct gen_device_info *devinfo,
972 unsigned opcode,
973 enum brw_reg_type type,
974 unsigned _reg_file,
975 unsigned _vert_stride,
976 unsigned _reg_nr,
977 unsigned _subreg_nr,
978 unsigned __abs,
979 unsigned _negate,
980 unsigned swz_x, unsigned swz_y, unsigned swz_z, unsigned swz_w)
981 {
982 int err = 0;
983
984 if (devinfo->gen >= 8 && is_logic_instruction(opcode))
985 err |= control(file, "bitnot", m_bitnot, _negate, NULL);
986 else
987 err |= control(file, "negate", m_negate, _negate, NULL);
988
989 err |= control(file, "abs", _abs, __abs, NULL);
990
991 err |= reg(file, _reg_file, _reg_nr);
992 if (err == -1)
993 return 0;
994 if (_subreg_nr) {
995 unsigned elem_size = brw_reg_type_to_size(type);
996
997 /* bit4 for subreg number byte addressing. Make this same meaning as
998 in da1 case, so output looks consistent. */
999 format(file, ".%d", 16 / elem_size);
1000 }
1001 string(file, "<");
1002 err |= control(file, "vert stride", vert_stride, _vert_stride, NULL);
1003 string(file, ">");
1004 err |= src_swizzle(file, BRW_SWIZZLE4(swz_x, swz_y, swz_z, swz_w));
1005 string(file, brw_reg_type_to_letters(type));
1006 return err;
1007 }
1008
1009 static enum brw_vertical_stride
1010 vstride_from_align1_3src_vstride(const struct gen_device_info *devinfo,
1011 enum gen10_align1_3src_vertical_stride vstride)
1012 {
1013 switch (vstride) {
1014 case BRW_ALIGN1_3SRC_VERTICAL_STRIDE_0: return BRW_VERTICAL_STRIDE_0;
1015 case BRW_ALIGN1_3SRC_VERTICAL_STRIDE_2:
1016 if (devinfo->gen >= 12)
1017 return BRW_VERTICAL_STRIDE_1;
1018 else
1019 return BRW_VERTICAL_STRIDE_2;
1020 case BRW_ALIGN1_3SRC_VERTICAL_STRIDE_4: return BRW_VERTICAL_STRIDE_4;
1021 case BRW_ALIGN1_3SRC_VERTICAL_STRIDE_8: return BRW_VERTICAL_STRIDE_8;
1022 default:
1023 unreachable("not reached");
1024 }
1025 }
1026
1027 static enum brw_horizontal_stride
1028 hstride_from_align1_3src_hstride(enum gen10_align1_3src_src_horizontal_stride hstride)
1029 {
1030 switch (hstride) {
1031 case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0: return BRW_HORIZONTAL_STRIDE_0;
1032 case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_1: return BRW_HORIZONTAL_STRIDE_1;
1033 case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_2: return BRW_HORIZONTAL_STRIDE_2;
1034 case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_4: return BRW_HORIZONTAL_STRIDE_4;
1035 default:
1036 unreachable("not reached");
1037 }
1038 }
1039
1040 static enum brw_vertical_stride
1041 vstride_from_align1_3src_hstride(enum gen10_align1_3src_src_horizontal_stride hstride)
1042 {
1043 switch (hstride) {
1044 case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0: return BRW_VERTICAL_STRIDE_0;
1045 case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_1: return BRW_VERTICAL_STRIDE_1;
1046 case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_2: return BRW_VERTICAL_STRIDE_2;
1047 case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_4: return BRW_VERTICAL_STRIDE_4;
1048 default:
1049 unreachable("not reached");
1050 }
1051 }
1052
1053 /* From "GEN10 Regioning Rules for Align1 Ternary Operations" in the
1054 * "Register Region Restrictions" documentation
1055 */
1056 static enum brw_width
1057 implied_width(enum brw_vertical_stride _vert_stride,
1058 enum brw_horizontal_stride _horiz_stride)
1059 {
1060 /* "1. Width is 1 when Vertical and Horizontal Strides are both zero." */
1061 if (_vert_stride == BRW_VERTICAL_STRIDE_0 &&
1062 _horiz_stride == BRW_HORIZONTAL_STRIDE_0) {
1063 return BRW_WIDTH_1;
1064
1065 /* "2. Width is equal to vertical stride when Horizontal Stride is zero." */
1066 } else if (_horiz_stride == BRW_HORIZONTAL_STRIDE_0) {
1067 switch (_vert_stride) {
1068 case BRW_VERTICAL_STRIDE_2: return BRW_WIDTH_2;
1069 case BRW_VERTICAL_STRIDE_4: return BRW_WIDTH_4;
1070 case BRW_VERTICAL_STRIDE_8: return BRW_WIDTH_8;
1071 case BRW_VERTICAL_STRIDE_0:
1072 default:
1073 unreachable("not reached");
1074 }
1075
1076 } else {
1077 /* FINISHME: Implement these: */
1078
1079 /* "3. Width is equal to Vertical Stride/Horizontal Stride when both
1080 * Strides are non-zero.
1081 *
1082 * 4. Vertical Stride must not be zero if Horizontal Stride is non-zero.
1083 * This implies Vertical Stride is always greater than Horizontal
1084 * Stride."
1085 *
1086 * Given these statements and the knowledge that the stride and width
1087 * values are encoded in logarithmic form, we can perform the division
1088 * by just subtracting.
1089 */
1090 return _vert_stride - _horiz_stride;
1091 }
1092 }
1093
1094 static int
1095 src0_3src(FILE *file, const struct gen_device_info *devinfo, const brw_inst *inst)
1096 {
1097 int err = 0;
1098 unsigned reg_nr, subreg_nr;
1099 enum brw_reg_file _file;
1100 enum brw_reg_type type;
1101 enum brw_vertical_stride _vert_stride;
1102 enum brw_width _width;
1103 enum brw_horizontal_stride _horiz_stride;
1104 bool is_scalar_region;
1105 bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1;
1106
1107 if (devinfo->gen < 10 && is_align1)
1108 return 0;
1109
1110 if (is_align1) {
1111 if (devinfo->gen >= 12 && !brw_inst_3src_a1_src0_is_imm(devinfo, inst)) {
1112 _file = brw_inst_3src_a1_src0_reg_file(devinfo, inst);
1113 } else if (brw_inst_3src_a1_src0_reg_file(devinfo, inst) ==
1114 BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE) {
1115 _file = BRW_GENERAL_REGISTER_FILE;
1116 } else if (brw_inst_3src_a1_src0_type(devinfo, inst) ==
1117 BRW_REGISTER_TYPE_NF) {
1118 _file = BRW_ARCHITECTURE_REGISTER_FILE;
1119 } else {
1120 _file = BRW_IMMEDIATE_VALUE;
1121 uint16_t imm_val = brw_inst_3src_a1_src0_imm(devinfo, inst);
1122 enum brw_reg_type type = brw_inst_3src_a1_src0_type(devinfo, inst);
1123
1124 if (type == BRW_REGISTER_TYPE_W) {
1125 format(file, "%dW", imm_val);
1126 } else if (type == BRW_REGISTER_TYPE_UW) {
1127 format(file, "0x%04xUW", imm_val);
1128 } else if (type == BRW_REGISTER_TYPE_HF) {
1129 format(file, "0x%04xHF", imm_val);
1130 }
1131 return 0;
1132 }
1133
1134 reg_nr = brw_inst_3src_src0_reg_nr(devinfo, inst);
1135 subreg_nr = brw_inst_3src_a1_src0_subreg_nr(devinfo, inst);
1136 type = brw_inst_3src_a1_src0_type(devinfo, inst);
1137 _vert_stride = vstride_from_align1_3src_vstride(
1138 devinfo, brw_inst_3src_a1_src0_vstride(devinfo, inst));
1139 _horiz_stride = hstride_from_align1_3src_hstride(
1140 brw_inst_3src_a1_src0_hstride(devinfo, inst));
1141 _width = implied_width(_vert_stride, _horiz_stride);
1142 } else {
1143 _file = BRW_GENERAL_REGISTER_FILE;
1144 reg_nr = brw_inst_3src_src0_reg_nr(devinfo, inst);
1145 subreg_nr = brw_inst_3src_a16_src0_subreg_nr(devinfo, inst) * 4;
1146 type = brw_inst_3src_a16_src_type(devinfo, inst);
1147
1148 if (brw_inst_3src_a16_src0_rep_ctrl(devinfo, inst)) {
1149 _vert_stride = BRW_VERTICAL_STRIDE_0;
1150 _width = BRW_WIDTH_1;
1151 _horiz_stride = BRW_HORIZONTAL_STRIDE_0;
1152 } else {
1153 _vert_stride = BRW_VERTICAL_STRIDE_4;
1154 _width = BRW_WIDTH_4;
1155 _horiz_stride = BRW_HORIZONTAL_STRIDE_1;
1156 }
1157 }
1158 is_scalar_region = _vert_stride == BRW_VERTICAL_STRIDE_0 &&
1159 _width == BRW_WIDTH_1 &&
1160 _horiz_stride == BRW_HORIZONTAL_STRIDE_0;
1161
1162 subreg_nr /= brw_reg_type_to_size(type);
1163
1164 err |= control(file, "negate", m_negate,
1165 brw_inst_3src_src0_negate(devinfo, inst), NULL);
1166 err |= control(file, "abs", _abs, brw_inst_3src_src0_abs(devinfo, inst), NULL);
1167
1168 err |= reg(file, _file, reg_nr);
1169 if (err == -1)
1170 return 0;
1171 if (subreg_nr || is_scalar_region)
1172 format(file, ".%d", subreg_nr);
1173 src_align1_region(file, _vert_stride, _width, _horiz_stride);
1174 if (!is_scalar_region && !is_align1)
1175 err |= src_swizzle(file, brw_inst_3src_a16_src0_swizzle(devinfo, inst));
1176 string(file, brw_reg_type_to_letters(type));
1177 return err;
1178 }
1179
1180 static int
1181 src1_3src(FILE *file, const struct gen_device_info *devinfo, const brw_inst *inst)
1182 {
1183 int err = 0;
1184 unsigned reg_nr, subreg_nr;
1185 enum brw_reg_file _file;
1186 enum brw_reg_type type;
1187 enum brw_vertical_stride _vert_stride;
1188 enum brw_width _width;
1189 enum brw_horizontal_stride _horiz_stride;
1190 bool is_scalar_region;
1191 bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1;
1192
1193 if (devinfo->gen < 10 && is_align1)
1194 return 0;
1195
1196 if (is_align1) {
1197 if (devinfo->gen >= 12) {
1198 _file = brw_inst_3src_a1_src1_reg_file(devinfo, inst);
1199 } else if (brw_inst_3src_a1_src1_reg_file(devinfo, inst) ==
1200 BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE) {
1201 _file = BRW_GENERAL_REGISTER_FILE;
1202 } else {
1203 _file = BRW_ARCHITECTURE_REGISTER_FILE;
1204 }
1205
1206 reg_nr = brw_inst_3src_src1_reg_nr(devinfo, inst);
1207 subreg_nr = brw_inst_3src_a1_src1_subreg_nr(devinfo, inst);
1208 type = brw_inst_3src_a1_src1_type(devinfo, inst);
1209
1210 _vert_stride = vstride_from_align1_3src_vstride(
1211 devinfo, brw_inst_3src_a1_src1_vstride(devinfo, inst));
1212 _horiz_stride = hstride_from_align1_3src_hstride(
1213 brw_inst_3src_a1_src1_hstride(devinfo, inst));
1214 _width = implied_width(_vert_stride, _horiz_stride);
1215 } else {
1216 _file = BRW_GENERAL_REGISTER_FILE;
1217 reg_nr = brw_inst_3src_src1_reg_nr(devinfo, inst);
1218 subreg_nr = brw_inst_3src_a16_src1_subreg_nr(devinfo, inst) * 4;
1219 type = brw_inst_3src_a16_src_type(devinfo, inst);
1220
1221 if (brw_inst_3src_a16_src1_rep_ctrl(devinfo, inst)) {
1222 _vert_stride = BRW_VERTICAL_STRIDE_0;
1223 _width = BRW_WIDTH_1;
1224 _horiz_stride = BRW_HORIZONTAL_STRIDE_0;
1225 } else {
1226 _vert_stride = BRW_VERTICAL_STRIDE_4;
1227 _width = BRW_WIDTH_4;
1228 _horiz_stride = BRW_HORIZONTAL_STRIDE_1;
1229 }
1230 }
1231 is_scalar_region = _vert_stride == BRW_VERTICAL_STRIDE_0 &&
1232 _width == BRW_WIDTH_1 &&
1233 _horiz_stride == BRW_HORIZONTAL_STRIDE_0;
1234
1235 subreg_nr /= brw_reg_type_to_size(type);
1236
1237 err |= control(file, "negate", m_negate,
1238 brw_inst_3src_src1_negate(devinfo, inst), NULL);
1239 err |= control(file, "abs", _abs, brw_inst_3src_src1_abs(devinfo, inst), NULL);
1240
1241 err |= reg(file, _file, reg_nr);
1242 if (err == -1)
1243 return 0;
1244 if (subreg_nr || is_scalar_region)
1245 format(file, ".%d", subreg_nr);
1246 src_align1_region(file, _vert_stride, _width, _horiz_stride);
1247 if (!is_scalar_region && !is_align1)
1248 err |= src_swizzle(file, brw_inst_3src_a16_src1_swizzle(devinfo, inst));
1249 string(file, brw_reg_type_to_letters(type));
1250 return err;
1251 }
1252
1253 static int
1254 src2_3src(FILE *file, const struct gen_device_info *devinfo, const brw_inst *inst)
1255 {
1256 int err = 0;
1257 unsigned reg_nr, subreg_nr;
1258 enum brw_reg_file _file;
1259 enum brw_reg_type type;
1260 enum brw_vertical_stride _vert_stride;
1261 enum brw_width _width;
1262 enum brw_horizontal_stride _horiz_stride;
1263 bool is_scalar_region;
1264 bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1;
1265
1266 if (devinfo->gen < 10 && is_align1)
1267 return 0;
1268
1269 if (is_align1) {
1270 if (devinfo->gen >= 12 && !brw_inst_3src_a1_src2_is_imm(devinfo, inst)) {
1271 _file = brw_inst_3src_a1_src2_reg_file(devinfo, inst);
1272 } else if (brw_inst_3src_a1_src2_reg_file(devinfo, inst) ==
1273 BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE) {
1274 _file = BRW_GENERAL_REGISTER_FILE;
1275 } else {
1276 _file = BRW_IMMEDIATE_VALUE;
1277 uint16_t imm_val = brw_inst_3src_a1_src2_imm(devinfo, inst);
1278 enum brw_reg_type type = brw_inst_3src_a1_src2_type(devinfo, inst);
1279
1280 if (type == BRW_REGISTER_TYPE_W) {
1281 format(file, "%dW", imm_val);
1282 } else if (type == BRW_REGISTER_TYPE_UW) {
1283 format(file, "0x%04xUW", imm_val);
1284 } else if (type == BRW_REGISTER_TYPE_HF) {
1285 format(file, "0x%04xHF", imm_val);
1286 }
1287 return 0;
1288 }
1289
1290 reg_nr = brw_inst_3src_src2_reg_nr(devinfo, inst);
1291 subreg_nr = brw_inst_3src_a1_src2_subreg_nr(devinfo, inst);
1292 type = brw_inst_3src_a1_src2_type(devinfo, inst);
1293 /* FINISHME: No vertical stride on src2. Is using the hstride in place
1294 * correct? Doesn't seem like it, since there's hstride=1 but
1295 * no vstride=1.
1296 */
1297 _vert_stride = vstride_from_align1_3src_hstride(
1298 brw_inst_3src_a1_src2_hstride(devinfo, inst));
1299 _horiz_stride = hstride_from_align1_3src_hstride(
1300 brw_inst_3src_a1_src2_hstride(devinfo, inst));
1301 _width = implied_width(_vert_stride, _horiz_stride);
1302 } else {
1303 _file = BRW_GENERAL_REGISTER_FILE;
1304 reg_nr = brw_inst_3src_src2_reg_nr(devinfo, inst);
1305 subreg_nr = brw_inst_3src_a16_src2_subreg_nr(devinfo, inst) * 4;
1306 type = brw_inst_3src_a16_src_type(devinfo, inst);
1307
1308 if (brw_inst_3src_a16_src2_rep_ctrl(devinfo, inst)) {
1309 _vert_stride = BRW_VERTICAL_STRIDE_0;
1310 _width = BRW_WIDTH_1;
1311 _horiz_stride = BRW_HORIZONTAL_STRIDE_0;
1312 } else {
1313 _vert_stride = BRW_VERTICAL_STRIDE_4;
1314 _width = BRW_WIDTH_4;
1315 _horiz_stride = BRW_HORIZONTAL_STRIDE_1;
1316 }
1317 }
1318 is_scalar_region = _vert_stride == BRW_VERTICAL_STRIDE_0 &&
1319 _width == BRW_WIDTH_1 &&
1320 _horiz_stride == BRW_HORIZONTAL_STRIDE_0;
1321
1322 subreg_nr /= brw_reg_type_to_size(type);
1323
1324 err |= control(file, "negate", m_negate,
1325 brw_inst_3src_src2_negate(devinfo, inst), NULL);
1326 err |= control(file, "abs", _abs, brw_inst_3src_src2_abs(devinfo, inst), NULL);
1327
1328 err |= reg(file, _file, reg_nr);
1329 if (err == -1)
1330 return 0;
1331 if (subreg_nr || is_scalar_region)
1332 format(file, ".%d", subreg_nr);
1333 src_align1_region(file, _vert_stride, _width, _horiz_stride);
1334 if (!is_scalar_region && !is_align1)
1335 err |= src_swizzle(file, brw_inst_3src_a16_src2_swizzle(devinfo, inst));
1336 string(file, brw_reg_type_to_letters(type));
1337 return err;
1338 }
1339
1340 static int
1341 imm(FILE *file, const struct gen_device_info *devinfo, enum brw_reg_type type,
1342 const brw_inst *inst)
1343 {
1344 switch (type) {
1345 case BRW_REGISTER_TYPE_UQ:
1346 format(file, "0x%016"PRIx64"UQ", brw_inst_imm_uq(devinfo, inst));
1347 break;
1348 case BRW_REGISTER_TYPE_Q:
1349 format(file, "0x%016"PRIx64"Q", brw_inst_imm_uq(devinfo, inst));
1350 break;
1351 case BRW_REGISTER_TYPE_UD:
1352 format(file, "0x%08xUD", brw_inst_imm_ud(devinfo, inst));
1353 break;
1354 case BRW_REGISTER_TYPE_D:
1355 format(file, "%dD", brw_inst_imm_d(devinfo, inst));
1356 break;
1357 case BRW_REGISTER_TYPE_UW:
1358 format(file, "0x%04xUW", (uint16_t) brw_inst_imm_ud(devinfo, inst));
1359 break;
1360 case BRW_REGISTER_TYPE_W:
1361 format(file, "%dW", (int16_t) brw_inst_imm_d(devinfo, inst));
1362 break;
1363 case BRW_REGISTER_TYPE_UV:
1364 format(file, "0x%08xUV", brw_inst_imm_ud(devinfo, inst));
1365 break;
1366 case BRW_REGISTER_TYPE_VF:
1367 format(file, "0x%"PRIx64"VF", brw_inst_bits(inst, 127, 96));
1368 pad(file, 48);
1369 format(file, "/* [%-gF, %-gF, %-gF, %-gF]VF */",
1370 brw_vf_to_float(brw_inst_imm_ud(devinfo, inst)),
1371 brw_vf_to_float(brw_inst_imm_ud(devinfo, inst) >> 8),
1372 brw_vf_to_float(brw_inst_imm_ud(devinfo, inst) >> 16),
1373 brw_vf_to_float(brw_inst_imm_ud(devinfo, inst) >> 24));
1374 break;
1375 case BRW_REGISTER_TYPE_V:
1376 format(file, "0x%08xV", brw_inst_imm_ud(devinfo, inst));
1377 break;
1378 case BRW_REGISTER_TYPE_F:
1379 /* The DIM instruction's src0 uses an F type but contains a
1380 * 64-bit immediate
1381 */
1382 if (brw_inst_opcode(devinfo, inst) == BRW_OPCODE_DIM) {
1383 format(file, "0x%"PRIx64"F", brw_inst_bits(inst, 127, 64));
1384 pad(file, 48);
1385 format(file, "/* %-gF */", brw_inst_imm_df(devinfo, inst));
1386 } else {
1387 format(file, "0x%"PRIx64"F", brw_inst_bits(inst, 127, 96));
1388 pad(file, 48);
1389 format(file, " /* %-gF */", brw_inst_imm_f(devinfo, inst));
1390 }
1391 break;
1392 case BRW_REGISTER_TYPE_DF:
1393 format(file, "0x%016"PRIx64"DF", brw_inst_bits(inst, 127, 64));
1394 pad(file, 48);
1395 format(file, "/* %-gDF */", brw_inst_imm_df(devinfo, inst));
1396 break;
1397 case BRW_REGISTER_TYPE_HF:
1398 string(file, "Half Float IMM");
1399 break;
1400 case BRW_REGISTER_TYPE_NF:
1401 case BRW_REGISTER_TYPE_UB:
1402 case BRW_REGISTER_TYPE_B:
1403 format(file, "*** invalid immediate type %d ", type);
1404 }
1405 return 0;
1406 }
1407
1408 static int
1409 src_sends_da(FILE *file,
1410 const struct gen_device_info *devinfo,
1411 enum brw_reg_type type,
1412 enum brw_reg_file _reg_file,
1413 unsigned _reg_nr,
1414 unsigned _reg_subnr)
1415 {
1416 int err = 0;
1417
1418 err |= reg(file, _reg_file, _reg_nr);
1419 if (err == -1)
1420 return 0;
1421 if (_reg_subnr)
1422 format(file, ".1");
1423 string(file, brw_reg_type_to_letters(type));
1424
1425 return err;
1426 }
1427
1428 static int
1429 src_sends_ia(FILE *file,
1430 const struct gen_device_info *devinfo,
1431 enum brw_reg_type type,
1432 int _addr_imm,
1433 unsigned _addr_subreg_nr)
1434 {
1435 string(file, "g[a0");
1436 if (_addr_subreg_nr)
1437 format(file, ".1");
1438 if (_addr_imm)
1439 format(file, " %d", _addr_imm);
1440 string(file, "]");
1441 string(file, brw_reg_type_to_letters(type));
1442
1443 return 0;
1444 }
1445
1446 static int
1447 src_send_desc_ia(FILE *file,
1448 const struct gen_device_info *devinfo,
1449 unsigned _addr_subreg_nr)
1450 {
1451 string(file, "a0");
1452 if (_addr_subreg_nr)
1453 format(file, ".%d", _addr_subreg_nr);
1454 format(file, "<0>UD");
1455
1456 return 0;
1457 }
1458
1459 static int
1460 src0(FILE *file, const struct gen_device_info *devinfo, const brw_inst *inst)
1461 {
1462 if (is_split_send(devinfo, brw_inst_opcode(devinfo, inst))) {
1463 if (devinfo->gen >= 12) {
1464 return src_sends_da(file,
1465 devinfo,
1466 BRW_REGISTER_TYPE_UD,
1467 brw_inst_send_src0_reg_file(devinfo, inst),
1468 brw_inst_src0_da_reg_nr(devinfo, inst),
1469 0);
1470 } else if (brw_inst_send_src0_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
1471 return src_sends_da(file,
1472 devinfo,
1473 BRW_REGISTER_TYPE_UD,
1474 BRW_GENERAL_REGISTER_FILE,
1475 brw_inst_src0_da_reg_nr(devinfo, inst),
1476 brw_inst_src0_da16_subreg_nr(devinfo, inst));
1477 } else {
1478 return src_sends_ia(file,
1479 devinfo,
1480 BRW_REGISTER_TYPE_UD,
1481 brw_inst_send_src0_ia16_addr_imm(devinfo, inst),
1482 brw_inst_src0_ia_subreg_nr(devinfo, inst));
1483 }
1484 } else if (brw_inst_src0_reg_file(devinfo, inst) == BRW_IMMEDIATE_VALUE) {
1485 return imm(file, devinfo, brw_inst_src0_type(devinfo, inst), inst);
1486 } else if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
1487 if (brw_inst_src0_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
1488 return src_da1(file,
1489 devinfo,
1490 brw_inst_opcode(devinfo, inst),
1491 brw_inst_src0_type(devinfo, inst),
1492 brw_inst_src0_reg_file(devinfo, inst),
1493 brw_inst_src0_vstride(devinfo, inst),
1494 brw_inst_src0_width(devinfo, inst),
1495 brw_inst_src0_hstride(devinfo, inst),
1496 brw_inst_src0_da_reg_nr(devinfo, inst),
1497 brw_inst_src0_da1_subreg_nr(devinfo, inst),
1498 brw_inst_src0_abs(devinfo, inst),
1499 brw_inst_src0_negate(devinfo, inst));
1500 } else {
1501 return src_ia1(file,
1502 devinfo,
1503 brw_inst_opcode(devinfo, inst),
1504 brw_inst_src0_type(devinfo, inst),
1505 brw_inst_src0_ia1_addr_imm(devinfo, inst),
1506 brw_inst_src0_ia_subreg_nr(devinfo, inst),
1507 brw_inst_src0_negate(devinfo, inst),
1508 brw_inst_src0_abs(devinfo, inst),
1509 brw_inst_src0_hstride(devinfo, inst),
1510 brw_inst_src0_width(devinfo, inst),
1511 brw_inst_src0_vstride(devinfo, inst));
1512 }
1513 } else {
1514 if (brw_inst_src0_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
1515 return src_da16(file,
1516 devinfo,
1517 brw_inst_opcode(devinfo, inst),
1518 brw_inst_src0_type(devinfo, inst),
1519 brw_inst_src0_reg_file(devinfo, inst),
1520 brw_inst_src0_vstride(devinfo, inst),
1521 brw_inst_src0_da_reg_nr(devinfo, inst),
1522 brw_inst_src0_da16_subreg_nr(devinfo, inst),
1523 brw_inst_src0_abs(devinfo, inst),
1524 brw_inst_src0_negate(devinfo, inst),
1525 brw_inst_src0_da16_swiz_x(devinfo, inst),
1526 brw_inst_src0_da16_swiz_y(devinfo, inst),
1527 brw_inst_src0_da16_swiz_z(devinfo, inst),
1528 brw_inst_src0_da16_swiz_w(devinfo, inst));
1529 } else {
1530 string(file, "Indirect align16 address mode not supported");
1531 return 1;
1532 }
1533 }
1534 }
1535
1536 static int
1537 src1(FILE *file, const struct gen_device_info *devinfo, const brw_inst *inst)
1538 {
1539 if (is_split_send(devinfo, brw_inst_opcode(devinfo, inst))) {
1540 return src_sends_da(file,
1541 devinfo,
1542 BRW_REGISTER_TYPE_UD,
1543 brw_inst_send_src1_reg_file(devinfo, inst),
1544 brw_inst_send_src1_reg_nr(devinfo, inst),
1545 0 /* subreg_nr */);
1546 } else if (brw_inst_src1_reg_file(devinfo, inst) == BRW_IMMEDIATE_VALUE) {
1547 return imm(file, devinfo, brw_inst_src1_type(devinfo, inst), inst);
1548 } else if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
1549 if (brw_inst_src1_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
1550 return src_da1(file,
1551 devinfo,
1552 brw_inst_opcode(devinfo, inst),
1553 brw_inst_src1_type(devinfo, inst),
1554 brw_inst_src1_reg_file(devinfo, inst),
1555 brw_inst_src1_vstride(devinfo, inst),
1556 brw_inst_src1_width(devinfo, inst),
1557 brw_inst_src1_hstride(devinfo, inst),
1558 brw_inst_src1_da_reg_nr(devinfo, inst),
1559 brw_inst_src1_da1_subreg_nr(devinfo, inst),
1560 brw_inst_src1_abs(devinfo, inst),
1561 brw_inst_src1_negate(devinfo, inst));
1562 } else {
1563 return src_ia1(file,
1564 devinfo,
1565 brw_inst_opcode(devinfo, inst),
1566 brw_inst_src1_type(devinfo, inst),
1567 brw_inst_src1_ia1_addr_imm(devinfo, inst),
1568 brw_inst_src1_ia_subreg_nr(devinfo, inst),
1569 brw_inst_src1_negate(devinfo, inst),
1570 brw_inst_src1_abs(devinfo, inst),
1571 brw_inst_src1_hstride(devinfo, inst),
1572 brw_inst_src1_width(devinfo, inst),
1573 brw_inst_src1_vstride(devinfo, inst));
1574 }
1575 } else {
1576 if (brw_inst_src1_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
1577 return src_da16(file,
1578 devinfo,
1579 brw_inst_opcode(devinfo, inst),
1580 brw_inst_src1_type(devinfo, inst),
1581 brw_inst_src1_reg_file(devinfo, inst),
1582 brw_inst_src1_vstride(devinfo, inst),
1583 brw_inst_src1_da_reg_nr(devinfo, inst),
1584 brw_inst_src1_da16_subreg_nr(devinfo, inst),
1585 brw_inst_src1_abs(devinfo, inst),
1586 brw_inst_src1_negate(devinfo, inst),
1587 brw_inst_src1_da16_swiz_x(devinfo, inst),
1588 brw_inst_src1_da16_swiz_y(devinfo, inst),
1589 brw_inst_src1_da16_swiz_z(devinfo, inst),
1590 brw_inst_src1_da16_swiz_w(devinfo, inst));
1591 } else {
1592 string(file, "Indirect align16 address mode not supported");
1593 return 1;
1594 }
1595 }
1596 }
1597
1598 static int
1599 qtr_ctrl(FILE *file, const struct gen_device_info *devinfo, const brw_inst *inst)
1600 {
1601 int qtr_ctl = brw_inst_qtr_control(devinfo, inst);
1602 int exec_size = 1 << brw_inst_exec_size(devinfo, inst);
1603 const unsigned nib_ctl = devinfo->gen < 7 ? 0 :
1604 brw_inst_nib_control(devinfo, inst);
1605
1606 if (exec_size < 8 || nib_ctl) {
1607 format(file, " %dN", qtr_ctl * 2 + nib_ctl + 1);
1608 } else if (exec_size == 8) {
1609 switch (qtr_ctl) {
1610 case 0:
1611 string(file, " 1Q");
1612 break;
1613 case 1:
1614 string(file, " 2Q");
1615 break;
1616 case 2:
1617 string(file, " 3Q");
1618 break;
1619 case 3:
1620 string(file, " 4Q");
1621 break;
1622 }
1623 } else if (exec_size == 16) {
1624 if (qtr_ctl < 2)
1625 string(file, " 1H");
1626 else
1627 string(file, " 2H");
1628 }
1629 return 0;
1630 }
1631
1632 static int
1633 swsb(FILE *file, const struct gen_device_info *devinfo, const brw_inst *inst)
1634 {
1635 const struct tgl_swsb swsb = tgl_swsb_decode(brw_inst_swsb(devinfo, inst));
1636 if (swsb.regdist)
1637 format(file, " @%d", swsb.regdist);
1638 if (swsb.mode)
1639 format(file, " $%d%s", swsb.sbid,
1640 (swsb.mode & TGL_SBID_SET ? "" :
1641 swsb.mode & TGL_SBID_DST ? ".dst" : ".src"));
1642 return 0;
1643 }
1644
1645 #ifdef DEBUG
1646 static __attribute__((__unused__)) int
1647 brw_disassemble_imm(const struct gen_device_info *devinfo,
1648 uint32_t dw3, uint32_t dw2, uint32_t dw1, uint32_t dw0)
1649 {
1650 brw_inst inst;
1651 inst.data[0] = (((uint64_t) dw1) << 32) | ((uint64_t) dw0);
1652 inst.data[1] = (((uint64_t) dw3) << 32) | ((uint64_t) dw2);
1653 return brw_disassemble_inst(stderr, devinfo, &inst, false);
1654 }
1655 #endif
1656
1657 int
1658 brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
1659 const brw_inst *inst, bool is_compacted)
1660 {
1661 int err = 0;
1662 int space = 0;
1663
1664 const enum opcode opcode = brw_inst_opcode(devinfo, inst);
1665 const struct opcode_desc *desc = brw_opcode_desc(devinfo, opcode);
1666
1667 if (brw_inst_pred_control(devinfo, inst)) {
1668 string(file, "(");
1669 err |= control(file, "predicate inverse", pred_inv,
1670 brw_inst_pred_inv(devinfo, inst), NULL);
1671 format(file, "f%"PRIu64".%"PRIu64,
1672 devinfo->gen >= 7 ? brw_inst_flag_reg_nr(devinfo, inst) : 0,
1673 brw_inst_flag_subreg_nr(devinfo, inst));
1674 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
1675 err |= control(file, "predicate control align1", pred_ctrl_align1,
1676 brw_inst_pred_control(devinfo, inst), NULL);
1677 } else {
1678 err |= control(file, "predicate control align16", pred_ctrl_align16,
1679 brw_inst_pred_control(devinfo, inst), NULL);
1680 }
1681 string(file, ") ");
1682 }
1683
1684 err |= print_opcode(file, devinfo, opcode);
1685
1686 if (!is_send(opcode))
1687 err |= control(file, "saturate", saturate, brw_inst_saturate(devinfo, inst),
1688 NULL);
1689
1690 err |= control(file, "debug control", debug_ctrl,
1691 brw_inst_debug_control(devinfo, inst), NULL);
1692
1693 if (opcode == BRW_OPCODE_MATH) {
1694 string(file, " ");
1695 err |= control(file, "function", math_function,
1696 brw_inst_math_function(devinfo, inst), NULL);
1697
1698 } else if (opcode == BRW_OPCODE_SYNC) {
1699 string(file, " ");
1700 err |= control(file, "function", sync_function,
1701 brw_inst_cond_modifier(devinfo, inst), NULL);
1702
1703 } else if (!is_send(opcode)) {
1704 err |= control(file, "conditional modifier", conditional_modifier,
1705 brw_inst_cond_modifier(devinfo, inst), NULL);
1706
1707 /* If we're using the conditional modifier, print which flags reg is
1708 * used for it. Note that on gen6+, the embedded-condition SEL and
1709 * control flow doesn't update flags.
1710 */
1711 if (brw_inst_cond_modifier(devinfo, inst) &&
1712 (devinfo->gen < 6 || (opcode != BRW_OPCODE_SEL &&
1713 opcode != BRW_OPCODE_CSEL &&
1714 opcode != BRW_OPCODE_IF &&
1715 opcode != BRW_OPCODE_WHILE))) {
1716 format(file, ".f%"PRIu64".%"PRIu64,
1717 devinfo->gen >= 7 ? brw_inst_flag_reg_nr(devinfo, inst) : 0,
1718 brw_inst_flag_subreg_nr(devinfo, inst));
1719 }
1720 }
1721
1722 if (opcode != BRW_OPCODE_NOP && opcode != BRW_OPCODE_NENOP) {
1723 string(file, "(");
1724 err |= control(file, "execution size", exec_size,
1725 brw_inst_exec_size(devinfo, inst), NULL);
1726 string(file, ")");
1727 }
1728
1729 if (opcode == BRW_OPCODE_SEND && devinfo->gen < 6)
1730 format(file, " %"PRIu64, brw_inst_base_mrf(devinfo, inst));
1731
1732 if (has_uip(devinfo, opcode)) {
1733 /* Instructions that have UIP also have JIP. */
1734 pad(file, 16);
1735 format(file, "JIP: %d", brw_inst_jip(devinfo, inst));
1736 pad(file, 32);
1737 format(file, "UIP: %d", brw_inst_uip(devinfo, inst));
1738 } else if (has_jip(devinfo, opcode)) {
1739 pad(file, 16);
1740 if (devinfo->gen >= 7) {
1741 format(file, "JIP: %d", brw_inst_jip(devinfo, inst));
1742 } else {
1743 format(file, "JIP: %d", brw_inst_gen6_jump_count(devinfo, inst));
1744 }
1745 } else if (devinfo->gen < 6 && (opcode == BRW_OPCODE_BREAK ||
1746 opcode == BRW_OPCODE_CONTINUE ||
1747 opcode == BRW_OPCODE_ELSE)) {
1748 pad(file, 16);
1749 format(file, "Jump: %d", brw_inst_gen4_jump_count(devinfo, inst));
1750 pad(file, 32);
1751 format(file, "Pop: %"PRIu64, brw_inst_gen4_pop_count(devinfo, inst));
1752 } else if (devinfo->gen < 6 && (opcode == BRW_OPCODE_IF ||
1753 opcode == BRW_OPCODE_IFF ||
1754 opcode == BRW_OPCODE_HALT ||
1755 opcode == BRW_OPCODE_WHILE)) {
1756 pad(file, 16);
1757 format(file, "Jump: %d", brw_inst_gen4_jump_count(devinfo, inst));
1758 } else if (devinfo->gen < 6 && opcode == BRW_OPCODE_ENDIF) {
1759 pad(file, 16);
1760 format(file, "Pop: %"PRIu64, brw_inst_gen4_pop_count(devinfo, inst));
1761 } else if (opcode == BRW_OPCODE_JMPI) {
1762 pad(file, 16);
1763 err |= src1(file, devinfo, inst);
1764 } else if (desc && desc->nsrc == 3) {
1765 pad(file, 16);
1766 err |= dest_3src(file, devinfo, inst);
1767
1768 pad(file, 32);
1769 err |= src0_3src(file, devinfo, inst);
1770
1771 pad(file, 48);
1772 err |= src1_3src(file, devinfo, inst);
1773
1774 pad(file, 64);
1775 err |= src2_3src(file, devinfo, inst);
1776 } else if (desc) {
1777 if (desc->ndst > 0) {
1778 pad(file, 16);
1779 err |= dest(file, devinfo, inst);
1780 }
1781
1782 if (desc->nsrc > 0) {
1783 pad(file, 32);
1784 err |= src0(file, devinfo, inst);
1785 }
1786
1787 if (desc->nsrc > 1) {
1788 pad(file, 48);
1789 err |= src1(file, devinfo, inst);
1790 }
1791 }
1792
1793 if (is_send(opcode)) {
1794 enum brw_message_target sfid = brw_inst_sfid(devinfo, inst);
1795
1796 bool has_imm_desc = false, has_imm_ex_desc = false;
1797 uint32_t imm_desc = 0, imm_ex_desc = 0;
1798 if (is_split_send(devinfo, opcode)) {
1799 pad(file, 64);
1800 if (brw_inst_send_sel_reg32_desc(devinfo, inst)) {
1801 /* show the indirect descriptor source */
1802 err |= src_send_desc_ia(file, devinfo, 0);
1803 } else {
1804 has_imm_desc = true;
1805 imm_desc = brw_inst_send_desc(devinfo, inst);
1806 fprintf(file, "0x%08"PRIx32, imm_desc);
1807 }
1808
1809 pad(file, 80);
1810 if (brw_inst_send_sel_reg32_ex_desc(devinfo, inst)) {
1811 /* show the indirect descriptor source */
1812 err |= src_send_desc_ia(file, devinfo,
1813 brw_inst_send_ex_desc_ia_subreg_nr(devinfo, inst));
1814 } else {
1815 has_imm_ex_desc = true;
1816 imm_ex_desc = brw_inst_sends_ex_desc(devinfo, inst);
1817 fprintf(file, "0x%08"PRIx32, imm_ex_desc);
1818 }
1819 } else {
1820 if (brw_inst_src1_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE) {
1821 /* show the indirect descriptor source */
1822 pad(file, 48);
1823 err |= src1(file, devinfo, inst);
1824 pad(file, 64);
1825 } else {
1826 has_imm_desc = true;
1827 imm_desc = brw_inst_send_desc(devinfo, inst);
1828 pad(file, 48);
1829 }
1830
1831 /* Print message descriptor as immediate source */
1832 fprintf(file, "0x%08"PRIx64, inst->data[1] >> 32);
1833 }
1834
1835 newline(file);
1836 pad(file, 16);
1837 space = 0;
1838
1839 fprintf(file, " ");
1840 err |= control(file, "SFID", devinfo->gen >= 6 ? gen6_sfid : gen4_sfid,
1841 sfid, &space);
1842 string(file, " MsgDesc:");
1843
1844 if (!has_imm_desc) {
1845 format(file, " indirect");
1846 } else {
1847 switch (sfid) {
1848 case BRW_SFID_MATH:
1849 err |= control(file, "math function", math_function,
1850 brw_inst_math_msg_function(devinfo, inst), &space);
1851 err |= control(file, "math saturate", math_saturate,
1852 brw_inst_math_msg_saturate(devinfo, inst), &space);
1853 err |= control(file, "math signed", math_signed,
1854 brw_inst_math_msg_signed_int(devinfo, inst), &space);
1855 err |= control(file, "math scalar", math_scalar,
1856 brw_inst_math_msg_data_type(devinfo, inst), &space);
1857 err |= control(file, "math precision", math_precision,
1858 brw_inst_math_msg_precision(devinfo, inst), &space);
1859 break;
1860 case BRW_SFID_SAMPLER:
1861 if (devinfo->gen >= 5) {
1862 err |= control(file, "sampler message", gen5_sampler_msg_type,
1863 brw_sampler_desc_msg_type(devinfo, imm_desc),
1864 &space);
1865 err |= control(file, "sampler simd mode", gen5_sampler_simd_mode,
1866 brw_sampler_desc_simd_mode(devinfo, imm_desc),
1867 &space);
1868 format(file, " Surface = %u Sampler = %u",
1869 brw_sampler_desc_binding_table_index(devinfo, imm_desc),
1870 brw_sampler_desc_sampler(devinfo, imm_desc));
1871 } else {
1872 format(file, " (%u, %u, %u, ",
1873 brw_sampler_desc_binding_table_index(devinfo, imm_desc),
1874 brw_sampler_desc_sampler(devinfo, imm_desc),
1875 brw_sampler_desc_msg_type(devinfo, imm_desc));
1876 if (!devinfo->is_g4x) {
1877 err |= control(file, "sampler target format",
1878 sampler_target_format,
1879 brw_sampler_desc_return_format(devinfo, imm_desc),
1880 NULL);
1881 }
1882 string(file, ")");
1883 }
1884 break;
1885 case GEN6_SFID_DATAPORT_SAMPLER_CACHE:
1886 case GEN6_SFID_DATAPORT_CONSTANT_CACHE:
1887 /* aka BRW_SFID_DATAPORT_READ on Gen4-5 */
1888 if (devinfo->gen >= 6) {
1889 format(file, " (%u, %u, %u, %u)",
1890 brw_dp_desc_binding_table_index(devinfo, imm_desc),
1891 brw_dp_desc_msg_control(devinfo, imm_desc),
1892 brw_dp_desc_msg_type(devinfo, imm_desc),
1893 devinfo->gen >= 7 ? 0u :
1894 brw_dp_write_desc_write_commit(devinfo, imm_desc));
1895 } else {
1896 bool is_965 = devinfo->gen == 4 && !devinfo->is_g4x;
1897 err |= control(file, "DP read message type",
1898 is_965 ? gen4_dp_read_port_msg_type :
1899 g45_dp_read_port_msg_type,
1900 brw_dp_read_desc_msg_type(devinfo, imm_desc),
1901 &space);
1902
1903 format(file, " MsgCtrl = 0x%u",
1904 brw_dp_read_desc_msg_control(devinfo, imm_desc));
1905
1906 format(file, " Surface = %u",
1907 brw_dp_desc_binding_table_index(devinfo, imm_desc));
1908 }
1909 break;
1910
1911 case GEN6_SFID_DATAPORT_RENDER_CACHE: {
1912 /* aka BRW_SFID_DATAPORT_WRITE on Gen4-5 */
1913 unsigned msg_type = brw_dp_write_desc_msg_type(devinfo, imm_desc);
1914
1915 err |= control(file, "DP rc message type",
1916 dp_rc_msg_type(devinfo), msg_type, &space);
1917
1918 bool is_rt_write = msg_type ==
1919 (devinfo->gen >= 6 ? GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE
1920 : BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE);
1921
1922 if (is_rt_write) {
1923 err |= control(file, "RT message type", m_rt_write_subtype,
1924 brw_inst_rt_message_type(devinfo, inst), &space);
1925 if (devinfo->gen >= 6 && brw_inst_rt_slot_group(devinfo, inst))
1926 string(file, " Hi");
1927 if (brw_dp_write_desc_last_render_target(devinfo, imm_desc))
1928 string(file, " LastRT");
1929 if (devinfo->gen < 7 &&
1930 brw_dp_write_desc_write_commit(devinfo, imm_desc))
1931 string(file, " WriteCommit");
1932 } else {
1933 format(file, " MsgCtrl = 0x%u",
1934 brw_dp_write_desc_msg_control(devinfo, imm_desc));
1935 }
1936
1937 format(file, " Surface = %u",
1938 brw_dp_desc_binding_table_index(devinfo, imm_desc));
1939 break;
1940 }
1941
1942 case BRW_SFID_URB: {
1943 unsigned opcode = brw_inst_urb_opcode(devinfo, inst);
1944
1945 format(file, " %"PRIu64, brw_inst_urb_global_offset(devinfo, inst));
1946
1947 space = 1;
1948
1949 err |= control(file, "urb opcode",
1950 devinfo->gen >= 7 ? gen7_urb_opcode
1951 : gen5_urb_opcode,
1952 opcode, &space);
1953
1954 if (devinfo->gen >= 7 &&
1955 brw_inst_urb_per_slot_offset(devinfo, inst)) {
1956 string(file, " per-slot");
1957 }
1958
1959 if (opcode == GEN8_URB_OPCODE_SIMD8_WRITE ||
1960 opcode == GEN8_URB_OPCODE_SIMD8_READ) {
1961 if (brw_inst_urb_channel_mask_present(devinfo, inst))
1962 string(file, " masked");
1963 } else {
1964 err |= control(file, "urb swizzle", urb_swizzle,
1965 brw_inst_urb_swizzle_control(devinfo, inst),
1966 &space);
1967 }
1968
1969 if (devinfo->gen < 7) {
1970 err |= control(file, "urb allocate", urb_allocate,
1971 brw_inst_urb_allocate(devinfo, inst), &space);
1972 err |= control(file, "urb used", urb_used,
1973 brw_inst_urb_used(devinfo, inst), &space);
1974 }
1975 if (devinfo->gen < 8) {
1976 err |= control(file, "urb complete", urb_complete,
1977 brw_inst_urb_complete(devinfo, inst), &space);
1978 }
1979 break;
1980 }
1981 case BRW_SFID_THREAD_SPAWNER:
1982 break;
1983
1984 case BRW_SFID_MESSAGE_GATEWAY:
1985 format(file, " (%s)",
1986 gen7_gateway_subfuncid[brw_inst_gateway_subfuncid(devinfo, inst)]);
1987 break;
1988
1989 case GEN7_SFID_DATAPORT_DATA_CACHE:
1990 if (devinfo->gen >= 7) {
1991 format(file, " (");
1992
1993 err |= control(file, "DP DC0 message type",
1994 dp_dc0_msg_type_gen7,
1995 brw_dp_desc_msg_type(devinfo, imm_desc), &space);
1996
1997 format(file, ", %u, ",
1998 brw_dp_desc_binding_table_index(devinfo, imm_desc));
1999
2000 switch (brw_inst_dp_msg_type(devinfo, inst)) {
2001 case GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP:
2002 control(file, "atomic op", aop,
2003 brw_dp_desc_msg_control(devinfo, imm_desc) & 0xf,
2004 &space);
2005 break;
2006 default:
2007 format(file, "%u",
2008 brw_dp_desc_msg_control(devinfo, imm_desc));
2009 }
2010 format(file, ")");
2011 break;
2012 }
2013 /* FALLTHROUGH */
2014
2015 case HSW_SFID_DATAPORT_DATA_CACHE_1: {
2016 if (devinfo->gen >= 7) {
2017 format(file, " (");
2018
2019 unsigned msg_ctrl = brw_dp_desc_msg_control(devinfo, imm_desc);
2020
2021 err |= control(file, "DP DC1 message type",
2022 dp_dc1_msg_type_hsw,
2023 brw_dp_desc_msg_type(devinfo, imm_desc), &space);
2024
2025 format(file, ", Surface = %u, ",
2026 brw_dp_desc_binding_table_index(devinfo, imm_desc));
2027
2028 switch (brw_inst_dp_msg_type(devinfo, inst)) {
2029 case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP:
2030 case HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP:
2031 case HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP:
2032 format(file, "SIMD%d,", (msg_ctrl & (1 << 4)) ? 8 : 16);
2033 /* fallthrough */
2034 case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2:
2035 case HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2:
2036 case HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2:
2037 case GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP:
2038 control(file, "atomic op", aop, msg_ctrl & 0xf, &space);
2039 break;
2040 case HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ:
2041 case HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE:
2042 case HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ:
2043 case HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE:
2044 case GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE:
2045 case GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ: {
2046 static const char *simd_modes[] = { "4x2", "16", "8" };
2047 format(file, "SIMD%s, Mask = 0x%x",
2048 simd_modes[msg_ctrl >> 4], msg_ctrl & 0xf);
2049 break;
2050 }
2051 case GEN9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP:
2052 case GEN9_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_FLOAT_OP:
2053 format(file, "SIMD%d,", (msg_ctrl & (1 << 4)) ? 8 : 16);
2054 control(file, "atomic float op", aop_float, msg_ctrl & 0xf,
2055 &space);
2056 break;
2057 default:
2058 format(file, "0x%x", msg_ctrl);
2059 }
2060 format(file, ")");
2061 break;
2062 }
2063 /* FALLTHROUGH */
2064 }
2065
2066 case GEN7_SFID_PIXEL_INTERPOLATOR:
2067 if (devinfo->gen >= 7) {
2068 format(file, " (%s, %s, 0x%02"PRIx64")",
2069 brw_inst_pi_nopersp(devinfo, inst) ? "linear" : "persp",
2070 pixel_interpolator_msg_types[brw_inst_pi_message_type(devinfo, inst)],
2071 brw_inst_pi_message_data(devinfo, inst));
2072 break;
2073 }
2074 /* FALLTHROUGH */
2075
2076 default:
2077 format(file, "unsupported shared function ID %d", sfid);
2078 break;
2079 }
2080
2081 if (space)
2082 string(file, " ");
2083 }
2084 if (has_imm_desc)
2085 format(file, "mlen %u", brw_message_desc_mlen(devinfo, imm_desc));
2086 if (has_imm_ex_desc) {
2087 format(file, " ex_mlen %u",
2088 brw_message_ex_desc_ex_mlen(devinfo, imm_ex_desc));
2089 }
2090 if (has_imm_desc)
2091 format(file, " rlen %u", brw_message_desc_rlen(devinfo, imm_desc));
2092 }
2093 pad(file, 64);
2094 if (opcode != BRW_OPCODE_NOP && opcode != BRW_OPCODE_NENOP) {
2095 string(file, "{");
2096 space = 1;
2097 err |= control(file, "access mode", access_mode,
2098 brw_inst_access_mode(devinfo, inst), &space);
2099 if (devinfo->gen >= 6) {
2100 err |= control(file, "write enable control", wectrl,
2101 brw_inst_mask_control(devinfo, inst), &space);
2102 } else {
2103 err |= control(file, "mask control", mask_ctrl,
2104 brw_inst_mask_control(devinfo, inst), &space);
2105 }
2106
2107 if (devinfo->gen < 12) {
2108 err |= control(file, "dependency control", dep_ctrl,
2109 ((brw_inst_no_dd_check(devinfo, inst) << 1) |
2110 brw_inst_no_dd_clear(devinfo, inst)), &space);
2111 }
2112
2113 if (devinfo->gen >= 6)
2114 err |= qtr_ctrl(file, devinfo, inst);
2115 else {
2116 if (brw_inst_qtr_control(devinfo, inst) == BRW_COMPRESSION_COMPRESSED &&
2117 desc && desc->ndst > 0 &&
2118 brw_inst_dst_reg_file(devinfo, inst) == BRW_MESSAGE_REGISTER_FILE &&
2119 brw_inst_dst_da_reg_nr(devinfo, inst) & BRW_MRF_COMPR4) {
2120 format(file, " compr4");
2121 } else {
2122 err |= control(file, "compression control", compr_ctrl,
2123 brw_inst_qtr_control(devinfo, inst), &space);
2124 }
2125 }
2126
2127 if (devinfo->gen >= 12)
2128 err |= swsb(file, devinfo, inst);
2129
2130 err |= control(file, "compaction", cmpt_ctrl, is_compacted, &space);
2131 err |= control(file, "thread control", thread_ctrl,
2132 (devinfo->gen >= 12 ? brw_inst_atomic_control(devinfo, inst) :
2133 brw_inst_thread_control(devinfo, inst)),
2134 &space);
2135 if (has_branch_ctrl(devinfo, opcode)) {
2136 err |= control(file, "branch ctrl", branch_ctrl,
2137 brw_inst_branch_control(devinfo, inst), &space);
2138 } else if (devinfo->gen >= 6) {
2139 err |= control(file, "acc write control", accwr,
2140 brw_inst_acc_wr_control(devinfo, inst), &space);
2141 }
2142 if (is_send(opcode))
2143 err |= control(file, "end of thread", end_of_thread,
2144 brw_inst_eot(devinfo, inst), &space);
2145 if (space)
2146 string(file, " ");
2147 string(file, "}");
2148 }
2149 string(file, ";");
2150 newline(file);
2151 return err;
2152 }